drm/msm: Add a struct to pass configuration to msm_gpu_init()

The amount of information that we need to pass into msm_gpu_init()
is steadily increasing, so add a new struct to stabilize the function
call and make it easier to add new configuration down the line.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 5b63fc649dcc5f2b399bd6e5cb281b0397367a6a..8f3809fc3576a80b2b160de7f2ea524a072a6a3e 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -342,6 +342,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
                struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs)
 {
        struct adreno_platform_config *config = pdev->dev.platform_data;
+       struct msm_gpu_config adreno_gpu_config  = { 0 };
        struct msm_gpu *gpu = &adreno_gpu->base;
        int ret;
 
@@ -360,9 +361,16 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
        DBG("fast_rate=%u, slow_rate=27000000, bus_freq=%u",
                        gpu->fast_rate, gpu->bus_freq);
 
+       adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
+       adreno_gpu_config.irqname = "kgsl_3d0_irq";
+
+       adreno_gpu_config.va_start = SZ_16M;
+       adreno_gpu_config.va_end = 0xffffffff;
+
+       adreno_gpu_config.ringsz = RB_SIZE;
+
        ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
-                       adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
-                       RB_SIZE);
+                       adreno_gpu->info->name, &adreno_gpu_config);
        if (ret)
                return ret;
 

diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 0fdc88d79ca87b3a54709aa4d527db80ca0997dc..5b118e8ead18cc18fd96b7eaa2b8425e61570c74 100644 (file)
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -562,7 +562,7 @@ static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
 
 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
                struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
-               const char *name, const char *ioname, const char *irqname, int ringsz)
+               const char *name, struct msm_gpu_config *config)
 {
        struct iommu_domain *iommu;
        int ret;
@@ -593,14 +593,14 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 
 
        /* Map registers: */
-       gpu->mmio = msm_ioremap(pdev, ioname, name);
+       gpu->mmio = msm_ioremap(pdev, config->ioname, name);
        if (IS_ERR(gpu->mmio)) {
                ret = PTR_ERR(gpu->mmio);
                goto fail;
        }
 
        /* Get Interrupt: */
-       gpu->irq = platform_get_irq_byname(pdev, irqname);
+       gpu->irq = platform_get_irq_byname(pdev, config->irqname);
        if (gpu->irq < 0) {
                ret = gpu->irq;
                dev_err(drm->dev, "failed to get irq: %d\n", ret);
@@ -640,9 +640,8 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
         */
        iommu = iommu_domain_alloc(&platform_bus_type);
        if (iommu) {
-               /* TODO 32b vs 64b address space.. */
-               iommu->geometry.aperture_start = SZ_16M;
-               iommu->geometry.aperture_end = 0xffffffff;
+               iommu->geometry.aperture_start = config->va_start;
+               iommu->geometry.aperture_end = config->va_end;
 
                dev_info(drm->dev, "%s: using IOMMU\n", name);
                gpu->aspace = msm_gem_address_space_create(&pdev->dev,
@@ -663,7 +662,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 
        /* Create ringbuffer: */
        mutex_lock(&drm->struct_mutex);
-       gpu->rb = msm_ringbuffer_new(gpu, ringsz);
+       gpu->rb = msm_ringbuffer_new(gpu, config->ringsz);
        mutex_unlock(&drm->struct_mutex);
        if (IS_ERR(gpu->rb)) {
                ret = PTR_ERR(gpu->rb);

diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 636450299c3397b92f9aba5e1895a66e27558fa5..fd8049592aae4d545ba07aa9da0fa76bfa5a8c4f 100644 (file)
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -28,6 +28,14 @@
 struct msm_gem_submit;
 struct msm_gpu_perfcntr;
 
+struct msm_gpu_config {
+       const char *ioname;
+       const char *irqname;
+       uint64_t va_start;
+       uint64_t va_end;
+       unsigned int ringsz;
+};
+
 /* So far, with hardware that I've seen to date, we can have:
  *  + zero, one, or two z180 2d cores
  *  + a3xx or a2xx 3d core, which share a common CP (the firmware
@@ -208,7 +216,8 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 
 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
                struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
-               const char *name, const char *ioname, const char *irqname, int ringsz);
+               const char *name, struct msm_gpu_config *config);
+
 void msm_gpu_cleanup(struct msm_gpu *gpu);
 
 struct msm_gpu *adreno_load_gpu(struct drm_device *dev);