]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/commitdiff
ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART
authorYixun Lan <yixun.lan@amlogic.com>
Thu, 11 Jan 2018 02:33:58 +0000 (10:33 +0800)
committerKevin Hilman <khilman@baylibre.com>
Mon, 12 Feb 2018 22:15:10 +0000 (14:15 -0800)
When update the clock info for the UART controller in the EE domain,
the driver explicitly require 'pclk' in order to work properly.

With current logic of the code, the driver will go for the legacy clock probe
routine if it find current compatible string match to 'amlogic,meson-uart',
which result in not requesting the 'pclk' clock, thus break the driver in the end.

Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
arch/arm64/boot/dts/amlogic/meson-axg.dtsi

index 5b5ef27ee7d4f2d4f36d1c0fed2deb34c95123ba..b14841499ee2660b1ffe0fb5adfdfbf5345a6464 100644 (file)
                        };
 
                        uart_A: serial@24000 {
-                               compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
+                               compatible = "amlogic,meson-gx-uart";
                                reg = <0x0 0x24000 0x0 0x18>;
                                interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
                                status = "disabled";
+                               clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+                               clock-names = "xtal", "pclk", "baud";
                        };
 
                        uart_B: serial@23000 {
-                               compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
+                               compatible = "amlogic,meson-gx-uart";
                                reg = <0x0 0x23000 0x0 0x18>;
                                interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
                                status = "disabled";
+                               clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+                               clock-names = "xtal", "pclk", "baud";
                        };
                };