#include "8255.h"
-#define BUF_C0 0x1
-#define BUF_B0 0x2
-#define BUF_A0 0x4
-#define BUF_C1 0x8
-#define BUF_B1 0x10
-#define BUF_A1 0x20
-
-#define GATE_A0 0x4
-#define GATE_B0 0x2
-#define GATE_C0 0x1
-#define GATE_A1 0x20
-#define GATE_B1 0x10
-#define GATE_C1 0x8
+/*
+ * Register I/O Map
+ *
+ * This board has two standard 8255 devices that provide six 8-bit DIO ports
+ * (48 channels total). Six 74HCT245 chips (one for each port) buffer the
+ * I/O lines to increase driving capability. Because the 74HCT245 is a
+ * bidirectional, tri-state line buffer, two additional I/O ports are used
+ * to control the direction of data and the enable of each port.
+ */
+#define PCM3724_8255_0_BASE 0x00
+#define PCM3724_8255_1_BASE 0x04
+#define PCM3724_DIO_DIR_REG 0x08
+#define PCM3724_DIO_DIR_C0_OUT BIT(0)
+#define PCM3724_DIO_DIR_B0_OUT BIT(1)
+#define PCM3724_DIO_DIR_A0_OUT BIT(2)
+#define PCM3724_DIO_DIR_C1_OUT BIT(3)
+#define PCM3724_DIO_DIR_B1_OUT BIT(4)
+#define PCM3724_DIO_DIR_A1_OUT BIT(5)
+#define PCM3724_GATE_CTRL_REG 0x09
+#define PCM3724_GATE_CTRL_C0_ENA BIT(0)
+#define PCM3724_GATE_CTRL_B0_ENA BIT(1)
+#define PCM3724_GATE_CTRL_A0_ENA BIT(2)
+#define PCM3724_GATE_CTRL_C1_ENA BIT(3)
+#define PCM3724_GATE_CTRL_B1_ENA BIT(4)
+#define PCM3724_GATE_CTRL_A1_ENA BIT(5)
/* used to track configured dios */
struct priv_pcm3724 {
/* 1 in io_bits indicates output */
if (s->io_bits & 0x0000ff) {
if (devno == 0)
- config |= BUF_A0;
+ config |= PCM3724_DIO_DIR_A0_OUT;
else
- config |= BUF_A1;
+ config |= PCM3724_DIO_DIR_A1_OUT;
}
if (s->io_bits & 0x00ff00) {
if (devno == 0)
- config |= BUF_B0;
+ config |= PCM3724_DIO_DIR_B0_OUT;
else
- config |= BUF_B1;
+ config |= PCM3724_DIO_DIR_B1_OUT;
}
if (s->io_bits & 0xff0000) {
if (devno == 0)
- config |= BUF_C0;
+ config |= PCM3724_DIO_DIR_C0_OUT;
else
- config |= BUF_C1;
+ config |= PCM3724_DIO_DIR_C1_OUT;
}
return config;
}
else
port_8255_cfg = dev->iobase + I8255_SIZE + I8255_CTRL_REG;
- outb(buffer_config, dev->iobase + 8); /* update buffer register */
+ outb(buffer_config, dev->iobase + PCM3724_DIO_DIR_REG);
outb(config, port_8255_cfg);
}
priv->dio_2 |= mask;
if (priv->dio_1 & 0xff0000)
- gatecfg |= GATE_C0;
+ gatecfg |= PCM3724_GATE_CTRL_C0_ENA;
if (priv->dio_1 & 0xff00)
- gatecfg |= GATE_B0;
+ gatecfg |= PCM3724_GATE_CTRL_B0_ENA;
if (priv->dio_1 & 0xff)
- gatecfg |= GATE_A0;
+ gatecfg |= PCM3724_GATE_CTRL_A0_ENA;
if (priv->dio_2 & 0xff0000)
- gatecfg |= GATE_C1;
+ gatecfg |= PCM3724_GATE_CTRL_C1_ENA;
if (priv->dio_2 & 0xff00)
- gatecfg |= GATE_B1;
+ gatecfg |= PCM3724_GATE_CTRL_B1_ENA;
if (priv->dio_2 & 0xff)
- gatecfg |= GATE_A1;
+ gatecfg |= PCM3724_GATE_CTRL_A1_ENA;
- outb(gatecfg, dev->iobase + 9);
+ outb(gatecfg, dev->iobase + PCM3724_GATE_CTRL_REG);
}
/* overriding the 8255 insn config */