drm: rcar-du: lvds: Fix LVDS startup on R-Car Gen3

BugLink: http://bugs.launchpad.net/bugs/1786352
[ Upstream commit 796ceb9269626afaed3b4955c40d2c3d7a8c5d01 ]

According to the latest revisions of the R-Car Gen3 manual, the LVDS mode
must be set before the LVDS I/O pins are enabled, not after -- fix the
Gen3 LVDS startup sequence accordingly.

Fixes: e947eccbeba4 ("drm: rcar-du: Add support for LVDS mode selection")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[Updated comment in rcar_du_lvdsenc_start_gen3()]
[Moved Gen2 startup comment update to separate commit]
[Fixed =| typo]
Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
index 12d22f3db1af0fd992693711080f87a3ca8bee5c..97342240c74d9a6c9a8276674511de9d79b8e3e7 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
@@ -95,7 +95,7 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds,
        u32 lvdcr0;
        u32 pllcr;
 
-       /* PLL clock configuration */
+       /* Set the PLL clock configuration and LVDS mode. */
        if (freq < 42000)
                pllcr = LVDPLLCR_PLLDIVCNT_42M;
        else if (freq < 85000)
@@ -107,6 +107,9 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds,
 
        rcar_lvds_write(lvds, LVDPLLCR, pllcr);
 
+       lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
+       rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+
        /* Turn all the channels on. */
        rcar_lvds_write(lvds, LVDCR1,
                        LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) |
@@ -117,7 +120,7 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds,
         * Turn the PLL on, set it to LVDS normal mode, wait for the startup
         * delay and turn the output on.
         */
-       lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_PLLON;
+       lvdcr0 |= LVDCR0_PLLON;
        rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 
        lvdcr0 |= LVDCR0_PWD;