drm/amd/display: Correct timings in build scaling params

A previous patch set the addressable timing as active + border,
when in fact, the VESA standard specifies active as equal to
addressable + border.

This patch makes the fix more correct and in line with the standard.

Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 55feb16b1fd735380c90ddda135c9b0b4893b8a3..0aca7a3d3dd6bf5f63ad4c68775b51b8ba84656a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -850,22 +850,11 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
         */
        pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
 
-       /**
-        * KMD sends us h and v_addressable without the borders, which causes us sometimes to draw
-        * the blank region on-screen. Correct for this by adding the borders back to their
-        * respective addressable values, and by shifting recout.
-        */
-       timing->h_addressable += timing->h_border_left + timing->h_border_right;
-       timing->v_addressable += timing->v_border_top + timing->v_border_bottom;
-       pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
        pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
-       timing->v_border_top = 0;
-       timing->v_border_bottom = 0;
-       timing->h_border_left = 0;
-       timing->h_border_right = 0;
+       pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
 
-       pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable;
-       pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable;
+       pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
+       pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
 
        /* Taps calculations */
        if (pipe_ctx->plane_res.xfm != NULL)