spi: spi-geni-qcom: Don't set {tx,rx}_rem_bytes unnecessarily

We only need to test for these counters being non-zero when we see the
end of a transfer. If we're doing a CS change then they will already be
zero.  This implies that we don't need to set these to 0 if we're
cancelling an in flight transfer too, because we only care to test these
counters when the 'DONE' bit is set in the hardware and we've set them
to non-zero for a transfer.

This is a non-functional change, just cleanup to consolidate code.

Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200620022233.64716-3-swboyd@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index d8f03ffb8594d25addffc2e814d20bda9f5f2d05..5b1dca1fff79af914792e19d7a540006da5a202b 100644 (file)
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -122,7 +122,6 @@ static void handle_fifo_timeout(struct spi_master *spi,
        reinit_completion(&mas->cancel_done);
        writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
        mas->cur_xfer = NULL;
-       mas->tx_rem_bytes = mas->rx_rem_bytes = 0;
        geni_se_cancel_m_cmd(se);
        spin_unlock_irq(&mas->lock);
 
@@ -513,29 +512,30 @@ static irqreturn_t geni_spi_isr(int irq, void *data)
                if (mas->cur_xfer) {
                        spi_finalize_current_transfer(spi);
                        mas->cur_xfer = NULL;
+                       /*
+                        * If this happens, then a CMD_DONE came before all the
+                        * Tx buffer bytes were sent out. This is unusual, log
+                        * this condition and disable the WM interrupt to
+                        * prevent the system from stalling due an interrupt
+                        * storm.
+                        *
+                        * If this happens when all Rx bytes haven't been
+                        * received, log the condition. The only known time
+                        * this can happen is if bits_per_word != 8 and some
+                        * registers that expect xfer lengths in num spi_words
+                        * weren't written correctly.
+                        */
+                       if (mas->tx_rem_bytes) {
+                               writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
+                               dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
+                                       mas->tx_rem_bytes, mas->cur_bits_per_word);
+                       }
+                       if (mas->rx_rem_bytes)
+                               dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
+                                       mas->rx_rem_bytes, mas->cur_bits_per_word);
                } else {
                        complete(&mas->cs_done);
                }
-
-               /*
-                * If this happens, then a CMD_DONE came before all the Tx
-                * buffer bytes were sent out. This is unusual, log this
-                * condition and disable the WM interrupt to prevent the
-                * system from stalling due an interrupt storm.
-                * If this happens when all Rx bytes haven't been received, log
-                * the condition.
-                * The only known time this can happen is if bits_per_word != 8
-                * and some registers that expect xfer lengths in num spi_words
-                * weren't written correctly.
-                */
-               if (mas->tx_rem_bytes) {
-                       writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
-                       dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
-                               mas->tx_rem_bytes, mas->cur_bits_per_word);
-               }
-               if (mas->rx_rem_bytes)
-                       dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
-                               mas->rx_rem_bytes, mas->cur_bits_per_word);
        }
 
        if (m_irq & M_CMD_CANCEL_EN)