dcrtc->extclk[0] = clk;
- /* Lower the watermark so to eliminate jitter at higher bandwidths */
- armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);
+ /*
+ * Lower the watermark so to eliminate jitter at higher bandwidths.
+ * Disable SRAM read wait state to avoid system hang with external
+ * clock.
+ */
+ armada_updatel(CFG_DMA_WM(0x20), CFG_SRAM_WAIT | CFG_DMA_WM_MASK,
+ dcrtc->base + LCD_CFG_RDREG4F);
/* Initialise SPU register */
writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
ADV_VSYNC_H_OFF = 0xfff << 0,
};
+/* LCD_CFG_RDREG4F - Armada 510 only */
+enum {
+ CFG_SRAM_WAIT = BIT(11),
+ CFG_SMPN_FASTTX = BIT(10),
+ CFG_DMA_ARB = BIT(9),
+ CFG_DMA_WM_EN = BIT(8),
+ CFG_DMA_WM_MASK = 0xff,
+#define CFG_DMA_WM(x) ((x) & CFG_DMA_WM_MASK)
+};
+
enum {
CFG_565 = 0,
CFG_1555 = 1,