hwspinlock: qcom: correct MMIO max register for newer SoCs

[ Upstream commit 90cb380f9ceb811059340d06ff5fd0c0e93ecbe1 ]

Newer ARMv8 Qualcomm SoCs using 0x1000 register stride have maximum
register 0x20000 (32 mutexes * 0x1000).

Fixes: 7a1e6fb1c606 ("hwspinlock: qcom: Allow mmio usage in addition to syscon")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220909092035.223915-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
(cherry picked from commit fa722006f762a1ddfd92663e05af52f4520decb6)
Signed-off-by: Thomas Lamprecht <t.lamprecht@proxmox.com>

diff --git a/drivers/hwspinlock/qcom_hwspinlock.c b/drivers/hwspinlock/qcom_hwspinlock.c
index 3647109666658c60a459e766e42bfbaf9db82881..e499146648639772eda4192d3981d046662fa6e2 100644 (file)
--- a/drivers/hwspinlock/qcom_hwspinlock.c
+++ b/drivers/hwspinlock/qcom_hwspinlock.c
@@ -105,7 +105,7 @@ static const struct regmap_config tcsr_mutex_config = {
        .reg_bits               = 32,
        .reg_stride             = 4,
        .val_bits               = 32,
-       .max_register           = 0x40000,
+       .max_register           = 0x20000,
        .fast_io                = true,
 };