]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/commitdiff
net: hns3: Add PCIe AER callback error_detected
authorShiju Jose <shiju.jose@huawei.com>
Fri, 19 Oct 2018 19:15:26 +0000 (20:15 +0100)
committerDavid S. Miller <davem@davemloft.net>
Tue, 23 Oct 2018 02:31:13 +0000 (19:31 -0700)
Set of hw errors occurred in the HNS3 are reported to the
hns3 driver through PCIe AER and RAS.The error info will be
processed and appropriately recovered.
This patch adds error_detected callback and error processing.

Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/hisilicon/hns3/hnae3.h
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
drivers/net/ethernet/hisilicon/hns3/hns3pf/Makefile
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c [new file with mode: 0644]
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h [new file with mode: 0644]
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

index c3bd2a10bc7d3bccf2b83c2efee2d478e7f861e0..2af3a2dc72b22193d9bda308686a32b7b41ca740 100644 (file)
@@ -429,6 +429,7 @@ struct hnae3_ae_ops {
                                struct ethtool_rxnfc *cmd, u32 *rule_locs);
        int (*restore_fd_rules)(struct hnae3_handle *handle);
        void (*enable_fd)(struct hnae3_handle *handle, bool enable);
+       pci_ers_result_t (*process_hw_error)(struct hnae3_ae_dev *ae_dev);
 };
 
 struct hnae3_dcb_ops {
index 76ce2f21178bfe3d13824cd3d0404b4da641650f..3c6fa39831e3068a49c82706657068644df13603 100644 (file)
@@ -1771,6 +1771,35 @@ static void hns3_shutdown(struct pci_dev *pdev)
                pci_set_power_state(pdev, PCI_D3hot);
 }
 
+static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
+                                           pci_channel_state_t state)
+{
+       struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
+       pci_ers_result_t ret;
+
+       dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
+
+       if (state == pci_channel_io_perm_failure)
+               return PCI_ERS_RESULT_DISCONNECT;
+
+       if (!ae_dev) {
+               dev_err(&pdev->dev,
+                       "Can't recover - error happened during device init\n");
+               return PCI_ERS_RESULT_NONE;
+       }
+
+       if (ae_dev->ops->process_hw_error)
+               ret = ae_dev->ops->process_hw_error(ae_dev);
+       else
+               return PCI_ERS_RESULT_NONE;
+
+       return ret;
+}
+
+static const struct pci_error_handlers hns3_err_handler = {
+       .error_detected = hns3_error_detected,
+};
+
 static struct pci_driver hns3_driver = {
        .name     = hns3_driver_name,
        .id_table = hns3_pci_tbl,
@@ -1778,6 +1807,7 @@ static struct pci_driver hns3_driver = {
        .remove   = hns3_remove,
        .shutdown = hns3_shutdown,
        .sriov_configure = hns3_pci_sriov_configure,
+       .err_handler    = &hns3_err_handler,
 };
 
 /* set default feature to hns3 */
index cb8ddd04347686ac436b1f3b8acfc155cf4db685..580e81743681a24b8f1883265bcf03bc07148279 100644 (file)
@@ -6,6 +6,6 @@
 ccflags-y := -Idrivers/net/ethernet/hisilicon/hns3
 
 obj-$(CONFIG_HNS3_HCLGE) += hclge.o
-hclge-objs = hclge_main.o hclge_cmd.o hclge_mdio.o hclge_tm.o hclge_mbx.o
+hclge-objs = hclge_main.o hclge_cmd.o hclge_mdio.o hclge_tm.o hclge_mbx.o hclge_err.o
 
 hclge-$(CONFIG_HNS3_DCB) += hclge_dcb.o
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
new file mode 100644 (file)
index 0000000..83aca6f
--- /dev/null
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2016-2017 Hisilicon Limited. */
+
+#include "hclge_err.h"
+
+static const struct hclge_hw_blk hw_blk[] = {
+       { /* sentinel */ }
+};
+
+pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev)
+{
+       struct hclge_dev *hdev = ae_dev->priv;
+       struct device *dev = &hdev->pdev->dev;
+       u32 sts, val;
+       int i = 0;
+
+       sts = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG);
+
+       /* Processing Non-fatal errors */
+       if (sts & HCLGE_RAS_REG_NFE_MASK) {
+               val = (sts >> HCLGE_RAS_REG_NFE_SHIFT) & 0xFF;
+               i = 0;
+               while (hw_blk[i].name) {
+                       if (!(hw_blk[i].msk & val)) {
+                               i++;
+                               continue;
+                       }
+                       dev_warn(dev, "%s ras non-fatal error identified\n",
+                                hw_blk[i].name);
+                       if (hw_blk[i].process_error)
+                               hw_blk[i].process_error(hdev,
+                                                        HCLGE_ERR_INT_RAS_NFE);
+                       i++;
+               }
+       }
+
+       return PCI_ERS_RESULT_NEED_RESET;
+}
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
new file mode 100644 (file)
index 0000000..ea1637c
--- /dev/null
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*  Copyright (c) 2016-2017 Hisilicon Limited. */
+
+#ifndef __HCLGE_ERR_H
+#define __HCLGE_ERR_H
+
+#include "hclge_main.h"
+
+#define HCLGE_RAS_PF_OTHER_INT_STS_REG   0x20B00
+#define HCLGE_RAS_REG_FE_MASK    0xFF
+#define HCLGE_RAS_REG_NFE_MASK   0xFF00
+#define HCLGE_RAS_REG_NFE_SHIFT        8
+
+enum hclge_err_int_type {
+       HCLGE_ERR_INT_MSIX = 0,
+       HCLGE_ERR_INT_RAS_CE = 1,
+       HCLGE_ERR_INT_RAS_NFE = 2,
+       HCLGE_ERR_INT_RAS_FE = 3,
+};
+
+struct hclge_hw_blk {
+       u32 msk;
+       const char *name;
+       void (*process_error)(struct hclge_dev *hdev,
+                             enum hclge_err_int_type type);
+};
+
+pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev);
+#endif
index 1bd83e8268fc606159edf51b6629b0c5729db28b..94d36787b4c9543e5c7ed3895dea37fac92005ca 100644 (file)
@@ -19,6 +19,7 @@
 #include "hclge_mbx.h"
 #include "hclge_mdio.h"
 #include "hclge_tm.h"
+#include "hclge_err.h"
 #include "hnae3.h"
 
 #define HCLGE_NAME                     "hclge"
@@ -7312,6 +7313,7 @@ static const struct hnae3_ae_ops hclge_ops = {
        .get_fd_all_rules = hclge_get_all_rules,
        .restore_fd_rules = hclge_restore_fd_entries,
        .enable_fd = hclge_enable_fd,
+       .process_hw_error = hclge_process_ras_hw_error,
 };
 
 static struct hnae3_ae_algo ae_algo = {