ARM: imx6: fix v7_invalidate_l1 by adding I-Cache invalidation

The recent suspend/resume and reset testing on imx6q discovers that
not only D-Cache but also I-Cache has random data and validity when
the core comes out of a power recycle.

This patch adds I-Cache invalidation into v7_invalidate_l1 to make
sure both D-Cache and I-Cache invalidated on power-up.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S
index 6229efbc70cbcb15d99c8d727db7c638282ea625..c844112061be2c7f01442d45eb54f064dfd9dfc1 100644 (file)
--- a/arch/arm/mach-imx/head-v7.S
+++ b/arch/arm/mach-imx/head-v7.S
@@ -33,6 +33,7 @@
  */
 ENTRY(v7_invalidate_l1)
        mov     r0, #0
+       mcr     p15, 0, r0, c7, c5, 0   @ invalidate I cache
        mcr     p15, 2, r0, c0, c0, 0
        mrc     p15, 1, r0, c0, c0, 0