Merge tag 'drm-intel-next-2012-04-23' of git://people.freedesktop.org/~danvet/drm...

Daniel Vetter writes:

A new drm-intel-next pull. Highlights:
- More gmbus patches from Daniel Kurtz, I think gmbus is now ready, all
 known issues fixed.
- Fencing cleanup and pipelined fencing removal from Chris.
- rc6 residency interface from Ben, useful for powertop.
- Cleanups and code reorg around the ringbuffer code (Ben&me).
- Use hw semaphores in the pageflip code from Ben.
- More vlv stuff from Jesse, unfortunately his vlv cpu is doa, so less
 merged than I've hoped for - we still have the unused function warning :(
- More hsw patches from Eugeni, again, not yet enabled fully.
- intel_pm.c refactoring from Eugeni.
- Ironlake sprite support from Chris.
- And various smaller improvements/fixes all over the place.

Note that this pull request also contains a backmerge of -rc3 to sort out
a few things in -next. I've also had to frob the shortlog a bit to exclude
anything that -rc3 brings in with this pull.

Regression wise we have a few strange bugs going on, but for all of them
closer inspection revealed that they've been pre-existing, just now
slightly more likely to be hit. And for most of them we have a patch
already. Otherwise QA has not reported any regressions, and I'm also not
aware of anything bad happening in 3.4.

* tag 'drm-intel-next-2012-04-23' of git://people.freedesktop.org/~danvet/drm-intel: (420 commits)
  drm/i915: rc6 residency (fix the fix)
  drm/i915/tv: fix open-coded ARRAY_SIZE.
  drm/i915: invalidate render cache on gen2
  drm/i915: Silence the change of LVDS sync polarity
  drm/i915: add generic power management initialization
  drm/i915: move clock gating functionality into intel_pm module
  drm/i915: move emon functionality into intel_pm module
  drm/i915: move drps, rps and rc6-related functions to intel_pm
  drm/i915: fix line breaks in intel_pm
  drm/i915: move watermarks settings into intel_pm module
  drm/i915: move fbc-related functionality into intel_pm module
  drm/i915: Refactor get_fence() to use the common fence writing routine
  drm/i915: Refactor fence clearing to use the common fence writing routine
  drm/i915: Refactor put_fence() to use the common fence writing routine
  drm/i915: Prepare to consolidate fence writing
  drm/i915: Remove the unsightly "optimisation" from flush_fence()
  drm/i915: Simplify fence finding
  drm/i915: Discard the unused obj->last_fenced_ring
  drm/i915: Remove unused ring->setup_seqno
  drm/i915: Remove fence pipelining
  ...

diff --combined drivers/gpu/drm/radeon/atombios_encoders.c
index 06b209b2e229e0351e8d4a66b81cb06a1032e5a6,2d39f9977e005dd2ba5f8e53930569dc461db109..b92a694caa0d8f6efdd3cb233411bf5fff9ae11e
--- 1/drivers/gpu/drm/radeon/atombios_encoders.c
--- 2/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@@ -230,6 -230,10 +230,10 @@@ atombios_dvo_setup(struct drm_encoder *
        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
                return;
  
+       /* some R4xx chips have the wrong frev */
+       if (rdev->family <= CHIP_RV410)
+               frev = 1;
+ 
        switch (frev) {
        case 1:
                switch (crev) {
@@@ -541,7 -545,7 +545,7 @@@ atombios_dig_encoder_setup(struct drm_e
                dp_clock = dig_connector->dp_clock;
                dp_lane_count = dig_connector->dp_lane_count;
                hpd_id = radeon_connector->hpd.hpd;
 -              /* bpc = connector->display_info.bpc; */
 +              bpc = radeon_get_monitor_bpc(connector);
        }
  
        /* no dig encoder assigned */
@@@ -1159,7 -1163,7 +1163,7 @@@ atombios_external_encoder_setup(struct 
                dp_lane_count = dig_connector->dp_lane_count;
                connector_object_id =
                        (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 -              /* bpc = connector->display_info.bpc; */
 +              bpc = radeon_get_monitor_bpc(connector);
        }
  
        memset(&args, 0, sizeof(args));

diff --combined drivers/gpu/drm/radeon/r600.c
index 8f84bd67ce7fcdc19411080ed13f6fb9719edd74,5b9b81c69b66e406bb4dc6de0a21d850afa8f39b..222245d0138a073efe7f7c72425f3a6d0ebecd94
--- 1/drivers/gpu/drm/radeon/r600.c
--- 2/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@@ -2839,7 -2839,7 +2839,7 @@@ void r600_rlc_stop(struct radeon_devic
                /* r7xx asics need to soft reset RLC before halting */
                WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
                RREG32(SRBM_SOFT_RESET);
-               udelay(15000);
+               mdelay(15);
                WREG32(SRBM_SOFT_RESET, 0);
                RREG32(SRBM_SOFT_RESET);
        }
@@@ -2968,15 -2968,6 +2968,15 @@@ static void r600_disable_interrupt_stat
                        WREG32(DC_HPD5_INT_CONTROL, tmp);
                        tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
                        WREG32(DC_HPD6_INT_CONTROL, tmp);
 +                      tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
 +                      WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
 +                      tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
 +                      WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
 +              } else {
 +                      tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
 +                      WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
 +                      tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
 +                      WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
                }
        } else {
                WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
@@@ -2987,10 -2978,6 +2987,10 @@@
                WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
                tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
                WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 +              tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
 +              WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
 +              tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
 +              WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
        }
  }
  
@@@ -3087,7 -3074,7 +3087,7 @@@ int r600_irq_set(struct radeon_device *
        u32 mode_int = 0;
        u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
        u32 grbm_int_cntl = 0;
 -      u32 hdmi1, hdmi2;
 +      u32 hdmi0, hdmi1;
        u32 d1grph = 0, d2grph = 0;
  
        if (!rdev->irq.installed) {
@@@ -3102,7 -3089,9 +3102,7 @@@
                return 0;
        }
  
 -      hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
        if (ASIC_IS_DCE3(rdev)) {
 -              hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
                hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
                hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
                hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
@@@ -3110,18 -3099,12 +3110,18 @@@
                if (ASIC_IS_DCE32(rdev)) {
                        hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
                        hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
 +                      hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
 +                      hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
 +              } else {
 +                      hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
 +                      hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
                }
        } else {
 -              hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
                hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
                hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
                hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
 +              hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
 +              hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
        }
  
        if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
@@@ -3163,13 -3146,13 +3163,13 @@@
                DRM_DEBUG("r600_irq_set: hpd 6\n");
                hpd6 |= DC_HPDx_INT_EN;
        }
 -      if (rdev->irq.hdmi[0]) {
 -              DRM_DEBUG("r600_irq_set: hdmi 1\n");
 -              hdmi1 |= R600_HDMI_INT_EN;
 +      if (rdev->irq.afmt[0]) {
 +              DRM_DEBUG("r600_irq_set: hdmi 0\n");
 +              hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
        }
 -      if (rdev->irq.hdmi[1]) {
 -              DRM_DEBUG("r600_irq_set: hdmi 2\n");
 -              hdmi2 |= R600_HDMI_INT_EN;
 +      if (rdev->irq.afmt[1]) {
 +              DRM_DEBUG("r600_irq_set: hdmi 0\n");
 +              hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
        }
        if (rdev->irq.gui_idle) {
                DRM_DEBUG("gui idle\n");
@@@ -3181,7 -3164,9 +3181,7 @@@
        WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
        WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
        WREG32(GRBM_INT_CNTL, grbm_int_cntl);
 -      WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
        if (ASIC_IS_DCE3(rdev)) {
 -              WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
                WREG32(DC_HPD1_INT_CONTROL, hpd1);
                WREG32(DC_HPD2_INT_CONTROL, hpd2);
                WREG32(DC_HPD3_INT_CONTROL, hpd3);
@@@ -3189,18 -3174,12 +3189,18 @@@
                if (ASIC_IS_DCE32(rdev)) {
                        WREG32(DC_HPD5_INT_CONTROL, hpd5);
                        WREG32(DC_HPD6_INT_CONTROL, hpd6);
 +                      WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
 +                      WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
 +              } else {
 +                      WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
 +                      WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
                }
        } else {
 -              WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
                WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
                WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
                WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
 +              WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
 +              WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
        }
  
        return 0;
@@@ -3214,19 -3193,10 +3214,19 @@@ static void r600_irq_ack(struct radeon_
                rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
                rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
                rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
 +              if (ASIC_IS_DCE32(rdev)) {
 +                      rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
 +                      rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
 +              } else {
 +                      rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
 +                      rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
 +              }
        } else {
                rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
                rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
                rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
 +              rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
 +              rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
        }
        rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
        rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
@@@ -3292,32 -3262,17 +3292,32 @@@
                        tmp |= DC_HPDx_INT_ACK;
                        WREG32(DC_HPD6_INT_CONTROL, tmp);
                }
 -      }
 -      if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
 -              WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
 -      }
 -      if (ASIC_IS_DCE3(rdev)) {
 -              if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
 -                      WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
 +              if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
 +                      tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
 +                      tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
 +                      WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
 +              }
 +              if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
 +                      tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
 +                      tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
 +                      WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
                }
        } else {
 -              if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
 -                      WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
 +              if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
 +                      tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
 +                      tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
 +                      WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
 +              }
 +              if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
 +                      if (ASIC_IS_DCE3(rdev)) {
 +                              tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
 +                              tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
 +                              WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
 +                      } else {
 +                              tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
 +                              tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
 +                              WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
 +                      }
                }
        }
  }
@@@ -3393,7 -3348,6 +3393,7 @@@ int r600_irq_process(struct radeon_devi
        u32 ring_index;
        unsigned long flags;
        bool queue_hotplug = false;
 +      bool queue_hdmi = false;
  
        if (!rdev->ih.enabled || rdev->shutdown)
                return IRQ_NONE;
@@@ -3529,26 -3483,9 +3529,26 @@@ restart_ih
                                break;
                        }
                        break;
 -              case 21: /* HDMI */
 -                      DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
 -                      r600_audio_schedule_polling(rdev);
 +              case 21: /* hdmi */
 +                      switch (src_data) {
 +                      case 4:
 +                              if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
 +                                      rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
 +                                      queue_hdmi = true;
 +                                      DRM_DEBUG("IH: HDMI0\n");
 +                              }
 +                              break;
 +                      case 5:
 +                              if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
 +                                      rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
 +                                      queue_hdmi = true;
 +                                      DRM_DEBUG("IH: HDMI1\n");
 +                              }
 +                              break;
 +                      default:
 +                              DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
 +                              break;
 +                      }
                        break;
                case 176: /* CP_INT in ring buffer */
                case 177: /* CP_INT in IB1 */
@@@ -3580,8 -3517,6 +3580,8 @@@
                goto restart_ih;
        if (queue_hotplug)
                schedule_work(&rdev->hotplug_work);
 +      if (queue_hdmi)
 +              schedule_work(&rdev->audio_work);
        rdev->ih.rptr = rptr;
        WREG32(IH_RB_RPTR, rdev->ih.rptr);
        spin_unlock_irqrestore(&rdev->ih.lock, flags);

diff --combined include/linux/vgaarb.h
index 759a25ba05396eab73a29554f1afce917cac7ec7,b572f80bdfd527d10a9793047c6d2f7c14f0d685..367ab18dccf7d2c9a97855557f51a6a7cd185d1c
--- 1/include/linux/vgaarb.h
--- 2/include/linux/vgaarb.h
+++ b/include/linux/vgaarb.h
@@@ -31,7 -31,6 +31,7 @@@
  #ifndef LINUX_VGA_H
  #define LINUX_VGA_H
  
 +#include <video/vga.h>
  
  /* Legacy VGA regions */
  #define VGA_RSRC_NONE        0x00
@@@ -48,6 -47,8 +48,8 @@@
   */
  #define VGA_DEFAULT_DEVICE     (NULL)
  
+ struct pci_dev;
+ 
  /* For use by clients */
  
  /**
@@@ -182,7 -183,6 +184,7 @@@ extern void vga_put(struct pci_dev *pde
  
  #ifndef __ARCH_HAS_VGA_DEFAULT_DEVICE
  extern struct pci_dev *vga_default_device(void);
 +extern void vga_set_default_device(struct pci_dev *pdev);
  #endif
  
  /**