gpio: grgpio: Do not use gc->pin2mask()

The pin2mask() accessor only shuffles BIT ORDER in big endian systems,
i.e. the bitstuffing is swizzled big endian so "bit 0" is bit 7 or
bit 15 or bit 31 or so.

The grgpio only uses big endian BYTE ORDER which will be taken car of
by the ->write_reg() callback.

Just use BIT(offset) to assign the bit.

Acked-by: Andreas Larsson <andreas@gaisler.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c
index 6544a16ab02e9b94f836d03e84757bc85a3ca711..e2fc561f4315a9abf84cd03cf87347ffacd346f5 100644 (file)
--- a/drivers/gpio/gpio-grgpio.c
+++ b/drivers/gpio/gpio-grgpio.c
@@ -35,6 +35,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/bitops.h>
 
 #define GRGPIO_MAX_NGPIO 32
 
@@ -96,12 +97,11 @@ static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
                             int val)
 {
        struct gpio_chip *gc = &priv->gc;
-       unsigned long mask = gc->pin2mask(gc, offset);
 
        if (val)
-               priv->imask |= mask;
+               priv->imask |= BIT(offset);
        else
-               priv->imask &= ~mask;
+               priv->imask &= ~BIT(offset);
        gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
 }