--- /dev/null
+* Microchip PIC32 GPIO devices (PIO).
+
+Required properties:
+ - compatible: "microchip,pic32mzda-gpio"
+ - reg: Base address and length for the device.
+ - interrupts: The port interrupt shared by all pins.
+ - gpio-controller: Marks the port as GPIO controller.
+ - #gpio-cells: Two. The first cell is the pin number and
+ the second cell is used to specify the gpio polarity as defined in
+ defined in <dt-bindings/gpio/gpio.h>:
+ 0 = GPIO_ACTIVE_HIGH
+ 1 = GPIO_ACTIVE_LOW
+ 2 = GPIO_OPEN_DRAIN
+ - interrupt-controller: Marks the device node as an interrupt controller.
+ - #interrupt-cells: Two. The first cell is the GPIO number and second cell
+ is used to specify the trigger type as defined in
+ <dt-bindings/interrupt-controller/irq.h>:
+ IRQ_TYPE_EDGE_RISING
+ IRQ_TYPE_EDGE_FALLING
+ IRQ_TYPE_EDGE_BOTH
+ - clocks: Clock specifier (see clock bindings for details).
+ - microchip,gpio-bank: Specifies which bank a controller owns.
+ - gpio-ranges: Interaction with the PINCTRL subsystem.
+
+Example:
+
+/* PORTA */
+gpio0: gpio0@1f860000 {
+ compatible = "microchip,pic32mzda-gpio";
+ reg = <0x1f860000 0x100>;
+ interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&PBCLK4>;
+ microchip,gpio-bank = <0>;
+ gpio-ranges = <&pic32_pinctrl 0 0 16>;
+};
+
+keys {
+ ...
+
+ button@sw1 {
+ label = "ESC";
+ linux,code = <1>;
+ gpios = <&gpio0 12 0>;
+ };
+};
"allwinner,sun9i-a80-r-pinctrl"
"allwinner,sun8i-a83t-pinctrl"
"allwinner,sun8i-h3-pinctrl"
+ "allwinner,sun8i-h3-r-pinctrl"
+ "allwinner,sun50i-a64-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.
--- /dev/null
+Broadcom Northstar2 IOMUX Controller
+
+The Northstar2 IOMUX controller supports group based mux configuration. There
+are some individual pins that support modifying the pinconf parameters.
+
+Required properties:
+
+- compatible:
+ Must be "brcm,ns2-pinmux"
+
+- reg:
+ Define the base and range of the I/O address space that contains the
+ Northstar2 IOMUX and pin configuration registers.
+
+Properties in sub nodes:
+
+- function:
+ The mux function to select
+
+- groups:
+ The list of groups to select with a given function
+
+- pins:
+ List of pin names to change configuration
+
+The generic properties bias-disable, bias-pull-down, bias-pull-up,
+drive-strength, slew-rate, input-enable, input-disable are supported
+for some individual pins listed at the end.
+
+For more details, refer to
+Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+For example:
+
+ pinctrl: pinctrl@6501d130 {
+ compatible = "brcm,ns2-pinmux";
+ reg = <0x6501d130 0x08>,
+ <0x660a0028 0x04>,
+ <0x660009b0 0x40>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_sel &uart3_rx &sdio0_d4>;
+
+ /* Select nand function */
+ nand_sel: nand_sel {
+ function = "nand";
+ groups = "nand_grp";
+ };
+
+ /* Pull up the uart3 rx pin */
+ uart3_rx: uart3_rx {
+ pins = "uart3_sin";
+ bias-pull-up;
+ };
+
+ /* Set the drive strength of sdio d4 pin */
+ sdio0_d4: sdio0_d4 {
+ pins = "sdio0_data4";
+ drive-strength = <8>;
+ };
+ };
+
+List of supported functions and groups in Northstar2:
+
+"nand": "nand_grp"
+
+"nor": "nor_data_grp", "nor_adv_grp", "nor_addr_0_3_grp", "nor_addr_4_5_grp",
+ "nor_addr_6_7_grp", "nor_addr_8_9_grp", "nor_addr_10_11_grp",
+ "nor_addr_12_15_grp"
+
+"gpio": "gpio_0_1_grp", "gpio_2_5_grp", "gpio_6_7_grp", "gpio_8_9_grp",
+ "gpio_10_11_grp", "gpio_12_13_grp", "gpio_14_17_grp", "gpio_18_19_grp",
+ "gpio_20_21_grp", "gpio_22_23_grp", "gpio_24_25_grp", "gpio_26_27_grp",
+ "gpio_28_29_grp", "gpio_30_31_grp"
+
+"pcie": "pcie_ab1_clk_wak_grp", "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp",
+ "pcie_b2_clk_wak_grp", "pcie_a2_clk_wak_grp"
+
+"uart0": "uart0_modem_grp", "uart0_rts_cts_grp", "uart0_in_out_grp"
+
+"uart1": "uart1_ext_clk_grp", "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp",
+ "uart1_rts_cts_grp", "uart1_in_out_grp"
+
+"uart2": "uart2_rts_cts_grp"
+
+"pwm": "pwm_0_grp", "pwm_1_grp", "pwm_2_grp", "pwm_3_grp"
+
+
+List of pins that support pinconf parameters:
+
+"qspi_wp", "qspi_hold", "qspi_cs", "qspi_sck", "uart3_sin", "uart3_sout",
+"qspi_mosi", "qspi_miso", "spi0_fss", "spi0_rxd", "spi0_txd", "spi0_sck",
+"spi1_fss", "spi1_rxd", "spi1_txd", "spi1_sck", "sdio0_data7",
+"sdio0_emmc_rst", "sdio0_led_on", "sdio0_wp", "sdio0_data3", "sdio0_data4",
+"sdio0_data5", "sdio0_data6", "sdio0_cmd", "sdio0_data0", "sdio0_data1",
+"sdio0_data2", "sdio1_led_on", "sdio1_wp", "sdio0_cd_l", "sdio0_clk",
+"sdio1_data5", "sdio1_data6", "sdio1_data7", "sdio1_emmc_rst", "sdio1_data1",
+"sdio1_data2", "sdio1_data3", "sdio1_data4", "sdio1_cd_l", "sdio1_clk",
+"sdio1_cmd", "sdio1_data0", "ext_mdio_0", "ext_mdc_0", "usb3_p1_vbus_ppc",
+"usb3_p1_overcurrent", "usb3_p0_vbus_ppc", "usb3_p0_overcurrent",
+"usb2_presence_indication", "usb2_vbus_present", "usb2_vbus_ppc",
+"usb2_overcurrent", "sata_led1", "sata_led0"
--- /dev/null
+* Microchip PIC32 Pin Controller
+
+Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
+../interrupt-controller/interrupts.txt for generic information regarding
+pin controller, GPIO, and interrupt bindings.
+
+PIC32 'pin configuration node' is a node of a group of pins which can be
+used for a specific device or function. This node represents configuraions of
+pins, optional function, and optional mux related configuration.
+
+Required properties for pin controller node:
+ - compatible: "microchip,pic32mada-pinctrl"
+ - reg: Address range of the pinctrl registers.
+ - clocks: Clock specifier (see clock bindings for details)
+
+Required properties for pin configuration sub-nodes:
+ - pins: List of pins to which the configuration applies.
+
+Optional properties for pin configuration sub-nodes:
+----------------------------------------------------
+ - function: Mux function for the specified pins.
+ - bias-pull-up: Enable weak pull-up.
+ - bias-pull-down: Enable weak pull-down.
+ - input-enable: Set the pin as an input.
+ - output-low: Set the pin as an output level low.
+ - output-high: Set the pin as an output level high.
+ - microchip,digital: Enable digital I/O.
+ - microchip,analog: Enable analog I/O.
+
+Example:
+
+pic32_pinctrl: pinctrl@1f801400{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "microchip,pic32mzda-pinctrl";
+ reg = <0x1f801400 0x400>;
+ clocks = <&PBCLK1>;
+
+ pinctrl_uart2: pinctrl_uart2 {
+ uart2-tx {
+ pins = "G9";
+ function = "U2TX";
+ microchip,digital;
+ output-low;
+ };
+ uart2-rx {
+ pins = "B0";
+ function = "U2RX";
+ microchip,digital;
+ input-enable;
+ };
+ };
+};
+
+uart2: serial@1f822200 {
+ compatible = "microchip,pic32mzda-uart";
+ reg = <0x1f822200 0x50>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+};
- input-schmitt-disable
- slew-rate
+NXP specific properties:
+ - nxp,gpio-pin-interrupt : Assign pin to gpio pin interrupt controller
+ irq number 0 to 7. See example below.
+
Not all pins support all properties so either refer to the NXP 1850/4350
user manual or the pin table in the pinctrl-lpc18xx driver for supported
pin properties.
bias-disable;
};
};
+
+ gpio_joystick_pins: gpio-joystick-pins {
+ gpio_joystick_1_cfg {
+ pins = "p9_0";
+ function = "gpio";
+ nxp,gpio-pin-interrupt = <0>;
+ input-enable;
+ bias-disable;
+ };
+ };
};
- compatible: value should be one of the following.
"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
+ "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
--- /dev/null
+Qualcomm Atheros IPQ4019 TLMM block
+
+This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
+platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
+
+Required properties:
+- compatible: "qcom,ipq4019-pinctrl"
+- reg: Should be the base address and length of the TLMM block.
+- interrupts: Should be the parent IRQ of the TLMM block.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be two.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells : Should be two.
+ The first cell is the gpio pin number and the
+ second cell is used for optional parameters.
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+ pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.
+
+Non-empty subnodes must specify the 'pins' property.
+Note that not all properties are valid for all pins.
+
+
+Valid values for qcom,pins are:
+ gpio0-gpio99
+ Supports mux, bias and drive-strength
+
+Valid values for qcom,function are:
+gpio, blsp_uart1, blsp_i2c0, blsp_i2c1, blsp_uart0, blsp_spi1, blsp_spi0
+
+Example:
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq4019-pinctrl";
+ reg = <0x1000000 0x300000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 208 0>;
+
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+ };
- compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
"rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
"rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl"
- "rockchip,rk3368-pinctrl"
+ "rockchip,rk3368-pinctrl", "rockchip,rk3399-pinctrl"
- rockchip,grf: phandle referencing a syscon providing the
"general register files"
--- /dev/null
+* STM32 GPIO and Pin Mux/Config controller
+
+STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
+controller. It controls the input/output settings on the available pins and
+also provides ability to multiplex and configure the output of various on-chip
+controllers onto these pads.
+
+Pin controller node:
+Required properies:
+ - compatible: value should be one of the following:
+ (a) "st,stm32f429-pinctrl"
+ - #address-cells: The value of this property must be 1
+ - #size-cells : The value of this property must be 1
+ - ranges : defines mapping between pin controller node (parent) to
+ gpio-bank node (children).
+ - pins-are-numbered: Specify the subnodes are using numbered pinmux to
+ specify pins.
+
+GPIO controller/bank node:
+Required properties:
+ - gpio-controller : Indicates this device is a GPIO controller
+ - #gpio-cells : Should be two.
+ The first cell is the pin number
+ The second one is the polarity:
+ - 0 for active high
+ - 1 for active low
+ - reg : The gpio address range, relative to the pinctrl range
+ - clocks : clock that drives this bank
+ - st,bank-name : Should be a name string for this bank as specified in
+ the datasheet
+
+Optional properties:
+ - reset: : Reference to the reset controller
+
+Example:
+#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
+...
+
+ pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32f429-pinctrl";
+ ranges = <0 0x40020000 0x3000>;
+ pins-are-numbered;
+
+ gpioa: gpio@40020000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x400>;
+ resets = <&reset_ahb1 0>;
+ st,bank-name = "GPIOA";
+ };
+ ...
+ pin-functions nodes follow...
+ };
+
+Contents of function subnode node:
+----------------------------------
+Subnode format
+A pinctrl node should contain at least one subnode representing the
+pinctrl group available on the machine. Each subnode will list the
+pins it needs, and how they should be configured, with regard to muxer
+configuration, pullups, drive, output high/low and output speed.
+
+ node {
+ pinmux = <PIN_NUMBER_PINMUX>;
+ GENERIC_PINCONFIG;
+ };
+
+Required properties:
+- pinmux: integer array, represents gpio pin number and mux setting.
+ Supported pin number and mux varies for different SoCs, and are defined in
+ dt-bindings/pinctrl/<soc>-pinfunc.h directly.
+ These defines are calculated as:
+ ((port * 16 + line) << 8) | function
+ With:
+ - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
+ - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
+ - function: The function number, can be:
+ * 0 : GPIO
+ * 1 : Alternate Function 0
+ * 2 : Alternate Function 1
+ * 3 : Alternate Function 2
+ * ...
+ * 16 : Alternate Function 15
+ * 17 : Analog
+
+Optional properties:
+- GENERIC_PINCONFIG: is the generic pinconfig options to use.
+ Available options are:
+ - bias-disable,
+ - bias-pull-down,
+ - bias-pull-up,
+ - drive-push-pull,
+ - drive-open-drain,
+ - output-low
+ - output-high
+ - slew-rate = <x>, with x being:
+ < 0 > : Low speed
+ < 1 > : Medium speed
+ < 2 > : Fast speed
+ < 3 > : High speed
+
+Example:
+
+pin-controller {
+...
+ usart1_pins_a: usart1@0 {
+ pins1 {
+ pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
+ bias-disable;
+ };
+ };
+};
+
+&usart1 {
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Biao Huang <biao.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DTS_MT2701_PINFUNC_H
+#define __DTS_MT2701_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
+#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)
+
+#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
+#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)
+
+#define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)
+
+#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)
+
+#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)
+
+#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
+#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5)
+
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5)
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7)
+
+#define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
+#define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4)
+#define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7)
+
+#define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
+#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
+#define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4)
+#define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7)
+
+#define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
+#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
+#define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
+#define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4)
+#define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7)
+
+#define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
+
+#define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)
+
+#define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)
+
+#define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)
+
+#define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1)
+#define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
+#define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5)
+#define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7)
+
+#define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
+#define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2)
+#define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7)
+
+#define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
+#define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2)
+#define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4)
+#define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5)
+#define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6)
+#define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7)
+
+#define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7)
+
+#define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
+#define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2)
+#define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3)
+#define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
+#define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5)
+#define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6)
+#define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7)
+
+#define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
+#define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2)
+#define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3)
+#define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
+#define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5)
+#define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6)
+#define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7)
+
+#define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
+#define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3)
+#define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4)
+#define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5)
+#define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7)
+#define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10)
+
+#define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1)
+#define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3)
+#define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4)
+#define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
+#define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7)
+#define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10)
+
+#define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
+#define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3)
+#define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4)
+#define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7)
+#define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10)
+
+#define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1)
+#define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3)
+#define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4)
+#define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7)
+
+#define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
+#define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2)
+#define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3)
+#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4)
+#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5)
+#define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
+#define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7)
+
+#define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1)
+#define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2)
+#define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3)
+#define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4)
+#define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
+#define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7)
+
+#define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
+#define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3)
+#define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4)
+#define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
+#define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7)
+
+#define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1)
+#define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
+#define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3)
+#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4)
+#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5)
+#define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7)
+#define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14)
+
+#define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7)
+
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7)
+
+#define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7)
+
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7)
+
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5)
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7)
+
+#define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1)
+#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2)
+#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3)
+#define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4)
+
+#define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1)
+#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2)
+#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3)
+#define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4)
+
+#define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1)
+#define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2)
+#define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4)
+
+#define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1)
+#define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2)
+#define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4)
+
+#define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1)
+#define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)
+
+#define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
+#define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2)
+
+#define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
+#define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)
+
+#define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1)
+
+#define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1)
+#define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2)
+
+#define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1)
+#define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2)
+
+#define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7)
+
+#define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7)
+
+#define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
+#define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3)
+#define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4)
+#define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7)
+
+#define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
+#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
+#define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
+#define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4)
+#define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5)
+#define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7)
+
+#define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
+#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
+#define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3)
+#define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7)
+
+#define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1)
+
+#define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1)
+
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7)
+
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7)
+
+#define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7)
+
+#define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1)
+
+#define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1)
+
+#define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1)
+
+#define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1)
+
+#define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1)
+#define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2)
+#define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5)
+
+#define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1)
+#define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2)
+
+#define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1)
+#define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2)
+
+#define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1)
+#define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2)
+
+#define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
+#define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2)
+#define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7)
+
+#define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
+#define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7)
+
+#define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0)
+#define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1)
+
+#define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)
+#define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1)
+
+#define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0)
+#define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1)
+
+#define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0)
+#define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1)
+
+#define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0)
+#define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1)
+
+#define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0)
+#define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1)
+
+#define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0)
+#define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1)
+
+#define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0)
+#define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1)
+
+#define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0)
+#define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1)
+
+#define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0)
+#define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1)
+
+#define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1)
+#define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3)
+#define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4)
+
+#define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1)
+#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2)
+#define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3)
+#define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4)
+
+#define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1)
+#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2)
+#define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3)
+#define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4)
+
+#define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1)
+#define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3)
+#define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4)
+
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7)
+
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7)
+
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7)
+
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7)
+
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7)
+
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7)
+
+#define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
+#define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4)
+
+#define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
+#define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4)
+
+#define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
+#define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4)
+
+#define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
+#define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4)
+
+#define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
+#define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4)
+
+#define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
+#define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4)
+
+#define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
+#define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4)
+
+#define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
+#define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4)
+
+#define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
+#define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4)
+
+#define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
+#define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4)
+
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4)
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
+
+#define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1)
+#define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4)
+#define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5)
+
+#define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1)
+#define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4)
+#define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
+
+#define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1)
+#define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4)
+#define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5)
+
+#define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1)
+#define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4)
+#define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5)
+
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6)
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7)
+
+#define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7)
+
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7)
+
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7)
+
+#define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
+#define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1)
+
+#define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
+#define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1)
+#define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
+#define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5)
+#define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7)
+#define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9)
+
+#define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
+#define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1)
+#define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2)
+#define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5)
+#define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7)
+#define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9)
+
+#define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
+#define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1)
+#define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2)
+#define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5)
+#define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7)
+
+#define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
+#define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1)
+#define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2)
+#define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3)
+#define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5)
+#define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7)
+
+#define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
+#define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1)
+#define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2)
+#define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3)
+#define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5)
+#define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7)
+
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11)
+
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11)
+
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2)
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7)
+
+#define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
+#define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
+#define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)
+
+#define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
+#define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
+#define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2)
+
+#define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
+#define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
+#define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2)
+
+#define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
+#define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)
+
+#define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
+#define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)
+
+#define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
+#define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1)
+#define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
+#define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3)
+#define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4)
+#define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7)
+
+#define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
+#define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
+#define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2)
+#define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
+#define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4)
+#define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7)
+
+#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0)
+#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1)
+
+#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0)
+#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1)
+
+#define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0)
+
+#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0)
+#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1)
+
+#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0)
+#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1)
+
+#define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9)
+
+#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9)
+#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14)
+
+#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9)
+#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14)
+
+#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9)
+#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14)
+
+#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9)
+#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14)
+
+#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9)
+#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14)
+
+#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9)
+#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14)
+
+#define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9)
+
+#define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9)
+
+#define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9)
+
+#define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9)
+
+#define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9)
+
+#define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
+#define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
+#define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7)
+
+#define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
+#define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)
+
+#define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
+#define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
+#define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6)
+
+#define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
+#define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
+#define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6)
+
+#define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
+#define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
+#define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6)
+
+#define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
+#define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
+#define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6)
+
+#define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
+#define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1)
+
+#define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
+#define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1)
+
+#define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
+#define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)
+
+#define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
+#define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)
+
+#define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
+#define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)
+
+#define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
+#define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
+
+#define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
+#define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
+
+#define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
+#define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1)
+#define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6)
+
+#define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
+#define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1)
+#define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6)
+
+#define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
+#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
+
+#endif /* __DTS_MT2701_PINFUNC_H */
controller available on sama5d2 SoC.
config PINCTRL_AMD
- bool "AMD GPIO pin control"
+ tristate "AMD GPIO pin control"
depends on GPIOLIB
select GPIOLIB_IRQCHIP
select PINCONF
select PINCONF
select GPIOLIB_IRQCHIP
-config PINCTRL_TEGRA
- bool
- select PINMUX
- select PINCONF
-
-config PINCTRL_TEGRA20
- bool
- select PINCTRL_TEGRA
-
-config PINCTRL_TEGRA30
- bool
- select PINCTRL_TEGRA
-
-config PINCTRL_TEGRA114
- bool
- select PINCTRL_TEGRA
-
-config PINCTRL_TEGRA124
- bool
- select PINCTRL_TEGRA
-
-config PINCTRL_TEGRA210
- bool
- select PINCTRL_TEGRA
-
-config PINCTRL_TEGRA_XUSB
- def_bool y if ARCH_TEGRA
- select GENERIC_PHY
- select PINCONF
- select PINMUX
-
config PINCTRL_TZ1090
bool "Toumaz Xenif TZ1090 pin control driver"
depends on SOC_TZ1090
open drain configuration for the Palmas series devices like
TPS65913, TPS80036 etc.
+config PINCTRL_PIC32
+ bool "Microchip PIC32 pin controller driver"
+ depends on OF
+ depends on MACH_PIC32
+ select PINMUX
+ select GENERIC_PINCONF
+ select GPIOLIB_IRQCHIP
+ select OF_GPIO
+ help
+ This is the pin controller and gpio driver for Microchip PIC32
+ microcontrollers. This option is selected automatically when specific
+ machine and arch are selected to build.
+
+config PINCTRL_PIC32MZDA
+ def_bool y if PIC32MZDA
+ select PINCTRL_PIC32
+
config PINCTRL_ZYNQ
bool "Pinctrl driver for Xilinx Zynq"
depends on ARCH_ZYNQ
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/sh-pfc/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
+source "drivers/pinctrl/stm32/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
+source "drivers/pinctrl/tegra/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/vt8500/Kconfig"
source "drivers/pinctrl/mediatek/Kconfig"
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
obj-$(CONFIG_PINCTRL_MESON) += meson/
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
+obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
-obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
-obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
-obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
-obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
-obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o
-obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o
-obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o
+obj-$(CONFIG_PINCTRL_TEGRA) += tegra/
obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o
obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_X86) += intel/
obj-$(CONFIG_PINCTRL_MVEBU) += mvebu/
obj-y += nomadik/
-obj-$(CONFIG_ARCH_PXA) += pxa/
+obj-$(CONFIG_PINCTRL_PXA) += pxa/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
-obj-$(CONFIG_ARCH_SUNXI) += sunxi/
+obj-$(CONFIG_PINCTRL_STM32) += stm32/
+obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
obj-$(CONFIG_ARCH_VT8500) += vt8500/
-obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
+obj-$(CONFIG_PINCTRL_MTK) += mediatek/
}
if (num_pulls) {
err = of_property_read_u32_index(np, "brcm,pull",
- (num_funcs > 1) ? i : 0, &pull);
+ (num_pulls > 1) ? i : 0, &pull);
if (err)
goto out;
err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
}
EXPORT_SYMBOL_GPL(pinctrl_get_group_pins);
-/**
- * pinctrl_find_gpio_range_from_pin() - locate the GPIO range for a pin
- * @pctldev: the pin controller device to look in
- * @pin: a controller-local number to find the range for
- */
struct pinctrl_gpio_range *
-pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev,
- unsigned int pin)
+pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
+ unsigned int pin)
{
struct pinctrl_gpio_range *range;
- mutex_lock(&pctldev->mutex);
/* Loop over the ranges */
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
/* Check if we're in the valid range */
int a;
for (a = 0; a < range->npins; a++) {
if (range->pins[a] == pin)
- goto out;
+ return range;
}
} else if (pin >= range->pin_base &&
pin < range->pin_base + range->npins)
- goto out;
+ return range;
}
- range = NULL;
-out:
+
+ return NULL;
+}
+EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin_nolock);
+
+/**
+ * pinctrl_find_gpio_range_from_pin() - locate the GPIO range for a pin
+ * @pctldev: the pin controller device to look in
+ * @pin: a controller-local number to find the range for
+ */
+struct pinctrl_gpio_range *
+pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev,
+ unsigned int pin)
+{
+ struct pinctrl_gpio_range *range;
+
+ mutex_lock(&pctldev->mutex);
+ range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
mutex_unlock(&pctldev->mutex);
+
return range;
}
EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin);
return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
}
+extern struct pinctrl_gpio_range *
+pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
+ unsigned int pin);
+
int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
bool dup);
void pinctrl_unregister_map(struct pinctrl_map const *map);
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
+#include <linux/regmap.h>
#include "../core.h"
#include "pinctrl-imx.h"
return 0;
}
+static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range, unsigned offset)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg;
+ u32 reg;
+
+ /*
+ * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
+ * They are part of the shared mux/conf register.
+ */
+ if (!(info->flags & SHARE_MUX_CONF_REG))
+ return;
+
+ pin_reg = &info->pin_regs[offset];
+ if (pin_reg->mux_reg == -1)
+ return;
+
+ /* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */
+ reg = readl(ipctl->base + pin_reg->mux_reg);
+ reg &= ~0x7;
+ writel(reg, ipctl->base + pin_reg->mux_reg);
+}
+
static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset, bool input)
{
.get_function_groups = imx_pmx_get_groups,
.set_mux = imx_pmx_set,
.gpio_request_enable = imx_pmx_gpio_request_enable,
+ .gpio_disable_free = imx_pmx_gpio_disable_free,
.gpio_set_direction = imx_pmx_gpio_set_direction,
};
int imx_pinctrl_probe(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
+ struct regmap_config config = { .name = "gpr" };
struct device_node *dev_np = pdev->dev.of_node;
struct device_node *np;
struct imx_pinctrl *ipctl;
struct resource *res;
+ struct regmap *gpr;
int ret, i;
if (!info || !info->pins || !info->npins) {
}
info->dev = &pdev->dev;
+ if (info->gpr_compatible) {
+ gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
+ if (!IS_ERR(gpr))
+ regmap_attach_dev(&pdev->dev, gpr, &config);
+ }
+
/* Create state holders etc for this driver */
ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
if (!ipctl)
struct imx_pmx_func *functions;
unsigned int nfunctions;
unsigned int flags;
+ const char *gpr_compatible;
};
#define SHARE_MUX_CONF_REG 0x1
static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
.pins = imx50_pinctrl_pads,
.npins = ARRAY_SIZE(imx50_pinctrl_pads),
+ .gpr_compatible = "fsl,imx50-iomuxc-gpr",
};
static const struct of_device_id imx50_pinctrl_of_match[] = {
static struct imx_pinctrl_soc_info imx53_pinctrl_info = {
.pins = imx53_pinctrl_pads,
.npins = ARRAY_SIZE(imx53_pinctrl_pads),
+ .gpr_compatible = "fsl,imx53-iomuxc-gpr",
};
static const struct of_device_id imx53_pinctrl_of_match[] = {
static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
.pins = imx6dl_pinctrl_pads,
.npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
+ .gpr_compatible = "fsl,imx6q-iomuxc-gpr",
};
static const struct of_device_id imx6dl_pinctrl_of_match[] = {
static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
.pins = imx6q_pinctrl_pads,
.npins = ARRAY_SIZE(imx6q_pinctrl_pads),
+ .gpr_compatible = "fsl,imx6q-iomuxc-gpr",
};
static const struct of_device_id imx6q_pinctrl_of_match[] = {
static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
.pins = imx6sl_pinctrl_pads,
.npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
+ .gpr_compatible = "fsl,imx6sl-iomuxc-gpr",
};
static const struct of_device_id imx6sl_pinctrl_of_match[] = {
static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
.pins = imx6sx_pinctrl_pads,
.npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
+ .gpr_compatible = "fsl,imx6sx-iomuxc-gpr",
};
static const struct of_device_id imx6sx_pinctrl_of_match[] = {
static struct imx_pinctrl_soc_info imx6ul_pinctrl_info = {
.pins = imx6ul_pinctrl_pads,
.npins = ARRAY_SIZE(imx6ul_pinctrl_pads),
+ .gpr_compatible = "fsl,imx6ul-iomuxc-gpr",
};
static struct of_device_id imx6ul_pinctrl_of_match[] = {
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
+ .gpr_compatible = "fsl,imx7d-iomuxc-gpr",
};
static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
*/
#include <linux/module.h>
-#include <linux/init.h>
#include <linux/interrupt.h>
-#include <linux/acpi.h>
-#include <linux/gpio.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
-#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
if ARCH_MEDIATEK || COMPILE_TEST
-config PINCTRL_MTK_COMMON
+config PINCTRL_MTK
bool
depends on OF
select PINMUX
select OF_GPIO
# For ARMv7 SoCs
+config PINCTRL_MT2701
+ bool "Mediatek MT2701 pin control" if COMPILE_TEST && !MACH_MT2701
+ depends on OF
+ default MACH_MT2701
+ select PINCTRL_MTK
+
+config PINCTRL_MT7623
+ bool "Mediatek MT7623 pin control" if COMPILE_TEST && !MACH_MT7623
+ depends on OF
+ default MACH_MT7623
+ select PINCTRL_MTK_COMMON
+
config PINCTRL_MT8135
bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
depends on OF
default MACH_MT8135
- select PINCTRL_MTK_COMMON
+ select PINCTRL_MTK
config PINCTRL_MT8127
bool "Mediatek MT8127 pin control" if COMPILE_TEST && !MACH_MT8127
depends on OF
default MACH_MT8127
- select PINCTRL_MTK_COMMON
+ select PINCTRL_MTK
# For ARMv8 SoCs
config PINCTRL_MT8173
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
- select PINCTRL_MTK_COMMON
+ select PINCTRL_MTK
# For PMIC
config PINCTRL_MT6397
bool "Mediatek MT6397 pin control" if COMPILE_TEST && !MFD_MT6397
depends on OF
default MFD_MT6397
- select PINCTRL_MTK_COMMON
+ select PINCTRL_MTK
endif
# Core
-obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o
+obj-y += pinctrl-mtk-common.o
# SoC Drivers
-obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
-obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
-obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
-obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o
+obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
+obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
+obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
+obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
+obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
+obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o
--- /dev/null
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Biao Huang <biao.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/regmap.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt2701.h"
+
+/**
+ * struct mtk_spec_pinmux_set
+ * - For special pins' mode setting
+ * @pin: The pin number.
+ * @offset: The offset of extra setting register.
+ * @bit: The bit of extra setting register.
+ */
+struct mtk_spec_pinmux_set {
+ unsigned short pin;
+ unsigned short offset;
+ unsigned char bit;
+};
+
+#define MTK_PINMUX_SPEC(_pin, _offset, _bit) \
+ { \
+ .pin = _pin, \
+ .offset = _offset, \
+ .bit = _bit, \
+ }
+
+static const struct mtk_drv_group_desc mt2701_drv_grp[] = {
+ /* 0E4E8SR 4/8/12/16 */
+ MTK_DRV_GRP(4, 16, 1, 2, 4),
+ /* 0E2E4SR 2/4/6/8 */
+ MTK_DRV_GRP(2, 8, 1, 2, 2),
+ /* E8E4E2 2/4/6/8/10/12/14/16 */
+ MTK_DRV_GRP(2, 16, 0, 2, 2)
+};
+
+static const struct mtk_pin_drv_grp mt2701_pin_drv[] = {
+ MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
+ MTK_PIN_DRV_GRP(7, 0xf50, 4, 1),
+ MTK_PIN_DRV_GRP(8, 0xf50, 4, 1),
+ MTK_PIN_DRV_GRP(9, 0xf50, 4, 1),
+ MTK_PIN_DRV_GRP(10, 0xf50, 8, 1),
+ MTK_PIN_DRV_GRP(11, 0xf50, 8, 1),
+ MTK_PIN_DRV_GRP(12, 0xf50, 8, 1),
+ MTK_PIN_DRV_GRP(13, 0xf50, 8, 1),
+ MTK_PIN_DRV_GRP(14, 0xf50, 12, 0),
+ MTK_PIN_DRV_GRP(15, 0xf50, 12, 0),
+ MTK_PIN_DRV_GRP(16, 0xf60, 0, 0),
+ MTK_PIN_DRV_GRP(17, 0xf60, 0, 0),
+ MTK_PIN_DRV_GRP(18, 0xf60, 4, 0),
+ MTK_PIN_DRV_GRP(19, 0xf60, 4, 0),
+ MTK_PIN_DRV_GRP(20, 0xf60, 4, 0),
+ MTK_PIN_DRV_GRP(21, 0xf60, 4, 0),
+ MTK_PIN_DRV_GRP(22, 0xf60, 8, 0),
+ MTK_PIN_DRV_GRP(23, 0xf60, 8, 0),
+ MTK_PIN_DRV_GRP(24, 0xf60, 8, 0),
+ MTK_PIN_DRV_GRP(25, 0xf60, 8, 0),
+ MTK_PIN_DRV_GRP(26, 0xf60, 8, 0),
+ MTK_PIN_DRV_GRP(27, 0xf60, 12, 0),
+ MTK_PIN_DRV_GRP(28, 0xf60, 12, 0),
+ MTK_PIN_DRV_GRP(29, 0xf60, 12, 0),
+ MTK_PIN_DRV_GRP(30, 0xf60, 0, 0),
+ MTK_PIN_DRV_GRP(31, 0xf60, 0, 0),
+ MTK_PIN_DRV_GRP(32, 0xf60, 0, 0),
+ MTK_PIN_DRV_GRP(33, 0xf70, 0, 0),
+ MTK_PIN_DRV_GRP(34, 0xf70, 0, 0),
+ MTK_PIN_DRV_GRP(35, 0xf70, 0, 0),
+ MTK_PIN_DRV_GRP(36, 0xf70, 0, 0),
+ MTK_PIN_DRV_GRP(37, 0xf70, 0, 0),
+ MTK_PIN_DRV_GRP(38, 0xf70, 4, 0),
+ MTK_PIN_DRV_GRP(39, 0xf70, 8, 1),
+ MTK_PIN_DRV_GRP(40, 0xf70, 8, 1),
+ MTK_PIN_DRV_GRP(41, 0xf70, 8, 1),
+ MTK_PIN_DRV_GRP(42, 0xf70, 8, 1),
+ MTK_PIN_DRV_GRP(43, 0xf70, 12, 0),
+ MTK_PIN_DRV_GRP(44, 0xf70, 12, 0),
+ MTK_PIN_DRV_GRP(45, 0xf70, 12, 0),
+ MTK_PIN_DRV_GRP(47, 0xf80, 0, 0),
+ MTK_PIN_DRV_GRP(48, 0xf80, 0, 0),
+ MTK_PIN_DRV_GRP(49, 0xf80, 4, 0),
+ MTK_PIN_DRV_GRP(50, 0xf70, 4, 0),
+ MTK_PIN_DRV_GRP(51, 0xf70, 4, 0),
+ MTK_PIN_DRV_GRP(52, 0xf70, 4, 0),
+ MTK_PIN_DRV_GRP(53, 0xf80, 12, 0),
+ MTK_PIN_DRV_GRP(54, 0xf80, 12, 0),
+ MTK_PIN_DRV_GRP(55, 0xf80, 12, 0),
+ MTK_PIN_DRV_GRP(56, 0xf80, 12, 0),
+ MTK_PIN_DRV_GRP(60, 0xf90, 8, 1),
+ MTK_PIN_DRV_GRP(61, 0xf90, 8, 1),
+ MTK_PIN_DRV_GRP(62, 0xf90, 8, 1),
+ MTK_PIN_DRV_GRP(63, 0xf90, 12, 1),
+ MTK_PIN_DRV_GRP(64, 0xf90, 12, 1),
+ MTK_PIN_DRV_GRP(65, 0xf90, 12, 1),
+ MTK_PIN_DRV_GRP(66, 0xfa0, 0, 1),
+ MTK_PIN_DRV_GRP(67, 0xfa0, 0, 1),
+ MTK_PIN_DRV_GRP(68, 0xfa0, 0, 1),
+ MTK_PIN_DRV_GRP(69, 0xfa0, 0, 1),
+ MTK_PIN_DRV_GRP(70, 0xfa0, 0, 1),
+ MTK_PIN_DRV_GRP(71, 0xfa0, 0, 1),
+ MTK_PIN_DRV_GRP(72, 0xf80, 4, 0),
+ MTK_PIN_DRV_GRP(73, 0xf80, 4, 0),
+ MTK_PIN_DRV_GRP(74, 0xf80, 4, 0),
+ MTK_PIN_DRV_GRP(85, 0xda0, 0, 2),
+ MTK_PIN_DRV_GRP(86, 0xd90, 0, 2),
+ MTK_PIN_DRV_GRP(87, 0xdb0, 0, 2),
+ MTK_PIN_DRV_GRP(88, 0xdb0, 0, 2),
+ MTK_PIN_DRV_GRP(89, 0xdb0, 0, 2),
+ MTK_PIN_DRV_GRP(90, 0xdb0, 0, 2),
+ MTK_PIN_DRV_GRP(105, 0xd40, 0, 2),
+ MTK_PIN_DRV_GRP(106, 0xd30, 0, 2),
+ MTK_PIN_DRV_GRP(107, 0xd50, 0, 2),
+ MTK_PIN_DRV_GRP(108, 0xd50, 0, 2),
+ MTK_PIN_DRV_GRP(109, 0xd50, 0, 2),
+ MTK_PIN_DRV_GRP(110, 0xd50, 0, 2),
+ MTK_PIN_DRV_GRP(111, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(112, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(113, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(114, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(115, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(116, 0xcd0, 0, 2),
+ MTK_PIN_DRV_GRP(117, 0xcc0, 0, 2),
+ MTK_PIN_DRV_GRP(118, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(119, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(120, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(121, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(126, 0xf80, 4, 0),
+ MTK_PIN_DRV_GRP(188, 0xf70, 4, 0),
+ MTK_PIN_DRV_GRP(189, 0xfe0, 8, 0),
+ MTK_PIN_DRV_GRP(190, 0xfe0, 8, 0),
+ MTK_PIN_DRV_GRP(191, 0xfe0, 8, 0),
+ MTK_PIN_DRV_GRP(192, 0xfe0, 8, 0),
+ MTK_PIN_DRV_GRP(193, 0xfe0, 8, 0),
+ MTK_PIN_DRV_GRP(194, 0xfe0, 12, 0),
+ MTK_PIN_DRV_GRP(195, 0xfe0, 12, 0),
+ MTK_PIN_DRV_GRP(196, 0xfe0, 12, 0),
+ MTK_PIN_DRV_GRP(197, 0xfe0, 12, 0),
+ MTK_PIN_DRV_GRP(198, 0xfe0, 12, 0),
+ MTK_PIN_DRV_GRP(199, 0xf50, 4, 1),
+ MTK_PIN_DRV_GRP(200, 0xfd0, 0, 0),
+ MTK_PIN_DRV_GRP(201, 0xfd0, 0, 0),
+ MTK_PIN_DRV_GRP(202, 0xfd0, 0, 0),
+ MTK_PIN_DRV_GRP(203, 0xfd0, 4, 0),
+ MTK_PIN_DRV_GRP(204, 0xfd0, 4, 0),
+ MTK_PIN_DRV_GRP(205, 0xfd0, 4, 0),
+ MTK_PIN_DRV_GRP(206, 0xfd0, 4, 0),
+ MTK_PIN_DRV_GRP(207, 0xfd0, 4, 0),
+ MTK_PIN_DRV_GRP(208, 0xfd0, 8, 0),
+ MTK_PIN_DRV_GRP(209, 0xfd0, 8, 0),
+ MTK_PIN_DRV_GRP(210, 0xfd0, 12, 1),
+ MTK_PIN_DRV_GRP(211, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(212, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(213, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(214, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(215, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(216, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(217, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(218, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(219, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(220, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(221, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(222, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(223, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(224, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(225, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(226, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(227, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(228, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(229, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(230, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(231, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(232, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(233, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(234, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(235, 0xff0, 0, 1),
+ MTK_PIN_DRV_GRP(236, 0xff0, 4, 0),
+ MTK_PIN_DRV_GRP(237, 0xff0, 4, 0),
+ MTK_PIN_DRV_GRP(238, 0xff0, 4, 0),
+ MTK_PIN_DRV_GRP(239, 0xff0, 4, 0),
+ MTK_PIN_DRV_GRP(240, 0xff0, 4, 0),
+ MTK_PIN_DRV_GRP(241, 0xff0, 4, 0),
+ MTK_PIN_DRV_GRP(242, 0xff0, 8, 0),
+ MTK_PIN_DRV_GRP(243, 0xff0, 8, 0),
+ MTK_PIN_DRV_GRP(248, 0xf00, 0, 0),
+ MTK_PIN_DRV_GRP(249, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(250, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(251, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(252, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(253, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(254, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(255, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(256, 0xfc0, 0, 2),
+ MTK_PIN_DRV_GRP(257, 0xce0, 0, 2),
+ MTK_PIN_DRV_GRP(258, 0xcb0, 0, 2),
+ MTK_PIN_DRV_GRP(259, 0xc90, 0, 2),
+ MTK_PIN_DRV_GRP(260, 0x3a0, 0, 2),
+ MTK_PIN_DRV_GRP(261, 0xd50, 0, 2),
+ MTK_PIN_DRV_GRP(262, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(263, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(264, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(265, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(266, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(267, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(268, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(269, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(270, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(271, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(272, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(273, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(274, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(275, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(276, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(277, 0xf00, 8, 0),
+ MTK_PIN_DRV_GRP(278, 0xf70, 8, 1),
+};
+
+static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = {
+ MTK_PIN_PUPD_SPEC_SR(111, 0xd00, 12, 13, 14), /* ms0 data7 */
+ MTK_PIN_PUPD_SPEC_SR(112, 0xd00, 8, 9, 10), /* ms0 data6 */
+ MTK_PIN_PUPD_SPEC_SR(113, 0xd00, 4, 5, 6), /* ms0 data5 */
+ MTK_PIN_PUPD_SPEC_SR(114, 0xd00, 0, 1, 2), /* ms0 data4 */
+ MTK_PIN_PUPD_SPEC_SR(115, 0xd10, 0, 1, 2), /* ms0 rstb */
+ MTK_PIN_PUPD_SPEC_SR(116, 0xcd0, 8, 9, 10), /* ms0 cmd */
+ MTK_PIN_PUPD_SPEC_SR(117, 0xcc0, 8, 9, 10), /* ms0 clk */
+ MTK_PIN_PUPD_SPEC_SR(118, 0xcf0, 12, 13, 14), /* ms0 data3 */
+ MTK_PIN_PUPD_SPEC_SR(119, 0xcf0, 8, 9, 10), /* ms0 data2 */
+ MTK_PIN_PUPD_SPEC_SR(120, 0xcf0, 4, 5, 6), /* ms0 data1 */
+ MTK_PIN_PUPD_SPEC_SR(121, 0xcf0, 0, 1, 2), /* ms0 data0 */
+
+ MTK_PIN_PUPD_SPEC_SR(105, 0xd40, 8, 9, 10), /* ms1 cmd */
+ MTK_PIN_PUPD_SPEC_SR(106, 0xd30, 8, 9, 10), /* ms1 clk */
+ MTK_PIN_PUPD_SPEC_SR(107, 0xd60, 0, 1, 2), /* ms1 dat0 */
+ MTK_PIN_PUPD_SPEC_SR(108, 0xd60, 10, 9, 8), /* ms1 dat1 */
+ MTK_PIN_PUPD_SPEC_SR(109, 0xd60, 4, 5, 6), /* ms1 dat2 */
+ MTK_PIN_PUPD_SPEC_SR(110, 0xc60, 12, 13, 14), /* ms1 dat3 */
+
+ MTK_PIN_PUPD_SPEC_SR(85, 0xda0, 8, 9, 10), /* ms2 cmd */
+ MTK_PIN_PUPD_SPEC_SR(86, 0xd90, 8, 9, 10), /* ms2 clk */
+ MTK_PIN_PUPD_SPEC_SR(87, 0xdc0, 0, 1, 2), /* ms2 dat0 */
+ MTK_PIN_PUPD_SPEC_SR(88, 0xdc0, 10, 9, 8), /* ms2 dat1 */
+ MTK_PIN_PUPD_SPEC_SR(89, 0xdc0, 4, 5, 6), /* ms2 dat2 */
+ MTK_PIN_PUPD_SPEC_SR(90, 0xdc0, 12, 13, 14), /* ms2 dat3 */
+
+ MTK_PIN_PUPD_SPEC_SR(249, 0x140, 0, 1, 2), /* ms0e rstb */
+ MTK_PIN_PUPD_SPEC_SR(250, 0x130, 12, 13, 14), /* ms0e dat7 */
+ MTK_PIN_PUPD_SPEC_SR(251, 0x130, 8, 9, 10), /* ms0e dat6 */
+ MTK_PIN_PUPD_SPEC_SR(252, 0x130, 4, 5, 6), /* ms0e dat5 */
+ MTK_PIN_PUPD_SPEC_SR(253, 0x130, 0, 1, 2), /* ms0e dat4 */
+ MTK_PIN_PUPD_SPEC_SR(254, 0xf40, 12, 13, 14), /* ms0e dat3 */
+ MTK_PIN_PUPD_SPEC_SR(255, 0xf40, 8, 9, 10), /* ms0e dat2 */
+ MTK_PIN_PUPD_SPEC_SR(256, 0xf40, 4, 5, 6), /* ms0e dat1 */
+ MTK_PIN_PUPD_SPEC_SR(257, 0xf40, 0, 1, 2), /* ms0e dat0 */
+ MTK_PIN_PUPD_SPEC_SR(258, 0xcb0, 8, 9, 10), /* ms0e cmd */
+ MTK_PIN_PUPD_SPEC_SR(259, 0xc90, 8, 9, 10), /* ms0e clk */
+ MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10), /* ms1 ins */
+};
+
+static int mt2701_spec_pull_set(struct regmap *regmap, unsigned int pin,
+ unsigned char align, bool isup, unsigned int r1r0)
+{
+ return mtk_pctrl_spec_pull_set_samereg(regmap, mt2701_spec_pupd,
+ ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0);
+}
+
+static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = {
+ MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0),
+ MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1),
+ MTK_PIN_IES_SMT_SPEC(10, 13, 0xb30, 3),
+ MTK_PIN_IES_SMT_SPEC(14, 15, 0xb30, 13),
+ MTK_PIN_IES_SMT_SPEC(16, 17, 0xb40, 7),
+ MTK_PIN_IES_SMT_SPEC(18, 21, 0xb40, 13),
+ MTK_PIN_IES_SMT_SPEC(22, 26, 0xb40, 13),
+ MTK_PIN_IES_SMT_SPEC(27, 29, 0xb40, 13),
+ MTK_PIN_IES_SMT_SPEC(30, 32, 0xb40, 7),
+ MTK_PIN_IES_SMT_SPEC(33, 37, 0xb40, 13),
+ MTK_PIN_IES_SMT_SPEC(38, 38, 0xb20, 13),
+ MTK_PIN_IES_SMT_SPEC(39, 42, 0xb40, 13),
+ MTK_PIN_IES_SMT_SPEC(43, 45, 0xb20, 10),
+ MTK_PIN_IES_SMT_SPEC(47, 48, 0xb20, 11),
+ MTK_PIN_IES_SMT_SPEC(49, 49, 0xb20, 12),
+ MTK_PIN_IES_SMT_SPEC(50, 52, 0xb20, 13),
+ MTK_PIN_IES_SMT_SPEC(53, 56, 0xb20, 14),
+ MTK_PIN_IES_SMT_SPEC(57, 58, 0xb20, 15),
+ MTK_PIN_IES_SMT_SPEC(59, 59, 0xb30, 10),
+ MTK_PIN_IES_SMT_SPEC(60, 62, 0xb30, 0),
+ MTK_PIN_IES_SMT_SPEC(63, 65, 0xb30, 1),
+ MTK_PIN_IES_SMT_SPEC(66, 71, 0xb30, 2),
+ MTK_PIN_IES_SMT_SPEC(72, 74, 0xb20, 12),
+ MTK_PIN_IES_SMT_SPEC(75, 76, 0xb30, 3),
+ MTK_PIN_IES_SMT_SPEC(77, 78, 0xb30, 4),
+ MTK_PIN_IES_SMT_SPEC(79, 82, 0xb30, 5),
+ MTK_PIN_IES_SMT_SPEC(83, 84, 0xb30, 2),
+ MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 4),
+ MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 4),
+ MTK_PIN_IES_SMT_SPEC(87, 90, 0xdb0, 4),
+ MTK_PIN_IES_SMT_SPEC(101, 104, 0xb30, 6),
+ MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 4),
+ MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 4),
+ MTK_PIN_IES_SMT_SPEC(107, 110, 0xd50, 4),
+ MTK_PIN_IES_SMT_SPEC(111, 115, 0xce0, 4),
+ MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 4),
+ MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 4),
+ MTK_PIN_IES_SMT_SPEC(118, 121, 0xce0, 4),
+ MTK_PIN_IES_SMT_SPEC(122, 125, 0xb30, 7),
+ MTK_PIN_IES_SMT_SPEC(126, 126, 0xb20, 12),
+ MTK_PIN_IES_SMT_SPEC(127, 142, 0xb30, 9),
+ MTK_PIN_IES_SMT_SPEC(143, 160, 0xb30, 10),
+ MTK_PIN_IES_SMT_SPEC(161, 168, 0xb30, 12),
+ MTK_PIN_IES_SMT_SPEC(169, 183, 0xb30, 10),
+ MTK_PIN_IES_SMT_SPEC(184, 186, 0xb30, 9),
+ MTK_PIN_IES_SMT_SPEC(187, 187, 0xb30, 14),
+ MTK_PIN_IES_SMT_SPEC(188, 188, 0xb20, 13),
+ MTK_PIN_IES_SMT_SPEC(189, 193, 0xb30, 15),
+ MTK_PIN_IES_SMT_SPEC(194, 198, 0xb40, 0),
+ MTK_PIN_IES_SMT_SPEC(199, 199, 0xb20, 1),
+ MTK_PIN_IES_SMT_SPEC(200, 202, 0xb40, 1),
+ MTK_PIN_IES_SMT_SPEC(203, 207, 0xb40, 2),
+ MTK_PIN_IES_SMT_SPEC(208, 209, 0xb40, 3),
+ MTK_PIN_IES_SMT_SPEC(210, 210, 0xb40, 4),
+ MTK_PIN_IES_SMT_SPEC(211, 235, 0xb40, 5),
+ MTK_PIN_IES_SMT_SPEC(236, 241, 0xb40, 6),
+ MTK_PIN_IES_SMT_SPEC(242, 243, 0xb40, 7),
+ MTK_PIN_IES_SMT_SPEC(244, 247, 0xb40, 8),
+ MTK_PIN_IES_SMT_SPEC(248, 248, 0xb40, 9),
+ MTK_PIN_IES_SMT_SPEC(249, 257, 0xfc0, 4),
+ MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 4),
+ MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 4),
+ MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 4),
+ MTK_PIN_IES_SMT_SPEC(261, 261, 0xd50, 4),
+ MTK_PIN_IES_SMT_SPEC(262, 277, 0xb40, 12),
+ MTK_PIN_IES_SMT_SPEC(278, 278, 0xb40, 13),
+};
+
+static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = {
+ MTK_PIN_IES_SMT_SPEC(0, 6, 0xb50, 0),
+ MTK_PIN_IES_SMT_SPEC(7, 9, 0xb50, 1),
+ MTK_PIN_IES_SMT_SPEC(10, 13, 0xb60, 3),
+ MTK_PIN_IES_SMT_SPEC(14, 15, 0xb60, 13),
+ MTK_PIN_IES_SMT_SPEC(16, 17, 0xb70, 7),
+ MTK_PIN_IES_SMT_SPEC(18, 21, 0xb70, 13),
+ MTK_PIN_IES_SMT_SPEC(22, 26, 0xb70, 13),
+ MTK_PIN_IES_SMT_SPEC(27, 29, 0xb70, 13),
+ MTK_PIN_IES_SMT_SPEC(30, 32, 0xb70, 7),
+ MTK_PIN_IES_SMT_SPEC(33, 37, 0xb70, 13),
+ MTK_PIN_IES_SMT_SPEC(38, 38, 0xb50, 13),
+ MTK_PIN_IES_SMT_SPEC(39, 42, 0xb70, 13),
+ MTK_PIN_IES_SMT_SPEC(43, 45, 0xb50, 10),
+ MTK_PIN_IES_SMT_SPEC(47, 48, 0xb50, 11),
+ MTK_PIN_IES_SMT_SPEC(49, 49, 0xb50, 12),
+ MTK_PIN_IES_SMT_SPEC(50, 52, 0xb50, 13),
+ MTK_PIN_IES_SMT_SPEC(53, 56, 0xb50, 14),
+ MTK_PIN_IES_SMT_SPEC(57, 58, 0xb50, 15),
+ MTK_PIN_IES_SMT_SPEC(59, 59, 0xb60, 10),
+ MTK_PIN_IES_SMT_SPEC(60, 62, 0xb60, 0),
+ MTK_PIN_IES_SMT_SPEC(63, 65, 0xb60, 1),
+ MTK_PIN_IES_SMT_SPEC(66, 71, 0xb60, 2),
+ MTK_PIN_IES_SMT_SPEC(72, 74, 0xb50, 12),
+ MTK_PIN_IES_SMT_SPEC(75, 76, 0xb60, 3),
+ MTK_PIN_IES_SMT_SPEC(77, 78, 0xb60, 4),
+ MTK_PIN_IES_SMT_SPEC(79, 82, 0xb60, 5),
+ MTK_PIN_IES_SMT_SPEC(83, 84, 0xb60, 2),
+ MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 11),
+ MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 11),
+ MTK_PIN_IES_SMT_SPEC(87, 87, 0xdc0, 3),
+ MTK_PIN_IES_SMT_SPEC(88, 88, 0xdc0, 7),
+ MTK_PIN_IES_SMT_SPEC(89, 89, 0xdc0, 11),
+ MTK_PIN_IES_SMT_SPEC(90, 90, 0xdc0, 15),
+ MTK_PIN_IES_SMT_SPEC(101, 104, 0xb60, 6),
+ MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 11),
+ MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 11),
+ MTK_PIN_IES_SMT_SPEC(107, 107, 0xd60, 3),
+ MTK_PIN_IES_SMT_SPEC(108, 108, 0xd60, 7),
+ MTK_PIN_IES_SMT_SPEC(109, 109, 0xd60, 11),
+ MTK_PIN_IES_SMT_SPEC(110, 110, 0xd60, 15),
+ MTK_PIN_IES_SMT_SPEC(111, 111, 0xd00, 15),
+ MTK_PIN_IES_SMT_SPEC(112, 112, 0xd00, 11),
+ MTK_PIN_IES_SMT_SPEC(113, 113, 0xd00, 7),
+ MTK_PIN_IES_SMT_SPEC(114, 114, 0xd00, 3),
+ MTK_PIN_IES_SMT_SPEC(115, 115, 0xd10, 3),
+ MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 11),
+ MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 11),
+ MTK_PIN_IES_SMT_SPEC(118, 118, 0xcf0, 15),
+ MTK_PIN_IES_SMT_SPEC(119, 119, 0xcf0, 11),
+ MTK_PIN_IES_SMT_SPEC(120, 120, 0xcf0, 7),
+ MTK_PIN_IES_SMT_SPEC(121, 121, 0xcf0, 3),
+ MTK_PIN_IES_SMT_SPEC(122, 125, 0xb60, 7),
+ MTK_PIN_IES_SMT_SPEC(126, 126, 0xb50, 12),
+ MTK_PIN_IES_SMT_SPEC(127, 142, 0xb60, 9),
+ MTK_PIN_IES_SMT_SPEC(143, 160, 0xb60, 10),
+ MTK_PIN_IES_SMT_SPEC(161, 168, 0xb60, 12),
+ MTK_PIN_IES_SMT_SPEC(169, 183, 0xb60, 10),
+ MTK_PIN_IES_SMT_SPEC(184, 186, 0xb60, 9),
+ MTK_PIN_IES_SMT_SPEC(187, 187, 0xb60, 14),
+ MTK_PIN_IES_SMT_SPEC(188, 188, 0xb50, 13),
+ MTK_PIN_IES_SMT_SPEC(189, 193, 0xb60, 15),
+ MTK_PIN_IES_SMT_SPEC(194, 198, 0xb70, 0),
+ MTK_PIN_IES_SMT_SPEC(199, 199, 0xb50, 1),
+ MTK_PIN_IES_SMT_SPEC(200, 202, 0xb70, 1),
+ MTK_PIN_IES_SMT_SPEC(203, 207, 0xb70, 2),
+ MTK_PIN_IES_SMT_SPEC(208, 209, 0xb70, 3),
+ MTK_PIN_IES_SMT_SPEC(210, 210, 0xb70, 4),
+ MTK_PIN_IES_SMT_SPEC(211, 235, 0xb70, 5),
+ MTK_PIN_IES_SMT_SPEC(236, 241, 0xb70, 6),
+ MTK_PIN_IES_SMT_SPEC(242, 243, 0xb70, 7),
+ MTK_PIN_IES_SMT_SPEC(244, 247, 0xb70, 8),
+ MTK_PIN_IES_SMT_SPEC(248, 248, 0xb70, 9),
+ MTK_PIN_IES_SMT_SPEC(249, 249, 0x140, 3),
+ MTK_PIN_IES_SMT_SPEC(250, 250, 0x130, 15),
+ MTK_PIN_IES_SMT_SPEC(251, 251, 0x130, 11),
+ MTK_PIN_IES_SMT_SPEC(252, 252, 0x130, 7),
+ MTK_PIN_IES_SMT_SPEC(253, 253, 0x130, 3),
+ MTK_PIN_IES_SMT_SPEC(254, 254, 0xf40, 15),
+ MTK_PIN_IES_SMT_SPEC(255, 255, 0xf40, 11),
+ MTK_PIN_IES_SMT_SPEC(256, 256, 0xf40, 7),
+ MTK_PIN_IES_SMT_SPEC(257, 257, 0xf40, 3),
+ MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 11),
+ MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 11),
+ MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 11),
+ MTK_PIN_IES_SMT_SPEC(261, 261, 0x0b0, 3),
+ MTK_PIN_IES_SMT_SPEC(262, 277, 0xb70, 12),
+ MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13),
+};
+
+static int mt2701_ies_smt_set(struct regmap *regmap, unsigned int pin,
+ unsigned char align, int value, enum pin_config_param arg)
+{
+ if (arg == PIN_CONFIG_INPUT_ENABLE)
+ return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set,
+ ARRAY_SIZE(mt2701_ies_set), pin, align, value);
+ else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
+ return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set,
+ ARRAY_SIZE(mt2701_smt_set), pin, align, value);
+ return -EINVAL;
+}
+
+static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = {
+ MTK_PINMUX_SPEC(22, 0xb10, 3),
+ MTK_PINMUX_SPEC(23, 0xb10, 4),
+ MTK_PINMUX_SPEC(24, 0xb10, 5),
+ MTK_PINMUX_SPEC(29, 0xb10, 9),
+ MTK_PINMUX_SPEC(208, 0xb10, 7),
+ MTK_PINMUX_SPEC(209, 0xb10, 8),
+ MTK_PINMUX_SPEC(203, 0xf20, 0),
+ MTK_PINMUX_SPEC(204, 0xf20, 1),
+ MTK_PINMUX_SPEC(249, 0xef0, 0),
+ MTK_PINMUX_SPEC(250, 0xef0, 0),
+ MTK_PINMUX_SPEC(251, 0xef0, 0),
+ MTK_PINMUX_SPEC(252, 0xef0, 0),
+ MTK_PINMUX_SPEC(253, 0xef0, 0),
+ MTK_PINMUX_SPEC(254, 0xef0, 0),
+ MTK_PINMUX_SPEC(255, 0xef0, 0),
+ MTK_PINMUX_SPEC(256, 0xef0, 0),
+ MTK_PINMUX_SPEC(257, 0xef0, 0),
+ MTK_PINMUX_SPEC(258, 0xef0, 0),
+ MTK_PINMUX_SPEC(259, 0xef0, 0),
+ MTK_PINMUX_SPEC(260, 0xef0, 0),
+};
+
+static void mt2701_spec_pinmux_set(struct regmap *reg, unsigned int pin,
+ unsigned int mode)
+{
+ unsigned int i, value, mask;
+ unsigned int info_num = ARRAY_SIZE(mt2701_spec_pinmux);
+ unsigned int spec_flag;
+
+ for (i = 0; i < info_num; i++) {
+ if (pin == mt2701_spec_pinmux[i].pin)
+ break;
+ }
+
+ if (i == info_num)
+ return;
+
+ spec_flag = (mode >> 3);
+ mask = BIT(mt2701_spec_pinmux[i].bit);
+ if (!spec_flag)
+ value = mask;
+ else
+ value = 0;
+ regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value);
+}
+
+static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin)
+{
+ if (pin > 175)
+ *reg_addr += 0x10;
+}
+
+static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
+ .pins = mtk_pins_mt2701,
+ .npins = ARRAY_SIZE(mtk_pins_mt2701),
+ .grp_desc = mt2701_drv_grp,
+ .n_grp_cls = ARRAY_SIZE(mt2701_drv_grp),
+ .pin_drv_grp = mt2701_pin_drv,
+ .n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv),
+ .spec_pull_set = mt2701_spec_pull_set,
+ .spec_ies_smt_set = mt2701_ies_smt_set,
+ .spec_pinmux_set = mt2701_spec_pinmux_set,
+ .spec_dir_set = mt2701_spec_dir_set,
+ .dir_offset = 0x0000,
+ .pullen_offset = 0x0150,
+ .pullsel_offset = 0x0280,
+ .dout_offset = 0x0500,
+ .din_offset = 0x0630,
+ .pinmux_offset = 0x0760,
+ .type1_start = 280,
+ .type1_end = 280,
+ .port_shf = 4,
+ .port_mask = 0x1f,
+ .port_align = 4,
+ .eint_offsets = {
+ .name = "mt2701_eint",
+ .stat = 0x000,
+ .ack = 0x040,
+ .mask = 0x080,
+ .mask_set = 0x0c0,
+ .mask_clr = 0x100,
+ .sens = 0x140,
+ .sens_set = 0x180,
+ .sens_clr = 0x1c0,
+ .soft = 0x200,
+ .soft_set = 0x240,
+ .soft_clr = 0x280,
+ .pol = 0x300,
+ .pol_set = 0x340,
+ .pol_clr = 0x380,
+ .dom_en = 0x400,
+ .dbnc_ctrl = 0x500,
+ .dbnc_set = 0x600,
+ .dbnc_clr = 0x700,
+ .port_mask = 6,
+ .ports = 6,
+ },
+ .ap_num = 169,
+ .db_cnt = 16,
+};
+
+static int mt2701_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL);
+}
+
+static const struct of_device_id mt2701_pctrl_match[] = {
+ { .compatible = "mediatek,mt2701-pinctrl", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
+
+static struct platform_driver mtk_pinctrl_driver = {
+ .probe = mt2701_pinctrl_probe,
+ .driver = {
+ .name = "mediatek-mt2701-pinctrl",
+ .of_match_table = mt2701_pctrl_match,
+ .pm = &mtk_eint_pm_ops,
+ },
+};
+
+static int __init mtk_pinctrl_init(void)
+{
+ return platform_driver_register(&mtk_pinctrl_driver);
+}
+arch_initcall(mtk_pinctrl_init);
* GNU General Public License for more details.
*/
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
{ .compatible = "mediatek,mt6397-pinctrl", },
{ }
};
-MODULE_DEVICE_TABLE(of, mt6397_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt6397_pinctrl_probe,
{
return platform_driver_register(&mtk_pinctrl_driver);
}
-
-module_init(mtk_pinctrl_init);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("MediaTek MT6397 Pinctrl Driver");
-MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
+device_initcall(mtk_pinctrl_init);
--- /dev/null
+/*
+ * Copyright (c) 2016 John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/regmap.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt7623.h"
+
+static const struct mtk_drv_group_desc mt7623_drv_grp[] = {
+ /* 0E4E8SR 4/8/12/16 */
+ MTK_DRV_GRP(4, 16, 1, 2, 4),
+ /* 0E2E4SR 2/4/6/8 */
+ MTK_DRV_GRP(2, 8, 1, 2, 2),
+ /* E8E4E2 2/4/6/8/10/12/14/16 */
+ MTK_DRV_GRP(2, 16, 0, 2, 2)
+};
+
+#define DRV_SEL0 0xf50
+#define DRV_SEL1 0xf60
+#define DRV_SEL2 0xf70
+#define DRV_SEL3 0xf80
+#define DRV_SEL4 0xf90
+#define DRV_SEL5 0xfa0
+#define DRV_SEL6 0xfb0
+#define DRV_SEL7 0xfe0
+#define DRV_SEL8 0xfd0
+#define DRV_SEL9 0xff0
+#define DRV_SEL10 0xf00
+
+#define MSDC0_CTRL0 0xcc0
+#define MSDC0_CTRL1 0xcd0
+#define MSDC0_CTRL2 0xce0
+#define MSDC0_CTRL3 0xcf0
+#define MSDC0_CTRL4 0xd00
+#define MSDC0_CTRL5 0xd10
+#define MSDC0_CTRL6 0xd20
+#define MSDC1_CTRL0 0xd30
+#define MSDC1_CTRL1 0xd40
+#define MSDC1_CTRL2 0xd50
+#define MSDC1_CTRL3 0xd60
+#define MSDC1_CTRL4 0xd70
+#define MSDC1_CTRL5 0xd80
+#define MSDC1_CTRL6 0xd90
+
+#define IES_EN0 0xb20
+#define IES_EN1 0xb30
+#define IES_EN2 0xb40
+
+#define SMT_EN0 0xb50
+#define SMT_EN1 0xb60
+#define SMT_EN2 0xb70
+
+static const struct mtk_pin_drv_grp mt7623_pin_drv[] = {
+ MTK_PIN_DRV_GRP(0, DRV_SEL0, 0, 1),
+ MTK_PIN_DRV_GRP(1, DRV_SEL0, 0, 1),
+ MTK_PIN_DRV_GRP(2, DRV_SEL0, 0, 1),
+ MTK_PIN_DRV_GRP(3, DRV_SEL0, 0, 1),
+ MTK_PIN_DRV_GRP(4, DRV_SEL0, 0, 1),
+ MTK_PIN_DRV_GRP(5, DRV_SEL0, 0, 1),
+ MTK_PIN_DRV_GRP(6, DRV_SEL0, 0, 1),
+ MTK_PIN_DRV_GRP(7, DRV_SEL0, 4, 1),
+ MTK_PIN_DRV_GRP(8, DRV_SEL0, 4, 1),
+ MTK_PIN_DRV_GRP(9, DRV_SEL0, 4, 1),
+ MTK_PIN_DRV_GRP(10, DRV_SEL0, 8, 1),
+ MTK_PIN_DRV_GRP(11, DRV_SEL0, 8, 1),
+ MTK_PIN_DRV_GRP(12, DRV_SEL0, 8, 1),
+ MTK_PIN_DRV_GRP(13, DRV_SEL0, 8, 1),
+ MTK_PIN_DRV_GRP(14, DRV_SEL0, 12, 0),
+ MTK_PIN_DRV_GRP(15, DRV_SEL0, 12, 0),
+ MTK_PIN_DRV_GRP(18, DRV_SEL1, 4, 0),
+ MTK_PIN_DRV_GRP(19, DRV_SEL1, 4, 0),
+ MTK_PIN_DRV_GRP(20, DRV_SEL1, 4, 0),
+ MTK_PIN_DRV_GRP(21, DRV_SEL1, 4, 0),
+ MTK_PIN_DRV_GRP(22, DRV_SEL1, 8, 0),
+ MTK_PIN_DRV_GRP(23, DRV_SEL1, 8, 0),
+ MTK_PIN_DRV_GRP(24, DRV_SEL1, 8, 0),
+ MTK_PIN_DRV_GRP(25, DRV_SEL1, 8, 0),
+ MTK_PIN_DRV_GRP(26, DRV_SEL1, 8, 0),
+ MTK_PIN_DRV_GRP(27, DRV_SEL1, 12, 0),
+ MTK_PIN_DRV_GRP(28, DRV_SEL1, 12, 0),
+ MTK_PIN_DRV_GRP(29, DRV_SEL1, 12, 0),
+ MTK_PIN_DRV_GRP(33, DRV_SEL2, 0, 0),
+ MTK_PIN_DRV_GRP(34, DRV_SEL2, 0, 0),
+ MTK_PIN_DRV_GRP(35, DRV_SEL2, 0, 0),
+ MTK_PIN_DRV_GRP(36, DRV_SEL2, 0, 0),
+ MTK_PIN_DRV_GRP(37, DRV_SEL2, 0, 0),
+ MTK_PIN_DRV_GRP(39, DRV_SEL2, 8, 1),
+ MTK_PIN_DRV_GRP(40, DRV_SEL2, 8, 1),
+ MTK_PIN_DRV_GRP(41, DRV_SEL2, 8, 1),
+ MTK_PIN_DRV_GRP(42, DRV_SEL2, 8, 1),
+ MTK_PIN_DRV_GRP(43, DRV_SEL2, 12, 0),
+ MTK_PIN_DRV_GRP(44, DRV_SEL2, 12, 0),
+ MTK_PIN_DRV_GRP(45, DRV_SEL2, 12, 0),
+ MTK_PIN_DRV_GRP(47, DRV_SEL3, 0, 0),
+ MTK_PIN_DRV_GRP(48, DRV_SEL3, 0, 0),
+ MTK_PIN_DRV_GRP(49, DRV_SEL3, 4, 0),
+ MTK_PIN_DRV_GRP(53, DRV_SEL3, 12, 0),
+ MTK_PIN_DRV_GRP(54, DRV_SEL3, 12, 0),
+ MTK_PIN_DRV_GRP(55, DRV_SEL3, 12, 0),
+ MTK_PIN_DRV_GRP(56, DRV_SEL3, 12, 0),
+ MTK_PIN_DRV_GRP(60, DRV_SEL4, 8, 1),
+ MTK_PIN_DRV_GRP(61, DRV_SEL4, 8, 1),
+ MTK_PIN_DRV_GRP(62, DRV_SEL4, 8, 1),
+ MTK_PIN_DRV_GRP(63, DRV_SEL4, 12, 1),
+ MTK_PIN_DRV_GRP(64, DRV_SEL4, 12, 1),
+ MTK_PIN_DRV_GRP(65, DRV_SEL4, 12, 1),
+ MTK_PIN_DRV_GRP(66, DRV_SEL5, 0, 1),
+ MTK_PIN_DRV_GRP(67, DRV_SEL5, 0, 1),
+ MTK_PIN_DRV_GRP(68, DRV_SEL5, 0, 1),
+ MTK_PIN_DRV_GRP(69, DRV_SEL5, 0, 1),
+ MTK_PIN_DRV_GRP(70, DRV_SEL5, 0, 1),
+ MTK_PIN_DRV_GRP(71, DRV_SEL5, 0, 1),
+ MTK_PIN_DRV_GRP(72, DRV_SEL3, 4, 0),
+ MTK_PIN_DRV_GRP(73, DRV_SEL3, 4, 0),
+ MTK_PIN_DRV_GRP(74, DRV_SEL3, 4, 0),
+ MTK_PIN_DRV_GRP(83, DRV_SEL5, 0, 1),
+ MTK_PIN_DRV_GRP(84, DRV_SEL5, 0, 1),
+ MTK_PIN_DRV_GRP(105, MSDC1_CTRL1, 0, 1),
+ MTK_PIN_DRV_GRP(106, MSDC1_CTRL0, 0, 1),
+ MTK_PIN_DRV_GRP(107, MSDC1_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(108, MSDC1_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(109, MSDC1_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(110, MSDC1_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(111, MSDC0_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(112, MSDC0_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(113, MSDC0_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(114, MSDC0_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(115, MSDC0_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(116, MSDC0_CTRL1, 0, 1),
+ MTK_PIN_DRV_GRP(117, MSDC0_CTRL0, 0, 1),
+ MTK_PIN_DRV_GRP(118, MSDC0_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(119, MSDC0_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(120, MSDC0_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(121, MSDC0_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(126, DRV_SEL3, 4, 0),
+ MTK_PIN_DRV_GRP(199, DRV_SEL0, 4, 1),
+ MTK_PIN_DRV_GRP(200, DRV_SEL8, 0, 0),
+ MTK_PIN_DRV_GRP(201, DRV_SEL8, 0, 0),
+ MTK_PIN_DRV_GRP(203, DRV_SEL8, 4, 0),
+ MTK_PIN_DRV_GRP(204, DRV_SEL8, 4, 0),
+ MTK_PIN_DRV_GRP(205, DRV_SEL8, 4, 0),
+ MTK_PIN_DRV_GRP(206, DRV_SEL8, 4, 0),
+ MTK_PIN_DRV_GRP(207, DRV_SEL8, 4, 0),
+ MTK_PIN_DRV_GRP(208, DRV_SEL8, 8, 0),
+ MTK_PIN_DRV_GRP(209, DRV_SEL8, 8, 0),
+ MTK_PIN_DRV_GRP(236, DRV_SEL9, 4, 0),
+ MTK_PIN_DRV_GRP(237, DRV_SEL9, 4, 0),
+ MTK_PIN_DRV_GRP(238, DRV_SEL9, 4, 0),
+ MTK_PIN_DRV_GRP(239, DRV_SEL9, 4, 0),
+ MTK_PIN_DRV_GRP(240, DRV_SEL9, 4, 0),
+ MTK_PIN_DRV_GRP(241, DRV_SEL9, 4, 0),
+ MTK_PIN_DRV_GRP(242, DRV_SEL9, 8, 0),
+ MTK_PIN_DRV_GRP(243, DRV_SEL9, 8, 0),
+ MTK_PIN_DRV_GRP(257, MSDC0_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(261, MSDC1_CTRL2, 0, 1),
+ MTK_PIN_DRV_GRP(262, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(263, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(264, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(265, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(266, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(267, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(268, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(269, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(270, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(271, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(272, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(274, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(275, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(276, DRV_SEL10, 8, 0),
+ MTK_PIN_DRV_GRP(278, DRV_SEL2, 8, 1),
+};
+
+static const struct mtk_pin_spec_pupd_set_samereg mt7623_spec_pupd[] = {
+ MTK_PIN_PUPD_SPEC_SR(105, MSDC1_CTRL1, 8, 9, 10),
+ MTK_PIN_PUPD_SPEC_SR(106, MSDC1_CTRL0, 8, 9, 10),
+ MTK_PIN_PUPD_SPEC_SR(107, MSDC1_CTRL3, 0, 1, 2),
+ MTK_PIN_PUPD_SPEC_SR(108, MSDC1_CTRL3, 4, 5, 6),
+ MTK_PIN_PUPD_SPEC_SR(109, MSDC1_CTRL3, 8, 9, 10),
+ MTK_PIN_PUPD_SPEC_SR(110, MSDC1_CTRL3, 12, 13, 14),
+ MTK_PIN_PUPD_SPEC_SR(111, MSDC0_CTRL4, 12, 13, 14),
+ MTK_PIN_PUPD_SPEC_SR(112, MSDC0_CTRL4, 8, 9, 10),
+ MTK_PIN_PUPD_SPEC_SR(113, MSDC0_CTRL4, 4, 5, 6),
+ MTK_PIN_PUPD_SPEC_SR(114, MSDC0_CTRL4, 0, 1, 2),
+ MTK_PIN_PUPD_SPEC_SR(115, MSDC0_CTRL5, 0, 1, 2),
+ MTK_PIN_PUPD_SPEC_SR(116, MSDC0_CTRL1, 8, 9, 10),
+ MTK_PIN_PUPD_SPEC_SR(117, MSDC0_CTRL0, 8, 9, 10),
+ MTK_PIN_PUPD_SPEC_SR(118, MSDC0_CTRL3, 12, 13, 14),
+ MTK_PIN_PUPD_SPEC_SR(119, MSDC0_CTRL3, 8, 9, 10),
+ MTK_PIN_PUPD_SPEC_SR(120, MSDC0_CTRL3, 4, 5, 6),
+ MTK_PIN_PUPD_SPEC_SR(121, MSDC0_CTRL3, 0, 1, 2),
+};
+
+static int mt7623_spec_pull_set(struct regmap *regmap, unsigned int pin,
+ unsigned char align, bool isup, unsigned int r1r0)
+{
+ return mtk_pctrl_spec_pull_set_samereg(regmap, mt7623_spec_pupd,
+ ARRAY_SIZE(mt7623_spec_pupd), pin, align, isup, r1r0);
+}
+
+static const struct mtk_pin_ies_smt_set mt7623_ies_set[] = {
+ MTK_PIN_IES_SMT_SPEC(0, 6, IES_EN0, 0),
+ MTK_PIN_IES_SMT_SPEC(7, 9, IES_EN0, 1),
+ MTK_PIN_IES_SMT_SPEC(10, 13, IES_EN0, 2),
+ MTK_PIN_IES_SMT_SPEC(14, 15, IES_EN0, 3),
+ MTK_PIN_IES_SMT_SPEC(18, 21, IES_EN0, 5),
+ MTK_PIN_IES_SMT_SPEC(22, 26, IES_EN0, 6),
+ MTK_PIN_IES_SMT_SPEC(27, 29, IES_EN0, 7),
+ MTK_PIN_IES_SMT_SPEC(33, 37, IES_EN0, 8),
+ MTK_PIN_IES_SMT_SPEC(39, 42, IES_EN0, 9),
+ MTK_PIN_IES_SMT_SPEC(43, 45, IES_EN0, 10),
+ MTK_PIN_IES_SMT_SPEC(47, 48, IES_EN0, 11),
+ MTK_PIN_IES_SMT_SPEC(49, 49, IES_EN0, 12),
+ MTK_PIN_IES_SMT_SPEC(53, 56, IES_EN0, 14),
+ MTK_PIN_IES_SMT_SPEC(60, 62, IES_EN1, 0),
+ MTK_PIN_IES_SMT_SPEC(63, 65, IES_EN1, 1),
+ MTK_PIN_IES_SMT_SPEC(66, 71, IES_EN1, 2),
+ MTK_PIN_IES_SMT_SPEC(72, 74, IES_EN0, 12),
+ MTK_PIN_IES_SMT_SPEC(75, 76, IES_EN1, 3),
+ MTK_PIN_IES_SMT_SPEC(83, 84, IES_EN1, 2),
+ MTK_PIN_IES_SMT_SPEC(105, 121, MSDC1_CTRL1, 4),
+ MTK_PIN_IES_SMT_SPEC(122, 125, IES_EN1, 7),
+ MTK_PIN_IES_SMT_SPEC(126, 126, IES_EN0, 12),
+ MTK_PIN_IES_SMT_SPEC(199, 201, IES_EN0, 1),
+ MTK_PIN_IES_SMT_SPEC(203, 207, IES_EN2, 2),
+ MTK_PIN_IES_SMT_SPEC(208, 209, IES_EN2, 3),
+ MTK_PIN_IES_SMT_SPEC(236, 241, IES_EN2, 6),
+ MTK_PIN_IES_SMT_SPEC(242, 243, IES_EN2, 7),
+ MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL2, 4),
+ MTK_PIN_IES_SMT_SPEC(262, 272, IES_EN2, 12),
+ MTK_PIN_IES_SMT_SPEC(274, 276, IES_EN2, 12),
+ MTK_PIN_IES_SMT_SPEC(278, 278, IES_EN2, 13),
+};
+
+static const struct mtk_pin_ies_smt_set mt7623_smt_set[] = {
+ MTK_PIN_IES_SMT_SPEC(0, 6, SMT_EN0, 0),
+ MTK_PIN_IES_SMT_SPEC(7, 9, SMT_EN0, 1),
+ MTK_PIN_IES_SMT_SPEC(10, 13, SMT_EN0, 2),
+ MTK_PIN_IES_SMT_SPEC(14, 15, SMT_EN0, 3),
+ MTK_PIN_IES_SMT_SPEC(18, 21, SMT_EN0, 5),
+ MTK_PIN_IES_SMT_SPEC(22, 26, SMT_EN0, 6),
+ MTK_PIN_IES_SMT_SPEC(27, 29, SMT_EN0, 7),
+ MTK_PIN_IES_SMT_SPEC(33, 37, SMT_EN0, 8),
+ MTK_PIN_IES_SMT_SPEC(39, 42, SMT_EN0, 9),
+ MTK_PIN_IES_SMT_SPEC(43, 45, SMT_EN0, 10),
+ MTK_PIN_IES_SMT_SPEC(47, 48, SMT_EN0, 11),
+ MTK_PIN_IES_SMT_SPEC(49, 49, SMT_EN0, 12),
+ MTK_PIN_IES_SMT_SPEC(53, 56, SMT_EN0, 14),
+ MTK_PIN_IES_SMT_SPEC(60, 62, SMT_EN1, 0),
+ MTK_PIN_IES_SMT_SPEC(63, 65, SMT_EN1, 1),
+ MTK_PIN_IES_SMT_SPEC(66, 71, SMT_EN1, 2),
+ MTK_PIN_IES_SMT_SPEC(72, 74, SMT_EN0, 12),
+ MTK_PIN_IES_SMT_SPEC(75, 76, SMT_EN1, 3),
+ MTK_PIN_IES_SMT_SPEC(83, 84, SMT_EN1, 2),
+ MTK_PIN_IES_SMT_SPEC(105, 106, MSDC1_CTRL1, 11),
+ MTK_PIN_IES_SMT_SPEC(107, 107, MSDC1_CTRL3, 3),
+ MTK_PIN_IES_SMT_SPEC(108, 108, MSDC1_CTRL3, 7),
+ MTK_PIN_IES_SMT_SPEC(109, 109, MSDC1_CTRL3, 11),
+ MTK_PIN_IES_SMT_SPEC(110, 111, MSDC1_CTRL3, 15),
+ MTK_PIN_IES_SMT_SPEC(112, 112, MSDC0_CTRL4, 11),
+ MTK_PIN_IES_SMT_SPEC(113, 113, MSDC0_CTRL4, 7),
+ MTK_PIN_IES_SMT_SPEC(114, 115, MSDC0_CTRL4, 3),
+ MTK_PIN_IES_SMT_SPEC(116, 117, MSDC0_CTRL1, 11),
+ MTK_PIN_IES_SMT_SPEC(118, 118, MSDC0_CTRL3, 15),
+ MTK_PIN_IES_SMT_SPEC(119, 119, MSDC0_CTRL3, 11),
+ MTK_PIN_IES_SMT_SPEC(120, 120, MSDC0_CTRL3, 7),
+ MTK_PIN_IES_SMT_SPEC(121, 121, MSDC0_CTRL3, 3),
+ MTK_PIN_IES_SMT_SPEC(122, 125, SMT_EN1, 7),
+ MTK_PIN_IES_SMT_SPEC(126, 126, SMT_EN0, 12),
+ MTK_PIN_IES_SMT_SPEC(199, 201, SMT_EN0, 1),
+ MTK_PIN_IES_SMT_SPEC(203, 207, SMT_EN2, 2),
+ MTK_PIN_IES_SMT_SPEC(208, 209, SMT_EN2, 3),
+ MTK_PIN_IES_SMT_SPEC(236, 241, SMT_EN2, 6),
+ MTK_PIN_IES_SMT_SPEC(242, 243, SMT_EN2, 7),
+ MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL6, 3),
+ MTK_PIN_IES_SMT_SPEC(262, 272, SMT_EN2, 12),
+ MTK_PIN_IES_SMT_SPEC(274, 276, SMT_EN2, 12),
+ MTK_PIN_IES_SMT_SPEC(278, 278, SMT_EN2, 13),
+};
+
+static int mt7623_ies_smt_set(struct regmap *regmap, unsigned int pin,
+ unsigned char align, int value, enum pin_config_param arg)
+{
+ if (arg == PIN_CONFIG_INPUT_ENABLE)
+ return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_ies_set,
+ ARRAY_SIZE(mt7623_ies_set), pin, align, value);
+ else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
+ return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_smt_set,
+ ARRAY_SIZE(mt7623_smt_set), pin, align, value);
+ return -EINVAL;
+}
+
+static const struct mtk_pinctrl_devdata mt7623_pinctrl_data = {
+ .pins = mtk_pins_mt7623,
+ .npins = ARRAY_SIZE(mtk_pins_mt7623),
+ .grp_desc = mt7623_drv_grp,
+ .n_grp_cls = ARRAY_SIZE(mt7623_drv_grp),
+ .pin_drv_grp = mt7623_pin_drv,
+ .n_pin_drv_grps = ARRAY_SIZE(mt7623_pin_drv),
+ .spec_pull_set = mt7623_spec_pull_set,
+ .spec_ies_smt_set = mt7623_ies_smt_set,
+ .dir_offset = 0x0000,
+ .pullen_offset = 0x0150,
+ .pullsel_offset = 0x0280,
+ .dout_offset = 0x0500,
+ .din_offset = 0x0630,
+ .pinmux_offset = 0x0760,
+ .type1_start = 280,
+ .type1_end = 280,
+ .port_shf = 4,
+ .port_mask = 0x1f,
+ .port_align = 4,
+ .eint_offsets = {
+ .name = "mt7623_eint",
+ .stat = 0x000,
+ .ack = 0x040,
+ .mask = 0x080,
+ .mask_set = 0x0c0,
+ .mask_clr = 0x100,
+ .sens = 0x140,
+ .sens_set = 0x180,
+ .sens_clr = 0x1c0,
+ .soft = 0x200,
+ .soft_set = 0x240,
+ .soft_clr = 0x280,
+ .pol = 0x300,
+ .pol_set = 0x340,
+ .pol_clr = 0x380,
+ .dom_en = 0x400,
+ .dbnc_ctrl = 0x500,
+ .dbnc_set = 0x600,
+ .dbnc_clr = 0x700,
+ .port_mask = 6,
+ .ports = 6,
+ },
+ .ap_num = 169,
+ .db_cnt = 16,
+};
+
+static int mt7623_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_pctrl_init(pdev, &mt7623_pinctrl_data, NULL);
+}
+
+static const struct of_device_id mt7623_pctrl_match[] = {
+ { .compatible = "mediatek,mt7623-pinctrl", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, mt7623_pctrl_match);
+
+static struct platform_driver mtk_pinctrl_driver = {
+ .probe = mt7623_pinctrl_probe,
+ .driver = {
+ .name = "mediatek-mt7623-pinctrl",
+ .of_match_table = mt7623_pctrl_match,
+ },
+};
+
+static int __init mtk_pinctrl_init(void)
+{
+ return platform_driver_register(&mtk_pinctrl_driver);
+}
+
+arch_initcall(mtk_pinctrl_init);
* GNU General Public License for more details.
*/
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
{ .compatible = "mediatek,mt8127-pinctrl", },
{ }
};
-MODULE_DEVICE_TABLE(of, mt8127_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8127_pinctrl_probe,
{
return platform_driver_register(&mtk_pinctrl_driver);
}
-
arch_initcall(mtk_pinctrl_init);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver");
-MODULE_AUTHOR("Yingjoe Chen <yingjoe.chen@mediatek.com>");
* GNU General Public License for more details.
*/
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
},
{ }
};
-MODULE_DEVICE_TABLE(of, mt8135_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8135_pinctrl_probe,
{
return platform_driver_register(&mtk_pinctrl_driver);
}
-
arch_initcall(mtk_pinctrl_init);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
-MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
* GNU General Public License for more details.
*/
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
},
{ }
};
-MODULE_DEVICE_TABLE(of, mt8173_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8173_pinctrl_probe,
{
return platform_driver_register(&mtk_pinctrl_driver);
}
-
arch_initcall(mtk_pinctrl_init);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
-MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
#define MAX_GPIO_MODE_PER_REG 5
#define GPIO_MODE_BITS 3
+#define GPIO_MODE_PREFIX "GPIO"
static const char * const mtk_gpio_functions[] = {
"func0", "func1", "func2", "func3",
"func4", "func5", "func6", "func7",
+ "func8", "func9", "func10", "func11",
+ "func12", "func13", "func14", "func15",
};
/*
reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
bit = BIT(offset & 0xf);
+ if (pctl->devdata->spec_dir_set)
+ pctl->devdata->spec_dir_set(®_addr, offset);
+
if (input)
/* Different SoC has different alignment offset. */
reg_addr = CLR_ADDR(reg_addr, pctl);
unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ if (pctl->devdata->spec_pinmux_set)
+ pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
+ pin, mode);
+
reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
+ pctl->devdata->pinmux_offset;
+ mode &= mask;
bit = pin % MAX_GPIO_MODE_PER_REG;
mask <<= (GPIO_MODE_BITS * bit);
val = (mode << (GPIO_MODE_BITS * bit));
return 0;
}
+static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
+ unsigned offset)
+{
+ const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
+ const struct mtk_desc_function *func = pin->functions;
+
+ while (func && func->name) {
+ if (!strncmp(func->name, GPIO_MODE_PREFIX,
+ sizeof(GPIO_MODE_PREFIX)-1))
+ return func->muxval;
+ func++;
+ }
+ return -EINVAL;
+}
+
+static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned offset)
+{
+ int muxval;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ muxval = mtk_pmx_find_gpio_mode(pctl, offset);
+
+ if (muxval < 0) {
+ dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
+ return -EINVAL;
+ }
+
+ mtk_pmx_set_mode(pctldev, offset, muxval);
+ mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE);
+
+ return 0;
+}
+
static const struct pinmux_ops mtk_pmx_ops = {
.get_functions_count = mtk_pmx_get_funcs_cnt,
.get_function_name = mtk_pmx_get_func_name,
.get_function_groups = mtk_pmx_get_func_groups,
.set_mux = mtk_pmx_set_mux,
.gpio_set_direction = mtk_pmx_gpio_set_direction,
+ .gpio_request_enable = mtk_pmx_gpio_request_enable,
};
static int mtk_gpio_direction_input(struct gpio_chip *chip,
reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
bit = BIT(offset & 0xf);
+
+ if (pctl->devdata->spec_dir_set)
+ pctl->devdata->spec_dir_set(®_addr, offset);
+
regmap_read(pctl->regmap1, reg_addr, &read_val);
return !(read_val & bit);
}
/* set mux to INT mode */
mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
+ /* set gpio direction to input */
+ mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number, true);
+ /* set input-enable */
+ mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1, PIN_CONFIG_INPUT_ENABLE);
return 0;
}
* means when user set smt, input enable is set at the same time. So they
* also need special control. If special control is success, this should
* return 0, otherwise return non-zero value.
- *
+ * @spec_pinmux_set: In some cases, there are two pinmux functions share
+ * the same value in the same segment of pinmux control register. If user
+ * want to use one of the two functions, they need an extra bit setting to
+ * select the right one.
+ * @spec_dir_set: In very few SoCs, direction control registers are not
+ * arranged continuously, they may be cut to parts. So they need special
+ * dir setting.
+
* @dir_offset: The direction register offset.
* @pullen_offset: The pull-up/pull-down enable register offset.
* @pinmux_offset: The pinmux register offset.
unsigned char align, bool isup, unsigned int arg);
int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
unsigned char align, int value, enum pin_config_param arg);
+ void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
+ unsigned int mode);
+ void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
unsigned int dir_offset;
unsigned int ies_offset;
unsigned int smt_offset;
--- /dev/null
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Biao Huang <biao.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PINCTRL_MTK_MT2701_H
+#define __PINCTRL_MTK_MT2701_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mtk-common.h"
+
+static const struct mtk_desc_pin mtk_pins_mt2701[] = {
+ MTK_PIN(
+ PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 148),
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "PWRAP_SPIDO"),
+ MTK_FUNCTION(2, "PWRAP_SPIDI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 149),
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "PWRAP_SPIDI"),
+ MTK_FUNCTION(2, "PWRAP_SPIDO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(2, "PWRAP_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 150),
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "PWRAP_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 151),
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "PWRAP_SPICK_I")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 152),
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 153),
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "PWRAP_SPICK2_I"),
+ MTK_FUNCTION(5, "ANT_SEL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 154),
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "PWRAP_SPICS2_B_I"),
+ MTK_FUNCTION(5, "ANT_SEL0"),
+ MTK_FUNCTION(7, "DBG_MON_A[0]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(7, "SPI1_CSN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 155),
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "SPI1_CS"),
+ MTK_FUNCTION(4, "KCOL0"),
+ MTK_FUNCTION(7, "DBG_MON_B[12]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(8, "SPI1_MI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 156),
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "SPI1_MI"),
+ MTK_FUNCTION(2, "SPI1_MO"),
+ MTK_FUNCTION(4, "KCOL1"),
+ MTK_FUNCTION(7, "DBG_MON_B[13]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(9, "SPI1_MO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 157),
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "SPI1_MO"),
+ MTK_FUNCTION(2, "SPI1_MI"),
+ MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(4, "KCOL2"),
+ MTK_FUNCTION(7, "DBG_MON_B[14]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(10, "RTC32K_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 158),
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "RTC32K_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(11, "WATCHDOG"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 159),
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "WATCHDOG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(12, "SRCLKENA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 160),
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "SRCLKENA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(13, "SRCLKENAI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 161),
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "SRCLKENAI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(14, "URXD2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 162),
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "URXD2"),
+ MTK_FUNCTION(2, "UTXD2"),
+ MTK_FUNCTION(5, "SRCCLKENAI2"),
+ MTK_FUNCTION(7, "DBG_MON_B[30]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(15, "UTXD2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 163),
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "UTXD2"),
+ MTK_FUNCTION(2, "URXD2"),
+ MTK_FUNCTION(7, "DBG_MON_B[31]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(16, "I2S5_DATA_IN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 164),
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "I2S5_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX"),
+ MTK_FUNCTION(4, "ANT_SEL4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(17, "I2S5_BCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 165),
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "I2S5_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0"),
+ MTK_FUNCTION(4, "ANT_SEL2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(18, "PCM_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 166),
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "PCM_CLK0"),
+ MTK_FUNCTION(2, "MRG_CLK"),
+ MTK_FUNCTION(4, "MM_TEST_CK"),
+ MTK_FUNCTION(5, "CONN_DSP_JCK"),
+ MTK_FUNCTION(6, "WCN_PCM_CLKO"),
+ MTK_FUNCTION(7, "DBG_MON_A[3]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(19, "PCM_SYNC"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 167),
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "PCM_SYNC"),
+ MTK_FUNCTION(2, "MRG_SYNC"),
+ MTK_FUNCTION(5, "CONN_DSP_JINTP"),
+ MTK_FUNCTION(6, "WCN_PCM_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_A[5]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(20, "PCM_RX"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "PCM_RX"),
+ MTK_FUNCTION(2, "MRG_RX"),
+ MTK_FUNCTION(3, "MRG_TX"),
+ MTK_FUNCTION(4, "PCM_TX"),
+ MTK_FUNCTION(5, "CONN_DSP_JDI"),
+ MTK_FUNCTION(6, "WCN_PCM_RX"),
+ MTK_FUNCTION(7, "DBG_MON_A[4]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(21, "PCM_TX"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "PCM_TX"),
+ MTK_FUNCTION(2, "MRG_TX"),
+ MTK_FUNCTION(3, "MRG_RX"),
+ MTK_FUNCTION(4, "PCM_RX"),
+ MTK_FUNCTION(5, "CONN_DSP_JMS"),
+ MTK_FUNCTION(6, "WCN_PCM_TX"),
+ MTK_FUNCTION(7, "DBG_MON_A[2]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(22, "EINT0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 0),
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "UCTS0"),
+ MTK_FUNCTION(3, "KCOL3"),
+ MTK_FUNCTION(4, "CONN_DSP_JDO"),
+ MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_A[30]"),
+ MTK_FUNCTION(10, "PCIE0_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(23, "EINT1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 1),
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "URTS0"),
+ MTK_FUNCTION(3, "KCOL2"),
+ MTK_FUNCTION(4, "CONN_MCU_TDO"),
+ MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_A[29]"),
+ MTK_FUNCTION(10, "PCIE1_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(24, "EINT2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 2),
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "UCTS1"),
+ MTK_FUNCTION(3, "KCOL1"),
+ MTK_FUNCTION(4, "CONN_MCU_DBGACK_N"),
+ MTK_FUNCTION(7, "DBG_MON_A[28]"),
+ MTK_FUNCTION(10, "PCIE2_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(25, "EINT3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 3),
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "URTS1"),
+ MTK_FUNCTION(3, "KCOL0"),
+ MTK_FUNCTION(4, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(7, "DBG_MON_A[27]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(26, "EINT4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 4),
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "UCTS3"),
+ MTK_FUNCTION(2, "DRV_VBUS_P1"),
+ MTK_FUNCTION(3, "KROW3"),
+ MTK_FUNCTION(4, "CONN_MCU_TCK0"),
+ MTK_FUNCTION(5, "CONN_MCU_AICE_JCKC"),
+ MTK_FUNCTION(6, "PCIE2_WAKE_N"),
+ MTK_FUNCTION(7, "DBG_MON_A[26]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(27, "EINT5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 5),
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "URTS3"),
+ MTK_FUNCTION(2, "IDDIG_P1"),
+ MTK_FUNCTION(3, "KROW2"),
+ MTK_FUNCTION(4, "CONN_MCU_TDI"),
+ MTK_FUNCTION(6, "PCIE1_WAKE_N"),
+ MTK_FUNCTION(7, "DBG_MON_A[25]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(28, "EINT6"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 6),
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "DRV_VBUS"),
+ MTK_FUNCTION(3, "KROW1"),
+ MTK_FUNCTION(4, "CONN_MCU_TRST_B"),
+ MTK_FUNCTION(6, "PCIE0_WAKE_N"),
+ MTK_FUNCTION(7, "DBG_MON_A[24]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(29, "EINT7"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 7),
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "IDDIG"),
+ MTK_FUNCTION(2, "MSDC1_WP"),
+ MTK_FUNCTION(3, "KROW0"),
+ MTK_FUNCTION(4, "CONN_MCU_TMS"),
+ MTK_FUNCTION(5, "CONN_MCU_AICE_JMSC"),
+ MTK_FUNCTION(7, "DBG_MON_A[23]"),
+ MTK_FUNCTION(14, "PCIE2_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(30, "I2S5_LRCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 12),
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "I2S5_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC"),
+ MTK_FUNCTION(4, "ANT_SEL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(31, "I2S5_MCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 13),
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "I2S5_MCLK"),
+ MTK_FUNCTION(4, "ANT_SEL0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(32, "I2S5_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 14),
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "I2S5_DATA"),
+ MTK_FUNCTION(2, "I2S5_DATA_BYPS"),
+ MTK_FUNCTION(3, "PCM_TX"),
+ MTK_FUNCTION(4, "ANT_SEL3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(33, "I2S1_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 15),
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "I2S1_DATA"),
+ MTK_FUNCTION(2, "I2S1_DATA_BYPS"),
+ MTK_FUNCTION(3, "PCM_TX"),
+ MTK_FUNCTION(4, "IMG_TEST_CK"),
+ MTK_FUNCTION(5, "G1_RXD0"),
+ MTK_FUNCTION(6, "WCN_PCM_TX"),
+ MTK_FUNCTION(7, "DBG_MON_B[8]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(34, "I2S1_DATA_IN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 16),
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "I2S1_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX"),
+ MTK_FUNCTION(4, "VDEC_TEST_CK"),
+ MTK_FUNCTION(5, "G1_RXD1"),
+ MTK_FUNCTION(6, "WCN_PCM_RX"),
+ MTK_FUNCTION(7, "DBG_MON_B[7]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(35, "I2S1_BCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 17),
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "I2S1_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0"),
+ MTK_FUNCTION(5, "G1_RXD2"),
+ MTK_FUNCTION(6, "WCN_PCM_CLKO"),
+ MTK_FUNCTION(7, "DBG_MON_B[9]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(36, "I2S1_LRCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 18),
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "I2S1_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC"),
+ MTK_FUNCTION(5, "G1_RXD3"),
+ MTK_FUNCTION(6, "WCN_PCM_SYNC"),
+ MTK_FUNCTION(7, "DBG_MON_B[10]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(37, "I2S1_MCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 19),
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "I2S1_MCLK"),
+ MTK_FUNCTION(5, "G1_RXDV"),
+ MTK_FUNCTION(7, "DBG_MON_B[11]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(38, "I2S2_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 20),
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(2, "I2S2_DATA_BYPS"),
+ MTK_FUNCTION(3, "PCM_TX"),
+ MTK_FUNCTION(4, "DMIC_DAT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(39, "JTMS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 21),
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "JTMS"),
+ MTK_FUNCTION(2, "CONN_MCU_TMS"),
+ MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC"),
+ MTK_FUNCTION(4, "DFD_TMS_XI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(40, "JTCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 22),
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "JTCK"),
+ MTK_FUNCTION(2, "CONN_MCU_TCK1"),
+ MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC"),
+ MTK_FUNCTION(4, "DFD_TCK_XI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(41, "JTDI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 23),
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "JTDI"),
+ MTK_FUNCTION(2, "CONN_MCU_TDI"),
+ MTK_FUNCTION(4, "DFD_TDI_XI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(42, "JTDO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 24),
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "JTDO"),
+ MTK_FUNCTION(2, "CONN_MCU_TDO"),
+ MTK_FUNCTION(4, "DFD_TDO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(43, "NCLE"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 25),
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "NCLE"),
+ MTK_FUNCTION(2, "EXT_XCS2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(44, "NCEB1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 26),
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "NCEB1"),
+ MTK_FUNCTION(2, "IDDIG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(45, "NCEB0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 27),
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "NCEB0"),
+ MTK_FUNCTION(2, "DRV_VBUS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(46, "IR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 28),
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "IR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(47, "NREB"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 29),
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "NREB"),
+ MTK_FUNCTION(2, "IDDIG_P1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(48, "NRNB"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 30),
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "NRNB"),
+ MTK_FUNCTION(2, "DRV_VBUS_P1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(49, "I2S0_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 31),
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "I2S0_DATA"),
+ MTK_FUNCTION(2, "I2S0_DATA_BYPS"),
+ MTK_FUNCTION(3, "PCM_TX"),
+ MTK_FUNCTION(6, "WCN_I2S_DO"),
+ MTK_FUNCTION(7, "DBG_MON_B[3]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(50, "I2S2_BCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 32),
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "I2S2_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0"),
+ MTK_FUNCTION(4, "DMIC_SCK1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(51, "I2S2_DATA_IN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 33),
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "I2S2_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX"),
+ MTK_FUNCTION(4, "DMIC_SCK0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(52, "I2S2_LRCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 34),
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "I2S2_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC"),
+ MTK_FUNCTION(4, "DMIC_DAT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(53, "SPI0_CSN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 35),
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "SPI0_CS"),
+ MTK_FUNCTION(3, "SPDIF"),
+ MTK_FUNCTION(4, "ADC_CK"),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(7, "DBG_MON_A[7]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(54, "SPI0_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 36),
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "SPI0_CK"),
+ MTK_FUNCTION(3, "SPDIF_IN1"),
+ MTK_FUNCTION(4, "ADC_DAT_IN"),
+ MTK_FUNCTION(7, "DBG_MON_A[10]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(55, "SPI0_MI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 37),
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "SPI0_MI"),
+ MTK_FUNCTION(2, "SPI0_MO"),
+ MTK_FUNCTION(3, "MSDC1_WP"),
+ MTK_FUNCTION(4, "ADC_WS"),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(7, "DBG_MON_A[8]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(56, "SPI0_MO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 38),
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "SPI0_MO"),
+ MTK_FUNCTION(2, "SPI0_MI"),
+ MTK_FUNCTION(3, "SPDIF_IN0"),
+ MTK_FUNCTION(7, "DBG_MON_A[9]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(57, "SDA1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 39),
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "SDA1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(58, "SCL1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 40),
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "SCL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(59, "RAMBUF_I_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "RAMBUF_I_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(60, "WB_RSTB"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 41),
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "WB_RSTB"),
+ MTK_FUNCTION(7, "DBG_MON_A[11]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(61, "F2W_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 42),
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "F2W_DATA"),
+ MTK_FUNCTION(7, "DBG_MON_A[16]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(62, "F2W_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 43),
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "F2W_CK"),
+ MTK_FUNCTION(7, "DBG_MON_A[15]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(63, "WB_SCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 44),
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "WB_SCLK"),
+ MTK_FUNCTION(7, "DBG_MON_A[13]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(64, "WB_SDATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 45),
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "WB_SDATA"),
+ MTK_FUNCTION(7, "DBG_MON_A[12]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(65, "WB_SEN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 46),
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "WB_SEN"),
+ MTK_FUNCTION(7, "DBG_MON_A[14]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(66, "WB_CRTL0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 47),
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "WB_CRTL0"),
+ MTK_FUNCTION(5, "DFD_NTRST_XI"),
+ MTK_FUNCTION(7, "DBG_MON_A[17]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(67, "WB_CRTL1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 48),
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "WB_CRTL1"),
+ MTK_FUNCTION(5, "DFD_TMS_XI"),
+ MTK_FUNCTION(7, "DBG_MON_A[18]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(68, "WB_CRTL2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 49),
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "WB_CRTL2"),
+ MTK_FUNCTION(5, "DFD_TCK_XI"),
+ MTK_FUNCTION(7, "DBG_MON_A[19]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(69, "WB_CRTL3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 50),
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "WB_CRTL3"),
+ MTK_FUNCTION(5, "DFD_TDI_XI"),
+ MTK_FUNCTION(7, "DBG_MON_A[20]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(70, "WB_CRTL4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 51),
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "WB_CRTL4"),
+ MTK_FUNCTION(5, "DFD_TDO"),
+ MTK_FUNCTION(7, "DBG_MON_A[21]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(71, "WB_CRTL5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 52),
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "WB_CRTL5"),
+ MTK_FUNCTION(7, "DBG_MON_A[22]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(72, "I2S0_DATA_IN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 53),
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "I2S0_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX"),
+ MTK_FUNCTION(4, "PWM0"),
+ MTK_FUNCTION(5, "DISP_PWM"),
+ MTK_FUNCTION(6, "WCN_I2S_DI"),
+ MTK_FUNCTION(7, "DBG_MON_B[2]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(73, "I2S0_LRCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 54),
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "I2S0_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC"),
+ MTK_FUNCTION(6, "WCN_I2S_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_B[5]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(74, "I2S0_BCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 55),
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "I2S0_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0"),
+ MTK_FUNCTION(6, "WCN_I2S_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_B[4]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(75, "SDA0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 56),
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "SDA0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(76, "SCL0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 57),
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "SCL0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(77, "SDA2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 58),
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "SDA2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(78, "SCL2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 59),
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "SCL2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(79, "URXD0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 60),
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "URXD0"),
+ MTK_FUNCTION(2, "UTXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(80, "UTXD0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 61),
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "UTXD0"),
+ MTK_FUNCTION(2, "URXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(81, "URXD1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 62),
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION(2, "UTXD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(82, "UTXD1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 63),
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION(2, "URXD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(83, "LCM_RST"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 64),
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "LCM_RST"),
+ MTK_FUNCTION(2, "VDAC_CK_XI"),
+ MTK_FUNCTION(7, "DBG_MON_B[1]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(84, "DSI_TE"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 65),
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "DSI_TE"),
+ MTK_FUNCTION(7, "DBG_MON_B[0]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(85, "MSDC2_CMD"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 66),
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "MSDC2_CMD"),
+ MTK_FUNCTION(2, "ANT_SEL0"),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(6, "I2SOUT_BCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(86, "MSDC2_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 67),
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "MSDC2_CLK"),
+ MTK_FUNCTION(2, "ANT_SEL1"),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(6, "I2SOUT_LRCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(87, "MSDC2_DAT0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 68),
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "MSDC2_DAT0"),
+ MTK_FUNCTION(2, "ANT_SEL2"),
+ MTK_FUNCTION(5, "UTXD0"),
+ MTK_FUNCTION(6, "I2SOUT_DATA_OUT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(88, "MSDC2_DAT1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 71),
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "MSDC2_DAT1"),
+ MTK_FUNCTION(2, "ANT_SEL3"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(5, "URXD0"),
+ MTK_FUNCTION(6, "PWM1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(89, "MSDC2_DAT2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 72),
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "MSDC2_DAT2"),
+ MTK_FUNCTION(2, "ANT_SEL4"),
+ MTK_FUNCTION(3, "SDA2"),
+ MTK_FUNCTION(5, "UTXD1"),
+ MTK_FUNCTION(6, "PWM2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(90, "MSDC2_DAT3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 73),
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "MSDC2_DAT3"),
+ MTK_FUNCTION(2, "ANT_SEL5"),
+ MTK_FUNCTION(3, "SCL2"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "URXD1"),
+ MTK_FUNCTION(6, "PWM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(91, "TDN3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI91"),
+ MTK_FUNCTION(1, "TDN3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(92, "TDP3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI92"),
+ MTK_FUNCTION(1, "TDP3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(93, "TDN2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI93"),
+ MTK_FUNCTION(1, "TDN2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(94, "TDP2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI94"),
+ MTK_FUNCTION(1, "TDP2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(95, "TCN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI95"),
+ MTK_FUNCTION(1, "TCN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(96, "TCP"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI96"),
+ MTK_FUNCTION(1, "TCP")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(97, "TDN1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI97"),
+ MTK_FUNCTION(1, "TDN1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(98, "TDP1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI98"),
+ MTK_FUNCTION(1, "TDP1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(99, "TDN0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI99"),
+ MTK_FUNCTION(1, "TDN0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(100, "TDP0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPI100"),
+ MTK_FUNCTION(1, "TDP0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(101, "SPI2_CSN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 74),
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "SPI2_CS"),
+ MTK_FUNCTION(3, "SCL3"),
+ MTK_FUNCTION(4, "KROW0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(102, "SPI2_MI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 75),
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION(1, "SPI2_MI"),
+ MTK_FUNCTION(2, "SPI2_MO"),
+ MTK_FUNCTION(3, "SDA3"),
+ MTK_FUNCTION(4, "KROW1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(103, "SPI2_MO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 76),
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION(1, "SPI2_MO"),
+ MTK_FUNCTION(2, "SPI2_MI"),
+ MTK_FUNCTION(3, "SCL3"),
+ MTK_FUNCTION(4, "KROW2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(104, "SPI2_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 77),
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION(1, "SPI2_CK"),
+ MTK_FUNCTION(3, "SDA3"),
+ MTK_FUNCTION(4, "KROW3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(105, "MSDC1_CMD"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 78),
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION(2, "ANT_SEL0"),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(6, "I2SOUT_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_B[27]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(106, "MSDC1_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 79),
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION(2, "ANT_SEL1"),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(6, "I2SOUT_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_B[28]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(107, "MSDC1_DAT0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 80),
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION(2, "ANT_SEL2"),
+ MTK_FUNCTION(5, "UTXD0"),
+ MTK_FUNCTION(6, "I2SOUT_DATA_OUT"),
+ MTK_FUNCTION(7, "DBG_MON_B[26]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(108, "MSDC1_DAT1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 81),
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION(2, "ANT_SEL3"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(5, "URXD0"),
+ MTK_FUNCTION(6, "PWM1"),
+ MTK_FUNCTION(7, "DBG_MON_B[25]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(109, "MSDC1_DAT2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 82),
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION(2, "ANT_SEL4"),
+ MTK_FUNCTION(3, "SDA2"),
+ MTK_FUNCTION(5, "UTXD1"),
+ MTK_FUNCTION(6, "PWM2"),
+ MTK_FUNCTION(7, "DBG_MON_B[24]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(110, "MSDC1_DAT3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 83),
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION(2, "ANT_SEL5"),
+ MTK_FUNCTION(3, "SCL2"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "URXD1"),
+ MTK_FUNCTION(6, "PWM3"),
+ MTK_FUNCTION(7, "DBG_MON_B[23]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(111, "MSDC0_DAT7"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 84),
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "MSDC0_DAT7"),
+ MTK_FUNCTION(4, "NLD7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(112, "MSDC0_DAT6"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 85),
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "MSDC0_DAT6"),
+ MTK_FUNCTION(4, "NLD6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(113, "MSDC0_DAT5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 86),
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "MSDC0_DAT5"),
+ MTK_FUNCTION(4, "NLD5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(114, "MSDC0_DAT4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 87),
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "MSDC0_DAT4"),
+ MTK_FUNCTION(4, "NLD4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(115, "MSDC0_RSTB"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 88),
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "MSDC0_RSTB"),
+ MTK_FUNCTION(4, "NLD8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(116, "MSDC0_CMD"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 89),
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "MSDC0_CMD"),
+ MTK_FUNCTION(4, "NALE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(117, "MSDC0_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 90),
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "MSDC0_CLK"),
+ MTK_FUNCTION(4, "NWEB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(118, "MSDC0_DAT3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 91),
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "MSDC0_DAT3"),
+ MTK_FUNCTION(4, "NLD3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(119, "MSDC0_DAT2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 92),
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "MSDC0_DAT2"),
+ MTK_FUNCTION(4, "NLD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(120, "MSDC0_DAT1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 93),
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "MSDC0_DAT1"),
+ MTK_FUNCTION(4, "NLD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(121, "MSDC0_DAT0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 94),
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "MSDC0_DAT0"),
+ MTK_FUNCTION(4, "NLD0"),
+ MTK_FUNCTION(5, "WATCHDOG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(122, "CEC"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 95),
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "CEC"),
+ MTK_FUNCTION(4, "SDA2"),
+ MTK_FUNCTION(5, "URXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(123, "HTPLG"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 96),
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "HTPLG"),
+ MTK_FUNCTION(4, "SCL2"),
+ MTK_FUNCTION(5, "UTXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(124, "HDMISCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 97),
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "HDMISCK"),
+ MTK_FUNCTION(4, "SDA1"),
+ MTK_FUNCTION(5, "PWM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(125, "HDMISD"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 98),
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "HDMISD"),
+ MTK_FUNCTION(4, "SCL1"),
+ MTK_FUNCTION(5, "PWM4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(126, "I2S0_MCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 99),
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "I2S0_MCLK"),
+ MTK_FUNCTION(6, "WCN_I2S_MCLK"),
+ MTK_FUNCTION(7, "DBG_MON_B[6]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(127, "RAMBUF_IDATA0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(128, "RAMBUF_IDATA1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(129, "RAMBUF_IDATA2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(130, "RAMBUF_IDATA3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(131, "RAMBUF_IDATA4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(132, "RAMBUF_IDATA5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(133, "RAMBUF_IDATA6"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(134, "RAMBUF_IDATA7"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(135, "RAMBUF_IDATA8"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(136, "RAMBUF_IDATA9"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(137, "RAMBUF_IDATA10"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(138, "RAMBUF_IDATA11"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(139, "RAMBUF_IDATA12"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA12")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(140, "RAMBUF_IDATA13"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA13")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(141, "RAMBUF_IDATA14"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA14")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(142, "RAMBUF_IDATA15"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "RAMBUF_IDATA15")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(143, "RAMBUF_ODATA0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(144, "RAMBUF_ODATA1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(145, "RAMBUF_ODATA2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(146, "RAMBUF_ODATA3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(147, "RAMBUF_ODATA4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(148, "RAMBUF_ODATA5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(149, "RAMBUF_ODATA6"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(150, "RAMBUF_ODATA7"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(151, "RAMBUF_ODATA8"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(152, "RAMBUF_ODATA9"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(153, "RAMBUF_ODATA10"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(154, "RAMBUF_ODATA11"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(155, "RAMBUF_ODATA12"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA12")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(156, "RAMBUF_ODATA13"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA13")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(157, "RAMBUF_ODATA14"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA14")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(158, "RAMBUF_ODATA15"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(1, "RAMBUF_ODATA15")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(159, "RAMBUF_BE0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(1, "RAMBUF_BE0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(160, "RAMBUF_BE1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(1, "RAMBUF_BE1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(161, "AP2PT_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO161"),
+ MTK_FUNCTION(1, "AP2PT_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(162, "AP2PT_INT_CLR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO162"),
+ MTK_FUNCTION(1, "AP2PT_INT_CLR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(163, "PT2AP_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO163"),
+ MTK_FUNCTION(1, "PT2AP_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(164, "PT2AP_INT_CLR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO164"),
+ MTK_FUNCTION(1, "PT2AP_INT_CLR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(165, "AP2UP_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO165"),
+ MTK_FUNCTION(1, "AP2UP_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(166, "AP2UP_INT_CLR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO166"),
+ MTK_FUNCTION(1, "AP2UP_INT_CLR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(167, "UP2AP_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO167"),
+ MTK_FUNCTION(1, "UP2AP_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(168, "UP2AP_INT_CLR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO168"),
+ MTK_FUNCTION(1, "UP2AP_INT_CLR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(169, "RAMBUF_ADDR0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO169"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(170, "RAMBUF_ADDR1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO170"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(171, "RAMBUF_ADDR2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO171"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(172, "RAMBUF_ADDR3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO172"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(173, "RAMBUF_ADDR4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO173"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(174, "RAMBUF_ADDR5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO174"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(175, "RAMBUF_ADDR6"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO175"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(176, "RAMBUF_ADDR7"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO176"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(177, "RAMBUF_ADDR8"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO177"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(178, "RAMBUF_ADDR9"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO178"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(179, "RAMBUF_ADDR10"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO179"),
+ MTK_FUNCTION(1, "RAMBUF_ADDR10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(180, "RAMBUF_RW"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO180"),
+ MTK_FUNCTION(1, "RAMBUF_RW")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(181, "RAMBUF_LAST"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO181"),
+ MTK_FUNCTION(1, "RAMBUF_LAST")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(182, "RAMBUF_HP"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO182"),
+ MTK_FUNCTION(1, "RAMBUF_HP")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(183, "RAMBUF_REQ"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO183"),
+ MTK_FUNCTION(1, "RAMBUF_REQ")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(184, "RAMBUF_ALE"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO184"),
+ MTK_FUNCTION(1, "RAMBUF_ALE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(185, "RAMBUF_DLE"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO185"),
+ MTK_FUNCTION(1, "RAMBUF_DLE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(186, "RAMBUF_WDLE"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO186"),
+ MTK_FUNCTION(1, "RAMBUF_WDLE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(187, "RAMBUF_O_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO187"),
+ MTK_FUNCTION(1, "RAMBUF_O_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(188, "I2S2_MCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 100),
+ MTK_FUNCTION(0, "GPIO188"),
+ MTK_FUNCTION(1, "I2S2_MCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(189, "I2S3_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 101),
+ MTK_FUNCTION(0, "GPIO189"),
+ MTK_FUNCTION(2, "I2S3_DATA_BYPS"),
+ MTK_FUNCTION(3, "PCM_TX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(190, "I2S3_DATA_IN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 102),
+ MTK_FUNCTION(0, "GPIO190"),
+ MTK_FUNCTION(1, "I2S3_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(191, "I2S3_BCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 103),
+ MTK_FUNCTION(0, "GPIO191"),
+ MTK_FUNCTION(1, "I2S3_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(192, "I2S3_LRCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 104),
+ MTK_FUNCTION(0, "GPIO192"),
+ MTK_FUNCTION(1, "I2S3_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(193, "I2S3_MCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 105),
+ MTK_FUNCTION(0, "GPIO193"),
+ MTK_FUNCTION(1, "I2S3_MCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(194, "I2S4_DATA"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 106),
+ MTK_FUNCTION(0, "GPIO194"),
+ MTK_FUNCTION(1, "I2S4_DATA"),
+ MTK_FUNCTION(2, "I2S4_DATA_BYPS"),
+ MTK_FUNCTION(3, "PCM_TX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(195, "I2S4_DATA_IN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 107),
+ MTK_FUNCTION(0, "GPIO195"),
+ MTK_FUNCTION(1, "I2S4_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(196, "I2S4_BCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 108),
+ MTK_FUNCTION(0, "GPIO196"),
+ MTK_FUNCTION(1, "I2S4_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(197, "I2S4_LRCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 109),
+ MTK_FUNCTION(0, "GPIO197"),
+ MTK_FUNCTION(1, "I2S4_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(198, "I2S4_MCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 110),
+ MTK_FUNCTION(0, "GPIO198"),
+ MTK_FUNCTION(1, "I2S4_MCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(199, "SPI1_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 111),
+ MTK_FUNCTION(0, "GPIO199"),
+ MTK_FUNCTION(1, "SPI1_CK"),
+ MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(4, "KCOL3"),
+ MTK_FUNCTION(7, "DBG_MON_B[15]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(200, "SPDIF_OUT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 112),
+ MTK_FUNCTION(0, "GPIO200"),
+ MTK_FUNCTION(1, "SPDIF_OUT"),
+ MTK_FUNCTION(5, "G1_TXD3"),
+ MTK_FUNCTION(6, "URXD2"),
+ MTK_FUNCTION(7, "DBG_MON_B[16]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(201, "SPDIF_IN0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 113),
+ MTK_FUNCTION(0, "GPIO201"),
+ MTK_FUNCTION(1, "SPDIF_IN0"),
+ MTK_FUNCTION(5, "G1_TXEN"),
+ MTK_FUNCTION(6, "UTXD2"),
+ MTK_FUNCTION(7, "DBG_MON_B[17]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(202, "SPDIF_IN1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 114),
+ MTK_FUNCTION(0, "GPIO202"),
+ MTK_FUNCTION(1, "SPDIF_IN1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(203, "PWM0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 115),
+ MTK_FUNCTION(0, "GPIO203"),
+ MTK_FUNCTION(1, "PWM0"),
+ MTK_FUNCTION(2, "DISP_PWM"),
+ MTK_FUNCTION(5, "G1_TXD2"),
+ MTK_FUNCTION(7, "DBG_MON_B[18]"),
+ MTK_FUNCTION(9, "I2S2_DATA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(204, "PWM1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 116),
+ MTK_FUNCTION(0, "GPIO204"),
+ MTK_FUNCTION(1, "PWM1"),
+ MTK_FUNCTION(2, "CLKM3"),
+ MTK_FUNCTION(5, "G1_TXD1"),
+ MTK_FUNCTION(7, "DBG_MON_B[19]"),
+ MTK_FUNCTION(9, "I2S3_DATA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(205, "PWM2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 117),
+ MTK_FUNCTION(0, "GPIO205"),
+ MTK_FUNCTION(1, "PWM2"),
+ MTK_FUNCTION(2, "CLKM2"),
+ MTK_FUNCTION(5, "G1_TXD0"),
+ MTK_FUNCTION(7, "DBG_MON_B[20]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(206, "PWM3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 118),
+ MTK_FUNCTION(0, "GPIO206"),
+ MTK_FUNCTION(1, "PWM3"),
+ MTK_FUNCTION(2, "CLKM1"),
+ MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "G1_TXC"),
+ MTK_FUNCTION(7, "DBG_MON_B[21]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(207, "PWM4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 119),
+ MTK_FUNCTION(0, "GPIO207"),
+ MTK_FUNCTION(1, "PWM4"),
+ MTK_FUNCTION(2, "CLKM0"),
+ MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "G1_RXC"),
+ MTK_FUNCTION(7, "DBG_MON_B[22]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(208, "AUD_EXT_CK1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 120),
+ MTK_FUNCTION(0, "GPIO208"),
+ MTK_FUNCTION(1, "AUD_EXT_CK1"),
+ MTK_FUNCTION(2, "PWM0"),
+ MTK_FUNCTION(4, "ANT_SEL5"),
+ MTK_FUNCTION(5, "DISP_PWM"),
+ MTK_FUNCTION(7, "DBG_MON_A[31]"),
+ MTK_FUNCTION(11, "PCIE0_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(209, "AUD_EXT_CK2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 121),
+ MTK_FUNCTION(0, "GPIO209"),
+ MTK_FUNCTION(1, "AUD_EXT_CK2"),
+ MTK_FUNCTION(2, "MSDC1_WP"),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(7, "DBG_MON_A[32]"),
+ MTK_FUNCTION(11, "PCIE1_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(210, "AUD_CLOCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO210"),
+ MTK_FUNCTION(1, "AUD_CLOCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(211, "DVP_RESET"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO211"),
+ MTK_FUNCTION(1, "DVP_RESET")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(212, "DVP_CLOCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO212"),
+ MTK_FUNCTION(1, "DVP_CLOCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(213, "DVP_CS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO213"),
+ MTK_FUNCTION(1, "DVP_CS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(214, "DVP_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO214"),
+ MTK_FUNCTION(1, "DVP_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(215, "DVP_DI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO215"),
+ MTK_FUNCTION(1, "DVP_DI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(216, "DVP_DO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO216"),
+ MTK_FUNCTION(1, "DVP_DO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(217, "AP_CS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO217"),
+ MTK_FUNCTION(1, "AP_CS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(218, "AP_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO218"),
+ MTK_FUNCTION(1, "AP_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(219, "AP_DI"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO219"),
+ MTK_FUNCTION(1, "AP_DI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(220, "AP_DO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO220"),
+ MTK_FUNCTION(1, "AP_DO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(221, "DVD_BCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO221"),
+ MTK_FUNCTION(1, "DVD_BCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(222, "T8032_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO222"),
+ MTK_FUNCTION(1, "T8032_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(223, "AP_BCLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO223"),
+ MTK_FUNCTION(1, "AP_BCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(224, "HOST_CS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO224"),
+ MTK_FUNCTION(1, "HOST_CS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(225, "HOST_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO225"),
+ MTK_FUNCTION(1, "HOST_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(226, "HOST_DO0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO226"),
+ MTK_FUNCTION(1, "HOST_DO0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(227, "HOST_DO1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO227"),
+ MTK_FUNCTION(1, "HOST_DO1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(228, "SLV_CS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO228"),
+ MTK_FUNCTION(1, "SLV_CS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(229, "SLV_CK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO229"),
+ MTK_FUNCTION(1, "SLV_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(230, "SLV_DI0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO230"),
+ MTK_FUNCTION(1, "SLV_DI0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(231, "SLV_DI1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO231"),
+ MTK_FUNCTION(1, "SLV_DI1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(232, "AP2DSP_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO232"),
+ MTK_FUNCTION(1, "AP2DSP_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(233, "AP2DSP_INT_CLR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO233"),
+ MTK_FUNCTION(1, "AP2DSP_INT_CLR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(234, "DSP2AP_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO234"),
+ MTK_FUNCTION(1, "DSP2AP_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(235, "DSP2AP_INT_CLR"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO235"),
+ MTK_FUNCTION(1, "DSP2AP_INT_CLR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(236, "EXT_SDIO3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 122),
+ MTK_FUNCTION(0, "GPIO236"),
+ MTK_FUNCTION(1, "EXT_SDIO3"),
+ MTK_FUNCTION(2, "IDDIG"),
+ MTK_FUNCTION(7, "DBG_MON_A[1]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(237, "EXT_SDIO2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 123),
+ MTK_FUNCTION(0, "GPIO237"),
+ MTK_FUNCTION(1, "EXT_SDIO2"),
+ MTK_FUNCTION(2, "DRV_VBUS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(238, "EXT_SDIO1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 124),
+ MTK_FUNCTION(0, "GPIO238"),
+ MTK_FUNCTION(1, "EXT_SDIO1"),
+ MTK_FUNCTION(2, "IDDIG_P1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(239, "EXT_SDIO0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 125),
+ MTK_FUNCTION(0, "GPIO239"),
+ MTK_FUNCTION(1, "EXT_SDIO0"),
+ MTK_FUNCTION(2, "DRV_VBUS_P1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(240, "EXT_XCS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 126),
+ MTK_FUNCTION(0, "GPIO240"),
+ MTK_FUNCTION(1, "EXT_XCS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(241, "EXT_SCK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 127),
+ MTK_FUNCTION(0, "GPIO241"),
+ MTK_FUNCTION(1, "EXT_SCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(242, "URTS2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 128),
+ MTK_FUNCTION(0, "GPIO242"),
+ MTK_FUNCTION(1, "URTS2"),
+ MTK_FUNCTION(2, "UTXD3"),
+ MTK_FUNCTION(3, "URXD3"),
+ MTK_FUNCTION(4, "SCL1"),
+ MTK_FUNCTION(7, "DBG_MON_B[32]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(243, "UCTS2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 129),
+ MTK_FUNCTION(0, "GPIO243"),
+ MTK_FUNCTION(1, "UCTS2"),
+ MTK_FUNCTION(2, "URXD3"),
+ MTK_FUNCTION(3, "UTXD3"),
+ MTK_FUNCTION(4, "SDA1"),
+ MTK_FUNCTION(7, "DBG_MON_A[6]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(244, "HDMI_SDA_RX"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 130),
+ MTK_FUNCTION(0, "GPIO244"),
+ MTK_FUNCTION(1, "HDMI_SDA_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(245, "HDMI_SCL_RX"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 131),
+ MTK_FUNCTION(0, "GPIO245"),
+ MTK_FUNCTION(1, "HDMI_SCL_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(246, "MHL_SENCE"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 132),
+ MTK_FUNCTION(0, "GPIO246")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(247, "HDMI_HPD_CBUS_RX"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 69),
+ MTK_FUNCTION(0, "GPIO247"),
+ MTK_FUNCTION(1, "HDMI_HPD_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(248, "HDMI_TESTOUTP_RX"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 133),
+ MTK_FUNCTION(0, "GPIO248"),
+ MTK_FUNCTION(1, "HDMI_TESTOUTP_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(249, "MSDC0E_RSTB"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 134),
+ MTK_FUNCTION(0, "GPIO249"),
+ MTK_FUNCTION(1, "MSDC0E_RSTB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(250, "MSDC0E_DAT7"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 135),
+ MTK_FUNCTION(0, "GPIO250"),
+ MTK_FUNCTION(1, "MSDC3_DAT7"),
+ MTK_FUNCTION(6, "PCIE0_CLKREQ_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(251, "MSDC0E_DAT6"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 136),
+ MTK_FUNCTION(0, "GPIO251"),
+ MTK_FUNCTION(1, "MSDC3_DAT6"),
+ MTK_FUNCTION(6, "PCIE0_WAKE_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(252, "MSDC0E_DAT5"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 137),
+ MTK_FUNCTION(0, "GPIO252"),
+ MTK_FUNCTION(1, "MSDC3_DAT5"),
+ MTK_FUNCTION(6, "PCIE1_CLKREQ_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(253, "MSDC0E_DAT4"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 138),
+ MTK_FUNCTION(0, "GPIO253"),
+ MTK_FUNCTION(1, "MSDC3_DAT4"),
+ MTK_FUNCTION(6, "PCIE1_WAKE_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(254, "MSDC0E_DAT3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 139),
+ MTK_FUNCTION(0, "GPIO254"),
+ MTK_FUNCTION(1, "MSDC3_DAT3"),
+ MTK_FUNCTION(6, "PCIE2_CLKREQ_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(255, "MSDC0E_DAT2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 140),
+ MTK_FUNCTION(0, "GPIO255"),
+ MTK_FUNCTION(1, "MSDC3_DAT2"),
+ MTK_FUNCTION(6, "PCIE2_WAKE_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(256, "MSDC0E_DAT1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 141),
+ MTK_FUNCTION(0, "GPIO256"),
+ MTK_FUNCTION(1, "MSDC3_DAT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(257, "MSDC0E_DAT0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 142),
+ MTK_FUNCTION(0, "GPIO257"),
+ MTK_FUNCTION(1, "MSDC3_DAT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(258, "MSDC0E_CMD"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 143),
+ MTK_FUNCTION(0, "GPIO258"),
+ MTK_FUNCTION(1, "MSDC3_CMD")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(259, "MSDC0E_CLK"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 144),
+ MTK_FUNCTION(0, "GPIO259"),
+ MTK_FUNCTION(1, "MSDC3_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(260, "MSDC0E_DSL"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 145),
+ MTK_FUNCTION(0, "GPIO260"),
+ MTK_FUNCTION(1, "MSDC3_DSL")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(261, "MSDC1_INS"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 146),
+ MTK_FUNCTION(0, "GPIO261"),
+ MTK_FUNCTION(1, "MSDC1_INS"),
+ MTK_FUNCTION(7, "DBG_MON_B[29]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(262, "G2_TXEN"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 8),
+ MTK_FUNCTION(0, "GPIO262"),
+ MTK_FUNCTION(1, "G2_TXEN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(263, "G2_TXD3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 9),
+ MTK_FUNCTION(0, "GPIO263"),
+ MTK_FUNCTION(1, "G2_TXD3"),
+ MTK_FUNCTION(6, "ANT_SEL5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(264, "G2_TXD2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 10),
+ MTK_FUNCTION(0, "GPIO264"),
+ MTK_FUNCTION(1, "G2_TXD2"),
+ MTK_FUNCTION(6, "ANT_SEL4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(265, "G2_TXD1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 11),
+ MTK_FUNCTION(0, "GPIO265"),
+ MTK_FUNCTION(1, "G2_TXD1"),
+ MTK_FUNCTION(6, "ANT_SEL3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(266, "G2_TXD0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO266"),
+ MTK_FUNCTION(1, "G2_TXD0"),
+ MTK_FUNCTION(6, "ANT_SEL2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(267, "G2_TXC"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO267"),
+ MTK_FUNCTION(1, "G2_TXC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(268, "G2_RXC"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO268"),
+ MTK_FUNCTION(1, "G2_RXC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(269, "G2_RXD0"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO269"),
+ MTK_FUNCTION(1, "G2_RXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(270, "G2_RXD1"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO270"),
+ MTK_FUNCTION(1, "G2_RXD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(271, "G2_RXD2"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO271"),
+ MTK_FUNCTION(1, "G2_RXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(272, "G2_RXD3"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO272"),
+ MTK_FUNCTION(1, "G2_RXD3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(273, "ESW_INT"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 168),
+ MTK_FUNCTION(0, "GPIO273"),
+ MTK_FUNCTION(1, "ESW_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(274, "G2_RXDV"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO274"),
+ MTK_FUNCTION(1, "G2_RXDV")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(275, "MDC"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO275"),
+ MTK_FUNCTION(1, "MDC"),
+ MTK_FUNCTION(6, "ANT_SEL0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(276, "MDIO"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO276"),
+ MTK_FUNCTION(1, "MDIO"),
+ MTK_FUNCTION(6, "ANT_SEL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(277, "ESW_RST"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO277"),
+ MTK_FUNCTION(1, "ESW_RST")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(278, "JTAG_RESET"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(0, 147),
+ MTK_FUNCTION(0, "GPIO278"),
+ MTK_FUNCTION(1, "JTAG_RESET")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(279, "USB3_RES_BOND"),
+ NULL, "mt2701",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO279"),
+ MTK_FUNCTION(1, "USB3_RES_BOND")
+ ),
+};
+
+#endif /* __PINCTRL_MTK_MT2701_H */
--- /dev/null
+/*
+ * Copyright (c) 2016 John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PINCTRL_MTK_MT7623_H
+#define __PINCTRL_MTK_MT7623_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mtk-common.h"
+
+static const struct mtk_desc_pin mtk_pins_mt7623[] = {
+ MTK_PIN(
+ PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
+ "J20", "mt7623",
+ MTK_EINT_FUNCTION(0, 148),
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "PWRAP_SPIDO"),
+ MTK_FUNCTION(2, "PWRAP_SPIDI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
+ "D10", "mt7623",
+ MTK_EINT_FUNCTION(0, 149),
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "PWRAP_SPIDI"),
+ MTK_FUNCTION(2, "PWRAP_SPIDO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(2, "PWRAP_INT"),
+ "E11", "mt7623",
+ MTK_EINT_FUNCTION(0, 150),
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "PWRAP_INT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
+ "H12", "mt7623",
+ MTK_EINT_FUNCTION(0, 151),
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "PWRAP_SPICK_I")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
+ "E12", "mt7623",
+ MTK_EINT_FUNCTION(0, 152),
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
+ "H11", "mt7623",
+ MTK_EINT_FUNCTION(0, 155),
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "PWRAP_SPICK2_I")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
+ "G11", "mt7623",
+ MTK_EINT_FUNCTION(0, 156),
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "PWRAP_SPICS2_B_I")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(7, "SPI1_CSN"),
+ "G19", "mt7623",
+ MTK_EINT_FUNCTION(0, 153),
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "SPI1_CS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(8, "SPI1_MI"),
+ "F19", "mt7623",
+ MTK_EINT_FUNCTION(0, 154),
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "SPI1_MI"),
+ MTK_FUNCTION(2, "SPI1_MO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(9, "SPI1_MO"),
+ "G20", "mt7623",
+ MTK_EINT_FUNCTION(0, 157),
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "SPI1_MO"),
+ MTK_FUNCTION(2, "SPI1_MI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(10, "RTC32K_CK"),
+ "A13", "mt7623",
+ MTK_EINT_FUNCTION(0, 158),
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "RTC32K_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(11, "WATCHDOG"),
+ "D14", "mt7623",
+ MTK_EINT_FUNCTION(0, 159),
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "WATCHDOG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(12, "SRCLKENA"),
+ "C13", "mt7623",
+ MTK_EINT_FUNCTION(0, 169),
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "SRCLKENA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(13, "SRCLKENAI"),
+ "B13", "mt7623",
+ MTK_EINT_FUNCTION(0, 161),
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "SRCLKENAI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(14, "GPIO14"),
+ "E18", "mt7623",
+ MTK_EINT_FUNCTION(0, 162),
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "URXD2"),
+ MTK_FUNCTION(2, "UTXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(15, "GPIO15"),
+ "E17", "mt7623",
+ MTK_EINT_FUNCTION(0, 163),
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "UTXD2"),
+ MTK_FUNCTION(2, "URXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(16, "GPIO16"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO16")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(17, "GPIO17"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO17")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(18, "PCM_CLK"),
+ "C19", "mt7623",
+ MTK_EINT_FUNCTION(0, 166),
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "PCM_CLK0"),
+ MTK_FUNCTION(6, "AP_PCM_CLKO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(19, "PCM_SYNC"),
+ "D19", "mt7623",
+ MTK_EINT_FUNCTION(0, 167),
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "PCM_SYNC"),
+ MTK_FUNCTION(6, "AP_PCM_SYNC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(20, "PCM_RX"),
+ "D18", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "PCM_RX"),
+ MTK_FUNCTION(4, "PCM_TX"),
+ MTK_FUNCTION(6, "AP_PCM_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(21, "PCM_TX"),
+ "C18", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "PCM_TX"),
+ MTK_FUNCTION(4, "PCM_RX"),
+ MTK_FUNCTION(6, "AP_PCM_TX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(22, "EINT0"),
+ "H15", "mt7623",
+ MTK_EINT_FUNCTION(0, 0),
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "UCTS0"),
+ MTK_FUNCTION(2, "PCIE0_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(23, "EINT1"),
+ "J16", "mt7623",
+ MTK_EINT_FUNCTION(0, 1),
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "URTS0"),
+ MTK_FUNCTION(2, "PCIE1_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(24, "EINT2"),
+ "H16", "mt7623",
+ MTK_EINT_FUNCTION(0, 2),
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "UCTS1"),
+ MTK_FUNCTION(2, "PCIE2_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(25, "EINT3"),
+ "K15", "mt7623",
+ MTK_EINT_FUNCTION(0, 3),
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "URTS1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(26, "EINT4"),
+ "G15", "mt7623",
+ MTK_EINT_FUNCTION(0, 4),
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "UCTS3"),
+ MTK_FUNCTION(6, "PCIE2_WAKE_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(27, "EINT5"),
+ "F15", "mt7623",
+ MTK_EINT_FUNCTION(0, 5),
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "URTS3"),
+ MTK_FUNCTION(6, "PCIE1_WAKE_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(28, "EINT6"),
+ "J15", "mt7623",
+ MTK_EINT_FUNCTION(0, 6),
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "DRV_VBUS"),
+ MTK_FUNCTION(6, "PCIE0_WAKE_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(29, "EINT7"),
+ "E15", "mt7623",
+ MTK_EINT_FUNCTION(0, 7),
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "IDDIG"),
+ MTK_FUNCTION(2, "MSDC1_WP"),
+ MTK_FUNCTION(6, "PCIE2_PERST_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(30, "GPIO30"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO30")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(31, "GPIO31"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO31")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(32, "GPIO32"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO32")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(33, "I2S1_DATA"),
+ "Y18", "mt7623",
+ MTK_EINT_FUNCTION(0, 15),
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "I2S1_DATA"),
+ MTK_FUNCTION(3, "PCM_TX"),
+ MTK_FUNCTION(6, "AP_PCM_TX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(34, "I2S1_DATA_IN"),
+ "Y17", "mt7623",
+ MTK_EINT_FUNCTION(0, 16),
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "I2S1_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX"),
+ MTK_FUNCTION(6, "AP_PCM_RX")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(35, "I2S1_BCK"),
+ "V17", "mt7623",
+ MTK_EINT_FUNCTION(0, 17),
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "I2S1_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0"),
+ MTK_FUNCTION(6, "AP_PCM_CLKO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(36, "I2S1_LRCK"),
+ "W17", "mt7623",
+ MTK_EINT_FUNCTION(0, 18),
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "I2S1_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC"),
+ MTK_FUNCTION(6, "AP_PCM_SYNC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(37, "I2S1_MCLK"),
+ "AA18", "mt7623",
+ MTK_EINT_FUNCTION(0, 19),
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "I2S1_MCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(38, "GPIO38"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO38")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(39, "JTMS"),
+ "G21", "mt7623",
+ MTK_EINT_FUNCTION(0, 21),
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "JTMS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(40, "GPIO40"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO40")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(41, "JTDI"),
+ "H22", "mt7623",
+ MTK_EINT_FUNCTION(0, 23),
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "JTDI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(42, "JTDO"),
+ "H21", "mt7623",
+ MTK_EINT_FUNCTION(0, 24),
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "JTDO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(43, "NCLE"),
+ "C7", "mt7623",
+ MTK_EINT_FUNCTION(0, 25),
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "NCLE"),
+ MTK_FUNCTION(2, "EXT_XCS2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(44, "NCEB1"),
+ "C6", "mt7623",
+ MTK_EINT_FUNCTION(0, 26),
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "NCEB1"),
+ MTK_FUNCTION(2, "IDDIG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(45, "NCEB0"),
+ "D7", "mt7623",
+ MTK_EINT_FUNCTION(0, 27),
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "NCEB0"),
+ MTK_FUNCTION(2, "DRV_VBUS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(46, "IR"),
+ "D15", "mt7623",
+ MTK_EINT_FUNCTION(0, 28),
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "IR")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(47, "NREB"),
+ "A6", "mt7623",
+ MTK_EINT_FUNCTION(0, 29),
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "NREB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(48, "NRNB"),
+ "B6", "mt7623",
+ MTK_EINT_FUNCTION(0, 30),
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "NRNB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(49, "I2S0_DATA"),
+ "AB18", "mt7623",
+ MTK_EINT_FUNCTION(0, 31),
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "I2S0_DATA"),
+ MTK_FUNCTION(3, "PCM_TX"),
+ MTK_FUNCTION(6, "AP_I2S_DO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(50, "GPIO50"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO50")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(51, "GPIO51"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO51")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(52, "GPIO52"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO52")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(53, "SPI0_CSN"),
+ "E7", "mt7623",
+ MTK_EINT_FUNCTION(0, 35),
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "SPI0_CS"),
+ MTK_FUNCTION(5, "PWM1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(54, "SPI0_CK"),
+ "F7", "mt7623",
+ MTK_EINT_FUNCTION(0, 36),
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "SPI0_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(55, "SPI0_MI"),
+ "E6", "mt7623",
+ MTK_EINT_FUNCTION(0, 37),
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "SPI0_MI"),
+ MTK_FUNCTION(2, "SPI0_MO"),
+ MTK_FUNCTION(3, "MSDC1_WP"),
+ MTK_FUNCTION(5, "PWM2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(56, "SPI0_MO"),
+ "G7", "mt7623",
+ MTK_EINT_FUNCTION(0, 38),
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "SPI0_MO"),
+ MTK_FUNCTION(2, "SPI0_MI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(57, "GPIO57"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO57")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(58, "GPIO58"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO58")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(59, "GPIO59"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO59")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(60, "WB_RSTB"),
+ "Y21", "mt7623",
+ MTK_EINT_FUNCTION(0, 41),
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "WB_RSTB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(61, "GPIO61"),
+ "AA21", "mt7623",
+ MTK_EINT_FUNCTION(0, 42),
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "TEST_FD")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(62, "GPIO62"),
+ "AB22", "mt7623",
+ MTK_EINT_FUNCTION(0, 43),
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "TEST_FC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(63, "WB_SCLK"),
+ "AC23", "mt7623",
+ MTK_EINT_FUNCTION(0, 44),
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "WB_SCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(64, "WB_SDATA"),
+ "AB21", "mt7623",
+ MTK_EINT_FUNCTION(0, 45),
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "WB_SDATA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(65, "WB_SEN"),
+ "AB24", "mt7623",
+ MTK_EINT_FUNCTION(0, 46),
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "WB_SEN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(66, "WB_CRTL0"),
+ "AB20", "mt7623",
+ MTK_EINT_FUNCTION(0, 47),
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "WB_CRTL0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(67, "WB_CRTL1"),
+ "AC20", "mt7623",
+ MTK_EINT_FUNCTION(0, 48),
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "WB_CRTL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(68, "WB_CRTL2"),
+ "AB19", "mt7623",
+ MTK_EINT_FUNCTION(0, 49),
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "WB_CRTL2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(69, "WB_CRTL3"),
+ "AC19", "mt7623",
+ MTK_EINT_FUNCTION(0, 50),
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "WB_CRTL3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(70, "WB_CRTL4"),
+ "AD19", "mt7623",
+ MTK_EINT_FUNCTION(0, 51),
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "WB_CRTL4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(71, "WB_CRTL5"),
+ "AE19", "mt7623",
+ MTK_EINT_FUNCTION(0, 52),
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "WB_CRTL5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(72, "I2S0_DATA_IN"),
+ "AA20", "mt7623",
+ MTK_EINT_FUNCTION(0, 53),
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "I2S0_DATA_IN"),
+ MTK_FUNCTION(3, "PCM_RX"),
+ MTK_FUNCTION(4, "PWM0"),
+ MTK_FUNCTION(5, "DISP_PWM"),
+ MTK_FUNCTION(6, "AP_I2S_DI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(73, "I2S0_LRCK"),
+ "Y20", "mt7623",
+ MTK_EINT_FUNCTION(0, 54),
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "I2S0_LRCK"),
+ MTK_FUNCTION(3, "PCM_SYNC"),
+ MTK_FUNCTION(6, "AP_I2S_LRCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(74, "I2S0_BCK"),
+ "Y19", "mt7623",
+ MTK_EINT_FUNCTION(0, 55),
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "I2S0_BCK"),
+ MTK_FUNCTION(3, "PCM_CLK0"),
+ MTK_FUNCTION(6, "AP_I2S_BCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(75, "SDA0"),
+ "K19", "mt7623",
+ MTK_EINT_FUNCTION(0, 56),
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "SDA0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(76, "SCL0"),
+ "K20", "mt7623",
+ MTK_EINT_FUNCTION(0, 57),
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "SCL0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(77, "GPIO77"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO77")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(78, "GPIO78"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO78")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(79, "GPIO79"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO79")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(80, "GPIO80"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO80")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(81, "GPIO81"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO81")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(82, "GPIO82"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO82")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(83, "LCM_RST"),
+ "V16", "mt7623",
+ MTK_EINT_FUNCTION(0, 64),
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "LCM_RST")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(84, "DSI_TE"),
+ "V14", "mt7623",
+ MTK_EINT_FUNCTION(0, 65),
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "DSI_TE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(85, "GPIO85"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO85")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(86, "GPIO86"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO86")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(87, "GPIO87"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO87")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(88, "GPIO88"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO88")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(89, "GPIO89"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO89")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(90, "GPIO90"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO90")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(91, "GPIO91"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO91")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(92, "GPIO92"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO92")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(93, "GPIO93"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO93")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(94, "GPIO94"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO94")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(95, "MIPI_TCN"),
+ "AB14", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "TCN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(96, "MIPI_TCP"),
+ "AC14", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(1, "TCP")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(97, "MIPI_TDN1"),
+ "AE15", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "TDN1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(98, "MIPI_TDP1"),
+ "AD15", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "TDP1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(99, "MIPI_TDN0"),
+ "AB15", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "TDN0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(100, "MIPI_TDP0"),
+ "AC15", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "TDP0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(101, "GPIO101"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO101")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(102, "GPIO102"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO102")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(103, "GPIO103"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO103")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(104, "GPIO104"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO104")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(105, "MSDC1_CMD"),
+ "AD2", "mt7623",
+ MTK_EINT_FUNCTION(0, 78),
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(6, "I2SOUT_BCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(106, "MSDC1_CLK"),
+ "AD3", "mt7623",
+ MTK_EINT_FUNCTION(0, 79),
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(6, "I2SOUT_LRCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(107, "MSDC1_DAT0"),
+ "AE2", "mt7623",
+ MTK_EINT_FUNCTION(0, 80),
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION(5, "UTXD0"),
+ MTK_FUNCTION(6, "I2SOUT_DATA_OUT")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(108, "MSDC1_DAT1"),
+ "AC1", "mt7623",
+ MTK_EINT_FUNCTION(0, 81),
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(5, "URXD0"),
+ MTK_FUNCTION(6, "PWM1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(109, "MSDC1_DAT2"),
+ "AC3", "mt7623",
+ MTK_EINT_FUNCTION(0, 82),
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION(3, "SDA2"),
+ MTK_FUNCTION(5, "UTXD1"),
+ MTK_FUNCTION(6, "PWM2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(110, "MSDC1_DAT3"),
+ "AC4", "mt7623",
+ MTK_EINT_FUNCTION(0, 83),
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION(3, "SCL2"),
+ MTK_FUNCTION(5, "URXD1"),
+ MTK_FUNCTION(6, "PWM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(111, "MSDC0_DAT7"),
+ "A2", "mt7623",
+ MTK_EINT_FUNCTION(0, 84),
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "MSDC0_DAT7"),
+ MTK_FUNCTION(4, "NLD7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(112, "MSDC0_DAT6"),
+ "B3", "mt7623",
+ MTK_EINT_FUNCTION(0, 85),
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "MSDC0_DAT6"),
+ MTK_FUNCTION(4, "NLD6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(113, "MSDC0_DAT5"),
+ "C4", "mt7623",
+ MTK_EINT_FUNCTION(0, 86),
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "MSDC0_DAT5"),
+ MTK_FUNCTION(4, "NLD5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(114, "MSDC0_DAT4"),
+ "A4", "mt7623",
+ MTK_EINT_FUNCTION(0, 87),
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "MSDC0_DAT4"),
+ MTK_FUNCTION(4, "NLD4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(115, "MSDC0_RSTB"),
+ "C5", "mt7623",
+ MTK_EINT_FUNCTION(0, 88),
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "MSDC0_RSTB"),
+ MTK_FUNCTION(4, "NLD8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(116, "MSDC0_CMD"),
+ "D5", "mt7623",
+ MTK_EINT_FUNCTION(0, 89),
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "MSDC0_CMD"),
+ MTK_FUNCTION(4, "NALE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(117, "MSDC0_CLK"),
+ "B1", "mt7623",
+ MTK_EINT_FUNCTION(0, 90),
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "MSDC0_CLK"),
+ MTK_FUNCTION(4, "NWEB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(118, "MSDC0_DAT3"),
+ "D6", "mt7623",
+ MTK_EINT_FUNCTION(0, 91),
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "MSDC0_DAT3"),
+ MTK_FUNCTION(4, "NLD3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(119, "MSDC0_DAT2"),
+ "B2", "mt7623",
+ MTK_EINT_FUNCTION(0, 92),
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "MSDC0_DAT2"),
+ MTK_FUNCTION(4, "NLD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(120, "MSDC0_DAT1"),
+ "A3", "mt7623",
+ MTK_EINT_FUNCTION(0, 93),
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "MSDC0_DAT1"),
+ MTK_FUNCTION(4, "NLD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(121, "MSDC0_DAT0"),
+ "B4", "mt7623",
+ MTK_EINT_FUNCTION(0, 94),
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "MSDC0_DAT0"),
+ MTK_FUNCTION(4, "NLD0"),
+ MTK_FUNCTION(5, "WATCHDOG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(122, "GPIO122"),
+ "H17", "mt7623",
+ MTK_EINT_FUNCTION(0, 95),
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "TEST"),
+ MTK_FUNCTION(4, "SDA2"),
+ MTK_FUNCTION(5, "URXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(123, "GPIO123"),
+ "F17", "mt7623",
+ MTK_EINT_FUNCTION(0, 96),
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "TEST"),
+ MTK_FUNCTION(4, "SCL2"),
+ MTK_FUNCTION(5, "UTXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(124, "GPIO124"),
+ "H18", "mt7623",
+ MTK_EINT_FUNCTION(0, 97),
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "TEST"),
+ MTK_FUNCTION(4, "SDA1"),
+ MTK_FUNCTION(5, "PWM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(125, "GPIO125"),
+ "G17", "mt7623",
+ MTK_EINT_FUNCTION(0, 98),
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "TEST"),
+ MTK_FUNCTION(4, "SCL1"),
+ MTK_FUNCTION(5, "PWM4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(126, "I2S0_MCLK"),
+ "AA19", "mt7623",
+ MTK_EINT_FUNCTION(0, 99),
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "I2S0_MCLK"),
+ MTK_FUNCTION(6, "AP_I2S_MCLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(127, "GPIO127"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO127")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(128, "GPIO128"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO128")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(129, "GPIO129"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO129")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(130, "GPIO130"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO130")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(131, "GPIO131"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO131")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(132, "GPIO132"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO132")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(133, "GPIO133"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO133")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(134, "GPIO134"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO134")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(135, "GPIO135"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO135")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(136, "GPIO136"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO136")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(137, "GPIO137"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO137")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(138, "GPIO138"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO138")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(139, "GPIO139"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO139")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(140, "GPIO140"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO140")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(141, "GPIO141"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO141")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(142, "GPIO142"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO142")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(143, "GPIO143"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO143")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(144, "GPIO144"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO144")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(145, "GPIO145"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO145")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(146, "GPIO146"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO146")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(147, "GPIO147"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO147")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(148, "GPIO148"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO148")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(149, "GPIO149"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO149")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(150, "GPIO150"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO150")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(151, "GPIO151"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO151")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(152, "GPIO152"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO152")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(153, "GPIO153"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO153")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(154, "GPIO154"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO154")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(155, "GPIO155"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO155")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(156, "GPIO156"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO156")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(157, "GPIO157"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO157")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(158, "GPIO158"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO158")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(159, "GPIO159"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO159")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(160, "GPIO160"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO160")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(161, "GPIO161"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO161")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(162, "GPIO162"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO162")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(163, "GPIO163"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO163")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(164, "GPIO164"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO164")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(165, "GPIO165"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO165")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(166, "GPIO166"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO166")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(167, "GPIO167"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO167")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(168, "GPIO168"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO168")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(169, "GPIO169"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO169")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(170, "GPIO170"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO170")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(171, "GPIO171"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO171")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(172, "GPIO172"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO172")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(173, "GPIO173"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO173")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(174, "GPIO174"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO174")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(175, "GPIO175"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO175")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(176, "GPIO176"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO176")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(177, "GPIO177"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO177")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(178, "GPIO178"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO178")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(179, "GPIO179"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO179")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(180, "GPIO180"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO180")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(181, "GPIO181"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO181")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(182, "GPIO182"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO182")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(183, "GPIO183"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO183")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(184, "GPIO184"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO184")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(185, "GPIO185"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO185")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(186, "GPIO186"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO186")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(187, "GPIO187"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO187")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(188, "GPIO188"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO188")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(189, "GPIO189"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO189")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(190, "GPIO190"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO190")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(191, "GPIO191"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO191")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(192, "GPIO192"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO192")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(193, "GPIO193"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO193")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(194, "GPIO194"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO194")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(195, "GPIO195"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO195")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(196, "GPIO196"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO196")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(197, "GPIO197"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO197")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(198, "GPIO198"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO198")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(199, "SPI1_CK"),
+ "E19", "mt7623",
+ MTK_EINT_FUNCTION(0, 111),
+ MTK_FUNCTION(0, "GPIO199"),
+ MTK_FUNCTION(1, "SPI1_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(200, "URXD2"),
+ "K18", "mt7623",
+ MTK_EINT_FUNCTION(0, 112),
+ MTK_FUNCTION(0, "GPIO200"),
+ MTK_FUNCTION(6, "URXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(201, "UTXD2"),
+ "L18", "mt7623",
+ MTK_EINT_FUNCTION(0, 113),
+ MTK_FUNCTION(0, "GPIO201"),
+ MTK_FUNCTION(6, "UTXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(202, "GPIO202"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO202")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(203, "PWM0"),
+ "AA16", "mt7623",
+ MTK_EINT_FUNCTION(0, 115),
+ MTK_FUNCTION(0, "GPIO203"),
+ MTK_FUNCTION(1, "PWM0"),
+ MTK_FUNCTION(2, "DISP_PWM")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(204, "PWM1"),
+ "Y16", "mt7623",
+ MTK_EINT_FUNCTION(0, 116),
+ MTK_FUNCTION(0, "GPIO204"),
+ MTK_FUNCTION(1, "PWM1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(205, "PWM2"),
+ "AA15", "mt7623",
+ MTK_EINT_FUNCTION(0, 117),
+ MTK_FUNCTION(0, "GPIO205"),
+ MTK_FUNCTION(1, "PWM2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(206, "PWM3"),
+ "AA17", "mt7623",
+ MTK_EINT_FUNCTION(0, 118),
+ MTK_FUNCTION(0, "GPIO206"),
+ MTK_FUNCTION(1, "PWM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(207, "PWM4"),
+ "Y15", "mt7623",
+ MTK_EINT_FUNCTION(0, 119),
+ MTK_FUNCTION(0, "GPIO207"),
+ MTK_FUNCTION(1, "PWM4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(208, "AUD_EXT_CK1"),
+ "W14", "mt7623",
+ MTK_EINT_FUNCTION(0, 120),
+ MTK_FUNCTION(0, "GPIO208"),
+ MTK_FUNCTION(1, "AUD_EXT_CK1"),
+ MTK_FUNCTION(2, "PWM0"),
+ MTK_FUNCTION(3, "PCIE0_PERST_N"),
+ MTK_FUNCTION(5, "DISP_PWM")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(209, "AUD_EXT_CK2"),
+ "V15", "mt7623",
+ MTK_EINT_FUNCTION(0, 121),
+ MTK_FUNCTION(0, "GPIO209"),
+ MTK_FUNCTION(1, "AUD_EXT_CK2"),
+ MTK_FUNCTION(2, "MSDC1_WP"),
+ MTK_FUNCTION(3, "PCIE1_PERST_N"),
+ MTK_FUNCTION(5, "PWM1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(210, "GPIO210"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO210")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(211, "GPIO211"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO211")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(212, "GPIO212"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO212")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(213, "GPIO213"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO213")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(214, "GPIO214"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO214")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(215, "GPIO215"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO215")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(216, "GPIO216"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO216")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(217, "GPIO217"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO217")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(218, "GPIO218"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO218")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(219, "GPIO219"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO219")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(220, "GPIO220"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO220")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(221, "GPIO221"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO221")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(222, "GPIO222"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO222")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(223, "GPIO223"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO223")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(224, "GPIO224"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO224")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(225, "GPIO225"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO225")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(226, "GPIO226"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO226")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(227, "GPIO227"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO227")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(228, "GPIO228"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO228")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(229, "GPIO229"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO229")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(230, "GPIO230"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO230")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(231, "GPIO231"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO231")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(232, "GPIO232"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO232")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(233, "GPIO233"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO233")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(234, "GPIO234"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO234")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(235, "GPIO235"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO235")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(236, "EXT_SDIO3"),
+ "A8", "mt7623",
+ MTK_EINT_FUNCTION(0, 122),
+ MTK_FUNCTION(0, "GPIO236"),
+ MTK_FUNCTION(1, "EXT_SDIO3"),
+ MTK_FUNCTION(2, "IDDIG")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(237, "EXT_SDIO2"),
+ "D8", "mt7623",
+ MTK_EINT_FUNCTION(0, 123),
+ MTK_FUNCTION(0, "GPIO237"),
+ MTK_FUNCTION(1, "EXT_SDIO2"),
+ MTK_FUNCTION(2, "DRV_VBUS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(238, "EXT_SDIO1"),
+ "D9", "mt7623",
+ MTK_EINT_FUNCTION(0, 124),
+ MTK_FUNCTION(0, "GPIO238"),
+ MTK_FUNCTION(1, "EXT_SDIO1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(239, "EXT_SDIO0"),
+ "B8", "mt7623",
+ MTK_EINT_FUNCTION(0, 125),
+ MTK_FUNCTION(0, "GPIO239"),
+ MTK_FUNCTION(1, "EXT_SDIO0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(240, "EXT_XCS"),
+ "C9", "mt7623",
+ MTK_EINT_FUNCTION(0, 126),
+ MTK_FUNCTION(0, "GPIO240"),
+ MTK_FUNCTION(1, "EXT_XCS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(241, "EXT_SCK"),
+ "C8", "mt7623",
+ MTK_EINT_FUNCTION(0, 127),
+ MTK_FUNCTION(0, "GPIO241"),
+ MTK_FUNCTION(1, "EXT_SCK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(242, "URTS2"),
+ "G18", "mt7623",
+ MTK_EINT_FUNCTION(0, 128),
+ MTK_FUNCTION(0, "GPIO242"),
+ MTK_FUNCTION(1, "URTS2"),
+ MTK_FUNCTION(2, "UTXD3"),
+ MTK_FUNCTION(3, "URXD3"),
+ MTK_FUNCTION(4, "SCL1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(243, "UCTS2"),
+ "H19", "mt7623",
+ MTK_EINT_FUNCTION(0, 129),
+ MTK_FUNCTION(0, "GPIO243"),
+ MTK_FUNCTION(1, "UCTS2"),
+ MTK_FUNCTION(2, "URXD3"),
+ MTK_FUNCTION(3, "UTXD3"),
+ MTK_FUNCTION(4, "SDA1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(244, "GPIO244"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO244")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(245, "GPIO245"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO245")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(246, "GPIO246"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO246")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(247, "GPIO247"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO247")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(248, "GPIO248"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO248")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(249, "GPIO249"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO249")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(250, "GPIO250"),
+ "A15", "mt7623",
+ MTK_EINT_FUNCTION(0, 135),
+ MTK_FUNCTION(0, "GPIO250"),
+ MTK_FUNCTION(1, "TEST_MD7"),
+ MTK_FUNCTION(6, "PCIE0_CLKREQ_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(251, "GPIO251"),
+ "B15", "mt7623",
+ MTK_EINT_FUNCTION(0, 136),
+ MTK_FUNCTION(0, "GPIO251"),
+ MTK_FUNCTION(1, "TEST_MD6"),
+ MTK_FUNCTION(6, "PCIE0_WAKE_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(252, "GPIO252"),
+ "C16", "mt7623",
+ MTK_EINT_FUNCTION(0, 137),
+ MTK_FUNCTION(0, "GPIO252"),
+ MTK_FUNCTION(1, "TEST_MD5"),
+ MTK_FUNCTION(6, "PCIE1_CLKREQ_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(253, "GPIO253"),
+ "D17", "mt7623",
+ MTK_EINT_FUNCTION(0, 138),
+ MTK_FUNCTION(0, "GPIO253"),
+ MTK_FUNCTION(1, "TEST_MD4"),
+ MTK_FUNCTION(6, "PCIE1_WAKE_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(254, "GPIO254"),
+ "D16", "mt7623",
+ MTK_EINT_FUNCTION(0, 139),
+ MTK_FUNCTION(0, "GPIO254"),
+ MTK_FUNCTION(1, "TEST_MD3"),
+ MTK_FUNCTION(6, "PCIE2_CLKREQ_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(255, "GPIO255"),
+ "C17", "mt7623",
+ MTK_EINT_FUNCTION(0, 140),
+ MTK_FUNCTION(0, "GPIO255"),
+ MTK_FUNCTION(1, "TEST_MD2"),
+ MTK_FUNCTION(6, "PCIE2_WAKE_N")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(256, "GPIO256"),
+ "B17", "mt7623",
+ MTK_EINT_FUNCTION(0, 141),
+ MTK_FUNCTION(0, "GPIO256"),
+ MTK_FUNCTION(1, "TEST_MD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(257, "GPIO257"),
+ "C15", "mt7623",
+ MTK_EINT_FUNCTION(0, 142),
+ MTK_FUNCTION(0, "GPIO257"),
+ MTK_FUNCTION(1, "TEST_MD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(258, "GPIO258"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO258")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(259, "GPIO259"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO259")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(260, "GPIO260"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO260")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(261, "MSDC1_INS"),
+ "AD1", "mt7623",
+ MTK_EINT_FUNCTION(0, 146),
+ MTK_FUNCTION(0, "GPIO261"),
+ MTK_FUNCTION(1, "MSDC1_INS")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(262, "G2_TXEN"),
+ "A23", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO262"),
+ MTK_FUNCTION(1, "G2_TXEN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(263, "G2_TXD3"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO263"),
+ MTK_FUNCTION(1, "G2_TXD3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(264, "G2_TXD2"),
+ "C24", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO264"),
+ MTK_FUNCTION(1, "G2_TXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(265, "G2_TXD1"),
+ "B25", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO265"),
+ MTK_FUNCTION(1, "G2_TXD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(266, "G2_TXD0"),
+ "A24", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO266"),
+ MTK_FUNCTION(1, "G2_TXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(267, "G2_TXCLK"),
+ "C23", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO267"),
+ MTK_FUNCTION(1, "G2_TXC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(268, "G2_RXCLK"),
+ "B23", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO268"),
+ MTK_FUNCTION(1, "G2_RXC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(269, "G2_RXD0"),
+ "D21", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO269"),
+ MTK_FUNCTION(1, "G2_RXD0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(270, "G2_RXD1"),
+ "B22", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO270"),
+ MTK_FUNCTION(1, "G2_RXD1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(271, "G2_RXD2"),
+ "A22", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO271"),
+ MTK_FUNCTION(1, "G2_RXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(272, "G2_RXD3"),
+ "C22", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO272"),
+ MTK_FUNCTION(1, "G2_RXD3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(273, "GPIO273"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO273")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(274, "G2_RXDV"),
+ "C21", "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO274"),
+ MTK_FUNCTION(1, "G2_RXDV")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(275, "G2_MDC"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO275"),
+ MTK_FUNCTION(1, "MDC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(276, "G2_MDIO"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO276"),
+ MTK_FUNCTION(1, "MDIO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(277, "GPIO277"),
+ NULL, "mt7623",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ MTK_FUNCTION(0, "GPIO277")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(278, "JTAG_RESET"),
+ "H20", "mt7623",
+ MTK_EINT_FUNCTION(0, 147),
+ MTK_FUNCTION(0, "GPIO278"),
+ MTK_FUNCTION(1, "JTAG_RESET")
+ ),
+};
+
+#endif /* __PINCTRL_MTK_MT7623_H */
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pinctrl/pinconf-generic.h>
struct meson_bank **bank)
{
struct meson_domain *d;
- int i;
- for (i = 0; i < pc->data->num_domains; i++) {
- d = &pc->domains[i];
- if (pin >= d->data->pin_base &&
- pin < d->data->pin_base + d->data->num_pins) {
- *domain = d;
- return meson_get_bank(d, pin, bank);
- }
+ d = pc->domain;
+
+ if (pin >= d->data->pin_base &&
+ pin < d->data->pin_base + d->data->num_pins) {
+ *domain = d;
+ return meson_get_bank(d, pin, bank);
}
return -EINVAL;
for (j = 0; j < group->num_pins; j++) {
if (group->pins[j] == pin) {
/* We have found a group using the pin */
- domain = &pc->domains[group->domain];
+ domain = pc->domain;
regmap_update_bits(domain->reg_mux,
group->reg * 4,
BIT(group->bit), 0);
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
struct meson_pmx_func *func = &pc->data->funcs[func_num];
struct meson_pmx_group *group = &pc->data->groups[group_num];
- struct meson_domain *domain = &pc->domains[group->domain];
+ struct meson_domain *domain = pc->domain;
int i, ret = 0;
dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
static const struct of_device_id meson_pinctrl_dt_match[] = {
{
- .compatible = "amlogic,meson8-pinctrl",
- .data = &meson8_pinctrl_data,
+ .compatible = "amlogic,meson8-cbus-pinctrl",
+ .data = &meson8_cbus_pinctrl_data,
+ },
+ {
+ .compatible = "amlogic,meson8b-cbus-pinctrl",
+ .data = &meson8b_cbus_pinctrl_data,
+ },
+ {
+ .compatible = "amlogic,meson8-aobus-pinctrl",
+ .data = &meson8_aobus_pinctrl_data,
},
{
- .compatible = "amlogic,meson8b-pinctrl",
- .data = &meson8b_pinctrl_data,
+ .compatible = "amlogic,meson8b-aobus-pinctrl",
+ .data = &meson8b_aobus_pinctrl_data,
},
{ },
};
-MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match);
static int meson_gpiolib_register(struct meson_pinctrl *pc)
{
struct meson_domain *domain;
- int i, ret;
+ int ret;
- for (i = 0; i < pc->data->num_domains; i++) {
- domain = &pc->domains[i];
-
- domain->chip.label = domain->data->name;
- domain->chip.parent = pc->dev;
- domain->chip.request = meson_gpio_request;
- domain->chip.free = meson_gpio_free;
- domain->chip.direction_input = meson_gpio_direction_input;
- domain->chip.direction_output = meson_gpio_direction_output;
- domain->chip.get = meson_gpio_get;
- domain->chip.set = meson_gpio_set;
- domain->chip.base = domain->data->pin_base;
- domain->chip.ngpio = domain->data->num_pins;
- domain->chip.can_sleep = false;
- domain->chip.of_node = domain->of_node;
- domain->chip.of_gpio_n_cells = 2;
-
- ret = gpiochip_add_data(&domain->chip, domain);
- if (ret) {
- dev_err(pc->dev, "can't add gpio chip %s\n",
- domain->data->name);
- goto fail;
- }
+ domain = pc->domain;
+
+ domain->chip.label = domain->data->name;
+ domain->chip.parent = pc->dev;
+ domain->chip.request = meson_gpio_request;
+ domain->chip.free = meson_gpio_free;
+ domain->chip.direction_input = meson_gpio_direction_input;
+ domain->chip.direction_output = meson_gpio_direction_output;
+ domain->chip.get = meson_gpio_get;
+ domain->chip.set = meson_gpio_set;
+ domain->chip.base = domain->data->pin_base;
+ domain->chip.ngpio = domain->data->num_pins;
+ domain->chip.can_sleep = false;
+ domain->chip.of_node = domain->of_node;
+ domain->chip.of_gpio_n_cells = 2;
+
+ ret = gpiochip_add_data(&domain->chip, domain);
+ if (ret) {
+ dev_err(pc->dev, "can't add gpio chip %s\n",
+ domain->data->name);
+ goto fail;
+ }
- ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
- 0, domain->data->pin_base,
- domain->chip.ngpio);
- if (ret) {
- dev_err(pc->dev, "can't add pin range\n");
- goto fail;
- }
+ ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
+ 0, domain->data->pin_base,
+ domain->chip.ngpio);
+ if (ret) {
+ dev_err(pc->dev, "can't add pin range\n");
+ goto fail;
}
return 0;
fail:
- for (i--; i >= 0; i--)
- gpiochip_remove(&pc->domains[i].chip);
+ gpiochip_remove(&pc->domain->chip);
return ret;
}
-static struct meson_domain_data *meson_get_domain_data(struct meson_pinctrl *pc,
- struct device_node *np)
-{
- int i;
-
- for (i = 0; i < pc->data->num_domains; i++) {
- if (!strcmp(np->name, pc->data->domain_data[i].name))
- return &pc->data->domain_data[i];
- }
-
- return NULL;
-}
-
static struct regmap_config meson_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
{
struct device_node *np;
struct meson_domain *domain;
- int i = 0, num_domains = 0;
+ int num_domains = 0;
for_each_child_of_node(node, np) {
if (!of_find_property(np, "gpio-controller", NULL))
num_domains++;
}
- if (num_domains != pc->data->num_domains) {
+ if (num_domains != 1) {
dev_err(pc->dev, "wrong number of subnodes\n");
return -EINVAL;
}
- pc->domains = devm_kzalloc(pc->dev, num_domains *
- sizeof(struct meson_domain), GFP_KERNEL);
- if (!pc->domains)
+ pc->domain = devm_kzalloc(pc->dev, sizeof(struct meson_domain), GFP_KERNEL);
+ if (!pc->domain)
return -ENOMEM;
+ domain = pc->domain;
+ domain->data = pc->data->domain_data;
+
for_each_child_of_node(node, np) {
if (!of_find_property(np, "gpio-controller", NULL))
continue;
- domain = &pc->domains[i];
-
- domain->data = meson_get_domain_data(pc, np);
- if (!domain->data) {
- dev_err(pc->dev, "domain data not found for node %s\n",
- np->name);
- return -ENODEV;
- }
-
domain->of_node = np;
domain->reg_mux = meson_map_resource(pc, np, "mux");
return PTR_ERR(domain->reg_gpio);
}
- i++;
+ break;
}
return 0;
pc->dev = dev;
match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node);
- pc->data = (struct meson_pinctrl_data *)match->data;
+ pc->data = (struct meson_pinctrl_data *) match->data;
ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node);
if (ret)
.of_match_table = meson_pinctrl_dt_match,
},
};
-module_platform_driver(meson_pinctrl_driver);
-
-MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
-MODULE_DESCRIPTION("Amlogic Meson pinctrl driver");
-MODULE_LICENSE("GPL v2");
+builtin_platform_driver(meson_pinctrl_driver);
bool is_gpio;
unsigned int reg;
unsigned int bit;
- unsigned int domain;
};
/**
unsigned int num_pins;
unsigned int num_groups;
unsigned int num_funcs;
- unsigned int num_domains;
};
struct meson_pinctrl {
struct pinctrl_dev *pcdev;
struct pinctrl_desc desc;
struct meson_pinctrl_data *data;
- struct meson_domain *domains;
+ struct meson_domain *domain;
};
#define PIN(x, b) (b + x)
.num_pins = ARRAY_SIZE(grp ## _pins), \
.reg = r, \
.bit = b, \
- .domain = 0, \
}
#define GPIO_GROUP(gpio, b) \
.is_gpio = true, \
}
-#define GROUP_AO(grp, r, b) \
- { \
- .name = #grp, \
- .pins = grp ## _pins, \
- .num_pins = ARRAY_SIZE(grp ## _pins), \
- .reg = r, \
- .bit = b, \
- .domain = 1, \
- }
-
#define FUNCTION(fn) \
{ \
.name = #fn, \
#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
-extern struct meson_pinctrl_data meson8_pinctrl_data;
-extern struct meson_pinctrl_data meson8b_pinctrl_data;
+extern struct meson_pinctrl_data meson8_cbus_pinctrl_data;
+extern struct meson_pinctrl_data meson8_aobus_pinctrl_data;
+extern struct meson_pinctrl_data meson8b_cbus_pinctrl_data;
+extern struct meson_pinctrl_data meson8b_aobus_pinctrl_data;
#define AO_OFF 120
-static const struct pinctrl_pin_desc meson8_pins[] = {
+static const struct pinctrl_pin_desc meson8_cbus_pins[] = {
MESON_PIN(GPIOX_0, 0),
MESON_PIN(GPIOX_1, 0),
MESON_PIN(GPIOX_2, 0),
MESON_PIN(BOOT_16, 0),
MESON_PIN(BOOT_17, 0),
MESON_PIN(BOOT_18, 0),
+};
+
+static const struct pinctrl_pin_desc meson8_aobus_pins[] = {
MESON_PIN(GPIOAO_0, AO_OFF),
MESON_PIN(GPIOAO_1, AO_OFF),
MESON_PIN(GPIOAO_2, AO_OFF),
static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
-static struct meson_pmx_group meson8_groups[] = {
+static struct meson_pmx_group meson8_cbus_groups[] = {
GPIO_GROUP(GPIOX_0, 0),
GPIO_GROUP(GPIOX_1, 0),
GPIO_GROUP(GPIOX_2, 0),
GPIO_GROUP(GPIOZ_12, 0),
GPIO_GROUP(GPIOZ_13, 0),
GPIO_GROUP(GPIOZ_14, 0),
- GPIO_GROUP(GPIOAO_0, AO_OFF),
- GPIO_GROUP(GPIOAO_1, AO_OFF),
- GPIO_GROUP(GPIOAO_2, AO_OFF),
- GPIO_GROUP(GPIOAO_3, AO_OFF),
- GPIO_GROUP(GPIOAO_4, AO_OFF),
- GPIO_GROUP(GPIOAO_5, AO_OFF),
- GPIO_GROUP(GPIOAO_6, AO_OFF),
- GPIO_GROUP(GPIOAO_7, AO_OFF),
- GPIO_GROUP(GPIOAO_8, AO_OFF),
- GPIO_GROUP(GPIOAO_9, AO_OFF),
- GPIO_GROUP(GPIOAO_10, AO_OFF),
- GPIO_GROUP(GPIOAO_11, AO_OFF),
- GPIO_GROUP(GPIOAO_12, AO_OFF),
- GPIO_GROUP(GPIOAO_13, AO_OFF),
- GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
- GPIO_GROUP(GPIO_TEST_N, AO_OFF),
/* bank X */
GROUP(sd_d0_a, 8, 5),
GROUP(sdxc_d0_b, 2, 7),
GROUP(sdxc_clk_b, 2, 5),
GROUP(sdxc_cmd_b, 2, 4),
+};
+
+static struct meson_pmx_group meson8_aobus_groups[] = {
+ GPIO_GROUP(GPIOAO_0, AO_OFF),
+ GPIO_GROUP(GPIOAO_1, AO_OFF),
+ GPIO_GROUP(GPIOAO_2, AO_OFF),
+ GPIO_GROUP(GPIOAO_3, AO_OFF),
+ GPIO_GROUP(GPIOAO_4, AO_OFF),
+ GPIO_GROUP(GPIOAO_5, AO_OFF),
+ GPIO_GROUP(GPIOAO_6, AO_OFF),
+ GPIO_GROUP(GPIOAO_7, AO_OFF),
+ GPIO_GROUP(GPIOAO_8, AO_OFF),
+ GPIO_GROUP(GPIOAO_9, AO_OFF),
+ GPIO_GROUP(GPIOAO_10, AO_OFF),
+ GPIO_GROUP(GPIOAO_11, AO_OFF),
+ GPIO_GROUP(GPIOAO_12, AO_OFF),
+ GPIO_GROUP(GPIOAO_13, AO_OFF),
+ GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
+ GPIO_GROUP(GPIO_TEST_N, AO_OFF),
/* bank AO */
- GROUP_AO(uart_tx_ao_a, 0, 12),
- GROUP_AO(uart_rx_ao_a, 0, 11),
- GROUP_AO(uart_cts_ao_a, 0, 10),
- GROUP_AO(uart_rts_ao_a, 0, 9),
+ GROUP(uart_tx_ao_a, 0, 12),
+ GROUP(uart_rx_ao_a, 0, 11),
+ GROUP(uart_cts_ao_a, 0, 10),
+ GROUP(uart_rts_ao_a, 0, 9),
- GROUP_AO(remote_input, 0, 0),
+ GROUP(remote_input, 0, 0),
- GROUP_AO(i2c_slave_sck_ao, 0, 2),
- GROUP_AO(i2c_slave_sda_ao, 0, 1),
+ GROUP(i2c_slave_sck_ao, 0, 2),
+ GROUP(i2c_slave_sda_ao, 0, 1),
- GROUP_AO(uart_tx_ao_b0, 0, 26),
- GROUP_AO(uart_rx_ao_b0, 0, 25),
+ GROUP(uart_tx_ao_b0, 0, 26),
+ GROUP(uart_rx_ao_b0, 0, 25),
- GROUP_AO(uart_tx_ao_b1, 0, 24),
- GROUP_AO(uart_rx_ao_b1, 0, 23),
+ GROUP(uart_tx_ao_b1, 0, 24),
+ GROUP(uart_rx_ao_b1, 0, 23),
- GROUP_AO(i2c_mst_sck_ao, 0, 6),
- GROUP_AO(i2c_mst_sda_ao, 0, 5),
+ GROUP(i2c_mst_sck_ao, 0, 6),
+ GROUP(i2c_mst_sda_ao, 0, 5),
};
static const char * const gpio_groups[] = {
"i2c_mst_sck_ao", "i2c_mst_sda_ao"
};
-static struct meson_pmx_func meson8_functions[] = {
+static struct meson_pmx_func meson8_cbus_functions[] = {
FUNCTION(gpio),
FUNCTION(sd_a),
FUNCTION(sdxc_a),
FUNCTION(nor),
FUNCTION(sd_b),
FUNCTION(sdxc_b),
+};
+
+static struct meson_pmx_func meson8_aobus_functions[] = {
FUNCTION(uart_ao),
FUNCTION(remote),
FUNCTION(i2c_slave_ao),
FUNCTION(i2c_mst_ao),
};
-static struct meson_bank meson8_banks[] = {
+static struct meson_bank meson8_cbus_banks[] = {
/* name first last pullen pull dir out in */
BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_16, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
};
-static struct meson_bank meson8_ao_banks[] = {
+static struct meson_bank meson8_aobus_banks[] = {
/* name first last pullen pull dir out in */
BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
};
-static struct meson_domain_data meson8_domain_data[] = {
- {
- .name = "banks",
- .banks = meson8_banks,
- .num_banks = ARRAY_SIZE(meson8_banks),
- .pin_base = 0,
- .num_pins = 120,
- },
- {
- .name = "ao-bank",
- .banks = meson8_ao_banks,
- .num_banks = ARRAY_SIZE(meson8_ao_banks),
- .pin_base = 120,
- .num_pins = 16,
- },
-};
-
-struct meson_pinctrl_data meson8_pinctrl_data = {
- .pins = meson8_pins,
- .groups = meson8_groups,
- .funcs = meson8_functions,
- .domain_data = meson8_domain_data,
- .num_pins = ARRAY_SIZE(meson8_pins),
- .num_groups = ARRAY_SIZE(meson8_groups),
- .num_funcs = ARRAY_SIZE(meson8_functions),
- .num_domains = ARRAY_SIZE(meson8_domain_data),
+static struct meson_domain_data meson8_cbus_domain_data = {
+ .name = "cbus-banks",
+ .banks = meson8_cbus_banks,
+ .num_banks = ARRAY_SIZE(meson8_cbus_banks),
+ .pin_base = 0,
+ .num_pins = 120,
+};
+
+static struct meson_domain_data meson8_aobus_domain_data = {
+ .name = "ao-bank",
+ .banks = meson8_aobus_banks,
+ .num_banks = ARRAY_SIZE(meson8_aobus_banks),
+ .pin_base = 120,
+ .num_pins = 16,
+};
+
+struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
+ .pins = meson8_cbus_pins,
+ .groups = meson8_cbus_groups,
+ .funcs = meson8_cbus_functions,
+ .domain_data = &meson8_cbus_domain_data,
+ .num_pins = ARRAY_SIZE(meson8_cbus_pins),
+ .num_groups = ARRAY_SIZE(meson8_cbus_groups),
+ .num_funcs = ARRAY_SIZE(meson8_cbus_functions),
+};
+
+struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
+ .pins = meson8_aobus_pins,
+ .groups = meson8_aobus_groups,
+ .funcs = meson8_aobus_functions,
+ .domain_data = &meson8_aobus_domain_data,
+ .num_pins = ARRAY_SIZE(meson8_aobus_pins),
+ .num_groups = ARRAY_SIZE(meson8_aobus_groups),
+ .num_funcs = ARRAY_SIZE(meson8_aobus_functions),
};
#define AO_OFF 130
-static const struct pinctrl_pin_desc meson8b_pins[] = {
+static const struct pinctrl_pin_desc meson8b_cbus_pins[] = {
MESON_PIN(GPIOX_0, 0),
MESON_PIN(GPIOX_1, 0),
MESON_PIN(GPIOX_2, 0),
MESON_PIN(DIF_3_N, 0),
MESON_PIN(DIF_4_P, 0),
MESON_PIN(DIF_4_N, 0),
+};
+static const struct pinctrl_pin_desc meson8b_aobus_pins[] = {
MESON_PIN(GPIOAO_0, AO_OFF),
MESON_PIN(GPIOAO_1, AO_OFF),
MESON_PIN(GPIOAO_2, AO_OFF),
static const unsigned int eth_mdc_pins[] = { PIN(DIF_4_P, 0) };
static const unsigned int eth_mdio_en_pins[] = { PIN(DIF_4_N, 0) };
-static struct meson_pmx_group meson8b_groups[] = {
+static struct meson_pmx_group meson8b_cbus_groups[] = {
GPIO_GROUP(GPIOX_0, 0),
GPIO_GROUP(GPIOX_1, 0),
GPIO_GROUP(GPIOX_2, 0),
GPIO_GROUP(DIF_4_P, 0),
GPIO_GROUP(DIF_4_N, 0),
- GPIO_GROUP(GPIOAO_0, AO_OFF),
- GPIO_GROUP(GPIOAO_1, AO_OFF),
- GPIO_GROUP(GPIOAO_2, AO_OFF),
- GPIO_GROUP(GPIOAO_3, AO_OFF),
- GPIO_GROUP(GPIOAO_4, AO_OFF),
- GPIO_GROUP(GPIOAO_5, AO_OFF),
- GPIO_GROUP(GPIOAO_6, AO_OFF),
- GPIO_GROUP(GPIOAO_7, AO_OFF),
- GPIO_GROUP(GPIOAO_8, AO_OFF),
- GPIO_GROUP(GPIOAO_9, AO_OFF),
- GPIO_GROUP(GPIOAO_10, AO_OFF),
- GPIO_GROUP(GPIOAO_11, AO_OFF),
- GPIO_GROUP(GPIOAO_12, AO_OFF),
- GPIO_GROUP(GPIOAO_13, AO_OFF),
- GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
- GPIO_GROUP(GPIO_TEST_N, AO_OFF),
-
/* bank X */
GROUP(sd_d0_a, 8, 5),
GROUP(sd_d1_a, 8, 4),
GROUP(sdxc_clk_b, 2, 5),
GROUP(sdxc_cmd_b, 2, 4),
+ /* bank DIF */
+ GROUP(eth_rxd1, 6, 0),
+ GROUP(eth_rxd0, 6, 1),
+ GROUP(eth_rx_dv, 6, 2),
+ GROUP(eth_rx_clk, 6, 3),
+ GROUP(eth_txd0_1, 6, 4),
+ GROUP(eth_txd1_1, 6, 5),
+ GROUP(eth_tx_en, 6, 0),
+ GROUP(eth_ref_clk, 6, 8),
+ GROUP(eth_mdc, 6, 9),
+ GROUP(eth_mdio_en, 6, 10),
+};
+
+static struct meson_pmx_group meson8b_aobus_groups[] = {
+ GPIO_GROUP(GPIOAO_0, AO_OFF),
+ GPIO_GROUP(GPIOAO_1, AO_OFF),
+ GPIO_GROUP(GPIOAO_2, AO_OFF),
+ GPIO_GROUP(GPIOAO_3, AO_OFF),
+ GPIO_GROUP(GPIOAO_4, AO_OFF),
+ GPIO_GROUP(GPIOAO_5, AO_OFF),
+ GPIO_GROUP(GPIOAO_6, AO_OFF),
+ GPIO_GROUP(GPIOAO_7, AO_OFF),
+ GPIO_GROUP(GPIOAO_8, AO_OFF),
+ GPIO_GROUP(GPIOAO_9, AO_OFF),
+ GPIO_GROUP(GPIOAO_10, AO_OFF),
+ GPIO_GROUP(GPIOAO_11, AO_OFF),
+ GPIO_GROUP(GPIOAO_12, AO_OFF),
+ GPIO_GROUP(GPIOAO_13, AO_OFF),
+ GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
+ GPIO_GROUP(GPIO_TEST_N, AO_OFF),
+
/* bank AO */
GROUP(uart_tx_ao_a, 0, 12),
GROUP(uart_rx_ao_a, 0, 11),
GROUP(i2s_in_ch01, 0, 13),
GROUP(i2s_ao_clk_in, 0, 15),
GROUP(i2s_lr_clk_in, 0, 14),
-
- /* bank DIF */
- GROUP(eth_rxd1, 6, 0),
- GROUP(eth_rxd0, 6, 1),
- GROUP(eth_rx_dv, 6, 2),
- GROUP(eth_rx_clk, 6, 3),
- GROUP(eth_txd0_1, 6, 4),
- GROUP(eth_txd1_1, 6, 5),
- GROUP(eth_tx_en, 6, 0),
- GROUP(eth_ref_clk, 6, 8),
- GROUP(eth_mdc, 6, 9),
- GROUP(eth_mdio_en, 6, 10),
};
static const char * const gpio_groups[] = {
};
static const char * const hdmi_groups[] = {
- "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0",
+ "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0"
+};
+
+static const char * const hdmi_cec_groups[] = {
"hdmi_cec_1"
};
"i2c_mst_sck_ao", "i2c_mst_sda_ao"
};
-static const char * const clk_groups[] = {
- "clk_24m_out", "clk_32k_in_out"
+static const char * const clk_24m_groups[] = {
+ "clk_24m_out"
};
-static const char * const spdif_groups[] = {
- "spdif_out_1", "spdif_out_0"
+static const char * const clk_32k_groups[] = {
+ "clk_32k_in_out"
+};
+
+static const char * const spdif_0_groups[] = {
+ "spdif_out_0"
+};
+
+static const char * const spdif_1_groups[] = {
+ "spdif_out_1"
};
static const char * const i2s_groups[] = {
};
static const char * const pwm_c_groups[] = {
- "pwm_c0", "pwm_c1", "pwm_c2"
+ "pwm_c0", "pwm_c1"
+};
+
+static const char * const pwm_c_ao_groups[] = {
+ "pwm_c2"
};
static const char * const pwm_d_groups[] = {
"tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b"
};
-static struct meson_pmx_func meson8b_functions[] = {
+static struct meson_pmx_func meson8b_cbus_functions[] = {
FUNCTION(gpio),
FUNCTION(sd_a),
FUNCTION(sdxc_a),
FUNCTION(nor),
FUNCTION(sd_b),
FUNCTION(sdxc_b),
- FUNCTION(uart_ao),
- FUNCTION(remote),
- FUNCTION(i2c_slave_ao),
- FUNCTION(uart_ao_b),
- FUNCTION(i2c_mst_ao),
- FUNCTION(clk),
- FUNCTION(spdif),
- FUNCTION(i2s),
+ FUNCTION(spdif_0),
FUNCTION(pwm_b),
FUNCTION(pwm_c),
FUNCTION(pwm_d),
FUNCTION(pwm_vs),
FUNCTION(tsin_a),
FUNCTION(tsin_b),
+ FUNCTION(clk_24m),
+};
+
+static struct meson_pmx_func meson8b_aobus_functions[] = {
+ FUNCTION(uart_ao),
+ FUNCTION(uart_ao_b),
+ FUNCTION(i2c_slave_ao),
+ FUNCTION(i2c_mst_ao),
+ FUNCTION(i2s),
+ FUNCTION(remote),
+ FUNCTION(clk_32k),
+ FUNCTION(pwm_c_ao),
+ FUNCTION(spdif_1),
+ FUNCTION(hdmi_cec),
};
-static struct meson_bank meson8b_banks[] = {
+static struct meson_bank meson8b_cbus_banks[] = {
/* name first last pullen pull dir out in */
BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_14, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
BANK("DIF", PIN(DIF_0_P, 0), PIN(DIF_4_N, 0), 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
};
-static struct meson_bank meson8b_ao_banks[] = {
+static struct meson_bank meson8b_aobus_banks[] = {
/* name first last pullen pull dir out in */
BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
};
-static struct meson_domain_data meson8b_domain_data[] = {
- {
- .name = "banks",
- .banks = meson8b_banks,
- .num_banks = ARRAY_SIZE(meson8b_banks),
- .pin_base = 0,
- .num_pins = 130,
- },
- {
- .name = "ao-bank",
- .banks = meson8b_ao_banks,
- .num_banks = ARRAY_SIZE(meson8b_ao_banks),
- .pin_base = 130,
- .num_pins = 16,
- },
-};
-
-struct meson_pinctrl_data meson8b_pinctrl_data = {
- .pins = meson8b_pins,
- .groups = meson8b_groups,
- .funcs = meson8b_functions,
- .domain_data = meson8b_domain_data,
- .num_pins = ARRAY_SIZE(meson8b_pins),
- .num_groups = ARRAY_SIZE(meson8b_groups),
- .num_funcs = ARRAY_SIZE(meson8b_functions),
- .num_domains = ARRAY_SIZE(meson8b_domain_data),
+static struct meson_domain_data meson8b_cbus_domain_data = {
+ .name = "cbus-banks",
+ .banks = meson8b_cbus_banks,
+ .num_banks = ARRAY_SIZE(meson8b_cbus_banks),
+ .pin_base = 0,
+ .num_pins = 130,
+};
+
+static struct meson_domain_data meson8b_aobus_domain_data = {
+ .name = "aobus-banks",
+ .banks = meson8b_aobus_banks,
+ .num_banks = ARRAY_SIZE(meson8b_aobus_banks),
+ .pin_base = 130,
+ .num_pins = 16,
+};
+
+struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
+ .pins = meson8b_cbus_pins,
+ .groups = meson8b_cbus_groups,
+ .funcs = meson8b_cbus_functions,
+ .domain_data = &meson8b_cbus_domain_data,
+ .num_pins = ARRAY_SIZE(meson8b_cbus_pins),
+ .num_groups = ARRAY_SIZE(meson8b_cbus_groups),
+ .num_funcs = ARRAY_SIZE(meson8b_cbus_functions),
+};
+
+struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {
+ .pins = meson8b_aobus_pins,
+ .groups = meson8b_aobus_groups,
+ .funcs = meson8b_aobus_functions,
+ .domain_data = &meson8b_aobus_domain_data,
+ .num_pins = ARRAY_SIZE(meson8b_aobus_pins),
+ .num_groups = ARRAY_SIZE(meson8b_aobus_groups),
+ .num_funcs = ARRAY_SIZE(meson8b_aobus_functions),
};
/* Altfunction B */
static const unsigned u1_b_1_pins[] = { STN8815_PIN_B16, STN8815_PIN_A16 };
static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 };
+static const unsigned clcd_16_23_b_1_pins[] = { STN8815_PIN_AB6,
+ STN8815_PIN_AA6, STN8815_PIN_Y6, STN8815_PIN_Y5, STN8815_PIN_AA5,
+ STN8815_PIN_AB5, STN8815_PIN_AB4, STN8815_PIN_Y4 };
+
#define STN8815_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
+ STN8815_PIN_GROUP(clcd_16_23_b_1, NMK_GPIO_ALT_B),
};
/* We use this macro to define the groups applicable to a function */
STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1");
STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1");
STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1");
+STN8815_FUNC_GROUPS(clcd, "clcd_16_23_b_1");
#define FUNCTION(fname) \
{ \
FUNCTION(i2c1),
FUNCTION(i2c0),
FUNCTION(i2cusb),
+ FUNCTION(clcd),
};
static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = {
gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
resource_size(res));
- if (IS_ERR(gpio_dev->base))
- return PTR_ERR(gpio_dev->base);
+ if (!gpio_dev->base)
+ return -ENOMEM;
irq_base = platform_get_irq(pdev, 0);
if (irq_base < 0) {
.pmxops = &atmel_pmxops,
};
-static int atmel_pctrl_suspend(struct device *dev)
+static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
return 0;
}
-static int atmel_pctrl_resume(struct device *dev)
+static int __maybe_unused atmel_pctrl_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
}
/* Initial configuration */
-static const struct __initconst u300_gpio_confdata
+static const struct u300_gpio_confdata __initconst
bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
/* Port 0, pins 0-7 */
{
#define LPC18XX_SCU_FUNC_PER_PIN 8
+/* LPC18XX SCU pin interrupt select registers */
+#define LPC18XX_SCU_PINTSEL0 0xe00
+#define LPC18XX_SCU_PINTSEL1 0xe04
+#define LPC18XX_SCU_PINTSEL_VAL_MASK 0xff
+#define LPC18XX_SCU_PINTSEL_PORT_SHIFT 5
+#define LPC18XX_SCU_IRQ_PER_PINTSEL 4
+#define LPC18XX_GPIO_PINS_PER_PORT 32
+#define LPC18XX_GPIO_PIN_INT_MAX 8
+
+#define LPC18XX_SCU_PINTSEL_VAL(val, n) \
+ ((val) << (((n) % LPC18XX_SCU_IRQ_PER_PINTSEL) * 8))
+
/* LPC18xx pin types */
enum {
TYPE_ND, /* Normal-drive */
LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA),
};
+/**
+ * enum lpc18xx_pin_config_param - possible pin configuration parameters
+ * @PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt
+ * controller.
+ */
+enum lpc18xx_pin_config_param {
+ PIN_CONFIG_GPIO_PIN_INT = PIN_CONFIG_END + 1,
+};
+
+static const struct pinconf_generic_params lpc18xx_params[] = {
+ {"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0},
+};
+
+#ifdef CONFIG_DEBUG_FS
+static const struct pin_config_item lpc18xx_conf_items[ARRAY_SIZE(lpc18xx_params)] = {
+ PCONFDUMP(PIN_CONFIG_GPIO_PIN_INT, "gpio pin int", NULL, true),
+};
+#endif
+
static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg)
{
switch (param) {
return 0;
}
-static int lpc18xx_pconf_get_pin(enum pin_config_param param, int *arg, u32 reg,
+static int lpc18xx_pin_to_gpio(struct pinctrl_dev *pctldev, unsigned pin)
+{
+ struct pinctrl_gpio_range *range;
+
+ range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
+ if (!range)
+ return -EINVAL;
+
+ return pin - range->pin_base + range->base;
+}
+
+static int lpc18xx_get_pintsel(void __iomem *addr, u32 val, int *arg)
+{
+ u32 reg_val;
+ int i;
+
+ reg_val = readl(addr);
+ for (i = 0; i < LPC18XX_SCU_IRQ_PER_PINTSEL; i++) {
+ if ((reg_val & LPC18XX_SCU_PINTSEL_VAL_MASK) == val)
+ return 0;
+
+ reg_val >>= BITS_PER_BYTE;
+ *arg += 1;
+ }
+
+ return -EINVAL;
+}
+
+static u32 lpc18xx_gpio_to_pintsel_val(int gpio)
+{
+ unsigned int gpio_port, gpio_pin;
+
+ gpio_port = gpio / LPC18XX_GPIO_PINS_PER_PORT;
+ gpio_pin = gpio % LPC18XX_GPIO_PINS_PER_PORT;
+
+ return gpio_pin | (gpio_port << LPC18XX_SCU_PINTSEL_PORT_SHIFT);
+}
+
+static int lpc18xx_pconf_get_gpio_pin_int(struct pinctrl_dev *pctldev,
+ int *arg, unsigned pin)
+{
+ struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
+ int gpio, ret;
+ u32 val;
+
+ gpio = lpc18xx_pin_to_gpio(pctldev, pin);
+ if (gpio < 0)
+ return -ENOTSUPP;
+
+ val = lpc18xx_gpio_to_pintsel_val(gpio);
+
+ /*
+ * Check if this pin has been enabled as a interrupt in any of the two
+ * PINTSEL registers. *arg indicates which interrupt number (0-7).
+ */
+ *arg = 0;
+ ret = lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL0, val, arg);
+ if (ret == 0)
+ return ret;
+
+ return lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL1, val, arg);
+}
+
+static int lpc18xx_pconf_get_pin(struct pinctrl_dev *pctldev, unsigned param,
+ int *arg, u32 reg, unsigned pin,
struct lpc18xx_pin_caps *pin_cap)
{
switch (param) {
}
break;
+ case PIN_CONFIG_GPIO_PIN_INT:
+ return lpc18xx_pconf_get_gpio_pin_int(pctldev, arg, pin);
+
default:
return -ENOTSUPP;
}
else if (pin_cap->type == TYPE_USB1)
ret = lpc18xx_pconf_get_usb1(param, &arg, reg);
else
- ret = lpc18xx_pconf_get_pin(param, &arg, reg, pin_cap);
+ ret = lpc18xx_pconf_get_pin(pctldev, param, &arg, reg, pin, pin_cap);
if (ret < 0)
return ret;
return 0;
}
-static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev,
- enum pin_config_param param,
- u16 param_val, u32 *reg,
+static int lpc18xx_pconf_set_gpio_pin_int(struct pinctrl_dev *pctldev,
+ u16 param_val, unsigned pin)
+{
+ struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
+ u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0;
+ int gpio;
+
+ if (param_val >= LPC18XX_GPIO_PIN_INT_MAX)
+ return -EINVAL;
+
+ gpio = lpc18xx_pin_to_gpio(pctldev, pin);
+ if (gpio < 0)
+ return -ENOTSUPP;
+
+ val = lpc18xx_gpio_to_pintsel_val(gpio);
+
+ reg_offset += (param_val / LPC18XX_SCU_IRQ_PER_PINTSEL) * sizeof(u32);
+
+ reg_val = readl(scu->base + reg_offset);
+ reg_val &= ~LPC18XX_SCU_PINTSEL_VAL(LPC18XX_SCU_PINTSEL_VAL_MASK, param_val);
+ reg_val |= LPC18XX_SCU_PINTSEL_VAL(val, param_val);
+ writel(reg_val, scu->base + reg_offset);
+
+ return 0;
+}
+
+static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, unsigned param,
+ u16 param_val, u32 *reg, unsigned pin,
struct lpc18xx_pin_caps *pin_cap)
{
switch (param) {
*reg |= param_val << LPC18XX_SCU_PIN_EHD_POS;
break;
+ case PIN_CONFIG_GPIO_PIN_INT:
+ return lpc18xx_pconf_set_gpio_pin_int(pctldev, param_val, pin);
+
default:
dev_err(pctldev->dev, "Property not supported\n");
return -ENOTSUPP;
else if (pin_cap->type == TYPE_USB1)
ret = lpc18xx_pconf_set_usb1(pctldev, param, param_val, ®);
else
- ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, ®, pin_cap);
+ ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, ®, pin, pin_cap);
if (ret)
return ret;
.pctlops = &lpc18xx_pctl_ops,
.pmxops = &lpc18xx_pmx_ops,
.confops = &lpc18xx_pconf_ops,
+ .num_custom_params = ARRAY_SIZE(lpc18xx_params),
+ .custom_params = lpc18xx_params,
+#ifdef CONFIG_DEBUG_FS
+ .custom_conf_items = lpc18xx_conf_items,
+#endif
.owner = THIS_MODULE,
};
u16 pins[ARRAY_SIZE(lpc18xx_pins)];
int func, ngroups, i;
- for (func = 0; func < FUNC_MAX; ngroups = 0, func++) {
-
- for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
+ for (func = 0; func < FUNC_MAX; func++) {
+ for (ngroups = 0, i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
if (lpc18xx_valid_pin_function(i, func))
pins[ngroups++] = i;
}
--- /dev/null
+/*
+ * PIC32 pinctrl driver
+ *
+ * Joshua Henderson, <joshua.henderson@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include <asm/mach-pic32/pic32.h>
+
+#include "pinctrl-utils.h"
+#include "pinctrl-pic32.h"
+
+#define PINS_PER_BANK 16
+
+#define PIC32_CNCON_EDGE 11
+#define PIC32_CNCON_ON 15
+
+#define PIN_CONFIG_MICROCHIP_DIGITAL (PIN_CONFIG_END + 1)
+#define PIN_CONFIG_MICROCHIP_ANALOG (PIN_CONFIG_END + 2)
+
+static const struct pinconf_generic_params pic32_mpp_bindings[] = {
+ {"microchip,digital", PIN_CONFIG_MICROCHIP_DIGITAL, 0},
+ {"microchip,analog", PIN_CONFIG_MICROCHIP_ANALOG, 0},
+};
+
+#define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK)
+
+struct pic32_function {
+ const char *name;
+ const char * const *groups;
+ unsigned int ngroups;
+};
+
+struct pic32_pin_group {
+ const char *name;
+ unsigned int pin;
+ struct pic32_desc_function *functions;
+};
+
+struct pic32_desc_function {
+ const char *name;
+ u32 muxreg;
+ u32 muxval;
+};
+
+struct pic32_gpio_bank {
+ void __iomem *reg_base;
+ struct gpio_chip gpio_chip;
+ struct irq_chip irq_chip;
+ struct clk *clk;
+};
+
+struct pic32_pinctrl {
+ void __iomem *reg_base;
+ struct device *dev;
+ struct pinctrl_dev *pctldev;
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ const struct pic32_function *functions;
+ unsigned int nfunctions;
+ const struct pic32_pin_group *groups;
+ unsigned int ngroups;
+ struct pic32_gpio_bank *gpio_banks;
+ unsigned int nbanks;
+ struct clk *clk;
+};
+
+static const struct pinctrl_pin_desc pic32_pins[] = {
+ PINCTRL_PIN(0, "A0"),
+ PINCTRL_PIN(1, "A1"),
+ PINCTRL_PIN(2, "A2"),
+ PINCTRL_PIN(3, "A3"),
+ PINCTRL_PIN(4, "A4"),
+ PINCTRL_PIN(5, "A5"),
+ PINCTRL_PIN(6, "A6"),
+ PINCTRL_PIN(7, "A7"),
+ PINCTRL_PIN(8, "A8"),
+ PINCTRL_PIN(9, "A9"),
+ PINCTRL_PIN(10, "A10"),
+ PINCTRL_PIN(11, "A11"),
+ PINCTRL_PIN(12, "A12"),
+ PINCTRL_PIN(13, "A13"),
+ PINCTRL_PIN(14, "A14"),
+ PINCTRL_PIN(15, "A15"),
+ PINCTRL_PIN(16, "B0"),
+ PINCTRL_PIN(17, "B1"),
+ PINCTRL_PIN(18, "B2"),
+ PINCTRL_PIN(19, "B3"),
+ PINCTRL_PIN(20, "B4"),
+ PINCTRL_PIN(21, "B5"),
+ PINCTRL_PIN(22, "B6"),
+ PINCTRL_PIN(23, "B7"),
+ PINCTRL_PIN(24, "B8"),
+ PINCTRL_PIN(25, "B9"),
+ PINCTRL_PIN(26, "B10"),
+ PINCTRL_PIN(27, "B11"),
+ PINCTRL_PIN(28, "B12"),
+ PINCTRL_PIN(29, "B13"),
+ PINCTRL_PIN(30, "B14"),
+ PINCTRL_PIN(31, "B15"),
+ PINCTRL_PIN(33, "C1"),
+ PINCTRL_PIN(34, "C2"),
+ PINCTRL_PIN(35, "C3"),
+ PINCTRL_PIN(36, "C4"),
+ PINCTRL_PIN(44, "C12"),
+ PINCTRL_PIN(45, "C13"),
+ PINCTRL_PIN(46, "C14"),
+ PINCTRL_PIN(47, "C15"),
+ PINCTRL_PIN(48, "D0"),
+ PINCTRL_PIN(49, "D1"),
+ PINCTRL_PIN(50, "D2"),
+ PINCTRL_PIN(51, "D3"),
+ PINCTRL_PIN(52, "D4"),
+ PINCTRL_PIN(53, "D5"),
+ PINCTRL_PIN(54, "D6"),
+ PINCTRL_PIN(55, "D7"),
+ PINCTRL_PIN(57, "D9"),
+ PINCTRL_PIN(58, "D10"),
+ PINCTRL_PIN(59, "D11"),
+ PINCTRL_PIN(60, "D12"),
+ PINCTRL_PIN(61, "D13"),
+ PINCTRL_PIN(62, "D14"),
+ PINCTRL_PIN(63, "D15"),
+ PINCTRL_PIN(64, "E0"),
+ PINCTRL_PIN(65, "E1"),
+ PINCTRL_PIN(66, "E2"),
+ PINCTRL_PIN(67, "E3"),
+ PINCTRL_PIN(68, "E4"),
+ PINCTRL_PIN(69, "E5"),
+ PINCTRL_PIN(70, "E6"),
+ PINCTRL_PIN(71, "E7"),
+ PINCTRL_PIN(72, "E8"),
+ PINCTRL_PIN(73, "E9"),
+ PINCTRL_PIN(80, "F0"),
+ PINCTRL_PIN(81, "F1"),
+ PINCTRL_PIN(82, "F2"),
+ PINCTRL_PIN(83, "F3"),
+ PINCTRL_PIN(84, "F4"),
+ PINCTRL_PIN(85, "F5"),
+ PINCTRL_PIN(88, "F8"),
+ PINCTRL_PIN(92, "F12"),
+ PINCTRL_PIN(93, "F13"),
+ PINCTRL_PIN(96, "G0"),
+ PINCTRL_PIN(97, "G1"),
+ PINCTRL_PIN(102, "G6"),
+ PINCTRL_PIN(103, "G7"),
+ PINCTRL_PIN(104, "G8"),
+ PINCTRL_PIN(105, "G9"),
+ PINCTRL_PIN(108, "G12"),
+ PINCTRL_PIN(109, "G13"),
+ PINCTRL_PIN(110, "G14"),
+ PINCTRL_PIN(111, "G15"),
+ PINCTRL_PIN(112, "H0"),
+ PINCTRL_PIN(113, "H1"),
+ PINCTRL_PIN(114, "H2"),
+ PINCTRL_PIN(115, "H3"),
+ PINCTRL_PIN(116, "H4"),
+ PINCTRL_PIN(117, "H5"),
+ PINCTRL_PIN(118, "H6"),
+ PINCTRL_PIN(119, "H7"),
+ PINCTRL_PIN(120, "H8"),
+ PINCTRL_PIN(121, "H9"),
+ PINCTRL_PIN(122, "H10"),
+ PINCTRL_PIN(123, "H11"),
+ PINCTRL_PIN(124, "H12"),
+ PINCTRL_PIN(125, "H13"),
+ PINCTRL_PIN(126, "H14"),
+ PINCTRL_PIN(127, "H15"),
+ PINCTRL_PIN(128, "J0"),
+ PINCTRL_PIN(129, "J1"),
+ PINCTRL_PIN(130, "J2"),
+ PINCTRL_PIN(131, "J3"),
+ PINCTRL_PIN(132, "J4"),
+ PINCTRL_PIN(133, "J5"),
+ PINCTRL_PIN(134, "J6"),
+ PINCTRL_PIN(135, "J7"),
+ PINCTRL_PIN(136, "J8"),
+ PINCTRL_PIN(137, "J9"),
+ PINCTRL_PIN(138, "J10"),
+ PINCTRL_PIN(139, "J11"),
+ PINCTRL_PIN(140, "J12"),
+ PINCTRL_PIN(141, "J13"),
+ PINCTRL_PIN(142, "J14"),
+ PINCTRL_PIN(143, "J15"),
+ PINCTRL_PIN(144, "K0"),
+ PINCTRL_PIN(145, "K1"),
+ PINCTRL_PIN(146, "K2"),
+ PINCTRL_PIN(147, "K3"),
+ PINCTRL_PIN(148, "K4"),
+ PINCTRL_PIN(149, "K5"),
+ PINCTRL_PIN(150, "K6"),
+ PINCTRL_PIN(151, "K7"),
+};
+
+static const char * const pic32_input0_group[] = {
+ "D2", "G8", "F4", "F1", "B9", "B10", "C14", "B5",
+ "C1", "D14", "G1", "A14", "D6",
+};
+
+static const char * const pic32_input1_group[] = {
+ "D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13",
+ "B3", "C4", "G0", "A15", "D7",
+};
+
+static const char * const pic32_input2_group[] = {
+ "D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7",
+ "F12", "D12", "F8", "C3", "E9",
+};
+
+static const char * const pic32_input3_group[] = {
+ "G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13",
+ "F2", "C2", "E8",
+};
+
+static const char * const pic32_output0_group[] = {
+ "D2", "G8", "F4", "D10", "F1", "B9", "B10", "C14",
+ "B5", "C1", "D14", "G1", "A14", "D6",
+};
+
+static const char * const pic32_output0_1_group[] = {
+ "D2", "G8", "F4", "D10", "F1", "B9", "B10", "C14",
+ "B5", "C1", "D14", "G1", "A14", "D6",
+ "D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13",
+ "B3", "C4", "D15", "G0", "A15", "D7",
+};
+
+static const char *const pic32_output1_group[] = {
+ "D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13",
+ "B3", "C4", "D15", "G0", "A15", "D7",
+};
+
+static const char *const pic32_output1_3_group[] = {
+ "D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13",
+ "B3", "C4", "D15", "G0", "A15", "D7",
+ "G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13",
+ "C2", "E8", "F2",
+};
+
+static const char * const pic32_output2_group[] = {
+ "D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7",
+ "F12", "D12", "F8", "C3", "E9",
+};
+
+static const char * const pic32_output2_3_group[] = {
+ "D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7",
+ "F12", "D12", "F8", "C3", "E9",
+ "G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13",
+ "C2", "E8", "F2",
+};
+
+static const char * const pic32_output3_group[] = {
+ "G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13",
+ "C2", "E8", "F2",
+};
+
+#define FUNCTION(_name, _gr) \
+ { \
+ .name = #_name, \
+ .groups = pic32_##_gr##_group, \
+ .ngroups = ARRAY_SIZE(pic32_##_gr##_group), \
+ }
+
+static const struct pic32_function pic32_functions[] = {
+ FUNCTION(INT3, input0),
+ FUNCTION(T2CK, input0),
+ FUNCTION(T6CK, input0),
+ FUNCTION(IC3, input0),
+ FUNCTION(IC7, input0),
+ FUNCTION(U1RX, input0),
+ FUNCTION(U2CTS, input0),
+ FUNCTION(U5RX, input0),
+ FUNCTION(U6CTS, input0),
+ FUNCTION(SDI1, input0),
+ FUNCTION(SDI3, input0),
+ FUNCTION(SDI5, input0),
+ FUNCTION(SS6IN, input0),
+ FUNCTION(REFCLKI1, input0),
+ FUNCTION(INT4, input1),
+ FUNCTION(T5CK, input1),
+ FUNCTION(T7CK, input1),
+ FUNCTION(IC4, input1),
+ FUNCTION(IC8, input1),
+ FUNCTION(U3RX, input1),
+ FUNCTION(U4CTS, input1),
+ FUNCTION(SDI2, input1),
+ FUNCTION(SDI4, input1),
+ FUNCTION(C1RX, input1),
+ FUNCTION(REFCLKI4, input1),
+ FUNCTION(INT2, input2),
+ FUNCTION(T3CK, input2),
+ FUNCTION(T8CK, input2),
+ FUNCTION(IC2, input2),
+ FUNCTION(IC5, input2),
+ FUNCTION(IC9, input2),
+ FUNCTION(U1CTS, input2),
+ FUNCTION(U2RX, input2),
+ FUNCTION(U5CTS, input2),
+ FUNCTION(SS1IN, input2),
+ FUNCTION(SS3IN, input2),
+ FUNCTION(SS4IN, input2),
+ FUNCTION(SS5IN, input2),
+ FUNCTION(C2RX, input2),
+ FUNCTION(INT1, input3),
+ FUNCTION(T4CK, input3),
+ FUNCTION(T9CK, input3),
+ FUNCTION(IC1, input3),
+ FUNCTION(IC6, input3),
+ FUNCTION(U3CTS, input3),
+ FUNCTION(U4RX, input3),
+ FUNCTION(U6RX, input3),
+ FUNCTION(SS2IN, input3),
+ FUNCTION(SDI6, input3),
+ FUNCTION(OCFA, input3),
+ FUNCTION(REFCLKI3, input3),
+ FUNCTION(U3TX, output0),
+ FUNCTION(U4RTS, output0),
+ FUNCTION(SDO1, output0_1),
+ FUNCTION(SDO2, output0_1),
+ FUNCTION(SDO3, output0_1),
+ FUNCTION(SDO5, output0_1),
+ FUNCTION(SS6OUT, output0),
+ FUNCTION(OC3, output0),
+ FUNCTION(OC6, output0),
+ FUNCTION(REFCLKO4, output0),
+ FUNCTION(C2OUT, output0),
+ FUNCTION(C1TX, output0),
+ FUNCTION(U1TX, output1),
+ FUNCTION(U2RTS, output1),
+ FUNCTION(U5TX, output1),
+ FUNCTION(U6RTS, output1),
+ FUNCTION(SDO4, output1_3),
+ FUNCTION(OC4, output1),
+ FUNCTION(OC7, output1),
+ FUNCTION(REFCLKO1, output1),
+ FUNCTION(U3RTS, output2),
+ FUNCTION(U4TX, output2),
+ FUNCTION(U6TX, output2_3),
+ FUNCTION(SS1OUT, output2),
+ FUNCTION(SS3OUT, output2),
+ FUNCTION(SS4OUT, output2),
+ FUNCTION(SS5OUT, output2),
+ FUNCTION(SDO6, output2_3),
+ FUNCTION(OC5, output2),
+ FUNCTION(OC8, output2),
+ FUNCTION(C1OUT, output2),
+ FUNCTION(REFCLKO3, output2),
+ FUNCTION(U1RTS, output3),
+ FUNCTION(U2TX, output3),
+ FUNCTION(U5RTS, output3),
+ FUNCTION(SS2OUT, output3),
+ FUNCTION(OC2, output3),
+ FUNCTION(OC1, output3),
+ FUNCTION(OC9, output3),
+ FUNCTION(C2TX, output3),
+};
+
+#define PIC32_PINCTRL_GROUP(_pin, _name, ...) \
+ { \
+ .name = #_name, \
+ .pin = _pin, \
+ .functions = (struct pic32_desc_function[]){ \
+ __VA_ARGS__, { } }, \
+ }
+
+#define PIC32_PINCTRL_FUNCTION(_name, _muxreg, _muxval) \
+ { \
+ .name = #_name, \
+ .muxreg = _muxreg, \
+ .muxval = _muxval, \
+ }
+
+static const struct pic32_pin_group pic32_groups[] = {
+ PIC32_PINCTRL_GROUP(14, A14,
+ PIC32_PINCTRL_FUNCTION(INT3, INT3R, 13),
+ PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 13),
+ PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 13),
+ PIC32_PINCTRL_FUNCTION(IC3, IC3R, 13),
+ PIC32_PINCTRL_FUNCTION(IC7, IC7R, 13),
+ PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 13),
+ PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 13),
+ PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 13),
+ PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 13),
+ PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 13),
+ PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 13),
+ PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 13),
+ PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 13),
+ PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 13),
+ PIC32_PINCTRL_FUNCTION(U3TX, RPA14R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPA14R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPA14R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPA14R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPA14R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPA14R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPA14R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPA14R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPA14R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPA14R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPA14R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPA14R, 15)),
+ PIC32_PINCTRL_GROUP(15, A15,
+ PIC32_PINCTRL_FUNCTION(INT4, INT4R, 13),
+ PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 13),
+ PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 13),
+ PIC32_PINCTRL_FUNCTION(IC4, IC4R, 13),
+ PIC32_PINCTRL_FUNCTION(IC8, IC8R, 13),
+ PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 13),
+ PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 13),
+ PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 13),
+ PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 13),
+ PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 13),
+ PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 13),
+ PIC32_PINCTRL_FUNCTION(U1TX, RPA15R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPA15R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPA15R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPA15R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPA15R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPA15R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPA15R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPA15R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPA15R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPA15R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPA15R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPA15R, 15)),
+ PIC32_PINCTRL_GROUP(16, B0,
+ PIC32_PINCTRL_FUNCTION(INT2, INT2R, 5),
+ PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 5),
+ PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 5),
+ PIC32_PINCTRL_FUNCTION(IC2, IC2R, 5),
+ PIC32_PINCTRL_FUNCTION(IC5, IC5R, 5),
+ PIC32_PINCTRL_FUNCTION(IC9, IC9R, 5),
+ PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 5),
+ PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 5),
+ PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 5),
+ PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 5),
+ PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 5),
+ PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 5),
+ PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 5),
+ PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 5),
+ PIC32_PINCTRL_FUNCTION(U3RTS, RPB0R, 1),
+ PIC32_PINCTRL_FUNCTION(U4TX, RPB0R, 2),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPB0R, 4),
+ PIC32_PINCTRL_FUNCTION(SS1OUT, RPB0R, 5),
+ PIC32_PINCTRL_FUNCTION(SS3OUT, RPB0R, 7),
+ PIC32_PINCTRL_FUNCTION(SS4OUT, RPB0R, 8),
+ PIC32_PINCTRL_FUNCTION(SS5OUT, RPB0R, 9),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPB0R, 10),
+ PIC32_PINCTRL_FUNCTION(OC5, RPB0R, 11),
+ PIC32_PINCTRL_FUNCTION(OC8, RPB0R, 12),
+ PIC32_PINCTRL_FUNCTION(C1OUT, RPB0R, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB0R, 15)),
+ PIC32_PINCTRL_GROUP(17, B1,
+ PIC32_PINCTRL_FUNCTION(INT4, INT4R, 5),
+ PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 5),
+ PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 5),
+ PIC32_PINCTRL_FUNCTION(IC4, IC4R, 5),
+ PIC32_PINCTRL_FUNCTION(IC8, IC8R, 5),
+ PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 5),
+ PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 5),
+ PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 5),
+ PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 5),
+ PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 5),
+ PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 5),
+ PIC32_PINCTRL_FUNCTION(U1TX, RPB1R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPB1R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPB1R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPB1R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPB1R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPB1R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPB1R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPB1R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPB1R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPB1R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPB1R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPB1R, 15)),
+ PIC32_PINCTRL_GROUP(18, B2,
+ PIC32_PINCTRL_FUNCTION(INT1, INT1R, 7),
+ PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 7),
+ PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 7),
+ PIC32_PINCTRL_FUNCTION(IC1, IC1R, 7),
+ PIC32_PINCTRL_FUNCTION(IC6, IC6R, 7),
+ PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 7),
+ PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 7),
+ PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 7),
+ PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 7),
+ PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 7),
+ PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 7),
+ PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 7),
+ PIC32_PINCTRL_FUNCTION(U1RTS, RPB2R, 1),
+ PIC32_PINCTRL_FUNCTION(U2TX, RPB2R, 2),
+ PIC32_PINCTRL_FUNCTION(U5RTS, RPB2R, 3),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPB2R, 4),
+ PIC32_PINCTRL_FUNCTION(SS2OUT, RPB2R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPB2R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPB2R, 10),
+ PIC32_PINCTRL_FUNCTION(OC2, RPB2R, 11),
+ PIC32_PINCTRL_FUNCTION(OC1, RPB2R, 12),
+ PIC32_PINCTRL_FUNCTION(OC9, RPB2R, 13),
+ PIC32_PINCTRL_FUNCTION(C2TX, RPB2R, 15)),
+ PIC32_PINCTRL_GROUP(19, B3,
+ PIC32_PINCTRL_FUNCTION(INT4, INT4R, 8),
+ PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 8),
+ PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 8),
+ PIC32_PINCTRL_FUNCTION(IC4, IC4R, 8),
+ PIC32_PINCTRL_FUNCTION(IC8, IC8R, 8),
+ PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 8),
+ PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 8),
+ PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 8),
+ PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 8),
+ PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 8),
+ PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 8),
+ PIC32_PINCTRL_FUNCTION(U1TX, RPB3R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPB3R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPB3R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPB3R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPB3R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPB3R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPB3R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPB3R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPB3R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPB3R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPB3R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPB3R, 15)),
+ PIC32_PINCTRL_GROUP(21, B5,
+ PIC32_PINCTRL_FUNCTION(INT3, INT3R, 8),
+ PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 8),
+ PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 8),
+ PIC32_PINCTRL_FUNCTION(IC3, IC3R, 8),
+ PIC32_PINCTRL_FUNCTION(IC7, IC7R, 8),
+ PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 8),
+ PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 8),
+ PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 8),
+ PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 8),
+ PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 8),
+ PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 8),
+ PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 8),
+ PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 8),
+ PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 8),
+ PIC32_PINCTRL_FUNCTION(U3TX, RPB5R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPB5R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPB5R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPB5R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPB5R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPB5R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPB5R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPB5R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPB5R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPB5R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPB5R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPB5R, 15)),
+ PIC32_PINCTRL_GROUP(22, B6,
+ PIC32_PINCTRL_FUNCTION(INT1, INT1R, 4),
+ PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 4),
+ PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 4),
+ PIC32_PINCTRL_FUNCTION(IC1, IC1R, 4),
+ PIC32_PINCTRL_FUNCTION(IC6, IC6R, 4),
+ PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 4),
+ PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 4),
+ PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 4),
+ PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 4),
+ PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 4),
+ PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 4),
+ PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 4),
+ PIC32_PINCTRL_FUNCTION(U1RTS, RPB6R, 1),
+ PIC32_PINCTRL_FUNCTION(U2TX, RPB6R, 2),
+ PIC32_PINCTRL_FUNCTION(U5RTS, RPB6R, 3),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPB6R, 4),
+ PIC32_PINCTRL_FUNCTION(SS2OUT, RPB6R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPB6R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPB6R, 10),
+ PIC32_PINCTRL_FUNCTION(OC2, RPB6R, 11),
+ PIC32_PINCTRL_FUNCTION(OC1, RPB6R, 12),
+ PIC32_PINCTRL_FUNCTION(OC9, RPB6R, 13),
+ PIC32_PINCTRL_FUNCTION(C2TX, RPB6R, 15)),
+ PIC32_PINCTRL_GROUP(23, B7,
+ PIC32_PINCTRL_FUNCTION(INT2, INT2R, 7),
+ PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 7),
+ PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 7),
+ PIC32_PINCTRL_FUNCTION(IC2, IC2R, 7),
+ PIC32_PINCTRL_FUNCTION(IC5, IC5R, 7),
+ PIC32_PINCTRL_FUNCTION(IC9, IC9R, 7),
+ PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 7),
+ PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 7),
+ PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 7),
+ PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 7),
+ PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 7),
+ PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 7),
+ PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 7),
+ PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 7),
+ PIC32_PINCTRL_FUNCTION(U3RTS, RPB7R, 1),
+ PIC32_PINCTRL_FUNCTION(U4TX, RPB7R, 2),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPB7R, 4),
+ PIC32_PINCTRL_FUNCTION(SS1OUT, RPB7R, 5),
+ PIC32_PINCTRL_FUNCTION(SS3OUT, RPB7R, 7),
+ PIC32_PINCTRL_FUNCTION(SS4OUT, RPB7R, 8),
+ PIC32_PINCTRL_FUNCTION(SS5OUT, RPB7R, 9),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPB7R, 10),
+ PIC32_PINCTRL_FUNCTION(OC5, RPB7R, 11),
+ PIC32_PINCTRL_FUNCTION(OC8, RPB7R, 12),
+ PIC32_PINCTRL_FUNCTION(C1OUT, RPB7R, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB7R, 15)),
+ PIC32_PINCTRL_GROUP(24, B8,
+ PIC32_PINCTRL_FUNCTION(INT2, INT2R, 2),
+ PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 2),
+ PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 2),
+ PIC32_PINCTRL_FUNCTION(IC2, IC2R, 2),
+ PIC32_PINCTRL_FUNCTION(IC5, IC5R, 2),
+ PIC32_PINCTRL_FUNCTION(IC9, IC9R, 2),
+ PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 2),
+ PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 2),
+ PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 2),
+ PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 2),
+ PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 2),
+ PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 2),
+ PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 2),
+ PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 2),
+ PIC32_PINCTRL_FUNCTION(U3RTS, RPB8R, 1),
+ PIC32_PINCTRL_FUNCTION(U4TX, RPB8R, 2),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPB8R, 4),
+ PIC32_PINCTRL_FUNCTION(SS1OUT, RPB8R, 5),
+ PIC32_PINCTRL_FUNCTION(SS3OUT, RPB8R, 7),
+ PIC32_PINCTRL_FUNCTION(SS4OUT, RPB8R, 8),
+ PIC32_PINCTRL_FUNCTION(SS5OUT, RPB8R, 9),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPB8R, 10),
+ PIC32_PINCTRL_FUNCTION(OC5, RPB8R, 11),
+ PIC32_PINCTRL_FUNCTION(OC8, RPB8R, 12),
+ PIC32_PINCTRL_FUNCTION(C1OUT, RPB8R, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB8R, 15)),
+ PIC32_PINCTRL_GROUP(25, B9,
+ PIC32_PINCTRL_FUNCTION(INT3, INT3R, 5),
+ PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 5),
+ PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 5),
+ PIC32_PINCTRL_FUNCTION(IC3, IC3R, 5),
+ PIC32_PINCTRL_FUNCTION(IC7, IC7R, 5),
+ PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 5),
+ PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 5),
+ PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 5),
+ PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 5),
+ PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 5),
+ PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 5),
+ PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 5),
+ PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 5),
+ PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 5),
+ PIC32_PINCTRL_FUNCTION(U3TX, RPB9R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPB9R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPB9R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPB9R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPB9R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPB9R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPB9R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPB9R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPB9R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPB9R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPB9R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPB9R, 15)),
+ PIC32_PINCTRL_GROUP(26, B10,
+ PIC32_PINCTRL_FUNCTION(INT3, INT3R, 6),
+ PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 6),
+ PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 6),
+ PIC32_PINCTRL_FUNCTION(IC3, IC3R, 6),
+ PIC32_PINCTRL_FUNCTION(IC7, IC7R, 6),
+ PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 6),
+ PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 6),
+ PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 6),
+ PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 6),
+ PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 6),
+ PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 6),
+ PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 6),
+ PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 6),
+ PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 6),
+ PIC32_PINCTRL_FUNCTION(U3TX, RPB10R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPB10R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPB10R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPB10R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPB10R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPB10R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPB10R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPB10R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPB10R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPB10R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPB10R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPB10R, 15)),
+ PIC32_PINCTRL_GROUP(30, B14,
+ PIC32_PINCTRL_FUNCTION(INT1, INT1R, 2),
+ PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 2),
+ PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 2),
+ PIC32_PINCTRL_FUNCTION(IC1, IC1R, 2),
+ PIC32_PINCTRL_FUNCTION(IC6, IC6R, 2),
+ PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 2),
+ PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 2),
+ PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 2),
+ PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 2),
+ PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 2),
+ PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 2),
+ PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 2),
+ PIC32_PINCTRL_FUNCTION(U1RTS, RPB14R, 1),
+ PIC32_PINCTRL_FUNCTION(U2TX, RPB14R, 2),
+ PIC32_PINCTRL_FUNCTION(U5RTS, RPB14R, 3),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPB14R, 4),
+ PIC32_PINCTRL_FUNCTION(SS2OUT, RPB14R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPB14R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPB14R, 10),
+ PIC32_PINCTRL_FUNCTION(OC2, RPB14R, 11),
+ PIC32_PINCTRL_FUNCTION(OC1, RPB14R, 12),
+ PIC32_PINCTRL_FUNCTION(OC9, RPB14R, 13),
+ PIC32_PINCTRL_FUNCTION(C2TX, RPB14R, 15)),
+ PIC32_PINCTRL_GROUP(31, B15,
+ PIC32_PINCTRL_FUNCTION(INT2, INT2R, 3),
+ PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 3),
+ PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 3),
+ PIC32_PINCTRL_FUNCTION(IC2, IC2R, 3),
+ PIC32_PINCTRL_FUNCTION(IC5, IC5R, 3),
+ PIC32_PINCTRL_FUNCTION(IC9, IC9R, 3),
+ PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 3),
+ PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 3),
+ PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 3),
+ PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 3),
+ PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 3),
+ PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 3),
+ PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 3),
+ PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 3),
+ PIC32_PINCTRL_FUNCTION(U3RTS, RPB15R, 1),
+ PIC32_PINCTRL_FUNCTION(U4TX, RPB15R, 2),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPB15R, 4),
+ PIC32_PINCTRL_FUNCTION(SS1OUT, RPB15R, 5),
+ PIC32_PINCTRL_FUNCTION(SS3OUT, RPB15R, 7),
+ PIC32_PINCTRL_FUNCTION(SS4OUT, RPB15R, 8),
+ PIC32_PINCTRL_FUNCTION(SS5OUT, RPB15R, 9),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPB15R, 10),
+ PIC32_PINCTRL_FUNCTION(OC5, RPB15R, 11),
+ PIC32_PINCTRL_FUNCTION(OC8, RPB15R, 12),
+ PIC32_PINCTRL_FUNCTION(C1OUT, RPB15R, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB15R, 15)),
+ PIC32_PINCTRL_GROUP(33, C1,
+ PIC32_PINCTRL_FUNCTION(INT3, INT3R, 10),
+ PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 10),
+ PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 10),
+ PIC32_PINCTRL_FUNCTION(IC3, IC3R, 10),
+ PIC32_PINCTRL_FUNCTION(IC7, IC7R, 10),
+ PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 10),
+ PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 10),
+ PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 10),
+ PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 10),
+ PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 10),
+ PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 10),
+ PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 10),
+ PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 10),
+ PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 10),
+ PIC32_PINCTRL_FUNCTION(U3TX, RPC1R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPC1R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPC1R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPC1R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPC1R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPC1R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPC1R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPC1R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPC1R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPC1R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPC1R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPC1R, 15)),
+ PIC32_PINCTRL_GROUP(34, C2,
+ PIC32_PINCTRL_FUNCTION(INT1, INT1R, 12),
+ PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 12),
+ PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 12),
+ PIC32_PINCTRL_FUNCTION(IC1, IC1R, 12),
+ PIC32_PINCTRL_FUNCTION(IC6, IC6R, 12),
+ PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 12),
+ PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 12),
+ PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 12),
+ PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 12),
+ PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 12),
+ PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 12),
+ PIC32_PINCTRL_FUNCTION(U1RTS, RPC2R, 1),
+ PIC32_PINCTRL_FUNCTION(U2TX, RPC2R, 2),
+ PIC32_PINCTRL_FUNCTION(U5RTS, RPC2R, 3),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPC2R, 4),
+ PIC32_PINCTRL_FUNCTION(SS2OUT, RPC2R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPC2R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPC2R, 10),
+ PIC32_PINCTRL_FUNCTION(OC2, RPC2R, 11),
+ PIC32_PINCTRL_FUNCTION(OC1, RPC2R, 12),
+ PIC32_PINCTRL_FUNCTION(OC9, RPC2R, 13),
+ PIC32_PINCTRL_FUNCTION(C2TX, RPC2R, 15)),
+ PIC32_PINCTRL_GROUP(35, C3,
+ PIC32_PINCTRL_FUNCTION(INT2, INT2R, 12),
+ PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 12),
+ PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 12),
+ PIC32_PINCTRL_FUNCTION(IC2, IC2R, 12),
+ PIC32_PINCTRL_FUNCTION(IC5, IC5R, 12),
+ PIC32_PINCTRL_FUNCTION(IC9, IC9R, 12),
+ PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 12),
+ PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 12),
+ PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 12),
+ PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 12),
+ PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 12),
+ PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 12),
+ PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 12),
+ PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 12),
+ PIC32_PINCTRL_FUNCTION(U3RTS, RPC3R, 1),
+ PIC32_PINCTRL_FUNCTION(U4TX, RPC3R, 2),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPC3R, 4),
+ PIC32_PINCTRL_FUNCTION(SS1OUT, RPC3R, 5),
+ PIC32_PINCTRL_FUNCTION(SS3OUT, RPC3R, 7),
+ PIC32_PINCTRL_FUNCTION(SS4OUT, RPC3R, 8),
+ PIC32_PINCTRL_FUNCTION(SS5OUT, RPC3R, 9),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPC3R, 10),
+ PIC32_PINCTRL_FUNCTION(OC5, RPC3R, 11),
+ PIC32_PINCTRL_FUNCTION(OC8, RPC3R, 12),
+ PIC32_PINCTRL_FUNCTION(C1OUT, RPC3R, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKO3, RPC3R, 15)),
+ PIC32_PINCTRL_GROUP(36, C4,
+ PIC32_PINCTRL_FUNCTION(INT4, INT4R, 10),
+ PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 10),
+ PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 10),
+ PIC32_PINCTRL_FUNCTION(IC4, IC4R, 10),
+ PIC32_PINCTRL_FUNCTION(IC8, IC8R, 10),
+ PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 10),
+ PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 10),
+ PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 10),
+ PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 10),
+ PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 10),
+ PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 10),
+ PIC32_PINCTRL_FUNCTION(U1TX, RPC4R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPC4R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPC4R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPC4R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPC4R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPC4R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPC4R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPC4R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPC4R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPC4R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPC4R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPC4R, 15)),
+ PIC32_PINCTRL_GROUP(45, C13,
+ PIC32_PINCTRL_FUNCTION(INT4, INT4R, 7),
+ PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 7),
+ PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 7),
+ PIC32_PINCTRL_FUNCTION(IC4, IC4R, 7),
+ PIC32_PINCTRL_FUNCTION(IC8, IC8R, 7),
+ PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 7),
+ PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 7),
+ PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 7),
+ PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 7),
+ PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 7),
+ PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 7),
+ PIC32_PINCTRL_FUNCTION(U1TX, RPC13R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPC13R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPC13R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPC13R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPC13R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPC13R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPC13R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPC13R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPC13R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPC13R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPC13R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPC13R, 15)),
+ PIC32_PINCTRL_GROUP(46, C14,
+ PIC32_PINCTRL_FUNCTION(INT3, INT3R, 7),
+ PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 7),
+ PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 7),
+ PIC32_PINCTRL_FUNCTION(IC3, IC3R, 7),
+ PIC32_PINCTRL_FUNCTION(IC7, IC7R, 7),
+ PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 7),
+ PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 7),
+ PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 7),
+ PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 7),
+ PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 7),
+ PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 7),
+ PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 7),
+ PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 7),
+ PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 7),
+ PIC32_PINCTRL_FUNCTION(U3TX, RPC14R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPC14R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPC14R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPC14R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPC14R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPC14R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPC14R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPC14R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPC14R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPC14R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPC14R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPC14R, 15)),
+ PIC32_PINCTRL_GROUP(48, D0,
+ PIC32_PINCTRL_FUNCTION(INT1, INT1R, 3),
+ PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 3),
+ PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 3),
+ PIC32_PINCTRL_FUNCTION(IC1, IC1R, 3),
+ PIC32_PINCTRL_FUNCTION(IC6, IC6R, 3),
+ PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 3),
+ PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 3),
+ PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 3),
+ PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 3),
+ PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 3),
+ PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 3),
+ PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 3),
+ PIC32_PINCTRL_FUNCTION(U1RTS, RPD0R, 1),
+ PIC32_PINCTRL_FUNCTION(U2TX, RPD0R, 2),
+ PIC32_PINCTRL_FUNCTION(U5RTS, RPD0R, 3),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPD0R, 4),
+ PIC32_PINCTRL_FUNCTION(SS2OUT, RPD0R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPD0R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPD0R, 10),
+ PIC32_PINCTRL_FUNCTION(OC2, RPD0R, 11),
+ PIC32_PINCTRL_FUNCTION(OC1, RPD0R, 12),
+ PIC32_PINCTRL_FUNCTION(OC9, RPD0R, 13),
+ PIC32_PINCTRL_FUNCTION(C2TX, RPD0R, 15)),
+ PIC32_PINCTRL_GROUP(50, D2,
+ PIC32_PINCTRL_FUNCTION(INT3, INT3R, 0),
+ PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 0),
+ PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 0),
+ PIC32_PINCTRL_FUNCTION(IC3, IC3R, 0),
+ PIC32_PINCTRL_FUNCTION(IC7, IC7R, 0),
+ PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 0),
+ PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 0),
+ PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 0),
+ PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 0),
+ PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 0),
+ PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 0),
+ PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 0),
+ PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 0),
+ PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 0),
+ PIC32_PINCTRL_FUNCTION(U3TX, RPD2R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPD2R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPD2R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPD2R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPD2R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPD2R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPD2R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPD2R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPD2R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD2R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPD2R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPD2R, 15)),
+ PIC32_PINCTRL_GROUP(51, D3,
+ PIC32_PINCTRL_FUNCTION(INT4, INT4R, 0),
+ PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 0),
+ PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 0),
+ PIC32_PINCTRL_FUNCTION(IC4, IC4R, 0),
+ PIC32_PINCTRL_FUNCTION(IC8, IC8R, 0),
+ PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 0),
+ PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 0),
+ PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 0),
+ PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 0),
+ PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 0),
+ PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 0),
+ PIC32_PINCTRL_FUNCTION(U1TX, RPD3R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPD3R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPD3R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPD3R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPD3R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPD3R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPD3R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPD3R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPD3R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPD3R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPD3R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD3R, 15)),
+ PIC32_PINCTRL_GROUP(52, D4,
+ PIC32_PINCTRL_FUNCTION(INT2, INT2R, 4),
+ PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 4),
+ PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 4),
+ PIC32_PINCTRL_FUNCTION(IC2, IC2R, 4),
+ PIC32_PINCTRL_FUNCTION(IC5, IC5R, 4),
+ PIC32_PINCTRL_FUNCTION(IC9, IC9R, 4),
+ PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 4),
+ PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 4),
+ PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 4),
+ PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 4),
+ PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 4),
+ PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 4),
+ PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 4),
+ PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 4),
+ PIC32_PINCTRL_FUNCTION(U3RTS, RPD4R, 1),
+ PIC32_PINCTRL_FUNCTION(U4TX, RPD4R, 2),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPD4R, 4),
+ PIC32_PINCTRL_FUNCTION(SS1OUT, RPD4R, 5),
+ PIC32_PINCTRL_FUNCTION(SS3OUT, RPD4R, 7),
+ PIC32_PINCTRL_FUNCTION(SS4OUT, RPD4R, 8),
+ PIC32_PINCTRL_FUNCTION(SS5OUT, RPD4R, 9),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPD4R, 10),
+ PIC32_PINCTRL_FUNCTION(OC5, RPD4R, 11),
+ PIC32_PINCTRL_FUNCTION(OC8, RPD4R, 12),
+ PIC32_PINCTRL_FUNCTION(C1OUT, RPD4R, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKO3, RPD4R, 15)),
+ PIC32_PINCTRL_GROUP(53, D5,
+ PIC32_PINCTRL_FUNCTION(INT1, INT1R, 6),
+ PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 6),
+ PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 6),
+ PIC32_PINCTRL_FUNCTION(IC1, IC1R, 6),
+ PIC32_PINCTRL_FUNCTION(IC6, IC6R, 6),
+ PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 6),
+ PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 6),
+ PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 6),
+ PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 6),
+ PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 6),
+ PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 6),
+ PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 6),
+ PIC32_PINCTRL_FUNCTION(U1RTS, RPD5R, 1),
+ PIC32_PINCTRL_FUNCTION(U2TX, RPD5R, 2),
+ PIC32_PINCTRL_FUNCTION(U5RTS, RPD5R, 3),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPD5R, 4),
+ PIC32_PINCTRL_FUNCTION(SS2OUT, RPD5R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPD5R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPD5R, 10),
+ PIC32_PINCTRL_FUNCTION(OC2, RPD5R, 11),
+ PIC32_PINCTRL_FUNCTION(OC1, RPD5R, 12),
+ PIC32_PINCTRL_FUNCTION(OC9, RPD5R, 13),
+ PIC32_PINCTRL_FUNCTION(C2TX, RPD5R, 15)),
+ PIC32_PINCTRL_GROUP(54, D6,
+ PIC32_PINCTRL_FUNCTION(INT3, INT3R, 14),
+ PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 14),
+ PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 14),
+ PIC32_PINCTRL_FUNCTION(IC3, IC3R, 14),
+ PIC32_PINCTRL_FUNCTION(IC7, IC7R, 14),
+ PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 14),
+ PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 14),
+ PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 14),
+ PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 14),
+ PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 14),
+ PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 14),
+ PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 14),
+ PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 14),
+ PIC32_PINCTRL_FUNCTION(U3TX, RPD6R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPD6R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPD6R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPD6R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPD6R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPD6R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPD6R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPD6R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPD6R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD6R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPD6R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPD6R, 15)),
+ PIC32_PINCTRL_GROUP(55, D7,
+ PIC32_PINCTRL_FUNCTION(INT4, INT4R, 14),
+ PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 14),
+ PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 14),
+ PIC32_PINCTRL_FUNCTION(IC4, IC4R, 14),
+ PIC32_PINCTRL_FUNCTION(IC8, IC8R, 14),
+ PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 14),
+ PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 14),
+ PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 14),
+ PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 14),
+ PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 14),
+ PIC32_PINCTRL_FUNCTION(U1TX, RPD7R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPD7R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPD7R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPD7R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPD7R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPD7R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPD7R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPD7R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPD7R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPD7R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPD7R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD7R, 15)),
+ PIC32_PINCTRL_GROUP(57, D9,
+ PIC32_PINCTRL_FUNCTION(INT2, INT2R, 0),
+ PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 0),
+ PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 0),
+ PIC32_PINCTRL_FUNCTION(IC2, IC2R, 0),
+ PIC32_PINCTRL_FUNCTION(IC5, IC5R, 0),
+ PIC32_PINCTRL_FUNCTION(IC9, IC9R, 0),
+ PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 0),
+ PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 0),
+ PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 0),
+ PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 0),
+ PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 0),
+ PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 0),
+ PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 0),
+ PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 0),
+ PIC32_PINCTRL_FUNCTION(U3RTS, RPD9R, 1),
+ PIC32_PINCTRL_FUNCTION(U4TX, RPD9R, 2),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPD9R, 4),
+ PIC32_PINCTRL_FUNCTION(SS1OUT, RPD9R, 5),
+ PIC32_PINCTRL_FUNCTION(SS3OUT, RPD9R, 7),
+ PIC32_PINCTRL_FUNCTION(SS4OUT, RPD9R, 8),
+ PIC32_PINCTRL_FUNCTION(SS5OUT, RPD9R, 9),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPD9R, 10),
+ PIC32_PINCTRL_FUNCTION(OC5, RPD9R, 11),
+ PIC32_PINCTRL_FUNCTION(OC8, RPD9R, 12),
+ PIC32_PINCTRL_FUNCTION(C1OUT, RPD9R, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKO3, RPD9R, 15)),
+ PIC32_PINCTRL_GROUP(58, D10,
+ PIC32_PINCTRL_FUNCTION(U3TX, RPD10R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPD10R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPD10R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPD10R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPD10R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPD10R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPD10R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPD10R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPD10R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD10R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPD10R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPD10R, 15)),
+ PIC32_PINCTRL_GROUP(59, D11,
+ PIC32_PINCTRL_FUNCTION(INT4, INT4R, 3),
+ PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 3),
+ PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 3),
+ PIC32_PINCTRL_FUNCTION(IC4, IC4R, 3),
+ PIC32_PINCTRL_FUNCTION(IC8, IC8R, 3),
+ PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 3),
+ PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 3),
+ PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 3),
+ PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 3),
+ PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 3),
+ PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 3),
+ PIC32_PINCTRL_FUNCTION(U1TX, RPD11R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPD11R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPD11R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPD11R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPD11R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPD11R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPD11R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPD11R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPD11R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPD11R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPD11R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD11R, 15)),
+ PIC32_PINCTRL_GROUP(60, D12,
+ PIC32_PINCTRL_FUNCTION(INT2, INT2R, 10),
+ PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 10),
+ PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 10),
+ PIC32_PINCTRL_FUNCTION(IC2, IC2R, 10),
+ PIC32_PINCTRL_FUNCTION(IC5, IC5R, 10),
+ PIC32_PINCTRL_FUNCTION(IC9, IC9R, 10),
+ PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 10),
+ PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 10),
+ PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 10),
+ PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 10),
+ PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 10),
+ PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 10),
+ PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 10),
+ PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 10),
+ PIC32_PINCTRL_FUNCTION(U3RTS, RPD12R, 1),
+ PIC32_PINCTRL_FUNCTION(U4TX, RPD12R, 2),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPD12R, 4),
+ PIC32_PINCTRL_FUNCTION(SS1OUT, RPD12R, 5),
+ PIC32_PINCTRL_FUNCTION(SS3OUT, RPD12R, 7),
+ PIC32_PINCTRL_FUNCTION(SS4OUT, RPD12R, 8),
+ PIC32_PINCTRL_FUNCTION(SS5OUT, RPD12R, 9),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPD12R, 10),
+ PIC32_PINCTRL_FUNCTION(OC5, RPD12R, 11),
+ PIC32_PINCTRL_FUNCTION(OC8, RPD12R, 12),
+ PIC32_PINCTRL_FUNCTION(C1OUT, RPD12R, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKO3, RPD12R, 15)),
+ PIC32_PINCTRL_GROUP(62, D14,
+ PIC32_PINCTRL_FUNCTION(INT3, INT3R, 11),
+ PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 11),
+ PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 11),
+ PIC32_PINCTRL_FUNCTION(IC3, IC3R, 11),
+ PIC32_PINCTRL_FUNCTION(IC7, IC7R, 11),
+ PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 11),
+ PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 11),
+ PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 11),
+ PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 11),
+ PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 11),
+ PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 11),
+ PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 11),
+ PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 11),
+ PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 11),
+ PIC32_PINCTRL_FUNCTION(U3TX, RPD14R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPD14R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPD14R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPD14R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPD14R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPD14R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPD14R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPD14R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPD14R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD14R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPD14R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPD14R, 15)),
+ PIC32_PINCTRL_GROUP(63, D15,
+ PIC32_PINCTRL_FUNCTION(U1TX, RPD15R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPD15R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPD15R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPD15R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPD15R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPD15R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPD15R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPD15R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPD15R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPD15R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPD15R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD15R, 15)),
+ PIC32_PINCTRL_GROUP(67, E3,
+ PIC32_PINCTRL_FUNCTION(INT2, INT2R, 6),
+ PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 6),
+ PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 6),
+ PIC32_PINCTRL_FUNCTION(IC2, IC2R, 6),
+ PIC32_PINCTRL_FUNCTION(IC5, IC5R, 6),
+ PIC32_PINCTRL_FUNCTION(IC9, IC9R, 6),
+ PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 6),
+ PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 6),
+ PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 6),
+ PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 6),
+ PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 6),
+ PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 6),
+ PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 6),
+ PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 6),
+ PIC32_PINCTRL_FUNCTION(U3RTS, RPE3R, 1),
+ PIC32_PINCTRL_FUNCTION(U4TX, RPE3R, 2),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPE3R, 4),
+ PIC32_PINCTRL_FUNCTION(SS1OUT, RPE3R, 5),
+ PIC32_PINCTRL_FUNCTION(SS3OUT, RPE3R, 7),
+ PIC32_PINCTRL_FUNCTION(SS4OUT, RPE3R, 8),
+ PIC32_PINCTRL_FUNCTION(SS5OUT, RPE3R, 9),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPE3R, 10),
+ PIC32_PINCTRL_FUNCTION(OC5, RPE3R, 11),
+ PIC32_PINCTRL_FUNCTION(OC8, RPE3R, 12),
+ PIC32_PINCTRL_FUNCTION(C1OUT, RPE3R, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKO3, RPE3R, 15)),
+ PIC32_PINCTRL_GROUP(69, E5,
+ PIC32_PINCTRL_FUNCTION(INT4, INT4R, 6),
+ PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 6),
+ PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 6),
+ PIC32_PINCTRL_FUNCTION(IC4, IC4R, 6),
+ PIC32_PINCTRL_FUNCTION(IC8, IC8R, 6),
+ PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 6),
+ PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 6),
+ PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 6),
+ PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 6),
+ PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 6),
+ PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 6),
+ PIC32_PINCTRL_FUNCTION(U1TX, RPE5R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPE5R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPE5R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPE5R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPE5R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPE5R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPE5R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPE5R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPE5R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPE5R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPE5R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPE5R, 15)),
+ PIC32_PINCTRL_GROUP(72, E8,
+ PIC32_PINCTRL_FUNCTION(INT1, INT1R, 13),
+ PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 13),
+ PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 13),
+ PIC32_PINCTRL_FUNCTION(IC1, IC1R, 13),
+ PIC32_PINCTRL_FUNCTION(IC6, IC6R, 13),
+ PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 13),
+ PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 13),
+ PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 13),
+ PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 13),
+ PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 13),
+ PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 13),
+ PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 13),
+ PIC32_PINCTRL_FUNCTION(U1RTS, RPE8R, 1),
+ PIC32_PINCTRL_FUNCTION(U2TX, RPE8R, 2),
+ PIC32_PINCTRL_FUNCTION(U5RTS, RPE8R, 3),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPE8R, 4),
+ PIC32_PINCTRL_FUNCTION(SS2OUT, RPE8R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPE8R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPE8R, 10),
+ PIC32_PINCTRL_FUNCTION(OC2, RPE8R, 11),
+ PIC32_PINCTRL_FUNCTION(OC1, RPE8R, 12),
+ PIC32_PINCTRL_FUNCTION(OC9, RPE8R, 13),
+ PIC32_PINCTRL_FUNCTION(C2TX, RPE8R, 15)),
+ PIC32_PINCTRL_GROUP(73, E9,
+ PIC32_PINCTRL_FUNCTION(INT2, INT2R, 13),
+ PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 13),
+ PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 13),
+ PIC32_PINCTRL_FUNCTION(IC2, IC2R, 13),
+ PIC32_PINCTRL_FUNCTION(IC5, IC5R, 13),
+ PIC32_PINCTRL_FUNCTION(IC9, IC9R, 13),
+ PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 13),
+ PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 13),
+ PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 13),
+ PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 13),
+ PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 13),
+ PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 13),
+ PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 13),
+ PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 13),
+ PIC32_PINCTRL_FUNCTION(U3RTS, RPE9R, 1),
+ PIC32_PINCTRL_FUNCTION(U4TX, RPE9R, 2),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPE9R, 4),
+ PIC32_PINCTRL_FUNCTION(SS1OUT, RPE9R, 5),
+ PIC32_PINCTRL_FUNCTION(SS3OUT, RPE9R, 7),
+ PIC32_PINCTRL_FUNCTION(SS4OUT, RPE9R, 8),
+ PIC32_PINCTRL_FUNCTION(SS5OUT, RPE9R, 9),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPE9R, 10),
+ PIC32_PINCTRL_FUNCTION(OC5, RPE9R, 11),
+ PIC32_PINCTRL_FUNCTION(OC8, RPE9R, 12),
+ PIC32_PINCTRL_FUNCTION(C1OUT, RPE9R, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKO3, RPE9R, 15)),
+ PIC32_PINCTRL_GROUP(80, F0,
+ PIC32_PINCTRL_FUNCTION(INT4, INT4R, 4),
+ PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 4),
+ PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 4),
+ PIC32_PINCTRL_FUNCTION(IC4, IC4R, 4),
+ PIC32_PINCTRL_FUNCTION(IC8, IC8R, 4),
+ PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 4),
+ PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 4),
+ PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 4),
+ PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 4),
+ PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 4),
+ PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 4),
+ PIC32_PINCTRL_FUNCTION(U1TX, RPF0R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPF0R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPF0R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPF0R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPF0R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPF0R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPF0R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPF0R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPF0R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPF0R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPF0R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPF0R, 15)),
+ PIC32_PINCTRL_GROUP(81, F1,
+ PIC32_PINCTRL_FUNCTION(INT3, INT3R, 4),
+ PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 4),
+ PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 4),
+ PIC32_PINCTRL_FUNCTION(IC3, IC3R, 4),
+ PIC32_PINCTRL_FUNCTION(IC7, IC7R, 4),
+ PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 4),
+ PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 4),
+ PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 4),
+ PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 4),
+ PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 4),
+ PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 4),
+ PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 4),
+ PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 4),
+ PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 4),
+ PIC32_PINCTRL_FUNCTION(U3TX, RPF1R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPF1R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPF1R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPF1R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPF1R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPF1R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPF1R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPF1R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPF1R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPF1R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPF1R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPF1R, 15)),
+ PIC32_PINCTRL_GROUP(82, F2,
+ PIC32_PINCTRL_FUNCTION(INT1, INT1R, 11),
+ PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 11),
+ PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 11),
+ PIC32_PINCTRL_FUNCTION(IC1, IC1R, 11),
+ PIC32_PINCTRL_FUNCTION(IC6, IC6R, 11),
+ PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 11),
+ PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 11),
+ PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 11),
+ PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 11),
+ PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 11),
+ PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 11),
+ PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 11),
+ PIC32_PINCTRL_FUNCTION(U1RTS, RPF2R, 1),
+ PIC32_PINCTRL_FUNCTION(U2TX, RPF2R, 2),
+ PIC32_PINCTRL_FUNCTION(U5RTS, RPF2R, 3),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPF2R, 4),
+ PIC32_PINCTRL_FUNCTION(SS2OUT, RPF2R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPF2R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPF2R, 10),
+ PIC32_PINCTRL_FUNCTION(OC2, RPF2R, 11),
+ PIC32_PINCTRL_FUNCTION(OC1, RPF2R, 12),
+ PIC32_PINCTRL_FUNCTION(OC9, RPF2R, 13),
+ PIC32_PINCTRL_FUNCTION(C2TX, RPF2R, 15)),
+ PIC32_PINCTRL_GROUP(83, F3,
+ PIC32_PINCTRL_FUNCTION(INT1, INT1R, 8),
+ PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 8),
+ PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 8),
+ PIC32_PINCTRL_FUNCTION(IC1, IC1R, 8),
+ PIC32_PINCTRL_FUNCTION(IC6, IC6R, 8),
+ PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 8),
+ PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 8),
+ PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 8),
+ PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 8),
+ PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 8),
+ PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 8),
+ PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 8),
+ PIC32_PINCTRL_FUNCTION(U1RTS, RPF3R, 1),
+ PIC32_PINCTRL_FUNCTION(U2TX, RPF3R, 2),
+ PIC32_PINCTRL_FUNCTION(U5RTS, RPF3R, 3),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPF3R, 4),
+ PIC32_PINCTRL_FUNCTION(SS2OUT, RPF3R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPF3R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPF3R, 10),
+ PIC32_PINCTRL_FUNCTION(OC2, RPF3R, 11),
+ PIC32_PINCTRL_FUNCTION(OC1, RPF3R, 12),
+ PIC32_PINCTRL_FUNCTION(OC9, RPF3R, 13),
+ PIC32_PINCTRL_FUNCTION(C2TX, RPF3R, 15)),
+ PIC32_PINCTRL_GROUP(84, F4,
+ PIC32_PINCTRL_FUNCTION(INT3, INT3R, 2),
+ PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 2),
+ PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 2),
+ PIC32_PINCTRL_FUNCTION(IC3, IC3R, 2),
+ PIC32_PINCTRL_FUNCTION(IC7, IC7R, 2),
+ PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 2),
+ PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 2),
+ PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 2),
+ PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 2),
+ PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 2),
+ PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 2),
+ PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 2),
+ PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 2),
+ PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 2),
+ PIC32_PINCTRL_FUNCTION(U3TX, RPF4R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPF4R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPF4R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPF4R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPF4R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPF4R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPF4R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPF4R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPF4R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPF4R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPF4R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPF4R, 15)),
+ PIC32_PINCTRL_GROUP(85, F5,
+ PIC32_PINCTRL_FUNCTION(INT4, INT4R, 2),
+ PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 2),
+ PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 2),
+ PIC32_PINCTRL_FUNCTION(IC4, IC4R, 2),
+ PIC32_PINCTRL_FUNCTION(IC8, IC8R, 2),
+ PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 2),
+ PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 2),
+ PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 2),
+ PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 2),
+ PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 2),
+ PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 2),
+ PIC32_PINCTRL_FUNCTION(U1TX, RPF5R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPF5R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPF5R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPF5R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPF5R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPF5R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPF5R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPF5R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPF5R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPF5R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPF5R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPF5R, 15)),
+ PIC32_PINCTRL_GROUP(88, F8,
+ PIC32_PINCTRL_FUNCTION(INT2, INT2R, 11),
+ PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 11),
+ PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 11),
+ PIC32_PINCTRL_FUNCTION(IC2, IC2R, 11),
+ PIC32_PINCTRL_FUNCTION(IC5, IC5R, 11),
+ PIC32_PINCTRL_FUNCTION(IC9, IC9R, 11),
+ PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 11),
+ PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 11),
+ PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 11),
+ PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 11),
+ PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 11),
+ PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 11),
+ PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 11),
+ PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 11),
+ PIC32_PINCTRL_FUNCTION(U3RTS, RPF8R, 1),
+ PIC32_PINCTRL_FUNCTION(U4TX, RPF8R, 2),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPF8R, 4),
+ PIC32_PINCTRL_FUNCTION(SS1OUT, RPF8R, 5),
+ PIC32_PINCTRL_FUNCTION(SS3OUT, RPF8R, 7),
+ PIC32_PINCTRL_FUNCTION(SS4OUT, RPF8R, 8),
+ PIC32_PINCTRL_FUNCTION(SS5OUT, RPF8R, 9),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPF8R, 10),
+ PIC32_PINCTRL_FUNCTION(OC5, RPF8R, 11),
+ PIC32_PINCTRL_FUNCTION(OC8, RPF8R, 12),
+ PIC32_PINCTRL_FUNCTION(C1OUT, RPF8R, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKO3, RPF8R, 15)),
+ PIC32_PINCTRL_GROUP(92, F12,
+ PIC32_PINCTRL_FUNCTION(INT2, INT2R, 9),
+ PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 9),
+ PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 9),
+ PIC32_PINCTRL_FUNCTION(IC2, IC2R, 9),
+ PIC32_PINCTRL_FUNCTION(IC5, IC5R, 9),
+ PIC32_PINCTRL_FUNCTION(IC9, IC9R, 9),
+ PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 9),
+ PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 9),
+ PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 9),
+ PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 9),
+ PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 9),
+ PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 9),
+ PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 9),
+ PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 9),
+ PIC32_PINCTRL_FUNCTION(U3RTS, RPF12R, 1),
+ PIC32_PINCTRL_FUNCTION(U4TX, RPF12R, 2),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPF12R, 4),
+ PIC32_PINCTRL_FUNCTION(SS1OUT, RPF12R, 5),
+ PIC32_PINCTRL_FUNCTION(SS3OUT, RPF12R, 7),
+ PIC32_PINCTRL_FUNCTION(SS4OUT, RPF12R, 8),
+ PIC32_PINCTRL_FUNCTION(SS5OUT, RPF12R, 9),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPF12R, 10),
+ PIC32_PINCTRL_FUNCTION(OC5, RPF12R, 11),
+ PIC32_PINCTRL_FUNCTION(OC8, RPF12R, 12),
+ PIC32_PINCTRL_FUNCTION(C1OUT, RPF12R, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKO3, RPF12R, 15)),
+ PIC32_PINCTRL_GROUP(93, F13,
+ PIC32_PINCTRL_FUNCTION(INT1, INT1R, 9),
+ PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 9),
+ PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 9),
+ PIC32_PINCTRL_FUNCTION(IC1, IC1R, 9),
+ PIC32_PINCTRL_FUNCTION(IC6, IC6R, 9),
+ PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 9),
+ PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 9),
+ PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 9),
+ PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 9),
+ PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 9),
+ PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 9),
+ PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 9),
+ PIC32_PINCTRL_FUNCTION(U1RTS, RPF13R, 1),
+ PIC32_PINCTRL_FUNCTION(U2TX, RPF13R, 2),
+ PIC32_PINCTRL_FUNCTION(U5RTS, RPF13R, 3),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPF13R, 4),
+ PIC32_PINCTRL_FUNCTION(SS2OUT, RPF13R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPF13R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPF13R, 10),
+ PIC32_PINCTRL_FUNCTION(OC2, RPF13R, 11),
+ PIC32_PINCTRL_FUNCTION(OC1, RPF13R, 12),
+ PIC32_PINCTRL_FUNCTION(OC9, RPF13R, 13),
+ PIC32_PINCTRL_FUNCTION(C2TX, RPF13R, 15)),
+ PIC32_PINCTRL_GROUP(96, G0,
+ PIC32_PINCTRL_FUNCTION(INT4, INT4R, 12),
+ PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 12),
+ PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 12),
+ PIC32_PINCTRL_FUNCTION(IC4, IC4R, 12),
+ PIC32_PINCTRL_FUNCTION(IC8, IC8R, 12),
+ PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 12),
+ PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 12),
+ PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 12),
+ PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 12),
+ PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 12),
+ PIC32_PINCTRL_FUNCTION(U1TX, RPG0R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPG0R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPG0R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPG0R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPG0R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPG0R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPG0R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPG0R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPG0R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPG0R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPG0R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPG0R, 15)),
+ PIC32_PINCTRL_GROUP(97, G1,
+ PIC32_PINCTRL_FUNCTION(INT3, INT3R, 12),
+ PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 12),
+ PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 12),
+ PIC32_PINCTRL_FUNCTION(IC3, IC3R, 12),
+ PIC32_PINCTRL_FUNCTION(IC7, IC7R, 12),
+ PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 12),
+ PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 12),
+ PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 12),
+ PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 12),
+ PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 12),
+ PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 12),
+ PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 12),
+ PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 12),
+ PIC32_PINCTRL_FUNCTION(U3TX, RPG1R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPG1R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPG1R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPG1R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPG1R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPG1R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPG1R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPG1R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPG1R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPG1R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPG1R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPG1R, 15)),
+ PIC32_PINCTRL_GROUP(102, G6,
+ PIC32_PINCTRL_FUNCTION(INT2, INT2R, 1),
+ PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 1),
+ PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 1),
+ PIC32_PINCTRL_FUNCTION(IC2, IC2R, 1),
+ PIC32_PINCTRL_FUNCTION(IC5, IC5R, 1),
+ PIC32_PINCTRL_FUNCTION(IC9, IC9R, 1),
+ PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 1),
+ PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 1),
+ PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 1),
+ PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 1),
+ PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 1),
+ PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 1),
+ PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 1),
+ PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 1),
+ PIC32_PINCTRL_FUNCTION(U3RTS, RPG6R, 1),
+ PIC32_PINCTRL_FUNCTION(U4TX, RPG6R, 2),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPG6R, 4),
+ PIC32_PINCTRL_FUNCTION(SS1OUT, RPG6R, 5),
+ PIC32_PINCTRL_FUNCTION(SS3OUT, RPG6R, 7),
+ PIC32_PINCTRL_FUNCTION(SS4OUT, RPG6R, 8),
+ PIC32_PINCTRL_FUNCTION(SS5OUT, RPG6R, 9),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPG6R, 10),
+ PIC32_PINCTRL_FUNCTION(OC5, RPG6R, 11),
+ PIC32_PINCTRL_FUNCTION(OC8, RPG6R, 12),
+ PIC32_PINCTRL_FUNCTION(C1OUT, RPG6R, 14),
+ PIC32_PINCTRL_FUNCTION(REFCLKO3, RPG6R, 15)),
+ PIC32_PINCTRL_GROUP(103, G7,
+ PIC32_PINCTRL_FUNCTION(INT4, INT4R, 1),
+ PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 1),
+ PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 1),
+ PIC32_PINCTRL_FUNCTION(IC4, IC4R, 1),
+ PIC32_PINCTRL_FUNCTION(IC8, IC8R, 1),
+ PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 1),
+ PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 1),
+ PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 1),
+ PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 1),
+ PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 1),
+ PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 1),
+ PIC32_PINCTRL_FUNCTION(U1TX, RPG7R, 1),
+ PIC32_PINCTRL_FUNCTION(U2RTS, RPG7R, 2),
+ PIC32_PINCTRL_FUNCTION(U5TX, RPG7R, 3),
+ PIC32_PINCTRL_FUNCTION(U6RTS, RPG7R, 4),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPG7R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPG7R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPG7R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPG7R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPG7R, 9),
+ PIC32_PINCTRL_FUNCTION(OC4, RPG7R, 11),
+ PIC32_PINCTRL_FUNCTION(OC7, RPG7R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO1, RPG7R, 15)),
+ PIC32_PINCTRL_GROUP(104, G8,
+ PIC32_PINCTRL_FUNCTION(INT3, INT3R, 1),
+ PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 1),
+ PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 1),
+ PIC32_PINCTRL_FUNCTION(IC3, IC3R, 1),
+ PIC32_PINCTRL_FUNCTION(IC7, IC7R, 1),
+ PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 1),
+ PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 1),
+ PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 1),
+ PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 1),
+ PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 1),
+ PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 1),
+ PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 1),
+ PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 1),
+ PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 1),
+ PIC32_PINCTRL_FUNCTION(U3TX, RPG8R, 1),
+ PIC32_PINCTRL_FUNCTION(U4RTS, RPG8R, 2),
+ PIC32_PINCTRL_FUNCTION(SDO1, RPG8R, 5),
+ PIC32_PINCTRL_FUNCTION(SDO2, RPG8R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO3, RPG8R, 7),
+ PIC32_PINCTRL_FUNCTION(SDO5, RPG8R, 9),
+ PIC32_PINCTRL_FUNCTION(SS6OUT, RPG8R, 10),
+ PIC32_PINCTRL_FUNCTION(OC3, RPG8R, 11),
+ PIC32_PINCTRL_FUNCTION(OC6, RPG8R, 12),
+ PIC32_PINCTRL_FUNCTION(REFCLKO4, RPG8R, 13),
+ PIC32_PINCTRL_FUNCTION(C2OUT, RPG8R, 14),
+ PIC32_PINCTRL_FUNCTION(C1TX, RPG8R, 15)),
+ PIC32_PINCTRL_GROUP(105, G9,
+ PIC32_PINCTRL_FUNCTION(INT1, INT1R, 1),
+ PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 1),
+ PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 1),
+ PIC32_PINCTRL_FUNCTION(IC1, IC1R, 1),
+ PIC32_PINCTRL_FUNCTION(IC6, IC6R, 1),
+ PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 1),
+ PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 1),
+ PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 1),
+ PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 1),
+ PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 1),
+ PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 1),
+ PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 1),
+ PIC32_PINCTRL_FUNCTION(U1RTS, RPG9R, 1),
+ PIC32_PINCTRL_FUNCTION(U2TX, RPG9R, 2),
+ PIC32_PINCTRL_FUNCTION(U5RTS, RPG9R, 3),
+ PIC32_PINCTRL_FUNCTION(U6TX, RPG9R, 4),
+ PIC32_PINCTRL_FUNCTION(SS2OUT, RPG9R, 6),
+ PIC32_PINCTRL_FUNCTION(SDO4, RPG9R, 8),
+ PIC32_PINCTRL_FUNCTION(SDO6, RPG9R, 10),
+ PIC32_PINCTRL_FUNCTION(OC2, RPG9R, 11),
+ PIC32_PINCTRL_FUNCTION(OC1, RPG9R, 12),
+ PIC32_PINCTRL_FUNCTION(OC9, RPG9R, 13),
+ PIC32_PINCTRL_FUNCTION(C2TX, RPG9R, 15)),
+};
+
+static inline struct pic32_gpio_bank *irqd_to_bank(struct irq_data *d)
+{
+ return gpiochip_get_data(irq_data_get_irq_chip_data(d));
+}
+
+static inline struct pic32_gpio_bank *pctl_to_bank(struct pic32_pinctrl *pctl,
+ unsigned pin)
+{
+ return &pctl->gpio_banks[pin / PINS_PER_BANK];
+}
+
+static int pic32_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->ngroups;
+}
+
+static const char *pic32_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned group)
+{
+ struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->groups[group].name;
+}
+
+static int pic32_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned group,
+ const unsigned **pins,
+ unsigned *num_pins)
+{
+ struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = &pctl->groups[group].pin;
+ *num_pins = 1;
+
+ return 0;
+}
+
+static const struct pinctrl_ops pic32_pinctrl_ops = {
+ .get_groups_count = pic32_pinctrl_get_groups_count,
+ .get_group_name = pic32_pinctrl_get_group_name,
+ .get_group_pins = pic32_pinctrl_get_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+ .dt_free_map = pinctrl_utils_dt_free_map,
+};
+
+static int pic32_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
+{
+ struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->nfunctions;
+}
+
+static const char *
+pic32_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func)
+{
+ struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->functions[func].name;
+}
+
+static int pic32_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
+ unsigned func,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = pctl->functions[func].groups;
+ *num_groups = pctl->functions[func].ngroups;
+
+ return 0;
+}
+
+static int pic32_pinmux_enable(struct pinctrl_dev *pctldev,
+ unsigned func, unsigned group)
+{
+ struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct pic32_pin_group *pg = &pctl->groups[group];
+ const struct pic32_function *pf = &pctl->functions[func];
+ const char *fname = pf->name;
+ struct pic32_desc_function *functions = pg->functions;
+
+ while (functions->name) {
+ if (!strcmp(functions->name, fname)) {
+ dev_dbg(pctl->dev,
+ "setting function %s reg 0x%x = %d\n",
+ fname, functions->muxreg, functions->muxval);
+
+ writel(functions->muxval, pctl->reg_base + functions->muxreg);
+
+ return 0;
+ }
+
+ functions++;
+ }
+
+ dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
+
+ return -EINVAL;
+}
+
+static int pic32_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned offset)
+{
+ struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct pic32_gpio_bank *bank = gpiochip_get_data(range->gc);
+ u32 mask = BIT(offset - bank->gpio_chip.base);
+
+ dev_dbg(pctl->dev, "requesting gpio %d in bank %d with mask 0x%x\n",
+ offset, bank->gpio_chip.base, mask);
+
+ writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG));
+
+ return 0;
+}
+
+static int pic32_gpio_direction_input(struct gpio_chip *chip,
+ unsigned offset)
+{
+ struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
+ u32 mask = BIT(offset);
+
+ writel(mask, bank->reg_base + PIC32_SET(TRIS_REG));
+
+ return 0;
+}
+
+static int pic32_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
+
+ return !!(readl(bank->reg_base + PORT_REG) & BIT(offset));
+}
+
+static void pic32_gpio_set(struct gpio_chip *chip, unsigned offset,
+ int value)
+{
+ struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
+ u32 mask = BIT(offset);
+
+ if (value)
+ writel(mask, bank->reg_base + PIC32_SET(PORT_REG));
+ else
+ writel(mask, bank->reg_base + PIC32_CLR(PORT_REG));
+}
+
+static int pic32_gpio_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
+ u32 mask = BIT(offset);
+
+ pic32_gpio_set(chip, offset, value);
+ writel(mask, bank->reg_base + PIC32_CLR(TRIS_REG));
+
+ return 0;
+}
+
+static int pic32_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned offset, bool input)
+{
+ struct gpio_chip *chip = range->gc;
+
+ if (input)
+ pic32_gpio_direction_input(chip, offset);
+ else
+ pic32_gpio_direction_output(chip, offset, 0);
+
+ return 0;
+}
+
+static const struct pinmux_ops pic32_pinmux_ops = {
+ .get_functions_count = pic32_pinmux_get_functions_count,
+ .get_function_name = pic32_pinmux_get_function_name,
+ .get_function_groups = pic32_pinmux_get_function_groups,
+ .set_mux = pic32_pinmux_enable,
+ .gpio_request_enable = pic32_gpio_request_enable,
+ .gpio_set_direction = pic32_gpio_set_direction,
+};
+
+static int pic32_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
+ unsigned long *config)
+{
+ struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);
+ unsigned param = pinconf_to_config_param(*config);
+ u32 mask = BIT(pin - bank->gpio_chip.base);
+ u32 arg;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ arg = !!(readl(bank->reg_base + CNPU_REG) & mask);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ arg = !!(readl(bank->reg_base + CNPD_REG) & mask);
+ break;
+ case PIN_CONFIG_MICROCHIP_DIGITAL:
+ arg = !(readl(bank->reg_base + ANSEL_REG) & mask);
+ break;
+ case PIN_CONFIG_MICROCHIP_ANALOG:
+ arg = !!(readl(bank->reg_base + ANSEL_REG) & mask);
+ break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ arg = !!(readl(bank->reg_base + ODCU_REG) & mask);
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ arg = !!(readl(bank->reg_base + TRIS_REG) & mask);
+ break;
+ case PIN_CONFIG_OUTPUT:
+ arg = !(readl(bank->reg_base + TRIS_REG) & mask);
+ break;
+ default:
+ dev_err(pctl->dev, "Property %u not supported\n", param);
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+
+ return 0;
+}
+
+static int pic32_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
+ unsigned long *configs, unsigned num_configs)
+{
+ struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);
+ unsigned param;
+ u32 arg;
+ unsigned int i;
+ u32 offset = pin - bank->gpio_chip.base;
+ u32 mask = BIT(offset);
+
+ dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
+ pin, bank->gpio_chip.base, mask);
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ dev_dbg(pctl->dev, " pullup\n");
+ writel(mask, bank->reg_base +PIC32_SET(CNPU_REG));
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ dev_dbg(pctl->dev, " pulldown\n");
+ writel(mask, bank->reg_base + PIC32_SET(CNPD_REG));
+ break;
+ case PIN_CONFIG_MICROCHIP_DIGITAL:
+ dev_dbg(pctl->dev, " digital\n");
+ writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG));
+ break;
+ case PIN_CONFIG_MICROCHIP_ANALOG:
+ dev_dbg(pctl->dev, " analog\n");
+ writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG));
+ break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ dev_dbg(pctl->dev, " opendrain\n");
+ writel(mask, bank->reg_base + PIC32_SET(ODCU_REG));
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ pic32_gpio_direction_input(&bank->gpio_chip, offset);
+ break;
+ case PIN_CONFIG_OUTPUT:
+ pic32_gpio_direction_output(&bank->gpio_chip,
+ offset, arg);
+ break;
+ default:
+ dev_err(pctl->dev, "Property %u not supported\n",
+ param);
+ return -ENOTSUPP;
+ }
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops pic32_pinconf_ops = {
+ .pin_config_get = pic32_pinconf_get,
+ .pin_config_set = pic32_pinconf_set,
+ .is_generic = true,
+};
+
+static struct pinctrl_desc pic32_pinctrl_desc = {
+ .name = "pic32-pinctrl",
+ .pctlops = &pic32_pinctrl_ops,
+ .pmxops = &pic32_pinmux_ops,
+ .confops = &pic32_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static int pic32_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
+{
+ struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
+
+ return !!(readl(bank->reg_base + TRIS_REG) & BIT(offset));
+}
+
+static void pic32_gpio_irq_ack(struct irq_data *data)
+{
+ struct pic32_gpio_bank *bank = irqd_to_bank(data);
+
+ writel(0, bank->reg_base + CNF_REG);
+}
+
+static void pic32_gpio_irq_mask(struct irq_data *data)
+{
+ struct pic32_gpio_bank *bank = irqd_to_bank(data);
+
+ writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG));
+}
+
+static void pic32_gpio_irq_unmask(struct irq_data *data)
+{
+ struct pic32_gpio_bank *bank = irqd_to_bank(data);
+
+ writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG));
+}
+
+static unsigned int pic32_gpio_irq_startup(struct irq_data *data)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
+
+ pic32_gpio_direction_input(chip, data->hwirq);
+ pic32_gpio_irq_unmask(data);
+
+ return 0;
+}
+
+static int pic32_gpio_irq_set_type(struct irq_data *data, unsigned int type)
+{
+ struct pic32_gpio_bank *bank = irqd_to_bank(data);
+ u32 mask = BIT(data->hwirq);
+
+ switch (type & IRQ_TYPE_SENSE_MASK) {
+ case IRQ_TYPE_EDGE_RISING:
+ /* enable RISE */
+ writel(mask, bank->reg_base + PIC32_SET(CNEN_REG));
+ /* disable FALL */
+ writel(mask, bank->reg_base + PIC32_CLR(CNNE_REG));
+ /* enable EDGE */
+ writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ /* disable RISE */
+ writel(mask, bank->reg_base + PIC32_CLR(CNEN_REG));
+ /* enable FALL */
+ writel(mask, bank->reg_base + PIC32_SET(CNNE_REG));
+ /* enable EDGE */
+ writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ /* enable RISE */
+ writel(mask, bank->reg_base + PIC32_SET(CNEN_REG));
+ /* enable FALL */
+ writel(mask, bank->reg_base + PIC32_SET(CNNE_REG));
+ /* enable EDGE */
+ writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ irq_set_handler_locked(data, handle_edge_irq);
+
+ return 0;
+}
+
+static u32 pic32_gpio_get_pending(struct gpio_chip *gc, unsigned long status)
+{
+ struct pic32_gpio_bank *bank = gpiochip_get_data(gc);
+ u32 pending = 0;
+ u32 cnen_rise, cnne_fall;
+ u32 pin;
+
+ cnen_rise = readl(bank->reg_base + CNEN_REG);
+ cnne_fall = readl(bank->reg_base + CNNE_REG);
+
+ for_each_set_bit(pin, &status, BITS_PER_LONG) {
+ u32 mask = BIT(pin);
+
+ if ((mask & cnen_rise) || (mask && cnne_fall))
+ pending |= mask;
+ }
+
+ return pending;
+}
+
+static void pic32_gpio_irq_handler(struct irq_desc *desc)
+{
+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+ struct pic32_gpio_bank *bank = gpiochip_get_data(gc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned long pending;
+ unsigned int pin;
+ u32 stat;
+
+ chained_irq_enter(chip, desc);
+
+ stat = readl(bank->reg_base + CNF_REG);
+ pending = pic32_gpio_get_pending(gc, stat);
+
+ for_each_set_bit(pin, &pending, BITS_PER_LONG)
+ generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
+
+ chained_irq_exit(chip, desc);
+}
+
+#define GPIO_BANK(_bank, _npins) \
+ { \
+ .gpio_chip = { \
+ .label = "GPIO" #_bank, \
+ .request = gpiochip_generic_request, \
+ .free = gpiochip_generic_free, \
+ .get_direction = pic32_gpio_get_direction, \
+ .direction_input = pic32_gpio_direction_input, \
+ .direction_output = pic32_gpio_direction_output, \
+ .get = pic32_gpio_get, \
+ .set = pic32_gpio_set, \
+ .ngpio = _npins, \
+ .base = GPIO_BANK_START(_bank), \
+ .owner = THIS_MODULE, \
+ .can_sleep = 0, \
+ }, \
+ .irq_chip = { \
+ .name = "GPIO" #_bank, \
+ .irq_startup = pic32_gpio_irq_startup, \
+ .irq_ack = pic32_gpio_irq_ack, \
+ .irq_mask = pic32_gpio_irq_mask, \
+ .irq_unmask = pic32_gpio_irq_unmask, \
+ .irq_set_type = pic32_gpio_irq_set_type, \
+ }, \
+ }
+
+static struct pic32_gpio_bank pic32_gpio_banks[] = {
+ GPIO_BANK(0, PINS_PER_BANK),
+ GPIO_BANK(1, PINS_PER_BANK),
+ GPIO_BANK(2, PINS_PER_BANK),
+ GPIO_BANK(3, PINS_PER_BANK),
+ GPIO_BANK(4, PINS_PER_BANK),
+ GPIO_BANK(5, PINS_PER_BANK),
+ GPIO_BANK(6, PINS_PER_BANK),
+ GPIO_BANK(7, PINS_PER_BANK),
+ GPIO_BANK(8, PINS_PER_BANK),
+ GPIO_BANK(9, PINS_PER_BANK),
+};
+
+static int pic32_pinctrl_probe(struct platform_device *pdev)
+{
+ struct pic32_pinctrl *pctl;
+ struct resource *res;
+ int ret;
+
+ pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
+ if (!pctl)
+ return -ENOMEM;
+ pctl->dev = &pdev->dev;
+ dev_set_drvdata(&pdev->dev, pctl);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pctl->reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pctl->reg_base))
+ return PTR_ERR(pctl->reg_base);
+
+ pctl->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pctl->clk)) {
+ ret = PTR_ERR(pctl->clk);
+ dev_err(&pdev->dev, "clk get failed\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(pctl->clk);
+ if (ret) {
+ dev_err(&pdev->dev, "clk enable failed\n");
+ return ret;
+ }
+
+ pctl->pins = pic32_pins;
+ pctl->npins = ARRAY_SIZE(pic32_pins);
+ pctl->functions = pic32_functions;
+ pctl->nfunctions = ARRAY_SIZE(pic32_functions);
+ pctl->groups = pic32_groups;
+ pctl->ngroups = ARRAY_SIZE(pic32_groups);
+ pctl->gpio_banks = pic32_gpio_banks;
+ pctl->nbanks = ARRAY_SIZE(pic32_gpio_banks);
+
+ pic32_pinctrl_desc.pins = pctl->pins;
+ pic32_pinctrl_desc.npins = pctl->npins;
+ pic32_pinctrl_desc.custom_params = pic32_mpp_bindings;
+ pic32_pinctrl_desc.num_custom_params = ARRAY_SIZE(pic32_mpp_bindings);
+
+ pctl->pctldev = pinctrl_register(&pic32_pinctrl_desc, &pdev->dev, pctl);
+ if (IS_ERR(pctl->pctldev)) {
+ dev_err(&pdev->dev, "Failed to register pinctrl device\n");
+ return PTR_ERR(pctl->pctldev);
+ }
+
+ return 0;
+}
+
+static int pic32_gpio_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct pic32_gpio_bank *bank;
+ u32 id;
+ int irq, ret;
+ struct resource *res;
+
+ if (of_property_read_u32(np, "microchip,gpio-bank", &id)) {
+ dev_err(&pdev->dev, "microchip,gpio-bank property not found\n");
+ return -EINVAL;
+ }
+
+ if (id >= ARRAY_SIZE(pic32_gpio_banks)) {
+ dev_err(&pdev->dev, "invalid microchip,gpio-bank property\n");
+ return -EINVAL;
+ }
+
+ bank = &pic32_gpio_banks[id];
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ bank->reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(bank->reg_base))
+ return PTR_ERR(bank->reg_base);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "irq get failed\n");
+ return irq;
+ }
+
+ bank->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(bank->clk)) {
+ ret = PTR_ERR(bank->clk);
+ dev_err(&pdev->dev, "clk get failed\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(bank->clk);
+ if (ret) {
+ dev_err(&pdev->dev, "clk enable failed\n");
+ return ret;
+ }
+
+ bank->gpio_chip.parent = &pdev->dev;
+ bank->gpio_chip.of_node = np;
+ ret = gpiochip_add_data(&bank->gpio_chip, bank);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
+ id, ret);
+ return ret;
+ }
+
+ ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip,
+ 0, handle_level_irq, IRQ_TYPE_NONE);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to add IRQ chip %u: %d\n",
+ id, ret);
+ gpiochip_remove(&bank->gpio_chip);
+ return ret;
+ }
+
+ gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip,
+ irq, pic32_gpio_irq_handler);
+
+ return 0;
+}
+
+static const struct of_device_id pic32_pinctrl_of_match[] = {
+ { .compatible = "microchip,pic32mzda-pinctrl", },
+ { },
+};
+
+static struct platform_driver pic32_pinctrl_driver = {
+ .driver = {
+ .name = "pic32-pinctrl",
+ .of_match_table = pic32_pinctrl_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = pic32_pinctrl_probe,
+};
+
+static const struct of_device_id pic32_gpio_of_match[] = {
+ { .compatible = "microchip,pic32mzda-gpio", },
+ { },
+};
+
+static struct platform_driver pic32_gpio_driver = {
+ .driver = {
+ .name = "pic32-gpio",
+ .of_match_table = pic32_gpio_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = pic32_gpio_probe,
+};
+
+static int __init pic32_gpio_register(void)
+{
+ return platform_driver_register(&pic32_gpio_driver);
+}
+arch_initcall(pic32_gpio_register);
+
+static int __init pic32_pinctrl_register(void)
+{
+ return platform_driver_register(&pic32_pinctrl_driver);
+}
+arch_initcall(pic32_pinctrl_register);
--- /dev/null
+/*
+ * PIC32 pinctrl driver
+ *
+ * Joshua Henderson, <joshua.henderson@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef PINCTRL_PINCTRL_PIC32_H
+#define PINCTRL_PINCTRL_PIC32_H
+
+/* PORT Registers */
+#define ANSEL_REG 0x00
+#define TRIS_REG 0x10
+#define PORT_REG 0x20
+#define LAT_REG 0x30
+#define ODCU_REG 0x40
+#define CNPU_REG 0x50
+#define CNPD_REG 0x60
+#define CNCON_REG 0x70
+#define CNEN_REG 0x80
+#define CNSTAT_REG 0x90
+#define CNNE_REG 0xA0
+#define CNF_REG 0xB0
+
+/* Input PPS Registers */
+#define INT1R 0x04
+#define INT2R 0x08
+#define INT3R 0x0C
+#define INT4R 0x10
+#define T2CKR 0x18
+#define T3CKR 0x1C
+#define T4CKR 0x20
+#define T5CKR 0x24
+#define T6CKR 0x28
+#define T7CKR 0x2C
+#define T8CKR 0x30
+#define T9CKR 0x34
+#define IC1R 0x38
+#define IC2R 0x3C
+#define IC3R 0x40
+#define IC4R 0x44
+#define IC5R 0x48
+#define IC6R 0x4C
+#define IC7R 0x50
+#define IC8R 0x54
+#define IC9R 0x58
+#define OCFAR 0x60
+#define U1RXR 0x68
+#define U1CTSR 0x6C
+#define U2RXR 0x70
+#define U2CTSR 0x74
+#define U3RXR 0x78
+#define U3CTSR 0x7C
+#define U4RXR 0x80
+#define U4CTSR 0x84
+#define U5RXR 0x88
+#define U5CTSR 0x8C
+#define U6RXR 0x90
+#define U6CTSR 0x94
+#define SDI1R 0x9C
+#define SS1INR 0xA0
+#define SDI2R 0xA8
+#define SS2INR 0xAC
+#define SDI3R 0xB4
+#define SS3INR 0xB8
+#define SDI4R 0xC0
+#define SS4INR 0xC4
+#define SDI5R 0xCC
+#define SS5INR 0xD0
+#define SDI6R 0xD8
+#define SS6INR 0xDC
+#define C1RXR 0xE0
+#define C2RXR 0xE4
+#define REFCLKI1R 0xE8
+#define REFCLKI3R 0xF0
+#define REFCLKI4R 0xF4
+
+/* Output PPS Registers */
+#define RPA14R 0x138
+#define RPA15R 0x13C
+#define RPB0R 0x140
+#define RPB1R 0x144
+#define RPB2R 0x148
+#define RPB3R 0x14C
+#define RPB5R 0x154
+#define RPB6R 0x158
+#define RPB7R 0x15C
+#define RPB8R 0x160
+#define RPB9R 0x164
+#define RPB10R 0x168
+#define RPB14R 0x178
+#define RPB15R 0x17C
+#define RPC1R 0x184
+#define RPC2R 0x188
+#define RPC3R 0x18C
+#define RPC4R 0x190
+#define RPC13R 0x1B4
+#define RPC14R 0x1B8
+#define RPD0R 0x1C0
+#define RPD1R 0x1C4
+#define RPD2R 0x1C8
+#define RPD3R 0x1CC
+#define RPD4R 0x1D0
+#define RPD5R 0x1D4
+#define RPD6R 0x1D8
+#define RPD7R 0x1DC
+#define RPD9R 0x1E4
+#define RPD10R 0x1E8
+#define RPD11R 0x1EC
+#define RPD12R 0x1F0
+#define RPD14R 0x1F8
+#define RPD15R 0x1FC
+#define RPE3R 0x20C
+#define RPE5R 0x214
+#define RPE8R 0x220
+#define RPE9R 0x224
+#define RPF0R 0x240
+#define RPF1R 0x244
+#define RPF2R 0x248
+#define RPF3R 0x24C
+#define RPF4R 0x250
+#define RPF5R 0x254
+#define RPF8R 0x260
+#define RPF12R 0x270
+#define RPF13R 0x274
+#define RPG0R 0x280
+#define RPG1R 0x284
+#define RPG6R 0x298
+#define RPG7R 0x29C
+#define RPG8R 0x2A0
+#define RPG9R 0x2A4
+
+#endif /* PINCTRL_PINCTRL_PIC32_H */
RK3188,
RK3288,
RK3368,
+ RK3399,
};
/**
int offset;
};
+/**
+ * enum type index corresponding to rockchip_perpin_drv_list arrays index.
+ */
+enum rockchip_pin_drv_type {
+ DRV_TYPE_IO_DEFAULT = 0,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_ONLY,
+ DRV_TYPE_IO_1V8_3V0_AUTO,
+ DRV_TYPE_IO_3V3_ONLY,
+ DRV_TYPE_MAX
+};
+
+/**
+ * @drv_type: drive strength variant using rockchip_perpin_drv_type
+ * @offset: if initialized to -1 it will be autocalculated, by specifying
+ * an initial offset value the relevant source offset can be reset
+ * to a new value for autocalculating the following drive strength
+ * registers. if used chips own cal_drv func instead to calculate
+ * registers offset, the variant could be ignored.
+ */
+struct rockchip_drv {
+ enum rockchip_pin_drv_type drv_type;
+ int offset;
+};
+
/**
* @reg_base: register base of the gpio bank
* @reg_pull: optional separate register for additional pull settings
* @name: name of the bank
* @bank_num: number of the bank, to account for holes
* @iomux: array describing the 4 iomux sources of the bank
+ * @drv: array describing the 4 drive strength sources of the bank
* @valid: are all necessary informations present
* @of_node: dt node of this bank
* @drvdata: common pinctrl basedata
char *name;
u8 bank_num;
struct rockchip_iomux iomux[4];
+ struct rockchip_drv drv[4];
bool valid;
struct device_node *of_node;
struct rockchip_pinctrl *drvdata;
}, \
}
+#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ }, \
+ .drv = { \
+ { .drv_type = type0, .offset = -1 }, \
+ { .drv_type = type1, .offset = -1 }, \
+ { .drv_type = type2, .offset = -1 }, \
+ { .drv_type = type3, .offset = -1 }, \
+ }, \
+ }
+
+#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
+ iom2, iom3, drv0, drv1, drv2, \
+ drv3, offset0, offset1, \
+ offset2, offset3) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .type = iom0, .offset = -1 }, \
+ { .type = iom1, .offset = -1 }, \
+ { .type = iom2, .offset = -1 }, \
+ { .type = iom3, .offset = -1 }, \
+ }, \
+ .drv = { \
+ { .drv_type = drv0, .offset = offset0 }, \
+ { .drv_type = drv1, .offset = offset1 }, \
+ { .drv_type = drv2, .offset = offset2 }, \
+ { .drv_type = drv3, .offset = offset3 }, \
+ }, \
+ }
+
/**
*/
struct rockchip_pin_ctrl {
enum rockchip_pinctrl_type type;
int grf_mux_offset;
int pmu_mux_offset;
+ int grf_drv_offset;
+ int pmu_drv_offset;
+
void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
}
}
-static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 };
+#define RK3399_PULL_GRF_OFFSET 0xe040
+#define RK3399_PULL_PMU_OFFSET 0x40
+#define RK3399_DRV_3BITS_PER_PIN 3
+
+static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ /* The bank0:16 and bank1:32 pins are located in PMU */
+ if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
+ *regmap = info->regmap_pmu;
+ *reg = RK3399_PULL_PMU_OFFSET;
+
+ *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3188_PULL_PINS_PER_REG;
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RK3399_PULL_GRF_OFFSET;
+
+ /* correct the offset, as we're starting with the 3rd bank */
+ *reg -= 0x20;
+ *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ }
+}
+
+static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+ int drv_num = (pin_num / 8);
+
+ /* The bank0:16 and bank1:32 pins are located in PMU */
+ if ((bank->bank_num == 0) || (bank->bank_num == 1))
+ *regmap = info->regmap_pmu;
+ else
+ *regmap = info->regmap_base;
+
+ *reg = bank->drv[drv_num].offset;
+ if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
+ (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
+ *bit = (pin_num % 8) * 3;
+ else
+ *bit = (pin_num % 8) * 2;
+}
+
+static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
+ { 2, 4, 8, 12, -1, -1, -1, -1 },
+ { 3, 6, 9, 12, -1, -1, -1, -1 },
+ { 5, 10, 15, 20, -1, -1, -1, -1 },
+ { 4, 6, 8, 10, 12, 14, 16, 18 },
+ { 4, 7, 10, 13, 16, 19, 22, 26 }
+};
static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
int pin_num)
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
- u32 data;
+ u32 data, temp, rmask_bits;
u8 bit;
+ int drv_type = bank->drv[pin_num / 8].drv_type;
ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
+ switch (drv_type) {
+ case DRV_TYPE_IO_1V8_3V0_AUTO:
+ case DRV_TYPE_IO_3V3_ONLY:
+ rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+ switch (bit) {
+ case 0 ... 12:
+ /* regular case, nothing to do */
+ break;
+ case 15:
+ /*
+ * drive-strength offset is special, as it is
+ * spread over 2 registers
+ */
+ ret = regmap_read(regmap, reg, &data);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(regmap, reg + 0x4, &temp);
+ if (ret)
+ return ret;
+
+ /*
+ * the bit data[15] contains bit 0 of the value
+ * while temp[1:0] contains bits 2 and 1
+ */
+ data >>= 15;
+ temp &= 0x3;
+ temp <<= 1;
+ data |= temp;
+
+ return rockchip_perpin_drv_list[drv_type][data];
+ case 18 ... 21:
+ /* setting fully enclosed in the second register */
+ reg += 4;
+ bit -= 16;
+ break;
+ default:
+ dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
+ bit, drv_type);
+ return -EINVAL;
+ }
+
+ break;
+ case DRV_TYPE_IO_DEFAULT:
+ case DRV_TYPE_IO_1V8_OR_3V0:
+ case DRV_TYPE_IO_1V8_ONLY:
+ rmask_bits = RK3288_DRV_BITS_PER_PIN;
+ break;
+ default:
+ dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
+ drv_type);
+ return -EINVAL;
+ }
+
ret = regmap_read(regmap, reg, &data);
if (ret)
return ret;
data >>= bit;
- data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
+ data &= (1 << rmask_bits) - 1;
- return rockchip_perpin_drv_list[data];
+ return rockchip_perpin_drv_list[drv_type][data];
}
static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
struct regmap *regmap;
unsigned long flags;
int reg, ret, i;
- u32 data, rmask;
+ u32 data, rmask, rmask_bits, temp;
u8 bit;
+ int drv_type = bank->drv[pin_num / 8].drv_type;
+
+ dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
+ bank->bank_num, pin_num, strength);
ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
ret = -EINVAL;
- for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list); i++) {
- if (rockchip_perpin_drv_list[i] == strength) {
+ for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
+ if (rockchip_perpin_drv_list[drv_type][i] == strength) {
ret = i;
break;
+ } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
+ ret = rockchip_perpin_drv_list[drv_type][i];
+ break;
}
}
spin_lock_irqsave(&bank->slock, flags);
+ switch (drv_type) {
+ case DRV_TYPE_IO_1V8_3V0_AUTO:
+ case DRV_TYPE_IO_3V3_ONLY:
+ rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+ switch (bit) {
+ case 0 ... 12:
+ /* regular case, nothing to do */
+ break;
+ case 15:
+ /*
+ * drive-strength offset is special, as it is spread
+ * over 2 registers, the bit data[15] contains bit 0
+ * of the value while temp[1:0] contains bits 2 and 1
+ */
+ data = (ret & 0x1) << 15;
+ temp = (ret >> 0x1) & 0x3;
+
+ rmask = BIT(15) | BIT(31);
+ data |= BIT(31);
+ ret = regmap_update_bits(regmap, reg, rmask, data);
+ if (ret) {
+ spin_unlock_irqrestore(&bank->slock, flags);
+ return ret;
+ }
+
+ rmask = 0x3 | (0x3 << 16);
+ temp |= (0x3 << 16);
+ reg += 0x4;
+ ret = regmap_update_bits(regmap, reg, rmask, temp);
+
+ spin_unlock_irqrestore(&bank->slock, flags);
+ return ret;
+ case 18 ... 21:
+ /* setting fully enclosed in the second register */
+ reg += 4;
+ bit -= 16;
+ break;
+ default:
+ spin_unlock_irqrestore(&bank->slock, flags);
+ dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
+ bit, drv_type);
+ return -EINVAL;
+ }
+ break;
+ case DRV_TYPE_IO_DEFAULT:
+ case DRV_TYPE_IO_1V8_OR_3V0:
+ case DRV_TYPE_IO_1V8_ONLY:
+ rmask_bits = RK3288_DRV_BITS_PER_PIN;
+ break;
+ default:
+ spin_unlock_irqrestore(&bank->slock, flags);
+ dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
+ drv_type);
+ return -EINVAL;
+ }
+
/* enable the write to the equivalent lower bits */
- data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ data = ((1 << rmask_bits) - 1) << (bit + 16);
rmask = data | (data >> 16);
data |= (ret << bit);
case RK3188:
case RK3288:
case RK3368:
+ case RK3399:
data >>= bit;
data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
case RK3188:
case RK3288:
case RK3368:
+ case RK3399:
spin_lock_irqsave(&bank->slock, flags);
/* enable the write to the equivalent lower bits */
case RK3188:
case RK3288:
case RK3368:
+ case RK3399:
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
}
struct device_node *np;
struct rockchip_pin_ctrl *ctrl;
struct rockchip_pin_bank *bank;
- int grf_offs, pmu_offs, i, j;
+ int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
match = of_match_node(rockchip_pinctrl_dt_match, node);
ctrl = (struct rockchip_pin_ctrl *)match->data;
grf_offs = ctrl->grf_mux_offset;
pmu_offs = ctrl->pmu_mux_offset;
+ drv_pmu_offs = ctrl->pmu_drv_offset;
+ drv_grf_offs = ctrl->grf_drv_offset;
bank = ctrl->pin_banks;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
int bank_pins = 0;
bank->pin_base = ctrl->nr_pins;
ctrl->nr_pins += bank->nr_pins;
- /* calculate iomux offsets */
+ /* calculate iomux and drv offsets */
for (j = 0; j < 4; j++) {
struct rockchip_iomux *iom = &bank->iomux[j];
+ struct rockchip_drv *drv = &bank->drv[j];
int inc;
if (bank_pins >= bank->nr_pins)
break;
- /* preset offset value, set new start value */
+ /* preset iomux offset value, set new start value */
if (iom->offset >= 0) {
if (iom->type & IOMUX_SOURCE_PMU)
pmu_offs = iom->offset;
else
grf_offs = iom->offset;
- } else { /* set current offset */
+ } else { /* set current iomux offset */
iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
pmu_offs : grf_offs;
}
- dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
- i, j, iom->offset);
+ /* preset drv offset value, set new start value */
+ if (drv->offset >= 0) {
+ if (iom->type & IOMUX_SOURCE_PMU)
+ drv_pmu_offs = drv->offset;
+ else
+ drv_grf_offs = drv->offset;
+ } else { /* set current drv offset */
+ drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
+ drv_pmu_offs : drv_grf_offs;
+ }
+
+ dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
+ i, j, iom->offset, drv->offset);
/*
* Increase offset according to iomux width.
else
grf_offs += inc;
+ /*
+ * Increase offset according to drv width.
+ * 3bit drive-strenth'es are spread over two registers.
+ */
+ if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
+ (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
+ inc = 8;
+ else
+ inc = 4;
+
+ if (iom->type & IOMUX_SOURCE_PMU)
+ drv_pmu_offs += inc;
+ else
+ drv_grf_offs += inc;
+
bank_pins += 8;
}
}
.drv_calc_reg = rk3368_calc_drv_reg_and_bit,
};
+static struct rockchip_pin_bank rk3399_pin_banks[] = {
+ PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(0, 32, "gpio0", IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ DRV_TYPE_IO_1V8_ONLY,
+ DRV_TYPE_IO_1V8_ONLY,
+ DRV_TYPE_IO_DEFAULT,
+ DRV_TYPE_IO_DEFAULT,
+ 0x0,
+ 0x8,
+ -1,
+ -1
+ ),
+ PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ 0x20,
+ 0x28,
+ 0x30,
+ 0x38
+ ),
+ PIN_BANK_DRV_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_ONLY,
+ DRV_TYPE_IO_1V8_ONLY
+ ),
+ PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
+ DRV_TYPE_IO_3V3_ONLY,
+ DRV_TYPE_IO_3V3_ONLY,
+ DRV_TYPE_IO_1V8_OR_3V0
+ ),
+ PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_3V0_AUTO,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_OR_3V0
+ ),
+};
+
+static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
+ .pin_banks = rk3399_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
+ .label = "RK3399-GPIO",
+ .type = RK3399,
+ .grf_mux_offset = 0xe000,
+ .pmu_mux_offset = 0x0,
+ .grf_drv_offset = 0xe100,
+ .pmu_drv_offset = 0x80,
+ .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
+ .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
+};
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
{ .compatible = "rockchip,rk2928-pinctrl",
.data = (void *)&rk3288_pin_ctrl },
{ .compatible = "rockchip,rk3368-pinctrl",
.data = (void *)&rk3368_pin_ctrl },
+ { .compatible = "rockchip,rk3399-pinctrl",
+ .data = (void *)&rk3399_pin_ctrl },
{},
};
MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
PIN_CONFIG_BIAS_PULL_UP,
};
+/*
+ * This lock class tells lockdep that irqchip core that this single
+ * pinctrl can be in a different category than its parents, so it won't
+ * report false recursion.
+ */
+static struct lock_class_key pcs_lock_class;
+
/*
* REVISIT: Reads and writes could eventually use regmap or something
* generic. But at least on omaps, some mux registers are performance
irq_set_chip_data(irq, pcs_soc);
irq_set_chip_and_handler(irq, &pcs->chip,
handle_level_irq);
+ irq_set_lockdep_class(irq, &pcs_lock_class);
irq_set_noprobe(irq);
return 0;
.get_function_groups = st_pmx_get_groups,
.set_mux = st_pmx_set_mux,
.gpio_set_direction = st_pmx_set_gpio_direction,
+ .strict = true,
};
/* Pinconf */
+++ /dev/null
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/phy/phy.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/reset.h>
-#include <linux/slab.h>
-
-#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
-
-#include "core.h"
-#include "pinctrl-utils.h"
-
-#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
-#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
-#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
-#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
-
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
-
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
-
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
-
-#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
-#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
-#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
-
-struct tegra_xusb_padctl_function {
- const char *name;
- const char * const *groups;
- unsigned int num_groups;
-};
-
-struct tegra_xusb_padctl_soc {
- const struct pinctrl_pin_desc *pins;
- unsigned int num_pins;
-
- const struct tegra_xusb_padctl_function *functions;
- unsigned int num_functions;
-
- const struct tegra_xusb_padctl_lane *lanes;
- unsigned int num_lanes;
-};
-
-struct tegra_xusb_padctl_lane {
- const char *name;
-
- unsigned int offset;
- unsigned int shift;
- unsigned int mask;
- unsigned int iddq;
-
- const unsigned int *funcs;
- unsigned int num_funcs;
-};
-
-struct tegra_xusb_padctl {
- struct device *dev;
- void __iomem *regs;
- struct mutex lock;
- struct reset_control *rst;
-
- const struct tegra_xusb_padctl_soc *soc;
- struct pinctrl_dev *pinctrl;
- struct pinctrl_desc desc;
-
- struct phy_provider *provider;
- struct phy *phys[2];
-
- unsigned int enable;
-};
-
-static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
- unsigned long offset)
-{
- writel(value, padctl->regs + offset);
-}
-
-static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
- unsigned long offset)
-{
- return readl(padctl->regs + offset);
-}
-
-static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl)
-{
- struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
-
- return padctl->soc->num_pins;
-}
-
-static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
- unsigned int group)
-{
- struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
-
- return padctl->soc->pins[group].name;
-}
-
-static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl,
- unsigned group,
- const unsigned **pins,
- unsigned *num_pins)
-{
- /*
- * For the tegra-xusb pad controller groups are synonomous
- * with lanes/pins and there is always one lane/pin per group.
- */
- *pins = &pinctrl->desc->pins[group].number;
- *num_pins = 1;
-
- return 0;
-}
-
-enum tegra_xusb_padctl_param {
- TEGRA_XUSB_PADCTL_IDDQ,
-};
-
-static const struct tegra_xusb_padctl_property {
- const char *name;
- enum tegra_xusb_padctl_param param;
-} properties[] = {
- { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ },
-};
-
-#define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value))
-#define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16)
-#define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
-
-static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
- struct device_node *np,
- struct pinctrl_map **maps,
- unsigned int *reserved_maps,
- unsigned int *num_maps)
-{
- unsigned int i, reserve = 0, num_configs = 0;
- unsigned long config, *configs = NULL;
- const char *function, *group;
- struct property *prop;
- int err = 0;
- u32 value;
-
- err = of_property_read_string(np, "nvidia,function", &function);
- if (err < 0) {
- if (err != -EINVAL)
- return err;
-
- function = NULL;
- }
-
- for (i = 0; i < ARRAY_SIZE(properties); i++) {
- err = of_property_read_u32(np, properties[i].name, &value);
- if (err < 0) {
- if (err == -EINVAL)
- continue;
-
- goto out;
- }
-
- config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value);
-
- err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
- &num_configs, config);
- if (err < 0)
- goto out;
- }
-
- if (function)
- reserve++;
-
- if (num_configs)
- reserve++;
-
- err = of_property_count_strings(np, "nvidia,lanes");
- if (err < 0)
- goto out;
-
- reserve *= err;
-
- err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
- num_maps, reserve);
- if (err < 0)
- goto out;
-
- of_property_for_each_string(np, "nvidia,lanes", prop, group) {
- if (function) {
- err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
- reserved_maps, num_maps, group,
- function);
- if (err < 0)
- goto out;
- }
-
- if (num_configs) {
- err = pinctrl_utils_add_map_configs(padctl->pinctrl,
- maps, reserved_maps, num_maps, group,
- configs, num_configs,
- PIN_MAP_TYPE_CONFIGS_GROUP);
- if (err < 0)
- goto out;
- }
- }
-
- err = 0;
-
-out:
- kfree(configs);
- return err;
-}
-
-static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
- struct device_node *parent,
- struct pinctrl_map **maps,
- unsigned int *num_maps)
-{
- struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
- unsigned int reserved_maps = 0;
- struct device_node *np;
- int err;
-
- *num_maps = 0;
- *maps = NULL;
-
- for_each_child_of_node(parent, np) {
- err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
- &reserved_maps,
- num_maps);
- if (err < 0) {
- of_node_put(np);
- return err;
- }
- }
-
- return 0;
-}
-
-static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
- .get_groups_count = tegra_xusb_padctl_get_groups_count,
- .get_group_name = tegra_xusb_padctl_get_group_name,
- .get_group_pins = tegra_xusb_padctl_get_group_pins,
- .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
- .dt_free_map = pinctrl_utils_dt_free_map,
-};
-
-static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl)
-{
- struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
-
- return padctl->soc->num_functions;
-}
-
-static const char *
-tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl,
- unsigned int function)
-{
- struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
-
- return padctl->soc->functions[function].name;
-}
-
-static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
- unsigned int function,
- const char * const **groups,
- unsigned * const num_groups)
-{
- struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
-
- *num_groups = padctl->soc->functions[function].num_groups;
- *groups = padctl->soc->functions[function].groups;
-
- return 0;
-}
-
-static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
- unsigned int function,
- unsigned int group)
-{
- struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
- const struct tegra_xusb_padctl_lane *lane;
- unsigned int i;
- u32 value;
-
- lane = &padctl->soc->lanes[group];
-
- for (i = 0; i < lane->num_funcs; i++)
- if (lane->funcs[i] == function)
- break;
-
- if (i >= lane->num_funcs)
- return -EINVAL;
-
- value = padctl_readl(padctl, lane->offset);
- value &= ~(lane->mask << lane->shift);
- value |= i << lane->shift;
- padctl_writel(padctl, value, lane->offset);
-
- return 0;
-}
-
-static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
- .get_functions_count = tegra_xusb_padctl_get_functions_count,
- .get_function_name = tegra_xusb_padctl_get_function_name,
- .get_function_groups = tegra_xusb_padctl_get_function_groups,
- .set_mux = tegra_xusb_padctl_pinmux_set,
-};
-
-static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
- unsigned int group,
- unsigned long *config)
-{
- struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
- const struct tegra_xusb_padctl_lane *lane;
- enum tegra_xusb_padctl_param param;
- u32 value;
-
- param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config);
- lane = &padctl->soc->lanes[group];
-
- switch (param) {
- case TEGRA_XUSB_PADCTL_IDDQ:
- /* lanes with iddq == 0 don't support this parameter */
- if (lane->iddq == 0)
- return -EINVAL;
-
- value = padctl_readl(padctl, lane->offset);
-
- if (value & BIT(lane->iddq))
- value = 0;
- else
- value = 1;
-
- *config = TEGRA_XUSB_PADCTL_PACK(param, value);
- break;
-
- default:
- dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
- param);
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
- unsigned int group,
- unsigned long *configs,
- unsigned int num_configs)
-{
- struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
- const struct tegra_xusb_padctl_lane *lane;
- enum tegra_xusb_padctl_param param;
- unsigned long value;
- unsigned int i;
- u32 regval;
-
- lane = &padctl->soc->lanes[group];
-
- for (i = 0; i < num_configs; i++) {
- param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]);
- value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]);
-
- switch (param) {
- case TEGRA_XUSB_PADCTL_IDDQ:
- /* lanes with iddq == 0 don't support this parameter */
- if (lane->iddq == 0)
- return -EINVAL;
-
- regval = padctl_readl(padctl, lane->offset);
-
- if (value)
- regval &= ~BIT(lane->iddq);
- else
- regval |= BIT(lane->iddq);
-
- padctl_writel(padctl, regval, lane->offset);
- break;
-
- default:
- dev_err(padctl->dev,
- "invalid configuration parameter: %04x\n",
- param);
- return -ENOTSUPP;
- }
- }
-
- return 0;
-}
-
-#ifdef CONFIG_DEBUG_FS
-static const char *strip_prefix(const char *s)
-{
- const char *comma = strchr(s, ',');
- if (!comma)
- return s;
-
- return comma + 1;
-}
-
-static void
-tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl,
- struct seq_file *s,
- unsigned int group)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(properties); i++) {
- unsigned long config, value;
- int err;
-
- config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0);
-
- err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group,
- &config);
- if (err < 0)
- continue;
-
- value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
-
- seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name),
- value);
- }
-}
-
-static void
-tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl,
- struct seq_file *s,
- unsigned long config)
-{
- enum tegra_xusb_padctl_param param;
- const char *name = "unknown";
- unsigned long value;
- unsigned int i;
-
- param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config);
- value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
-
- for (i = 0; i < ARRAY_SIZE(properties); i++) {
- if (properties[i].param == param) {
- name = properties[i].name;
- break;
- }
- }
-
- seq_printf(s, "%s=%lu", strip_prefix(name), value);
-}
-#endif
-
-static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = {
- .pin_config_group_get = tegra_xusb_padctl_pinconf_group_get,
- .pin_config_group_set = tegra_xusb_padctl_pinconf_group_set,
-#ifdef CONFIG_DEBUG_FS
- .pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show,
- .pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show,
-#endif
-};
-
-static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
-{
- u32 value;
-
- mutex_lock(&padctl->lock);
-
- if (padctl->enable++ > 0)
- goto out;
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- usleep_range(100, 200);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- usleep_range(100, 200);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
-out:
- mutex_unlock(&padctl->lock);
- return 0;
-}
-
-static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
-{
- u32 value;
-
- mutex_lock(&padctl->lock);
-
- if (WARN_ON(padctl->enable == 0))
- goto out;
-
- if (--padctl->enable > 0)
- goto out;
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- usleep_range(100, 200);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- usleep_range(100, 200);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
-out:
- mutex_unlock(&padctl->lock);
- return 0;
-}
-
-static int tegra_xusb_phy_init(struct phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
-
- return tegra_xusb_padctl_enable(padctl);
-}
-
-static int tegra_xusb_phy_exit(struct phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
-
- return tegra_xusb_padctl_disable(padctl);
-}
-
-static int pcie_phy_power_on(struct phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
- unsigned long timeout;
- int err = -ETIMEDOUT;
- u32 value;
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
- value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
- XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
- XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
- value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
-
- timeout = jiffies + msecs_to_jiffies(50);
-
- while (time_before(jiffies, timeout)) {
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
- if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
- err = 0;
- break;
- }
-
- usleep_range(100, 200);
- }
-
- return err;
-}
-
-static int pcie_phy_power_off(struct phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
- u32 value;
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
-
- return 0;
-}
-
-static const struct phy_ops pcie_phy_ops = {
- .init = tegra_xusb_phy_init,
- .exit = tegra_xusb_phy_exit,
- .power_on = pcie_phy_power_on,
- .power_off = pcie_phy_power_off,
- .owner = THIS_MODULE,
-};
-
-static int sata_phy_power_on(struct phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
- unsigned long timeout;
- int err = -ETIMEDOUT;
- u32 value;
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
- value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
- value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- timeout = jiffies + msecs_to_jiffies(50);
-
- while (time_before(jiffies, timeout)) {
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
- err = 0;
- break;
- }
-
- usleep_range(100, 200);
- }
-
- return err;
-}
-
-static int sata_phy_power_off(struct phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
- u32 value;
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
- value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
- value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
- value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
-
- return 0;
-}
-
-static const struct phy_ops sata_phy_ops = {
- .init = tegra_xusb_phy_init,
- .exit = tegra_xusb_phy_exit,
- .power_on = sata_phy_power_on,
- .power_off = sata_phy_power_off,
- .owner = THIS_MODULE,
-};
-
-static struct phy *tegra_xusb_padctl_xlate(struct device *dev,
- struct of_phandle_args *args)
-{
- struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
- unsigned int index = args->args[0];
-
- if (args->args_count <= 0)
- return ERR_PTR(-EINVAL);
-
- if (index >= ARRAY_SIZE(padctl->phys))
- return ERR_PTR(-EINVAL);
-
- return padctl->phys[index];
-}
-
-#define PIN_OTG_0 0
-#define PIN_OTG_1 1
-#define PIN_OTG_2 2
-#define PIN_ULPI_0 3
-#define PIN_HSIC_0 4
-#define PIN_HSIC_1 5
-#define PIN_PCIE_0 6
-#define PIN_PCIE_1 7
-#define PIN_PCIE_2 8
-#define PIN_PCIE_3 9
-#define PIN_PCIE_4 10
-#define PIN_SATA_0 11
-
-static const struct pinctrl_pin_desc tegra124_pins[] = {
- PINCTRL_PIN(PIN_OTG_0, "otg-0"),
- PINCTRL_PIN(PIN_OTG_1, "otg-1"),
- PINCTRL_PIN(PIN_OTG_2, "otg-2"),
- PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
- PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
- PINCTRL_PIN(PIN_HSIC_1, "hsic-1"),
- PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
- PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
- PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
- PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
- PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
- PINCTRL_PIN(PIN_SATA_0, "sata-0"),
-};
-
-static const char * const tegra124_snps_groups[] = {
- "otg-0",
- "otg-1",
- "otg-2",
- "ulpi-0",
- "hsic-0",
- "hsic-1",
-};
-
-static const char * const tegra124_xusb_groups[] = {
- "otg-0",
- "otg-1",
- "otg-2",
- "ulpi-0",
- "hsic-0",
- "hsic-1",
-};
-
-static const char * const tegra124_uart_groups[] = {
- "otg-0",
- "otg-1",
- "otg-2",
-};
-
-static const char * const tegra124_pcie_groups[] = {
- "pcie-0",
- "pcie-1",
- "pcie-2",
- "pcie-3",
- "pcie-4",
-};
-
-static const char * const tegra124_usb3_groups[] = {
- "pcie-0",
- "pcie-1",
- "sata-0",
-};
-
-static const char * const tegra124_sata_groups[] = {
- "sata-0",
-};
-
-static const char * const tegra124_rsvd_groups[] = {
- "otg-0",
- "otg-1",
- "otg-2",
- "pcie-0",
- "pcie-1",
- "pcie-2",
- "pcie-3",
- "pcie-4",
- "sata-0",
-};
-
-#define TEGRA124_FUNCTION(_name) \
- { \
- .name = #_name, \
- .num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \
- .groups = tegra124_##_name##_groups, \
- }
-
-static struct tegra_xusb_padctl_function tegra124_functions[] = {
- TEGRA124_FUNCTION(snps),
- TEGRA124_FUNCTION(xusb),
- TEGRA124_FUNCTION(uart),
- TEGRA124_FUNCTION(pcie),
- TEGRA124_FUNCTION(usb3),
- TEGRA124_FUNCTION(sata),
- TEGRA124_FUNCTION(rsvd),
-};
-
-enum tegra124_function {
- TEGRA124_FUNC_SNPS,
- TEGRA124_FUNC_XUSB,
- TEGRA124_FUNC_UART,
- TEGRA124_FUNC_PCIE,
- TEGRA124_FUNC_USB3,
- TEGRA124_FUNC_SATA,
- TEGRA124_FUNC_RSVD,
-};
-
-static const unsigned int tegra124_otg_functions[] = {
- TEGRA124_FUNC_SNPS,
- TEGRA124_FUNC_XUSB,
- TEGRA124_FUNC_UART,
- TEGRA124_FUNC_RSVD,
-};
-
-static const unsigned int tegra124_usb_functions[] = {
- TEGRA124_FUNC_SNPS,
- TEGRA124_FUNC_XUSB,
-};
-
-static const unsigned int tegra124_pci_functions[] = {
- TEGRA124_FUNC_PCIE,
- TEGRA124_FUNC_USB3,
- TEGRA124_FUNC_SATA,
- TEGRA124_FUNC_RSVD,
-};
-
-#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
- { \
- .name = _name, \
- .offset = _offset, \
- .shift = _shift, \
- .mask = _mask, \
- .iddq = _iddq, \
- .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
- .funcs = tegra124_##_funcs##_functions, \
- }
-
-static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
- TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
- TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
- TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
- TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
- TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
- TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
- TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
- TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
- TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
- TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
- TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
- TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
-};
-
-static const struct tegra_xusb_padctl_soc tegra124_soc = {
- .num_pins = ARRAY_SIZE(tegra124_pins),
- .pins = tegra124_pins,
- .num_functions = ARRAY_SIZE(tegra124_functions),
- .functions = tegra124_functions,
- .num_lanes = ARRAY_SIZE(tegra124_lanes),
- .lanes = tegra124_lanes,
-};
-
-static const struct of_device_id tegra_xusb_padctl_of_match[] = {
- { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
- { }
-};
-MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match);
-
-static int tegra_xusb_padctl_probe(struct platform_device *pdev)
-{
- struct tegra_xusb_padctl *padctl;
- const struct of_device_id *match;
- struct resource *res;
- struct phy *phy;
- int err;
-
- padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
- if (!padctl)
- return -ENOMEM;
-
- platform_set_drvdata(pdev, padctl);
- mutex_init(&padctl->lock);
- padctl->dev = &pdev->dev;
-
- match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node);
- padctl->soc = match->data;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- padctl->regs = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(padctl->regs))
- return PTR_ERR(padctl->regs);
-
- padctl->rst = devm_reset_control_get(&pdev->dev, NULL);
- if (IS_ERR(padctl->rst))
- return PTR_ERR(padctl->rst);
-
- err = reset_control_deassert(padctl->rst);
- if (err < 0)
- return err;
-
- memset(&padctl->desc, 0, sizeof(padctl->desc));
- padctl->desc.name = dev_name(padctl->dev);
- padctl->desc.pins = tegra124_pins;
- padctl->desc.npins = ARRAY_SIZE(tegra124_pins);
- padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
- padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
- padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
- padctl->desc.owner = THIS_MODULE;
-
- padctl->pinctrl = pinctrl_register(&padctl->desc, &pdev->dev, padctl);
- if (IS_ERR(padctl->pinctrl)) {
- dev_err(&pdev->dev, "failed to register pincontrol\n");
- err = PTR_ERR(padctl->pinctrl);
- goto reset;
- }
-
- phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops);
- if (IS_ERR(phy)) {
- err = PTR_ERR(phy);
- goto unregister;
- }
-
- padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
- phy_set_drvdata(phy, padctl);
-
- phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops);
- if (IS_ERR(phy)) {
- err = PTR_ERR(phy);
- goto unregister;
- }
-
- padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
- phy_set_drvdata(phy, padctl);
-
- padctl->provider = devm_of_phy_provider_register(&pdev->dev,
- tegra_xusb_padctl_xlate);
- if (IS_ERR(padctl->provider)) {
- err = PTR_ERR(padctl->provider);
- dev_err(&pdev->dev, "failed to register PHYs: %d\n", err);
- goto unregister;
- }
-
- return 0;
-
-unregister:
- pinctrl_unregister(padctl->pinctrl);
-reset:
- reset_control_assert(padctl->rst);
- return err;
-}
-
-static int tegra_xusb_padctl_remove(struct platform_device *pdev)
-{
- struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
- int err;
-
- pinctrl_unregister(padctl->pinctrl);
-
- err = reset_control_assert(padctl->rst);
- if (err < 0)
- dev_err(&pdev->dev, "failed to assert reset: %d\n", err);
-
- return err;
-}
-
-static struct platform_driver tegra_xusb_padctl_driver = {
- .driver = {
- .name = "tegra-xusb-padctl",
- .of_match_table = tegra_xusb_padctl_of_match,
- },
- .probe = tegra_xusb_padctl_probe,
- .remove = tegra_xusb_padctl_remove,
-};
-module_platform_driver(tegra_xusb_padctl_driver);
-
-MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
-MODULE_DESCRIPTION("Tegra 124 XUSB Pad Control driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * Driver for the NVIDIA Tegra pinmux
- *
- * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
- *
- * Derived from code:
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2010 NVIDIA Corporation
- * Copyright (C) 2009-2011 ST-Ericsson AB
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/slab.h>
-
-#include "core.h"
-#include "pinctrl-tegra.h"
-#include "pinctrl-utils.h"
-
-struct tegra_pmx {
- struct device *dev;
- struct pinctrl_dev *pctl;
-
- const struct tegra_pinctrl_soc_data *soc;
- const char **group_pins;
-
- int nbanks;
- void __iomem **regs;
-};
-
-static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
-{
- return readl(pmx->regs[bank] + reg);
-}
-
-static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
-{
- writel(val, pmx->regs[bank] + reg);
-}
-
-static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
-{
- struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
- return pmx->soc->ngroups;
-}
-
-static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
- unsigned group)
-{
- struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
- return pmx->soc->groups[group].name;
-}
-
-static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
- unsigned group,
- const unsigned **pins,
- unsigned *num_pins)
-{
- struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
- *pins = pmx->soc->groups[group].pins;
- *num_pins = pmx->soc->groups[group].npins;
-
- return 0;
-}
-
-#ifdef CONFIG_DEBUG_FS
-static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s,
- unsigned offset)
-{
- seq_printf(s, " %s", dev_name(pctldev->dev));
-}
-#endif
-
-static const struct cfg_param {
- const char *property;
- enum tegra_pinconf_param param;
-} cfg_params[] = {
- {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
- {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
- {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
- {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
- {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
- {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
- {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
- {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
- {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
- {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
- {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
- {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
- {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
- {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
- {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
- {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
-};
-
-static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np,
- struct pinctrl_map **map,
- unsigned *reserved_maps,
- unsigned *num_maps)
-{
- struct device *dev = pctldev->dev;
- int ret, i;
- const char *function;
- u32 val;
- unsigned long config;
- unsigned long *configs = NULL;
- unsigned num_configs = 0;
- unsigned reserve;
- struct property *prop;
- const char *group;
-
- ret = of_property_read_string(np, "nvidia,function", &function);
- if (ret < 0) {
- /* EINVAL=missing, which is fine since it's optional */
- if (ret != -EINVAL)
- dev_err(dev,
- "could not parse property nvidia,function\n");
- function = NULL;
- }
-
- for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
- ret = of_property_read_u32(np, cfg_params[i].property, &val);
- if (!ret) {
- config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
- ret = pinctrl_utils_add_config(pctldev, &configs,
- &num_configs, config);
- if (ret < 0)
- goto exit;
- /* EINVAL=missing, which is fine since it's optional */
- } else if (ret != -EINVAL) {
- dev_err(dev, "could not parse property %s\n",
- cfg_params[i].property);
- }
- }
-
- reserve = 0;
- if (function != NULL)
- reserve++;
- if (num_configs)
- reserve++;
- ret = of_property_count_strings(np, "nvidia,pins");
- if (ret < 0) {
- dev_err(dev, "could not parse property nvidia,pins\n");
- goto exit;
- }
- reserve *= ret;
-
- ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
- num_maps, reserve);
- if (ret < 0)
- goto exit;
-
- of_property_for_each_string(np, "nvidia,pins", prop, group) {
- if (function) {
- ret = pinctrl_utils_add_map_mux(pctldev, map,
- reserved_maps, num_maps, group,
- function);
- if (ret < 0)
- goto exit;
- }
-
- if (num_configs) {
- ret = pinctrl_utils_add_map_configs(pctldev, map,
- reserved_maps, num_maps, group,
- configs, num_configs,
- PIN_MAP_TYPE_CONFIGS_GROUP);
- if (ret < 0)
- goto exit;
- }
- }
-
- ret = 0;
-
-exit:
- kfree(configs);
- return ret;
-}
-
-static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np_config,
- struct pinctrl_map **map,
- unsigned *num_maps)
-{
- unsigned reserved_maps;
- struct device_node *np;
- int ret;
-
- reserved_maps = 0;
- *map = NULL;
- *num_maps = 0;
-
- for_each_child_of_node(np_config, np) {
- ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
- &reserved_maps, num_maps);
- if (ret < 0) {
- pinctrl_utils_dt_free_map(pctldev, *map,
- *num_maps);
- of_node_put(np);
- return ret;
- }
- }
-
- return 0;
-}
-
-static const struct pinctrl_ops tegra_pinctrl_ops = {
- .get_groups_count = tegra_pinctrl_get_groups_count,
- .get_group_name = tegra_pinctrl_get_group_name,
- .get_group_pins = tegra_pinctrl_get_group_pins,
-#ifdef CONFIG_DEBUG_FS
- .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
-#endif
- .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
- .dt_free_map = pinctrl_utils_dt_free_map,
-};
-
-static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
-{
- struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
- return pmx->soc->nfunctions;
-}
-
-static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
- unsigned function)
-{
- struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
- return pmx->soc->functions[function].name;
-}
-
-static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
- unsigned function,
- const char * const **groups,
- unsigned * const num_groups)
-{
- struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
- *groups = pmx->soc->functions[function].groups;
- *num_groups = pmx->soc->functions[function].ngroups;
-
- return 0;
-}
-
-static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
- unsigned function,
- unsigned group)
-{
- struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- const struct tegra_pingroup *g;
- int i;
- u32 val;
-
- g = &pmx->soc->groups[group];
-
- if (WARN_ON(g->mux_reg < 0))
- return -EINVAL;
-
- for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
- if (g->funcs[i] == function)
- break;
- }
- if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
- return -EINVAL;
-
- val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
- val &= ~(0x3 << g->mux_bit);
- val |= i << g->mux_bit;
- pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
-
- return 0;
-}
-
-static const struct pinmux_ops tegra_pinmux_ops = {
- .get_functions_count = tegra_pinctrl_get_funcs_count,
- .get_function_name = tegra_pinctrl_get_func_name,
- .get_function_groups = tegra_pinctrl_get_func_groups,
- .set_mux = tegra_pinctrl_set_mux,
-};
-
-static int tegra_pinconf_reg(struct tegra_pmx *pmx,
- const struct tegra_pingroup *g,
- enum tegra_pinconf_param param,
- bool report_err,
- s8 *bank, s16 *reg, s8 *bit, s8 *width)
-{
- switch (param) {
- case TEGRA_PINCONF_PARAM_PULL:
- *bank = g->pupd_bank;
- *reg = g->pupd_reg;
- *bit = g->pupd_bit;
- *width = 2;
- break;
- case TEGRA_PINCONF_PARAM_TRISTATE:
- *bank = g->tri_bank;
- *reg = g->tri_reg;
- *bit = g->tri_bit;
- *width = 1;
- break;
- case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
- *bank = g->mux_bank;
- *reg = g->mux_reg;
- *bit = g->einput_bit;
- *width = 1;
- break;
- case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
- *bank = g->mux_bank;
- *reg = g->mux_reg;
- *bit = g->odrain_bit;
- *width = 1;
- break;
- case TEGRA_PINCONF_PARAM_LOCK:
- *bank = g->mux_bank;
- *reg = g->mux_reg;
- *bit = g->lock_bit;
- *width = 1;
- break;
- case TEGRA_PINCONF_PARAM_IORESET:
- *bank = g->mux_bank;
- *reg = g->mux_reg;
- *bit = g->ioreset_bit;
- *width = 1;
- break;
- case TEGRA_PINCONF_PARAM_RCV_SEL:
- *bank = g->mux_bank;
- *reg = g->mux_reg;
- *bit = g->rcv_sel_bit;
- *width = 1;
- break;
- case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
- if (pmx->soc->hsm_in_mux) {
- *bank = g->mux_bank;
- *reg = g->mux_reg;
- } else {
- *bank = g->drv_bank;
- *reg = g->drv_reg;
- }
- *bit = g->hsm_bit;
- *width = 1;
- break;
- case TEGRA_PINCONF_PARAM_SCHMITT:
- if (pmx->soc->schmitt_in_mux) {
- *bank = g->mux_bank;
- *reg = g->mux_reg;
- } else {
- *bank = g->drv_bank;
- *reg = g->drv_reg;
- }
- *bit = g->schmitt_bit;
- *width = 1;
- break;
- case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
- *bank = g->drv_bank;
- *reg = g->drv_reg;
- *bit = g->lpmd_bit;
- *width = 2;
- break;
- case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
- *bank = g->drv_bank;
- *reg = g->drv_reg;
- *bit = g->drvdn_bit;
- *width = g->drvdn_width;
- break;
- case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
- *bank = g->drv_bank;
- *reg = g->drv_reg;
- *bit = g->drvup_bit;
- *width = g->drvup_width;
- break;
- case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
- *bank = g->drv_bank;
- *reg = g->drv_reg;
- *bit = g->slwf_bit;
- *width = g->slwf_width;
- break;
- case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
- *bank = g->drv_bank;
- *reg = g->drv_reg;
- *bit = g->slwr_bit;
- *width = g->slwr_width;
- break;
- case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
- if (pmx->soc->drvtype_in_mux) {
- *bank = g->mux_bank;
- *reg = g->mux_reg;
- } else {
- *bank = g->drv_bank;
- *reg = g->drv_reg;
- }
- *bit = g->drvtype_bit;
- *width = 2;
- break;
- default:
- dev_err(pmx->dev, "Invalid config param %04x\n", param);
- return -ENOTSUPP;
- }
-
- if (*reg < 0 || *bit > 31) {
- if (report_err) {
- const char *prop = "unknown";
- int i;
-
- for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
- if (cfg_params[i].param == param) {
- prop = cfg_params[i].property;
- break;
- }
- }
-
- dev_err(pmx->dev,
- "Config param %04x (%s) not supported on group %s\n",
- param, prop, g->name);
- }
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
- unsigned pin, unsigned long *config)
-{
- dev_err(pctldev->dev, "pin_config_get op not supported\n");
- return -ENOTSUPP;
-}
-
-static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
- unsigned pin, unsigned long *configs,
- unsigned num_configs)
-{
- dev_err(pctldev->dev, "pin_config_set op not supported\n");
- return -ENOTSUPP;
-}
-
-static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
- unsigned group, unsigned long *config)
-{
- struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
- u16 arg;
- const struct tegra_pingroup *g;
- int ret;
- s8 bank, bit, width;
- s16 reg;
- u32 val, mask;
-
- g = &pmx->soc->groups[group];
-
- ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
- &width);
- if (ret < 0)
- return ret;
-
- val = pmx_readl(pmx, bank, reg);
- mask = (1 << width) - 1;
- arg = (val >> bit) & mask;
-
- *config = TEGRA_PINCONF_PACK(param, arg);
-
- return 0;
-}
-
-static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
- unsigned group, unsigned long *configs,
- unsigned num_configs)
-{
- struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- enum tegra_pinconf_param param;
- u16 arg;
- const struct tegra_pingroup *g;
- int ret, i;
- s8 bank, bit, width;
- s16 reg;
- u32 val, mask;
-
- g = &pmx->soc->groups[group];
-
- for (i = 0; i < num_configs; i++) {
- param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
- arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
-
- ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
- &width);
- if (ret < 0)
- return ret;
-
- val = pmx_readl(pmx, bank, reg);
-
- /* LOCK can't be cleared */
- if (param == TEGRA_PINCONF_PARAM_LOCK) {
- if ((val & BIT(bit)) && !arg) {
- dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
- return -EINVAL;
- }
- }
-
- /* Special-case Boolean values; allow any non-zero as true */
- if (width == 1)
- arg = !!arg;
-
- /* Range-check user-supplied value */
- mask = (1 << width) - 1;
- if (arg & ~mask) {
- dev_err(pctldev->dev,
- "config %lx: %x too big for %d bit register\n",
- configs[i], arg, width);
- return -EINVAL;
- }
-
- /* Update register */
- val &= ~(mask << bit);
- val |= arg << bit;
- pmx_writel(pmx, val, bank, reg);
- } /* for each config */
-
- return 0;
-}
-
-#ifdef CONFIG_DEBUG_FS
-static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned offset)
-{
-}
-
-static const char *strip_prefix(const char *s)
-{
- const char *comma = strchr(s, ',');
- if (!comma)
- return s;
-
- return comma + 1;
-}
-
-static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned group)
-{
- struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
- const struct tegra_pingroup *g;
- int i, ret;
- s8 bank, bit, width;
- s16 reg;
- u32 val;
-
- g = &pmx->soc->groups[group];
-
- for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
- ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
- &bank, ®, &bit, &width);
- if (ret < 0)
- continue;
-
- val = pmx_readl(pmx, bank, reg);
- val >>= bit;
- val &= (1 << width) - 1;
-
- seq_printf(s, "\n\t%s=%u",
- strip_prefix(cfg_params[i].property), val);
- }
-}
-
-static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s,
- unsigned long config)
-{
- enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
- u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
- const char *pname = "unknown";
- int i;
-
- for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
- if (cfg_params[i].param == param) {
- pname = cfg_params[i].property;
- break;
- }
- }
-
- seq_printf(s, "%s=%d", strip_prefix(pname), arg);
-}
-#endif
-
-static const struct pinconf_ops tegra_pinconf_ops = {
- .pin_config_get = tegra_pinconf_get,
- .pin_config_set = tegra_pinconf_set,
- .pin_config_group_get = tegra_pinconf_group_get,
- .pin_config_group_set = tegra_pinconf_group_set,
-#ifdef CONFIG_DEBUG_FS
- .pin_config_dbg_show = tegra_pinconf_dbg_show,
- .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
- .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
-#endif
-};
-
-static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
- .name = "Tegra GPIOs",
- .id = 0,
- .base = 0,
-};
-
-static struct pinctrl_desc tegra_pinctrl_desc = {
- .pctlops = &tegra_pinctrl_ops,
- .pmxops = &tegra_pinmux_ops,
- .confops = &tegra_pinconf_ops,
- .owner = THIS_MODULE,
-};
-
-static bool gpio_node_has_range(void)
-{
- struct device_node *np;
- bool has_prop = false;
-
- np = of_find_compatible_node(NULL, NULL, "nvidia,tegra30-gpio");
- if (!np)
- return has_prop;
-
- has_prop = of_find_property(np, "gpio-ranges", NULL);
-
- of_node_put(np);
-
- return has_prop;
-}
-
-int tegra_pinctrl_probe(struct platform_device *pdev,
- const struct tegra_pinctrl_soc_data *soc_data)
-{
- struct tegra_pmx *pmx;
- struct resource *res;
- int i;
- const char **group_pins;
- int fn, gn, gfn;
-
- pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
- if (!pmx) {
- dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
- return -ENOMEM;
- }
- pmx->dev = &pdev->dev;
- pmx->soc = soc_data;
-
- /*
- * Each mux group will appear in 4 functions' list of groups.
- * This over-allocates slightly, since not all groups are mux groups.
- */
- pmx->group_pins = devm_kzalloc(&pdev->dev,
- soc_data->ngroups * 4 * sizeof(*pmx->group_pins),
- GFP_KERNEL);
- if (!pmx->group_pins)
- return -ENOMEM;
-
- group_pins = pmx->group_pins;
- for (fn = 0; fn < soc_data->nfunctions; fn++) {
- struct tegra_function *func = &soc_data->functions[fn];
-
- func->groups = group_pins;
-
- for (gn = 0; gn < soc_data->ngroups; gn++) {
- const struct tegra_pingroup *g = &soc_data->groups[gn];
-
- if (g->mux_reg == -1)
- continue;
-
- for (gfn = 0; gfn < 4; gfn++)
- if (g->funcs[gfn] == fn)
- break;
- if (gfn == 4)
- continue;
-
- BUG_ON(group_pins - pmx->group_pins >=
- soc_data->ngroups * 4);
- *group_pins++ = g->name;
- func->ngroups++;
- }
- }
-
- tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
- tegra_pinctrl_desc.name = dev_name(&pdev->dev);
- tegra_pinctrl_desc.pins = pmx->soc->pins;
- tegra_pinctrl_desc.npins = pmx->soc->npins;
-
- for (i = 0; ; i++) {
- res = platform_get_resource(pdev, IORESOURCE_MEM, i);
- if (!res)
- break;
- }
- pmx->nbanks = i;
-
- pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
- GFP_KERNEL);
- if (!pmx->regs) {
- dev_err(&pdev->dev, "Can't alloc regs pointer\n");
- return -ENOMEM;
- }
-
- for (i = 0; i < pmx->nbanks; i++) {
- res = platform_get_resource(pdev, IORESOURCE_MEM, i);
- pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(pmx->regs[i]))
- return PTR_ERR(pmx->regs[i]);
- }
-
- pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
- if (IS_ERR(pmx->pctl)) {
- dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
- return PTR_ERR(pmx->pctl);
- }
-
- if (!gpio_node_has_range())
- pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
-
- platform_set_drvdata(pdev, pmx);
-
- dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
-
-int tegra_pinctrl_remove(struct platform_device *pdev)
-{
- struct tegra_pmx *pmx = platform_get_drvdata(pdev);
-
- pinctrl_unregister(pmx->pctl);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
+++ /dev/null
-/*
- * Driver for the NVIDIA Tegra pinmux
- *
- * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __PINMUX_TEGRA_H__
-#define __PINMUX_TEGRA_H__
-
-enum tegra_pinconf_param {
- /* argument: tegra_pinconf_pull */
- TEGRA_PINCONF_PARAM_PULL,
- /* argument: tegra_pinconf_tristate */
- TEGRA_PINCONF_PARAM_TRISTATE,
- /* argument: Boolean */
- TEGRA_PINCONF_PARAM_ENABLE_INPUT,
- /* argument: Boolean */
- TEGRA_PINCONF_PARAM_OPEN_DRAIN,
- /* argument: Boolean */
- TEGRA_PINCONF_PARAM_LOCK,
- /* argument: Boolean */
- TEGRA_PINCONF_PARAM_IORESET,
- /* argument: Boolean */
- TEGRA_PINCONF_PARAM_RCV_SEL,
- /* argument: Boolean */
- TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
- /* argument: Boolean */
- TEGRA_PINCONF_PARAM_SCHMITT,
- /* argument: Boolean */
- TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
- /* argument: Integer, range is HW-dependant */
- TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
- /* argument: Integer, range is HW-dependant */
- TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
- /* argument: Integer, range is HW-dependant */
- TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
- /* argument: Integer, range is HW-dependant */
- TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
- /* argument: Integer, range is HW-dependant */
- TEGRA_PINCONF_PARAM_DRIVE_TYPE,
-};
-
-enum tegra_pinconf_pull {
- TEGRA_PINCONFIG_PULL_NONE,
- TEGRA_PINCONFIG_PULL_DOWN,
- TEGRA_PINCONFIG_PULL_UP,
-};
-
-enum tegra_pinconf_tristate {
- TEGRA_PINCONFIG_DRIVEN,
- TEGRA_PINCONFIG_TRISTATE,
-};
-
-#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
-#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
-#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
-
-/**
- * struct tegra_function - Tegra pinctrl mux function
- * @name: The name of the function, exported to pinctrl core.
- * @groups: An array of pin groups that may select this function.
- * @ngroups: The number of entries in @groups.
- */
-struct tegra_function {
- const char *name;
- const char **groups;
- unsigned ngroups;
-};
-
-/**
- * struct tegra_pingroup - Tegra pin group
- * @name The name of the pin group.
- * @pins An array of pin IDs included in this pin group.
- * @npins The number of entries in @pins.
- * @funcs The mux functions which can be muxed onto this group.
- * @mux_reg: Mux register offset.
- * This register contains the mux, einput, odrain, lock,
- * ioreset, rcv_sel parameters.
- * @mux_bank: Mux register bank.
- * @mux_bit: Mux register bit.
- * @pupd_reg: Pull-up/down register offset.
- * @pupd_bank: Pull-up/down register bank.
- * @pupd_bit: Pull-up/down register bit.
- * @tri_reg: Tri-state register offset.
- * @tri_bank: Tri-state register bank.
- * @tri_bit: Tri-state register bit.
- * @einput_bit: Enable-input register bit.
- * @odrain_bit: Open-drain register bit.
- * @lock_bit: Lock register bit.
- * @ioreset_bit: IO reset register bit.
- * @rcv_sel_bit: Receiver select bit.
- * @drv_reg: Drive fields register offset.
- * This register contains hsm, schmitt, lpmd, drvdn,
- * drvup, slwr, slwf, and drvtype parameters.
- * @drv_bank: Drive fields register bank.
- * @hsm_bit: High Speed Mode register bit.
- * @schmitt_bit: Scmitt register bit.
- * @lpmd_bit: Low Power Mode register bit.
- * @drvdn_bit: Drive Down register bit.
- * @drvdn_width: Drive Down field width.
- * @drvup_bit: Drive Up register bit.
- * @drvup_width: Drive Up field width.
- * @slwr_bit: Slew Rising register bit.
- * @slwr_width: Slew Rising field width.
- * @slwf_bit: Slew Falling register bit.
- * @slwf_width: Slew Falling field width.
- * @drvtype_bit: Drive type register bit.
- *
- * -1 in a *_reg field means that feature is unsupported for this group.
- * *_bank and *_reg values are irrelevant when *_reg is -1.
- * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
- *
- * A representation of a group of pins (possibly just one pin) in the Tegra
- * pin controller. Each group allows some parameter or parameters to be
- * configured. The most common is mux function selection. Many others exist
- * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
- * certain groups may only support configuring certain parameters, hence
- * each parameter is optional.
- */
-struct tegra_pingroup {
- const char *name;
- const unsigned *pins;
- u8 npins;
- u8 funcs[4];
- s16 mux_reg;
- s16 pupd_reg;
- s16 tri_reg;
- s16 drv_reg;
- u32 mux_bank:2;
- u32 pupd_bank:2;
- u32 tri_bank:2;
- u32 drv_bank:2;
- s32 mux_bit:6;
- s32 pupd_bit:6;
- s32 tri_bit:6;
- s32 einput_bit:6;
- s32 odrain_bit:6;
- s32 lock_bit:6;
- s32 ioreset_bit:6;
- s32 rcv_sel_bit:6;
- s32 hsm_bit:6;
- s32 schmitt_bit:6;
- s32 lpmd_bit:6;
- s32 drvdn_bit:6;
- s32 drvup_bit:6;
- s32 slwr_bit:6;
- s32 slwf_bit:6;
- s32 drvtype_bit:6;
- s32 drvdn_width:6;
- s32 drvup_width:6;
- s32 slwr_width:6;
- s32 slwf_width:6;
-};
-
-/**
- * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
- * @ngpios: The number of GPIO pins the pin controller HW affects.
- * @pins: An array describing all pins the pin controller affects.
- * All pins which are also GPIOs must be listed first within the
- * array, and be numbered identically to the GPIO controller's
- * numbering.
- * @npins: The numbmer of entries in @pins.
- * @functions: An array describing all mux functions the SoC supports.
- * @nfunctions: The numbmer of entries in @functions.
- * @groups: An array describing all pin groups the pin SoC supports.
- * @ngroups: The numbmer of entries in @groups.
- */
-struct tegra_pinctrl_soc_data {
- unsigned ngpios;
- const struct pinctrl_pin_desc *pins;
- unsigned npins;
- struct tegra_function *functions;
- unsigned nfunctions;
- const struct tegra_pingroup *groups;
- unsigned ngroups;
- bool hsm_in_mux;
- bool schmitt_in_mux;
- bool drvtype_in_mux;
-};
-
-int tegra_pinctrl_probe(struct platform_device *pdev,
- const struct tegra_pinctrl_soc_data *soc_data);
-int tegra_pinctrl_remove(struct platform_device *pdev);
-
-#endif
+++ /dev/null
-/*
- * Pinctrl data for the NVIDIA Tegra114 pinmux
- *
- * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-
-#include "pinctrl-tegra.h"
-
-/*
- * Most pins affected by the pinmux can also be GPIOs. Define these first.
- * These must match how the GPIO driver names/numbers its pins.
- */
-#define _GPIO(offset) (offset)
-
-#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
-#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
-#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
-#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
-#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
-#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
-#define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
-#define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
-#define TEGRA_PIN_GMI_A17_PB0 _GPIO(8)
-#define TEGRA_PIN_GMI_A18_PB1 _GPIO(9)
-#define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
-#define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
-#define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
-#define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
-#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
-#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
-#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
-#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
-#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
-#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
-#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
-#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
-#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
-#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
-#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
-#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
-#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
-#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
-#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
-#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
-#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
-#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
-#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
-#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
-#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
-#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
-#define TEGRA_PIN_GMI_WR_N_PI0 _GPIO(64)
-#define TEGRA_PIN_GMI_OE_N_PI1 _GPIO(65)
-#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
-#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
-#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
-#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
-#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
-#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
-#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
-#define TEGRA_PIN_GMI_DQS_P_PJ3 _GPIO(75)
-#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
-#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
-#define TEGRA_PIN_GMI_A16_PJ7 _GPIO(79)
-#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
-#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
-#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
-#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
-#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
-#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
-#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
-#define TEGRA_PIN_GMI_A19_PK7 _GPIO(87)
-#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
-#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
-#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
-#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
-#define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108)
-#define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109)
-#define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
-#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
-#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
-#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
-#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
-#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
-#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
-#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
-#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
-#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
-#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
-#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
-#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
-#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
-#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
-#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
-#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
-#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
-#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
-#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
-#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
-#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
-#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
-#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
-#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
-#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
-#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
-#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
-#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
-#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
-#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
-#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
-#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
-#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
-#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
-#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
-#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
-#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
-#define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
-#define TEGRA_PIN_PU0 _GPIO(160)
-#define TEGRA_PIN_PU1 _GPIO(161)
-#define TEGRA_PIN_PU2 _GPIO(162)
-#define TEGRA_PIN_PU3 _GPIO(163)
-#define TEGRA_PIN_PU4 _GPIO(164)
-#define TEGRA_PIN_PU5 _GPIO(165)
-#define TEGRA_PIN_PU6 _GPIO(166)
-#define TEGRA_PIN_PV0 _GPIO(168)
-#define TEGRA_PIN_PV1 _GPIO(169)
-#define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170)
-#define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171)
-#define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
-#define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
-#define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178)
-#define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179)
-#define TEGRA_PIN_CLK1_OUT_PW4 _GPIO(180)
-#define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
-#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
-#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
-#define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184)
-#define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185)
-#define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186)
-#define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187)
-#define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188)
-#define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189)
-#define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190)
-#define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191)
-#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
-#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
-#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
-#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
-#define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
-#define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
-#define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
-#define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
-#define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
-#define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
-#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
-#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
-#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
-#define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
-#define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
-#define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
-#define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
-#define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
-#define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
-#define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
-#define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
-#define TEGRA_PIN_PBB0 _GPIO(216)
-#define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
-#define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
-#define TEGRA_PIN_PBB3 _GPIO(219)
-#define TEGRA_PIN_PBB4 _GPIO(220)
-#define TEGRA_PIN_PBB5 _GPIO(221)
-#define TEGRA_PIN_PBB6 _GPIO(222)
-#define TEGRA_PIN_PBB7 _GPIO(223)
-#define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
-#define TEGRA_PIN_PCC1 _GPIO(225)
-#define TEGRA_PIN_PCC2 _GPIO(226)
-#define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
-#define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
-#define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
-#define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
-#define TEGRA_PIN_CLK1_REQ_PEE2 _GPIO(242)
-#define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
-#define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244)
-#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
-
-/* All non-GPIO pins follow */
-#define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
-#define _PIN(offset) (NUM_GPIOS + (offset))
-
-/* Non-GPIO pins */
-#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
-#define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
-#define TEGRA_PIN_PWR_INT_N _PIN(2)
-#define TEGRA_PIN_RESET_OUT_N _PIN(3)
-#define TEGRA_PIN_OWR _PIN(4)
-#define TEGRA_PIN_JTAG_RTCK _PIN(5)
-#define TEGRA_PIN_CLK_32K_IN _PIN(6)
-#define TEGRA_PIN_GMI_CLK_LB _PIN(7)
-
-static const struct pinctrl_pin_desc tegra114_pins[] = {
- PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
- PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
- PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
- PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
- PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
- PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
- PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
- PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
- PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
- PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
- PINCTRL_PIN(TEGRA_PIN_GMI_DQS_P_PJ3, "GMI_DQS_P PJ3"),
- PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
- PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
- PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
- PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
- PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
- PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
- PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
- PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
- PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
- PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
- PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
- PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
- PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
- PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
- PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
- PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
- PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
- PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
- PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
- PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
- PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
- PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
- PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
- PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
- PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
- PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
- PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
- PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
- PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
- PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
- PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
- PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
- PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
- PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
- PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
- PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
- PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
- PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
- PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
- PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
- PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
- PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
- PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
- PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
- PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
- PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
- PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
- PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
- PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
- PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
- PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
-};
-
-static const unsigned clk_32k_out_pa0_pins[] = {
- TEGRA_PIN_CLK_32K_OUT_PA0,
-};
-
-static const unsigned uart3_cts_n_pa1_pins[] = {
- TEGRA_PIN_UART3_CTS_N_PA1,
-};
-
-static const unsigned dap2_fs_pa2_pins[] = {
- TEGRA_PIN_DAP2_FS_PA2,
-};
-
-static const unsigned dap2_sclk_pa3_pins[] = {
- TEGRA_PIN_DAP2_SCLK_PA3,
-};
-
-static const unsigned dap2_din_pa4_pins[] = {
- TEGRA_PIN_DAP2_DIN_PA4,
-};
-
-static const unsigned dap2_dout_pa5_pins[] = {
- TEGRA_PIN_DAP2_DOUT_PA5,
-};
-
-static const unsigned sdmmc3_clk_pa6_pins[] = {
- TEGRA_PIN_SDMMC3_CLK_PA6,
-};
-
-static const unsigned sdmmc3_cmd_pa7_pins[] = {
- TEGRA_PIN_SDMMC3_CMD_PA7,
-};
-
-static const unsigned gmi_a17_pb0_pins[] = {
- TEGRA_PIN_GMI_A17_PB0,
-};
-
-static const unsigned gmi_a18_pb1_pins[] = {
- TEGRA_PIN_GMI_A18_PB1,
-};
-
-static const unsigned sdmmc3_dat3_pb4_pins[] = {
- TEGRA_PIN_SDMMC3_DAT3_PB4,
-};
-
-static const unsigned sdmmc3_dat2_pb5_pins[] = {
- TEGRA_PIN_SDMMC3_DAT2_PB5,
-};
-
-static const unsigned sdmmc3_dat1_pb6_pins[] = {
- TEGRA_PIN_SDMMC3_DAT1_PB6,
-};
-
-static const unsigned sdmmc3_dat0_pb7_pins[] = {
- TEGRA_PIN_SDMMC3_DAT0_PB7,
-};
-
-static const unsigned uart3_rts_n_pc0_pins[] = {
- TEGRA_PIN_UART3_RTS_N_PC0,
-};
-
-static const unsigned uart2_txd_pc2_pins[] = {
- TEGRA_PIN_UART2_TXD_PC2,
-};
-
-static const unsigned uart2_rxd_pc3_pins[] = {
- TEGRA_PIN_UART2_RXD_PC3,
-};
-
-static const unsigned gen1_i2c_scl_pc4_pins[] = {
- TEGRA_PIN_GEN1_I2C_SCL_PC4,
-};
-
-static const unsigned gen1_i2c_sda_pc5_pins[] = {
- TEGRA_PIN_GEN1_I2C_SDA_PC5,
-};
-
-static const unsigned gmi_wp_n_pc7_pins[] = {
- TEGRA_PIN_GMI_WP_N_PC7,
-};
-
-static const unsigned gmi_ad0_pg0_pins[] = {
- TEGRA_PIN_GMI_AD0_PG0,
-};
-
-static const unsigned gmi_ad1_pg1_pins[] = {
- TEGRA_PIN_GMI_AD1_PG1,
-};
-
-static const unsigned gmi_ad2_pg2_pins[] = {
- TEGRA_PIN_GMI_AD2_PG2,
-};
-
-static const unsigned gmi_ad3_pg3_pins[] = {
- TEGRA_PIN_GMI_AD3_PG3,
-};
-
-static const unsigned gmi_ad4_pg4_pins[] = {
- TEGRA_PIN_GMI_AD4_PG4,
-};
-
-static const unsigned gmi_ad5_pg5_pins[] = {
- TEGRA_PIN_GMI_AD5_PG5,
-};
-
-static const unsigned gmi_ad6_pg6_pins[] = {
- TEGRA_PIN_GMI_AD6_PG6,
-};
-
-static const unsigned gmi_ad7_pg7_pins[] = {
- TEGRA_PIN_GMI_AD7_PG7,
-};
-
-static const unsigned gmi_ad8_ph0_pins[] = {
- TEGRA_PIN_GMI_AD8_PH0,
-};
-
-static const unsigned gmi_ad9_ph1_pins[] = {
- TEGRA_PIN_GMI_AD9_PH1,
-};
-
-static const unsigned gmi_ad10_ph2_pins[] = {
- TEGRA_PIN_GMI_AD10_PH2,
-};
-
-static const unsigned gmi_ad11_ph3_pins[] = {
- TEGRA_PIN_GMI_AD11_PH3,
-};
-
-static const unsigned gmi_ad12_ph4_pins[] = {
- TEGRA_PIN_GMI_AD12_PH4,
-};
-
-static const unsigned gmi_ad13_ph5_pins[] = {
- TEGRA_PIN_GMI_AD13_PH5,
-};
-
-static const unsigned gmi_ad14_ph6_pins[] = {
- TEGRA_PIN_GMI_AD14_PH6,
-};
-
-static const unsigned gmi_ad15_ph7_pins[] = {
- TEGRA_PIN_GMI_AD15_PH7,
-};
-
-static const unsigned gmi_wr_n_pi0_pins[] = {
- TEGRA_PIN_GMI_WR_N_PI0,
-};
-
-static const unsigned gmi_oe_n_pi1_pins[] = {
- TEGRA_PIN_GMI_OE_N_PI1,
-};
-
-static const unsigned gmi_cs6_n_pi3_pins[] = {
- TEGRA_PIN_GMI_CS6_N_PI3,
-};
-
-static const unsigned gmi_rst_n_pi4_pins[] = {
- TEGRA_PIN_GMI_RST_N_PI4,
-};
-
-static const unsigned gmi_iordy_pi5_pins[] = {
- TEGRA_PIN_GMI_IORDY_PI5,
-};
-
-static const unsigned gmi_cs7_n_pi6_pins[] = {
- TEGRA_PIN_GMI_CS7_N_PI6,
-};
-
-static const unsigned gmi_wait_pi7_pins[] = {
- TEGRA_PIN_GMI_WAIT_PI7,
-};
-
-static const unsigned gmi_cs0_n_pj0_pins[] = {
- TEGRA_PIN_GMI_CS0_N_PJ0,
-};
-
-static const unsigned gmi_cs1_n_pj2_pins[] = {
- TEGRA_PIN_GMI_CS1_N_PJ2,
-};
-
-static const unsigned gmi_dqs_p_pj3_pins[] = {
- TEGRA_PIN_GMI_DQS_P_PJ3,
-};
-
-static const unsigned uart2_cts_n_pj5_pins[] = {
- TEGRA_PIN_UART2_CTS_N_PJ5,
-};
-
-static const unsigned uart2_rts_n_pj6_pins[] = {
- TEGRA_PIN_UART2_RTS_N_PJ6,
-};
-
-static const unsigned gmi_a16_pj7_pins[] = {
- TEGRA_PIN_GMI_A16_PJ7,
-};
-
-static const unsigned gmi_adv_n_pk0_pins[] = {
- TEGRA_PIN_GMI_ADV_N_PK0,
-};
-
-static const unsigned gmi_clk_pk1_pins[] = {
- TEGRA_PIN_GMI_CLK_PK1,
-};
-
-static const unsigned gmi_cs4_n_pk2_pins[] = {
- TEGRA_PIN_GMI_CS4_N_PK2,
-};
-
-static const unsigned gmi_cs2_n_pk3_pins[] = {
- TEGRA_PIN_GMI_CS2_N_PK3,
-};
-
-static const unsigned gmi_cs3_n_pk4_pins[] = {
- TEGRA_PIN_GMI_CS3_N_PK4,
-};
-
-static const unsigned spdif_out_pk5_pins[] = {
- TEGRA_PIN_SPDIF_OUT_PK5,
-};
-
-static const unsigned spdif_in_pk6_pins[] = {
- TEGRA_PIN_SPDIF_IN_PK6,
-};
-
-static const unsigned gmi_a19_pk7_pins[] = {
- TEGRA_PIN_GMI_A19_PK7,
-};
-
-static const unsigned dap1_fs_pn0_pins[] = {
- TEGRA_PIN_DAP1_FS_PN0,
-};
-
-static const unsigned dap1_din_pn1_pins[] = {
- TEGRA_PIN_DAP1_DIN_PN1,
-};
-
-static const unsigned dap1_dout_pn2_pins[] = {
- TEGRA_PIN_DAP1_DOUT_PN2,
-};
-
-static const unsigned dap1_sclk_pn3_pins[] = {
- TEGRA_PIN_DAP1_SCLK_PN3,
-};
-
-static const unsigned usb_vbus_en0_pn4_pins[] = {
- TEGRA_PIN_USB_VBUS_EN0_PN4,
-};
-
-static const unsigned usb_vbus_en1_pn5_pins[] = {
- TEGRA_PIN_USB_VBUS_EN1_PN5,
-};
-
-static const unsigned hdmi_int_pn7_pins[] = {
- TEGRA_PIN_HDMI_INT_PN7,
-};
-
-static const unsigned ulpi_data7_po0_pins[] = {
- TEGRA_PIN_ULPI_DATA7_PO0,
-};
-
-static const unsigned ulpi_data0_po1_pins[] = {
- TEGRA_PIN_ULPI_DATA0_PO1,
-};
-
-static const unsigned ulpi_data1_po2_pins[] = {
- TEGRA_PIN_ULPI_DATA1_PO2,
-};
-
-static const unsigned ulpi_data2_po3_pins[] = {
- TEGRA_PIN_ULPI_DATA2_PO3,
-};
-
-static const unsigned ulpi_data3_po4_pins[] = {
- TEGRA_PIN_ULPI_DATA3_PO4,
-};
-
-static const unsigned ulpi_data4_po5_pins[] = {
- TEGRA_PIN_ULPI_DATA4_PO5,
-};
-
-static const unsigned ulpi_data5_po6_pins[] = {
- TEGRA_PIN_ULPI_DATA5_PO6,
-};
-
-static const unsigned ulpi_data6_po7_pins[] = {
- TEGRA_PIN_ULPI_DATA6_PO7,
-};
-
-static const unsigned dap3_fs_pp0_pins[] = {
- TEGRA_PIN_DAP3_FS_PP0,
-};
-
-static const unsigned dap3_din_pp1_pins[] = {
- TEGRA_PIN_DAP3_DIN_PP1,
-};
-
-static const unsigned dap3_dout_pp2_pins[] = {
- TEGRA_PIN_DAP3_DOUT_PP2,
-};
-
-static const unsigned dap3_sclk_pp3_pins[] = {
- TEGRA_PIN_DAP3_SCLK_PP3,
-};
-
-static const unsigned dap4_fs_pp4_pins[] = {
- TEGRA_PIN_DAP4_FS_PP4,
-};
-
-static const unsigned dap4_din_pp5_pins[] = {
- TEGRA_PIN_DAP4_DIN_PP5,
-};
-
-static const unsigned dap4_dout_pp6_pins[] = {
- TEGRA_PIN_DAP4_DOUT_PP6,
-};
-
-static const unsigned dap4_sclk_pp7_pins[] = {
- TEGRA_PIN_DAP4_SCLK_PP7,
-};
-
-static const unsigned kb_col0_pq0_pins[] = {
- TEGRA_PIN_KB_COL0_PQ0,
-};
-
-static const unsigned kb_col1_pq1_pins[] = {
- TEGRA_PIN_KB_COL1_PQ1,
-};
-
-static const unsigned kb_col2_pq2_pins[] = {
- TEGRA_PIN_KB_COL2_PQ2,
-};
-
-static const unsigned kb_col3_pq3_pins[] = {
- TEGRA_PIN_KB_COL3_PQ3,
-};
-
-static const unsigned kb_col4_pq4_pins[] = {
- TEGRA_PIN_KB_COL4_PQ4,
-};
-
-static const unsigned kb_col5_pq5_pins[] = {
- TEGRA_PIN_KB_COL5_PQ5,
-};
-
-static const unsigned kb_col6_pq6_pins[] = {
- TEGRA_PIN_KB_COL6_PQ6,
-};
-
-static const unsigned kb_col7_pq7_pins[] = {
- TEGRA_PIN_KB_COL7_PQ7,
-};
-
-static const unsigned kb_row0_pr0_pins[] = {
- TEGRA_PIN_KB_ROW0_PR0,
-};
-
-static const unsigned kb_row1_pr1_pins[] = {
- TEGRA_PIN_KB_ROW1_PR1,
-};
-
-static const unsigned kb_row2_pr2_pins[] = {
- TEGRA_PIN_KB_ROW2_PR2,
-};
-
-static const unsigned kb_row3_pr3_pins[] = {
- TEGRA_PIN_KB_ROW3_PR3,
-};
-
-static const unsigned kb_row4_pr4_pins[] = {
- TEGRA_PIN_KB_ROW4_PR4,
-};
-
-static const unsigned kb_row5_pr5_pins[] = {
- TEGRA_PIN_KB_ROW5_PR5,
-};
-
-static const unsigned kb_row6_pr6_pins[] = {
- TEGRA_PIN_KB_ROW6_PR6,
-};
-
-static const unsigned kb_row7_pr7_pins[] = {
- TEGRA_PIN_KB_ROW7_PR7,
-};
-
-static const unsigned kb_row8_ps0_pins[] = {
- TEGRA_PIN_KB_ROW8_PS0,
-};
-
-static const unsigned kb_row9_ps1_pins[] = {
- TEGRA_PIN_KB_ROW9_PS1,
-};
-
-static const unsigned kb_row10_ps2_pins[] = {
- TEGRA_PIN_KB_ROW10_PS2,
-};
-
-static const unsigned gen2_i2c_scl_pt5_pins[] = {
- TEGRA_PIN_GEN2_I2C_SCL_PT5,
-};
-
-static const unsigned gen2_i2c_sda_pt6_pins[] = {
- TEGRA_PIN_GEN2_I2C_SDA_PT6,
-};
-
-static const unsigned sdmmc4_cmd_pt7_pins[] = {
- TEGRA_PIN_SDMMC4_CMD_PT7,
-};
-
-static const unsigned pu0_pins[] = {
- TEGRA_PIN_PU0,
-};
-
-static const unsigned pu1_pins[] = {
- TEGRA_PIN_PU1,
-};
-
-static const unsigned pu2_pins[] = {
- TEGRA_PIN_PU2,
-};
-
-static const unsigned pu3_pins[] = {
- TEGRA_PIN_PU3,
-};
-
-static const unsigned pu4_pins[] = {
- TEGRA_PIN_PU4,
-};
-
-static const unsigned pu5_pins[] = {
- TEGRA_PIN_PU5,
-};
-
-static const unsigned pu6_pins[] = {
- TEGRA_PIN_PU6,
-};
-
-static const unsigned pv0_pins[] = {
- TEGRA_PIN_PV0,
-};
-
-static const unsigned pv1_pins[] = {
- TEGRA_PIN_PV1,
-};
-
-static const unsigned sdmmc3_cd_n_pv2_pins[] = {
- TEGRA_PIN_SDMMC3_CD_N_PV2,
-};
-
-static const unsigned sdmmc1_wp_n_pv3_pins[] = {
- TEGRA_PIN_SDMMC1_WP_N_PV3,
-};
-
-static const unsigned ddc_scl_pv4_pins[] = {
- TEGRA_PIN_DDC_SCL_PV4,
-};
-
-static const unsigned ddc_sda_pv5_pins[] = {
- TEGRA_PIN_DDC_SDA_PV5,
-};
-
-static const unsigned gpio_w2_aud_pw2_pins[] = {
- TEGRA_PIN_GPIO_W2_AUD_PW2,
-};
-
-static const unsigned gpio_w3_aud_pw3_pins[] = {
- TEGRA_PIN_GPIO_W3_AUD_PW3,
-};
-
-static const unsigned clk1_out_pw4_pins[] = {
- TEGRA_PIN_CLK1_OUT_PW4,
-};
-
-static const unsigned clk2_out_pw5_pins[] = {
- TEGRA_PIN_CLK2_OUT_PW5,
-};
-
-static const unsigned uart3_txd_pw6_pins[] = {
- TEGRA_PIN_UART3_TXD_PW6,
-};
-
-static const unsigned uart3_rxd_pw7_pins[] = {
- TEGRA_PIN_UART3_RXD_PW7,
-};
-
-static const unsigned dvfs_pwm_px0_pins[] = {
- TEGRA_PIN_DVFS_PWM_PX0,
-};
-
-static const unsigned gpio_x1_aud_px1_pins[] = {
- TEGRA_PIN_GPIO_X1_AUD_PX1,
-};
-
-static const unsigned dvfs_clk_px2_pins[] = {
- TEGRA_PIN_DVFS_CLK_PX2,
-};
-
-static const unsigned gpio_x3_aud_px3_pins[] = {
- TEGRA_PIN_GPIO_X3_AUD_PX3,
-};
-
-static const unsigned gpio_x4_aud_px4_pins[] = {
- TEGRA_PIN_GPIO_X4_AUD_PX4,
-};
-
-static const unsigned gpio_x5_aud_px5_pins[] = {
- TEGRA_PIN_GPIO_X5_AUD_PX5,
-};
-
-static const unsigned gpio_x6_aud_px6_pins[] = {
- TEGRA_PIN_GPIO_X6_AUD_PX6,
-};
-
-static const unsigned gpio_x7_aud_px7_pins[] = {
- TEGRA_PIN_GPIO_X7_AUD_PX7,
-};
-
-static const unsigned ulpi_clk_py0_pins[] = {
- TEGRA_PIN_ULPI_CLK_PY0,
-};
-
-static const unsigned ulpi_dir_py1_pins[] = {
- TEGRA_PIN_ULPI_DIR_PY1,
-};
-
-static const unsigned ulpi_nxt_py2_pins[] = {
- TEGRA_PIN_ULPI_NXT_PY2,
-};
-
-static const unsigned ulpi_stp_py3_pins[] = {
- TEGRA_PIN_ULPI_STP_PY3,
-};
-
-static const unsigned sdmmc1_dat3_py4_pins[] = {
- TEGRA_PIN_SDMMC1_DAT3_PY4,
-};
-
-static const unsigned sdmmc1_dat2_py5_pins[] = {
- TEGRA_PIN_SDMMC1_DAT2_PY5,
-};
-
-static const unsigned sdmmc1_dat1_py6_pins[] = {
- TEGRA_PIN_SDMMC1_DAT1_PY6,
-};
-
-static const unsigned sdmmc1_dat0_py7_pins[] = {
- TEGRA_PIN_SDMMC1_DAT0_PY7,
-};
-
-static const unsigned sdmmc1_clk_pz0_pins[] = {
- TEGRA_PIN_SDMMC1_CLK_PZ0,
-};
-
-static const unsigned sdmmc1_cmd_pz1_pins[] = {
- TEGRA_PIN_SDMMC1_CMD_PZ1,
-};
-
-static const unsigned sys_clk_req_pz5_pins[] = {
- TEGRA_PIN_SYS_CLK_REQ_PZ5,
-};
-
-static const unsigned pwr_i2c_scl_pz6_pins[] = {
- TEGRA_PIN_PWR_I2C_SCL_PZ6,
-};
-
-static const unsigned pwr_i2c_sda_pz7_pins[] = {
- TEGRA_PIN_PWR_I2C_SDA_PZ7,
-};
-
-static const unsigned sdmmc4_dat0_paa0_pins[] = {
- TEGRA_PIN_SDMMC4_DAT0_PAA0,
-};
-
-static const unsigned sdmmc4_dat1_paa1_pins[] = {
- TEGRA_PIN_SDMMC4_DAT1_PAA1,
-};
-
-static const unsigned sdmmc4_dat2_paa2_pins[] = {
- TEGRA_PIN_SDMMC4_DAT2_PAA2,
-};
-
-static const unsigned sdmmc4_dat3_paa3_pins[] = {
- TEGRA_PIN_SDMMC4_DAT3_PAA3,
-};
-
-static const unsigned sdmmc4_dat4_paa4_pins[] = {
- TEGRA_PIN_SDMMC4_DAT4_PAA4,
-};
-
-static const unsigned sdmmc4_dat5_paa5_pins[] = {
- TEGRA_PIN_SDMMC4_DAT5_PAA5,
-};
-
-static const unsigned sdmmc4_dat6_paa6_pins[] = {
- TEGRA_PIN_SDMMC4_DAT6_PAA6,
-};
-
-static const unsigned sdmmc4_dat7_paa7_pins[] = {
- TEGRA_PIN_SDMMC4_DAT7_PAA7,
-};
-
-static const unsigned pbb0_pins[] = {
- TEGRA_PIN_PBB0,
-};
-
-static const unsigned cam_i2c_scl_pbb1_pins[] = {
- TEGRA_PIN_CAM_I2C_SCL_PBB1,
-};
-
-static const unsigned cam_i2c_sda_pbb2_pins[] = {
- TEGRA_PIN_CAM_I2C_SDA_PBB2,
-};
-
-static const unsigned pbb3_pins[] = {
- TEGRA_PIN_PBB3,
-};
-
-static const unsigned pbb4_pins[] = {
- TEGRA_PIN_PBB4,
-};
-
-static const unsigned pbb5_pins[] = {
- TEGRA_PIN_PBB5,
-};
-
-static const unsigned pbb6_pins[] = {
- TEGRA_PIN_PBB6,
-};
-
-static const unsigned pbb7_pins[] = {
- TEGRA_PIN_PBB7,
-};
-
-static const unsigned cam_mclk_pcc0_pins[] = {
- TEGRA_PIN_CAM_MCLK_PCC0,
-};
-
-static const unsigned pcc1_pins[] = {
- TEGRA_PIN_PCC1,
-};
-
-static const unsigned pcc2_pins[] = {
- TEGRA_PIN_PCC2,
-};
-
-static const unsigned sdmmc4_clk_pcc4_pins[] = {
- TEGRA_PIN_SDMMC4_CLK_PCC4,
-};
-
-static const unsigned clk2_req_pcc5_pins[] = {
- TEGRA_PIN_CLK2_REQ_PCC5,
-};
-
-static const unsigned clk3_out_pee0_pins[] = {
- TEGRA_PIN_CLK3_OUT_PEE0,
-};
-
-static const unsigned clk3_req_pee1_pins[] = {
- TEGRA_PIN_CLK3_REQ_PEE1,
-};
-
-static const unsigned clk1_req_pee2_pins[] = {
- TEGRA_PIN_CLK1_REQ_PEE2,
-};
-
-static const unsigned hdmi_cec_pee3_pins[] = {
- TEGRA_PIN_HDMI_CEC_PEE3,
-};
-
-static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
- TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
-};
-
-static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
- TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
-};
-
-static const unsigned core_pwr_req_pins[] = {
- TEGRA_PIN_CORE_PWR_REQ,
-};
-
-static const unsigned cpu_pwr_req_pins[] = {
- TEGRA_PIN_CPU_PWR_REQ,
-};
-
-static const unsigned pwr_int_n_pins[] = {
- TEGRA_PIN_PWR_INT_N,
-};
-
-static const unsigned reset_out_n_pins[] = {
- TEGRA_PIN_RESET_OUT_N,
-};
-
-static const unsigned owr_pins[] = {
- TEGRA_PIN_OWR,
-};
-
-static const unsigned jtag_rtck_pins[] = {
- TEGRA_PIN_JTAG_RTCK,
-};
-
-static const unsigned clk_32k_in_pins[] = {
- TEGRA_PIN_CLK_32K_IN,
-};
-
-static const unsigned gmi_clk_lb_pins[] = {
- TEGRA_PIN_GMI_CLK_LB,
-};
-
-static const unsigned drive_ao1_pins[] = {
- TEGRA_PIN_KB_ROW0_PR0,
- TEGRA_PIN_KB_ROW1_PR1,
- TEGRA_PIN_KB_ROW2_PR2,
- TEGRA_PIN_KB_ROW3_PR3,
- TEGRA_PIN_KB_ROW4_PR4,
- TEGRA_PIN_KB_ROW5_PR5,
- TEGRA_PIN_KB_ROW6_PR6,
- TEGRA_PIN_KB_ROW7_PR7,
- TEGRA_PIN_PWR_I2C_SCL_PZ6,
- TEGRA_PIN_PWR_I2C_SDA_PZ7,
-};
-
-static const unsigned drive_ao2_pins[] = {
- TEGRA_PIN_CLK_32K_OUT_PA0,
- TEGRA_PIN_KB_COL0_PQ0,
- TEGRA_PIN_KB_COL1_PQ1,
- TEGRA_PIN_KB_COL2_PQ2,
- TEGRA_PIN_KB_COL3_PQ3,
- TEGRA_PIN_KB_COL4_PQ4,
- TEGRA_PIN_KB_COL5_PQ5,
- TEGRA_PIN_KB_COL6_PQ6,
- TEGRA_PIN_KB_COL7_PQ7,
- TEGRA_PIN_KB_ROW8_PS0,
- TEGRA_PIN_KB_ROW9_PS1,
- TEGRA_PIN_KB_ROW10_PS2,
- TEGRA_PIN_SYS_CLK_REQ_PZ5,
- TEGRA_PIN_CORE_PWR_REQ,
- TEGRA_PIN_CPU_PWR_REQ,
- TEGRA_PIN_RESET_OUT_N,
-};
-
-static const unsigned drive_at1_pins[] = {
- TEGRA_PIN_GMI_AD8_PH0,
- TEGRA_PIN_GMI_AD9_PH1,
- TEGRA_PIN_GMI_AD10_PH2,
- TEGRA_PIN_GMI_AD11_PH3,
- TEGRA_PIN_GMI_AD12_PH4,
- TEGRA_PIN_GMI_AD13_PH5,
- TEGRA_PIN_GMI_AD14_PH6,
- TEGRA_PIN_GMI_AD15_PH7,
- TEGRA_PIN_GMI_IORDY_PI5,
- TEGRA_PIN_GMI_CS7_N_PI6,
-};
-
-static const unsigned drive_at2_pins[] = {
- TEGRA_PIN_GMI_AD0_PG0,
- TEGRA_PIN_GMI_AD1_PG1,
- TEGRA_PIN_GMI_AD2_PG2,
- TEGRA_PIN_GMI_AD3_PG3,
- TEGRA_PIN_GMI_AD4_PG4,
- TEGRA_PIN_GMI_AD5_PG5,
- TEGRA_PIN_GMI_AD6_PG6,
- TEGRA_PIN_GMI_AD7_PG7,
- TEGRA_PIN_GMI_WR_N_PI0,
- TEGRA_PIN_GMI_OE_N_PI1,
- TEGRA_PIN_GMI_CS6_N_PI3,
- TEGRA_PIN_GMI_RST_N_PI4,
- TEGRA_PIN_GMI_WAIT_PI7,
- TEGRA_PIN_GMI_DQS_P_PJ3,
- TEGRA_PIN_GMI_ADV_N_PK0,
- TEGRA_PIN_GMI_CLK_PK1,
- TEGRA_PIN_GMI_CS4_N_PK2,
- TEGRA_PIN_GMI_CS2_N_PK3,
- TEGRA_PIN_GMI_CS3_N_PK4,
-};
-
-static const unsigned drive_at3_pins[] = {
- TEGRA_PIN_GMI_WP_N_PC7,
- TEGRA_PIN_GMI_CS0_N_PJ0,
-};
-
-static const unsigned drive_at4_pins[] = {
- TEGRA_PIN_GMI_A17_PB0,
- TEGRA_PIN_GMI_A18_PB1,
- TEGRA_PIN_GMI_CS1_N_PJ2,
- TEGRA_PIN_GMI_A16_PJ7,
- TEGRA_PIN_GMI_A19_PK7,
-};
-
-static const unsigned drive_at5_pins[] = {
- TEGRA_PIN_GEN2_I2C_SCL_PT5,
- TEGRA_PIN_GEN2_I2C_SDA_PT6,
-};
-
-static const unsigned drive_cdev1_pins[] = {
- TEGRA_PIN_CLK1_OUT_PW4,
- TEGRA_PIN_CLK1_REQ_PEE2,
-};
-
-static const unsigned drive_cdev2_pins[] = {
- TEGRA_PIN_CLK2_OUT_PW5,
- TEGRA_PIN_CLK2_REQ_PCC5,
- TEGRA_PIN_SDMMC1_WP_N_PV3,
-};
-
-static const unsigned drive_dap1_pins[] = {
- TEGRA_PIN_DAP1_FS_PN0,
- TEGRA_PIN_DAP1_DIN_PN1,
- TEGRA_PIN_DAP1_DOUT_PN2,
- TEGRA_PIN_DAP1_SCLK_PN3,
-};
-
-static const unsigned drive_dap2_pins[] = {
- TEGRA_PIN_DAP2_FS_PA2,
- TEGRA_PIN_DAP2_SCLK_PA3,
- TEGRA_PIN_DAP2_DIN_PA4,
- TEGRA_PIN_DAP2_DOUT_PA5,
-};
-
-static const unsigned drive_dap3_pins[] = {
- TEGRA_PIN_DAP3_FS_PP0,
- TEGRA_PIN_DAP3_DIN_PP1,
- TEGRA_PIN_DAP3_DOUT_PP2,
- TEGRA_PIN_DAP3_SCLK_PP3,
-};
-
-static const unsigned drive_dap4_pins[] = {
- TEGRA_PIN_DAP4_FS_PP4,
- TEGRA_PIN_DAP4_DIN_PP5,
- TEGRA_PIN_DAP4_DOUT_PP6,
- TEGRA_PIN_DAP4_SCLK_PP7,
-};
-
-static const unsigned drive_dbg_pins[] = {
- TEGRA_PIN_GEN1_I2C_SCL_PC4,
- TEGRA_PIN_GEN1_I2C_SDA_PC5,
- TEGRA_PIN_PU0,
- TEGRA_PIN_PU1,
- TEGRA_PIN_PU2,
- TEGRA_PIN_PU3,
- TEGRA_PIN_PU4,
- TEGRA_PIN_PU5,
- TEGRA_PIN_PU6,
-};
-
-static const unsigned drive_sdio3_pins[] = {
- TEGRA_PIN_SDMMC3_CLK_PA6,
- TEGRA_PIN_SDMMC3_CMD_PA7,
- TEGRA_PIN_SDMMC3_DAT3_PB4,
- TEGRA_PIN_SDMMC3_DAT2_PB5,
- TEGRA_PIN_SDMMC3_DAT1_PB6,
- TEGRA_PIN_SDMMC3_DAT0_PB7,
- TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
- TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
-};
-
-static const unsigned drive_spi_pins[] = {
- TEGRA_PIN_DVFS_PWM_PX0,
- TEGRA_PIN_GPIO_X1_AUD_PX1,
- TEGRA_PIN_DVFS_CLK_PX2,
- TEGRA_PIN_GPIO_X3_AUD_PX3,
- TEGRA_PIN_GPIO_X4_AUD_PX4,
- TEGRA_PIN_GPIO_X5_AUD_PX5,
- TEGRA_PIN_GPIO_X6_AUD_PX6,
- TEGRA_PIN_GPIO_X7_AUD_PX7,
- TEGRA_PIN_GPIO_W2_AUD_PW2,
- TEGRA_PIN_GPIO_W3_AUD_PW3,
-};
-
-static const unsigned drive_uaa_pins[] = {
- TEGRA_PIN_ULPI_DATA0_PO1,
- TEGRA_PIN_ULPI_DATA1_PO2,
- TEGRA_PIN_ULPI_DATA2_PO3,
- TEGRA_PIN_ULPI_DATA3_PO4,
-};
-
-static const unsigned drive_uab_pins[] = {
- TEGRA_PIN_ULPI_DATA7_PO0,
- TEGRA_PIN_ULPI_DATA4_PO5,
- TEGRA_PIN_ULPI_DATA5_PO6,
- TEGRA_PIN_ULPI_DATA6_PO7,
- TEGRA_PIN_PV0,
- TEGRA_PIN_PV1,
-};
-
-static const unsigned drive_uart2_pins[] = {
- TEGRA_PIN_UART2_TXD_PC2,
- TEGRA_PIN_UART2_RXD_PC3,
- TEGRA_PIN_UART2_CTS_N_PJ5,
- TEGRA_PIN_UART2_RTS_N_PJ6,
-};
-
-static const unsigned drive_uart3_pins[] = {
- TEGRA_PIN_UART3_CTS_N_PA1,
- TEGRA_PIN_UART3_RTS_N_PC0,
- TEGRA_PIN_UART3_TXD_PW6,
- TEGRA_PIN_UART3_RXD_PW7,
-};
-
-static const unsigned drive_sdio1_pins[] = {
- TEGRA_PIN_SDMMC1_DAT3_PY4,
- TEGRA_PIN_SDMMC1_DAT2_PY5,
- TEGRA_PIN_SDMMC1_DAT1_PY6,
- TEGRA_PIN_SDMMC1_DAT0_PY7,
- TEGRA_PIN_SDMMC1_CLK_PZ0,
- TEGRA_PIN_SDMMC1_CMD_PZ1,
-};
-
-static const unsigned drive_ddc_pins[] = {
- TEGRA_PIN_DDC_SCL_PV4,
- TEGRA_PIN_DDC_SDA_PV5,
-};
-
-static const unsigned drive_gma_pins[] = {
- TEGRA_PIN_SDMMC4_CLK_PCC4,
- TEGRA_PIN_SDMMC4_CMD_PT7,
- TEGRA_PIN_SDMMC4_DAT0_PAA0,
- TEGRA_PIN_SDMMC4_DAT1_PAA1,
- TEGRA_PIN_SDMMC4_DAT2_PAA2,
- TEGRA_PIN_SDMMC4_DAT3_PAA3,
- TEGRA_PIN_SDMMC4_DAT4_PAA4,
- TEGRA_PIN_SDMMC4_DAT5_PAA5,
- TEGRA_PIN_SDMMC4_DAT6_PAA6,
- TEGRA_PIN_SDMMC4_DAT7_PAA7,
-};
-
-static const unsigned drive_gme_pins[] = {
- TEGRA_PIN_PBB0,
- TEGRA_PIN_CAM_I2C_SCL_PBB1,
- TEGRA_PIN_CAM_I2C_SDA_PBB2,
- TEGRA_PIN_PBB3,
- TEGRA_PIN_PCC2,
-};
-
-static const unsigned drive_gmf_pins[] = {
- TEGRA_PIN_PBB4,
- TEGRA_PIN_PBB5,
- TEGRA_PIN_PBB6,
- TEGRA_PIN_PBB7,
-};
-
-static const unsigned drive_gmg_pins[] = {
- TEGRA_PIN_CAM_MCLK_PCC0,
-};
-
-static const unsigned drive_gmh_pins[] = {
- TEGRA_PIN_PCC1,
-};
-
-static const unsigned drive_owr_pins[] = {
- TEGRA_PIN_SDMMC3_CD_N_PV2,
-};
-
-static const unsigned drive_uda_pins[] = {
- TEGRA_PIN_ULPI_CLK_PY0,
- TEGRA_PIN_ULPI_DIR_PY1,
- TEGRA_PIN_ULPI_NXT_PY2,
- TEGRA_PIN_ULPI_STP_PY3,
-};
-
-static const unsigned drive_dev3_pins[] = {
-};
-
-static const unsigned drive_cec_pins[] = {
-};
-
-static const unsigned drive_at6_pins[] = {
-};
-
-static const unsigned drive_dap5_pins[] = {
-};
-
-static const unsigned drive_usb_vbus_en_pins[] = {
-};
-
-static const unsigned drive_ao3_pins[] = {
-};
-
-static const unsigned drive_hv0_pins[] = {
-};
-
-static const unsigned drive_sdio4_pins[] = {
-};
-
-static const unsigned drive_ao0_pins[] = {
-};
-
-enum tegra_mux {
- TEGRA_MUX_BLINK,
- TEGRA_MUX_CEC,
- TEGRA_MUX_CLDVFS,
- TEGRA_MUX_CLK,
- TEGRA_MUX_CLK12,
- TEGRA_MUX_CPU,
- TEGRA_MUX_DAP,
- TEGRA_MUX_DAP1,
- TEGRA_MUX_DAP2,
- TEGRA_MUX_DEV3,
- TEGRA_MUX_DISPLAYA,
- TEGRA_MUX_DISPLAYA_ALT,
- TEGRA_MUX_DISPLAYB,
- TEGRA_MUX_DTV,
- TEGRA_MUX_EMC_DLL,
- TEGRA_MUX_EXTPERIPH1,
- TEGRA_MUX_EXTPERIPH2,
- TEGRA_MUX_EXTPERIPH3,
- TEGRA_MUX_GMI,
- TEGRA_MUX_GMI_ALT,
- TEGRA_MUX_HDA,
- TEGRA_MUX_HSI,
- TEGRA_MUX_I2C1,
- TEGRA_MUX_I2C2,
- TEGRA_MUX_I2C3,
- TEGRA_MUX_I2C4,
- TEGRA_MUX_I2CPWR,
- TEGRA_MUX_I2S0,
- TEGRA_MUX_I2S1,
- TEGRA_MUX_I2S2,
- TEGRA_MUX_I2S3,
- TEGRA_MUX_I2S4,
- TEGRA_MUX_IRDA,
- TEGRA_MUX_KBC,
- TEGRA_MUX_NAND,
- TEGRA_MUX_NAND_ALT,
- TEGRA_MUX_OWR,
- TEGRA_MUX_PMI,
- TEGRA_MUX_PWM0,
- TEGRA_MUX_PWM1,
- TEGRA_MUX_PWM2,
- TEGRA_MUX_PWM3,
- TEGRA_MUX_PWRON,
- TEGRA_MUX_RESET_OUT_N,
- TEGRA_MUX_RSVD1,
- TEGRA_MUX_RSVD2,
- TEGRA_MUX_RSVD3,
- TEGRA_MUX_RSVD4,
- TEGRA_MUX_RTCK,
- TEGRA_MUX_SDMMC1,
- TEGRA_MUX_SDMMC2,
- TEGRA_MUX_SDMMC3,
- TEGRA_MUX_SDMMC4,
- TEGRA_MUX_SOC,
- TEGRA_MUX_SPDIF,
- TEGRA_MUX_SPI1,
- TEGRA_MUX_SPI2,
- TEGRA_MUX_SPI3,
- TEGRA_MUX_SPI4,
- TEGRA_MUX_SPI5,
- TEGRA_MUX_SPI6,
- TEGRA_MUX_SYSCLK,
- TEGRA_MUX_TRACE,
- TEGRA_MUX_UARTA,
- TEGRA_MUX_UARTB,
- TEGRA_MUX_UARTC,
- TEGRA_MUX_UARTD,
- TEGRA_MUX_ULPI,
- TEGRA_MUX_USB,
- TEGRA_MUX_VGP1,
- TEGRA_MUX_VGP2,
- TEGRA_MUX_VGP3,
- TEGRA_MUX_VGP4,
- TEGRA_MUX_VGP5,
- TEGRA_MUX_VGP6,
- TEGRA_MUX_VI,
- TEGRA_MUX_VI_ALT1,
- TEGRA_MUX_VI_ALT3,
-};
-
-#define FUNCTION(fname) \
- { \
- .name = #fname, \
- }
-
-static struct tegra_function tegra114_functions[] = {
- FUNCTION(blink),
- FUNCTION(cec),
- FUNCTION(cldvfs),
- FUNCTION(clk),
- FUNCTION(clk12),
- FUNCTION(cpu),
- FUNCTION(dap),
- FUNCTION(dap1),
- FUNCTION(dap2),
- FUNCTION(dev3),
- FUNCTION(displaya),
- FUNCTION(displaya_alt),
- FUNCTION(displayb),
- FUNCTION(dtv),
- FUNCTION(emc_dll),
- FUNCTION(extperiph1),
- FUNCTION(extperiph2),
- FUNCTION(extperiph3),
- FUNCTION(gmi),
- FUNCTION(gmi_alt),
- FUNCTION(hda),
- FUNCTION(hsi),
- FUNCTION(i2c1),
- FUNCTION(i2c2),
- FUNCTION(i2c3),
- FUNCTION(i2c4),
- FUNCTION(i2cpwr),
- FUNCTION(i2s0),
- FUNCTION(i2s1),
- FUNCTION(i2s2),
- FUNCTION(i2s3),
- FUNCTION(i2s4),
- FUNCTION(irda),
- FUNCTION(kbc),
- FUNCTION(nand),
- FUNCTION(nand_alt),
- FUNCTION(owr),
- FUNCTION(pmi),
- FUNCTION(pwm0),
- FUNCTION(pwm1),
- FUNCTION(pwm2),
- FUNCTION(pwm3),
- FUNCTION(pwron),
- FUNCTION(reset_out_n),
- FUNCTION(rsvd1),
- FUNCTION(rsvd2),
- FUNCTION(rsvd3),
- FUNCTION(rsvd4),
- FUNCTION(rtck),
- FUNCTION(sdmmc1),
- FUNCTION(sdmmc2),
- FUNCTION(sdmmc3),
- FUNCTION(sdmmc4),
- FUNCTION(soc),
- FUNCTION(spdif),
- FUNCTION(spi1),
- FUNCTION(spi2),
- FUNCTION(spi3),
- FUNCTION(spi4),
- FUNCTION(spi5),
- FUNCTION(spi6),
- FUNCTION(sysclk),
- FUNCTION(trace),
- FUNCTION(uarta),
- FUNCTION(uartb),
- FUNCTION(uartc),
- FUNCTION(uartd),
- FUNCTION(ulpi),
- FUNCTION(usb),
- FUNCTION(vgp1),
- FUNCTION(vgp2),
- FUNCTION(vgp3),
- FUNCTION(vgp4),
- FUNCTION(vgp5),
- FUNCTION(vgp6),
- FUNCTION(vi),
- FUNCTION(vi_alt1),
- FUNCTION(vi_alt3),
-};
-
-#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
-#define PINGROUP_REG_A 0x3000 /* bank 1 */
-
-#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
-#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
-
-#define PINGROUP_BIT_Y(b) (b)
-#define PINGROUP_BIT_N(b) (-1)
-
-#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \
- { \
- .name = #pg_name, \
- .pins = pg_name##_pins, \
- .npins = ARRAY_SIZE(pg_name##_pins), \
- .funcs = { \
- TEGRA_MUX_##f0, \
- TEGRA_MUX_##f1, \
- TEGRA_MUX_##f2, \
- TEGRA_MUX_##f3, \
- }, \
- .mux_reg = PINGROUP_REG(r), \
- .mux_bank = 1, \
- .mux_bit = 0, \
- .pupd_reg = PINGROUP_REG(r), \
- .pupd_bank = 1, \
- .pupd_bit = 2, \
- .tri_reg = PINGROUP_REG(r), \
- .tri_bank = 1, \
- .tri_bit = 4, \
- .einput_bit = 5, \
- .odrain_bit = PINGROUP_BIT_##od(6), \
- .lock_bit = 7, \
- .ioreset_bit = PINGROUP_BIT_##ior(8), \
- .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
- .drv_reg = -1, \
- }
-
-#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
- drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
- slwf_b, slwf_w, drvtype) \
- { \
- .name = "drive_" #pg_name, \
- .pins = drive_##pg_name##_pins, \
- .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
- .mux_reg = -1, \
- .pupd_reg = -1, \
- .tri_reg = -1, \
- .einput_bit = -1, \
- .odrain_bit = -1, \
- .lock_bit = -1, \
- .ioreset_bit = -1, \
- .rcv_sel_bit = -1, \
- .drv_reg = DRV_PINGROUP_REG(r), \
- .drv_bank = 0, \
- .hsm_bit = hsm_b, \
- .schmitt_bit = schmitt_b, \
- .lpmd_bit = lpmd_b, \
- .drvdn_bit = drvdn_b, \
- .drvdn_width = drvdn_w, \
- .drvup_bit = drvup_b, \
- .drvup_width = drvup_w, \
- .slwr_bit = slwr_b, \
- .slwr_width = slwr_w, \
- .slwf_bit = slwf_b, \
- .slwf_width = slwf_w, \
- .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
- }
-
-static const struct tegra_pingroup tegra114_groups[] = {
- /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
- PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
- PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N),
- PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N),
- PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N),
- PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N),
- PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N),
- PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N),
- PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N),
- PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N),
- PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N),
- PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N),
- PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N),
- PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N),
- PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N),
- PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3038, N, N, N),
- PINGROUP(dap3_sclk_pp3, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x303c, N, N, N),
- PINGROUP(pv0, USB, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N),
- PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N),
- PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N),
- PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N),
- PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N),
- PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N),
- PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N),
- PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N),
- PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N),
- PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N),
- PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y),
- PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y),
- PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y),
- PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N),
- PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N),
- PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, RSVD3, SPI4, 0x316c, N, N, N),
- PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, RSVD3, SPI4, 0x3170, N, N, N),
- PINGROUP(uart3_txd_pw6, UARTC, RSVD2, RSVD3, SPI4, 0x3174, N, N, N),
- PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, RSVD3, SPI4, 0x3178, N, N, N),
- PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, SPI4, 0x317c, N, N, N),
- PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, DISPLAYA, 0x3180, N, N, N),
- PINGROUP(pu0, OWR, UARTA, RSVD3, RSVD4, 0x3184, N, N, N),
- PINGROUP(pu1, RSVD1, UARTA, RSVD3, RSVD4, 0x3188, N, N, N),
- PINGROUP(pu2, RSVD1, UARTA, RSVD3, RSVD4, 0x318c, N, N, N),
- PINGROUP(pu3, PWM0, UARTA, DISPLAYA, DISPLAYB, 0x3190, N, N, N),
- PINGROUP(pu4, PWM1, UARTA, DISPLAYA, DISPLAYB, 0x3194, N, N, N),
- PINGROUP(pu5, PWM2, UARTA, DISPLAYA, DISPLAYB, 0x3198, N, N, N),
- PINGROUP(pu6, PWM3, UARTA, USB, DISPLAYB, 0x319c, N, N, N),
- PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N),
- PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N),
- PINGROUP(dap4_fs_pp4, I2S3, RSVD2, DTV, RSVD4, 0x31a8, N, N, N),
- PINGROUP(dap4_din_pp5, I2S3, RSVD2, RSVD3, RSVD4, 0x31ac, N, N, N),
- PINGROUP(dap4_dout_pp6, I2S3, RSVD2, DTV, RSVD4, 0x31b0, N, N, N),
- PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, RSVD3, RSVD4, 0x31b4, N, N, N),
- PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N),
- PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N),
- PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N, N),
- PINGROUP(gmi_iordy_pi5, SDMMC2, RSVD2, GMI, TRACE, 0x31c4, N, N, N),
- PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, 0x31c8, N, N, N),
- PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, 0x31cc, N, N, N),
- PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, 0x31d0, N, N, N),
- PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, 0x31d4, N, N, N),
- PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, 0x31d8, N, N, N),
- PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, 0x31dc, N, N, N),
- PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, 0x31e0, N, N, N),
- PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, 0x31e4, N, N, N),
- PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, 0x31e8, N, N, N),
- PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, SDMMC2, 0x31ec, N, N, N),
- PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, N, N),
- PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, N, N),
- PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, N, N),
- PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, N, N),
- PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, N, N),
- PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, SPI4, 0x3204, N, N, N),
- PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, SPI4, 0x3208, N, N, N),
- PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, SPI4, 0x320c, N, N, N),
- PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, DTV, 0x3210, N, N, N),
- PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, CLDVFS, 0x3214, N, N, N),
- PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, CLDVFS, 0x3218, N, N, N),
- PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, USB, 0x321c, N, N, N),
- PINGROUP(gmi_ad12_ph4, SDMMC2, NAND, GMI, RSVD4, 0x3220, N, N, N),
- PINGROUP(gmi_ad13_ph5, SDMMC2, NAND, GMI, RSVD4, 0x3224, N, N, N),
- PINGROUP(gmi_ad14_ph6, SDMMC2, NAND, GMI, DTV, 0x3228, N, N, N),
- PINGROUP(gmi_ad15_ph7, SDMMC2, NAND, GMI, DTV, 0x322c, N, N, N),
- PINGROUP(gmi_a16_pj7, UARTD, TRACE, GMI, GMI_ALT, 0x3230, N, N, N),
- PINGROUP(gmi_a17_pb0, UARTD, RSVD2, GMI, TRACE, 0x3234, N, N, N),
- PINGROUP(gmi_a18_pb1, UARTD, RSVD2, GMI, TRACE, 0x3238, N, N, N),
- PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, TRACE, 0x323c, N, N, N),
- PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, SPI4, 0x3240, N, N, N),
- PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, SOC, 0x3244, N, N, N),
- PINGROUP(gmi_dqs_p_pj3, SDMMC2, NAND, GMI, TRACE, 0x3248, N, N, N),
- PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, 0x324c, N, N, N),
- PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N),
- PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N),
- PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N),
- PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N),
- PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N),
- PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N),
- PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N),
- PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N),
- PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N),
- PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, GMI, RSVD4, 0x3274, N, Y, N),
- PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N),
- PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N),
- PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, RSVD4, 0x3284, N, N, N),
- PINGROUP(pcc1, I2S4, RSVD2, RSVD3, RSVD4, 0x3288, N, N, N),
- PINGROUP(pbb0, I2S4, VI, VI_ALT1, VI_ALT3, 0x328c, N, N, N),
- PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, RSVD4, 0x3290, Y, N, N),
- PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, RSVD4, 0x3294, Y, N, N),
- PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, RSVD4, 0x3298, N, N, N),
- PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, RSVD4, 0x329c, N, N, N),
- PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, RSVD4, 0x32a0, N, N, N),
- PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, RSVD4, 0x32a4, N, N, N),
- PINGROUP(pbb7, I2S4, RSVD2, RSVD3, RSVD4, 0x32a8, N, N, N),
- PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, 0x32ac, N, N, N),
- PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N),
- PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N),
- PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N),
- PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N),
- PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N),
- PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N),
- PINGROUP(kb_row3_pr3, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32c8, N, N, N),
- PINGROUP(kb_row4_pr4, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32cc, N, N, N),
- PINGROUP(kb_row5_pr5, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32d0, N, N, N),
- PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N),
- PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N),
- PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N),
- PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N),
- PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N),
- PINGROUP(kb_col0_pq0, KBC, USB, SPI2, EMC_DLL, 0x32fc, N, N, N),
- PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, EMC_DLL, 0x3300, N, N, N),
- PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N),
- PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N),
- PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N),
- PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC1, RSVD4, 0x3310, N, N, N),
- PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, RSVD4, 0x3314, N, N, N),
- PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, RSVD4, 0x3318, N, N, N),
- PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N),
- PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N, N),
- PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N),
- PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N),
- PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N),
- PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N),
- PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y),
- PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N),
- PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N),
- PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, RSVD4, 0x3340, N, N, N),
- PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N),
- PINGROUP(clk1_req_pee2, DAP, DAP1, RSVD3, RSVD4, 0x3348, N, N, N),
- PINGROUP(clk1_out_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N),
- PINGROUP(spdif_in_pk6, SPDIF, USB, RSVD3, RSVD4, 0x3350, N, N, N),
- PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, RSVD4, 0x3354, N, N, N),
- PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, RSVD4, 0x3358, N, N, N),
- PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, RSVD4, 0x335c, N, N, N),
- PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, RSVD4, 0x3360, N, N, N),
- PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, RSVD4, 0x3364, N, N, N),
- PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, RSVD3, RSVD4, 0x3368, N, N, N),
- PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, RSVD3, RSVD4, 0x336c, N, N, N),
- PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, RSVD3, RSVD4, 0x3370, N, N, N),
- PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, RSVD3, RSVD4, 0x3374, N, N, N),
- PINGROUP(gpio_x4_aud_px4, RSVD1, SPI1, SPI2, DAP2, 0x3378, N, N, N),
- PINGROUP(gpio_x5_aud_px5, RSVD1, SPI1, SPI2, RSVD4, 0x337c, N, N, N),
- PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, RSVD4, 0x3380, N, N, N),
- PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N),
- PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N),
- PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N),
- PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N),
- PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N),
- PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N),
- PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N),
- PINGROUP(hdmi_cec_pee3, CEC, SDMMC3, RSVD3, SOC, 0x33e0, Y, N, N),
- PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N),
- PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N),
- PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N),
- PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N),
- PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N),
- PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N),
- PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N),
- PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N),
- PINGROUP(gmi_clk_lb, SDMMC2, NAND, GMI, RSVD4, 0x3404, N, N, N),
- PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N),
-
- /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
- DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(at1, 0x870, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
- DRV_PINGROUP(at2, 0x874, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
- DRV_PINGROUP(at3, 0x878, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
- DRV_PINGROUP(at4, 0x87c, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
- DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
- DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
- DRV_PINGROUP(ddc, 0x8fc, 2, 3, -1, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(gma, 0x900, 2, 3, -1, 14, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, Y),
- DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(ao3, 0x9a0, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
- DRV_PINGROUP(hv0, 0x9a4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
- DRV_PINGROUP(sdio4, 0x9a8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(ao0, 0x9ac, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
-};
-
-static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {
- .ngpios = NUM_GPIOS,
- .pins = tegra114_pins,
- .npins = ARRAY_SIZE(tegra114_pins),
- .functions = tegra114_functions,
- .nfunctions = ARRAY_SIZE(tegra114_functions),
- .groups = tegra114_groups,
- .ngroups = ARRAY_SIZE(tegra114_groups),
- .hsm_in_mux = false,
- .schmitt_in_mux = false,
- .drvtype_in_mux = false,
-};
-
-static int tegra114_pinctrl_probe(struct platform_device *pdev)
-{
- return tegra_pinctrl_probe(pdev, &tegra114_pinctrl);
-}
-
-static const struct of_device_id tegra114_pinctrl_of_match[] = {
- { .compatible = "nvidia,tegra114-pinmux", },
- { },
-};
-MODULE_DEVICE_TABLE(of, tegra114_pinctrl_of_match);
-
-static struct platform_driver tegra114_pinctrl_driver = {
- .driver = {
- .name = "tegra114-pinctrl",
- .of_match_table = tegra114_pinctrl_of_match,
- },
- .probe = tegra114_pinctrl_probe,
- .remove = tegra_pinctrl_remove,
-};
-module_platform_driver(tegra114_pinctrl_driver);
-
-MODULE_AUTHOR("Pritesh Raithatha <praithatha@nvidia.com>");
-MODULE_DESCRIPTION("NVIDIA Tegra114 pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * Pinctrl data for the NVIDIA Tegra124 pinmux
- *
- * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-
-#include "pinctrl-tegra.h"
-
-/*
- * Most pins affected by the pinmux can also be GPIOs. Define these first.
- * These must match how the GPIO driver names/numbers its pins.
- */
-#define _GPIO(offset) (offset)
-
-#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
-#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
-#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
-#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
-#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
-#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
-#define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
-#define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
-#define TEGRA_PIN_PB0 _GPIO(8)
-#define TEGRA_PIN_PB1 _GPIO(9)
-#define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
-#define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
-#define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
-#define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
-#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
-#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
-#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
-#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
-#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
-#define TEGRA_PIN_PC7 _GPIO(23)
-#define TEGRA_PIN_PG0 _GPIO(48)
-#define TEGRA_PIN_PG1 _GPIO(49)
-#define TEGRA_PIN_PG2 _GPIO(50)
-#define TEGRA_PIN_PG3 _GPIO(51)
-#define TEGRA_PIN_PG4 _GPIO(52)
-#define TEGRA_PIN_PG5 _GPIO(53)
-#define TEGRA_PIN_PG6 _GPIO(54)
-#define TEGRA_PIN_PG7 _GPIO(55)
-#define TEGRA_PIN_PH0 _GPIO(56)
-#define TEGRA_PIN_PH1 _GPIO(57)
-#define TEGRA_PIN_PH2 _GPIO(58)
-#define TEGRA_PIN_PH3 _GPIO(59)
-#define TEGRA_PIN_PH4 _GPIO(60)
-#define TEGRA_PIN_PH5 _GPIO(61)
-#define TEGRA_PIN_PH6 _GPIO(62)
-#define TEGRA_PIN_PH7 _GPIO(63)
-#define TEGRA_PIN_PI0 _GPIO(64)
-#define TEGRA_PIN_PI1 _GPIO(65)
-#define TEGRA_PIN_PI2 _GPIO(66)
-#define TEGRA_PIN_PI3 _GPIO(67)
-#define TEGRA_PIN_PI4 _GPIO(68)
-#define TEGRA_PIN_PI5 _GPIO(69)
-#define TEGRA_PIN_PI6 _GPIO(70)
-#define TEGRA_PIN_PI7 _GPIO(71)
-#define TEGRA_PIN_PJ0 _GPIO(72)
-#define TEGRA_PIN_PJ2 _GPIO(74)
-#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
-#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
-#define TEGRA_PIN_PJ7 _GPIO(79)
-#define TEGRA_PIN_PK0 _GPIO(80)
-#define TEGRA_PIN_PK1 _GPIO(81)
-#define TEGRA_PIN_PK2 _GPIO(82)
-#define TEGRA_PIN_PK3 _GPIO(83)
-#define TEGRA_PIN_PK4 _GPIO(84)
-#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
-#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
-#define TEGRA_PIN_PK7 _GPIO(87)
-#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
-#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
-#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
-#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
-#define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108)
-#define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109)
-#define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
-#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
-#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
-#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
-#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
-#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
-#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
-#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
-#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
-#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
-#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
-#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
-#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
-#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
-#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
-#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
-#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
-#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
-#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
-#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
-#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
-#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
-#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
-#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
-#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
-#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
-#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
-#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
-#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
-#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
-#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
-#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
-#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
-#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
-#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
-#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
-#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
-#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
-#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
-#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
-#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
-#define TEGRA_PIN_KB_ROW16_PT0 _GPIO(152)
-#define TEGRA_PIN_KB_ROW17_PT1 _GPIO(153)
-#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
-#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
-#define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
-#define TEGRA_PIN_PU0 _GPIO(160)
-#define TEGRA_PIN_PU1 _GPIO(161)
-#define TEGRA_PIN_PU2 _GPIO(162)
-#define TEGRA_PIN_PU3 _GPIO(163)
-#define TEGRA_PIN_PU4 _GPIO(164)
-#define TEGRA_PIN_PU5 _GPIO(165)
-#define TEGRA_PIN_PU6 _GPIO(166)
-#define TEGRA_PIN_PV0 _GPIO(168)
-#define TEGRA_PIN_PV1 _GPIO(169)
-#define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170)
-#define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171)
-#define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
-#define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
-#define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178)
-#define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179)
-#define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
-#define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
-#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
-#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
-#define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184)
-#define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185)
-#define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186)
-#define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187)
-#define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188)
-#define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189)
-#define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190)
-#define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191)
-#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
-#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
-#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
-#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
-#define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
-#define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
-#define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
-#define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
-#define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
-#define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
-#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
-#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
-#define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
-#define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
-#define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
-#define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
-#define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
-#define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
-#define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
-#define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
-#define TEGRA_PIN_PBB0 _GPIO(216)
-#define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
-#define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
-#define TEGRA_PIN_PBB3 _GPIO(219)
-#define TEGRA_PIN_PBB4 _GPIO(220)
-#define TEGRA_PIN_PBB5 _GPIO(221)
-#define TEGRA_PIN_PBB6 _GPIO(222)
-#define TEGRA_PIN_PBB7 _GPIO(223)
-#define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
-#define TEGRA_PIN_PCC1 _GPIO(225)
-#define TEGRA_PIN_PCC2 _GPIO(226)
-#define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
-#define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
-#define TEGRA_PIN_PEX_L0_RST_N_PDD1 _GPIO(233)
-#define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2 _GPIO(234)
-#define TEGRA_PIN_PEX_WAKE_N_PDD3 _GPIO(235)
-#define TEGRA_PIN_PEX_L1_RST_N_PDD5 _GPIO(237)
-#define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6 _GPIO(238)
-#define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
-#define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
-#define TEGRA_PIN_DAP_MCLK1_REQ_PEE2 _GPIO(242)
-#define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
-#define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244)
-#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
-#define TEGRA_PIN_DP_HPD_PFF0 _GPIO(248)
-#define TEGRA_PIN_USB_VBUS_EN2_PFF1 _GPIO(249)
-#define TEGRA_PIN_PFF2 _GPIO(250)
-
-/* All non-GPIO pins follow */
-#define NUM_GPIOS (TEGRA_PIN_PFF2 + 1)
-#define _PIN(offset) (NUM_GPIOS + (offset))
-
-/* Non-GPIO pins */
-#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
-#define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
-#define TEGRA_PIN_PWR_INT_N _PIN(2)
-#define TEGRA_PIN_GMI_CLK_LB _PIN(3)
-#define TEGRA_PIN_RESET_OUT_N _PIN(4)
-#define TEGRA_PIN_OWR _PIN(5)
-#define TEGRA_PIN_CLK_32K_IN _PIN(6)
-#define TEGRA_PIN_JTAG_RTCK _PIN(7)
-#define TEGRA_PIN_DSI_B_CLK_P _PIN(8)
-#define TEGRA_PIN_DSI_B_CLK_N _PIN(9)
-#define TEGRA_PIN_DSI_B_D0_P _PIN(10)
-#define TEGRA_PIN_DSI_B_D0_N _PIN(11)
-#define TEGRA_PIN_DSI_B_D1_P _PIN(12)
-#define TEGRA_PIN_DSI_B_D1_N _PIN(13)
-#define TEGRA_PIN_DSI_B_D2_P _PIN(14)
-#define TEGRA_PIN_DSI_B_D2_N _PIN(15)
-#define TEGRA_PIN_DSI_B_D3_P _PIN(16)
-#define TEGRA_PIN_DSI_B_D3_N _PIN(17)
-
-static const struct pinctrl_pin_desc tegra124_pins[] = {
- PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
- PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
- PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"),
- PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
- PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
- PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
- PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
- PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
- PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
- PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"),
- PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"),
- PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"),
- PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"),
- PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"),
- PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"),
- PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"),
- PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"),
- PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"),
- PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"),
- PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"),
- PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"),
- PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"),
- PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"),
- PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"),
- PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
- PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"),
- PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"),
- PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"),
- PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"),
- PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"),
- PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"),
- PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"),
- PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"),
- PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"),
- PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"),
- PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"),
- PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
- PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
- PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"),
- PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
- PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
- PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
- PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
- PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
- PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
- PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
- PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
- PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
- PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
- PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW16 PT0"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW17 PT1"),
- PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
- PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
- PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
- PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
- PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
- PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
- PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
- PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
- PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
- PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
- PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
- PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
- PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
- PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
- PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
- PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
- PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
- PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
- PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
- PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
- PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
- PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
- PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
- PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
- PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
- PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
- PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
- PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
- PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
- PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
- PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
- PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
- PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
- PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
- PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
- PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
- PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"),
- PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
- PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
- PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
- PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
- PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
- PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
- PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
- PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
- PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
- PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
- PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"),
- PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"),
- PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"),
- PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"),
- PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"),
- PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"),
- PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"),
- PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"),
- PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"),
- PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"),
-};
-
-static const unsigned clk_32k_out_pa0_pins[] = {
- TEGRA_PIN_CLK_32K_OUT_PA0,
-};
-
-static const unsigned uart3_cts_n_pa1_pins[] = {
- TEGRA_PIN_UART3_CTS_N_PA1,
-};
-
-static const unsigned dap2_fs_pa2_pins[] = {
- TEGRA_PIN_DAP2_FS_PA2,
-};
-
-static const unsigned dap2_sclk_pa3_pins[] = {
- TEGRA_PIN_DAP2_SCLK_PA3,
-};
-
-static const unsigned dap2_din_pa4_pins[] = {
- TEGRA_PIN_DAP2_DIN_PA4,
-};
-
-static const unsigned dap2_dout_pa5_pins[] = {
- TEGRA_PIN_DAP2_DOUT_PA5,
-};
-
-static const unsigned sdmmc3_clk_pa6_pins[] = {
- TEGRA_PIN_SDMMC3_CLK_PA6,
-};
-
-static const unsigned sdmmc3_cmd_pa7_pins[] = {
- TEGRA_PIN_SDMMC3_CMD_PA7,
-};
-
-static const unsigned pb0_pins[] = {
- TEGRA_PIN_PB0,
-};
-
-static const unsigned pb1_pins[] = {
- TEGRA_PIN_PB1,
-};
-
-static const unsigned sdmmc3_dat3_pb4_pins[] = {
- TEGRA_PIN_SDMMC3_DAT3_PB4,
-};
-
-static const unsigned sdmmc3_dat2_pb5_pins[] = {
- TEGRA_PIN_SDMMC3_DAT2_PB5,
-};
-
-static const unsigned sdmmc3_dat1_pb6_pins[] = {
- TEGRA_PIN_SDMMC3_DAT1_PB6,
-};
-
-static const unsigned sdmmc3_dat0_pb7_pins[] = {
- TEGRA_PIN_SDMMC3_DAT0_PB7,
-};
-
-static const unsigned uart3_rts_n_pc0_pins[] = {
- TEGRA_PIN_UART3_RTS_N_PC0,
-};
-
-static const unsigned uart2_txd_pc2_pins[] = {
- TEGRA_PIN_UART2_TXD_PC2,
-};
-
-static const unsigned uart2_rxd_pc3_pins[] = {
- TEGRA_PIN_UART2_RXD_PC3,
-};
-
-static const unsigned gen1_i2c_scl_pc4_pins[] = {
- TEGRA_PIN_GEN1_I2C_SCL_PC4,
-};
-
-static const unsigned gen1_i2c_sda_pc5_pins[] = {
- TEGRA_PIN_GEN1_I2C_SDA_PC5,
-};
-
-static const unsigned pc7_pins[] = {
- TEGRA_PIN_PC7,
-};
-
-static const unsigned pg0_pins[] = {
- TEGRA_PIN_PG0,
-};
-
-static const unsigned pg1_pins[] = {
- TEGRA_PIN_PG1,
-};
-
-static const unsigned pg2_pins[] = {
- TEGRA_PIN_PG2,
-};
-
-static const unsigned pg3_pins[] = {
- TEGRA_PIN_PG3,
-};
-
-static const unsigned pg4_pins[] = {
- TEGRA_PIN_PG4,
-};
-
-static const unsigned pg5_pins[] = {
- TEGRA_PIN_PG5,
-};
-
-static const unsigned pg6_pins[] = {
- TEGRA_PIN_PG6,
-};
-
-static const unsigned pg7_pins[] = {
- TEGRA_PIN_PG7,
-};
-
-static const unsigned ph0_pins[] = {
- TEGRA_PIN_PH0,
-};
-
-static const unsigned ph1_pins[] = {
- TEGRA_PIN_PH1,
-};
-
-static const unsigned ph2_pins[] = {
- TEGRA_PIN_PH2,
-};
-
-static const unsigned ph3_pins[] = {
- TEGRA_PIN_PH3,
-};
-
-static const unsigned ph4_pins[] = {
- TEGRA_PIN_PH4,
-};
-
-static const unsigned ph5_pins[] = {
- TEGRA_PIN_PH5,
-};
-
-static const unsigned ph6_pins[] = {
- TEGRA_PIN_PH6,
-};
-
-static const unsigned ph7_pins[] = {
- TEGRA_PIN_PH7,
-};
-
-static const unsigned pi0_pins[] = {
- TEGRA_PIN_PI0,
-};
-
-static const unsigned pi1_pins[] = {
- TEGRA_PIN_PI1,
-};
-
-static const unsigned pi2_pins[] = {
- TEGRA_PIN_PI2,
-};
-
-static const unsigned pi3_pins[] = {
- TEGRA_PIN_PI3,
-};
-
-static const unsigned pi4_pins[] = {
- TEGRA_PIN_PI4,
-};
-
-static const unsigned pi5_pins[] = {
- TEGRA_PIN_PI5,
-};
-
-static const unsigned pi6_pins[] = {
- TEGRA_PIN_PI6,
-};
-
-static const unsigned pi7_pins[] = {
- TEGRA_PIN_PI7,
-};
-
-static const unsigned pj0_pins[] = {
- TEGRA_PIN_PJ0,
-};
-
-static const unsigned pj2_pins[] = {
- TEGRA_PIN_PJ2,
-};
-
-static const unsigned uart2_cts_n_pj5_pins[] = {
- TEGRA_PIN_UART2_CTS_N_PJ5,
-};
-
-static const unsigned uart2_rts_n_pj6_pins[] = {
- TEGRA_PIN_UART2_RTS_N_PJ6,
-};
-
-static const unsigned pj7_pins[] = {
- TEGRA_PIN_PJ7,
-};
-
-static const unsigned pk0_pins[] = {
- TEGRA_PIN_PK0,
-};
-
-static const unsigned pk1_pins[] = {
- TEGRA_PIN_PK1,
-};
-
-static const unsigned pk2_pins[] = {
- TEGRA_PIN_PK2,
-};
-
-static const unsigned pk3_pins[] = {
- TEGRA_PIN_PK3,
-};
-
-static const unsigned pk4_pins[] = {
- TEGRA_PIN_PK4,
-};
-
-static const unsigned spdif_out_pk5_pins[] = {
- TEGRA_PIN_SPDIF_OUT_PK5,
-};
-
-static const unsigned spdif_in_pk6_pins[] = {
- TEGRA_PIN_SPDIF_IN_PK6,
-};
-
-static const unsigned pk7_pins[] = {
- TEGRA_PIN_PK7,
-};
-
-static const unsigned dap1_fs_pn0_pins[] = {
- TEGRA_PIN_DAP1_FS_PN0,
-};
-
-static const unsigned dap1_din_pn1_pins[] = {
- TEGRA_PIN_DAP1_DIN_PN1,
-};
-
-static const unsigned dap1_dout_pn2_pins[] = {
- TEGRA_PIN_DAP1_DOUT_PN2,
-};
-
-static const unsigned dap1_sclk_pn3_pins[] = {
- TEGRA_PIN_DAP1_SCLK_PN3,
-};
-
-static const unsigned usb_vbus_en0_pn4_pins[] = {
- TEGRA_PIN_USB_VBUS_EN0_PN4,
-};
-
-static const unsigned usb_vbus_en1_pn5_pins[] = {
- TEGRA_PIN_USB_VBUS_EN1_PN5,
-};
-
-static const unsigned hdmi_int_pn7_pins[] = {
- TEGRA_PIN_HDMI_INT_PN7,
-};
-
-static const unsigned ulpi_data7_po0_pins[] = {
- TEGRA_PIN_ULPI_DATA7_PO0,
-};
-
-static const unsigned ulpi_data0_po1_pins[] = {
- TEGRA_PIN_ULPI_DATA0_PO1,
-};
-
-static const unsigned ulpi_data1_po2_pins[] = {
- TEGRA_PIN_ULPI_DATA1_PO2,
-};
-
-static const unsigned ulpi_data2_po3_pins[] = {
- TEGRA_PIN_ULPI_DATA2_PO3,
-};
-
-static const unsigned ulpi_data3_po4_pins[] = {
- TEGRA_PIN_ULPI_DATA3_PO4,
-};
-
-static const unsigned ulpi_data4_po5_pins[] = {
- TEGRA_PIN_ULPI_DATA4_PO5,
-};
-
-static const unsigned ulpi_data5_po6_pins[] = {
- TEGRA_PIN_ULPI_DATA5_PO6,
-};
-
-static const unsigned ulpi_data6_po7_pins[] = {
- TEGRA_PIN_ULPI_DATA6_PO7,
-};
-
-static const unsigned dap3_fs_pp0_pins[] = {
- TEGRA_PIN_DAP3_FS_PP0,
-};
-
-static const unsigned dap3_din_pp1_pins[] = {
- TEGRA_PIN_DAP3_DIN_PP1,
-};
-
-static const unsigned dap3_dout_pp2_pins[] = {
- TEGRA_PIN_DAP3_DOUT_PP2,
-};
-
-static const unsigned dap3_sclk_pp3_pins[] = {
- TEGRA_PIN_DAP3_SCLK_PP3,
-};
-
-static const unsigned dap4_fs_pp4_pins[] = {
- TEGRA_PIN_DAP4_FS_PP4,
-};
-
-static const unsigned dap4_din_pp5_pins[] = {
- TEGRA_PIN_DAP4_DIN_PP5,
-};
-
-static const unsigned dap4_dout_pp6_pins[] = {
- TEGRA_PIN_DAP4_DOUT_PP6,
-};
-
-static const unsigned dap4_sclk_pp7_pins[] = {
- TEGRA_PIN_DAP4_SCLK_PP7,
-};
-
-static const unsigned kb_col0_pq0_pins[] = {
- TEGRA_PIN_KB_COL0_PQ0,
-};
-
-static const unsigned kb_col1_pq1_pins[] = {
- TEGRA_PIN_KB_COL1_PQ1,
-};
-
-static const unsigned kb_col2_pq2_pins[] = {
- TEGRA_PIN_KB_COL2_PQ2,
-};
-
-static const unsigned kb_col3_pq3_pins[] = {
- TEGRA_PIN_KB_COL3_PQ3,
-};
-
-static const unsigned kb_col4_pq4_pins[] = {
- TEGRA_PIN_KB_COL4_PQ4,
-};
-
-static const unsigned kb_col5_pq5_pins[] = {
- TEGRA_PIN_KB_COL5_PQ5,
-};
-
-static const unsigned kb_col6_pq6_pins[] = {
- TEGRA_PIN_KB_COL6_PQ6,
-};
-
-static const unsigned kb_col7_pq7_pins[] = {
- TEGRA_PIN_KB_COL7_PQ7,
-};
-
-static const unsigned kb_row0_pr0_pins[] = {
- TEGRA_PIN_KB_ROW0_PR0,
-};
-
-static const unsigned kb_row1_pr1_pins[] = {
- TEGRA_PIN_KB_ROW1_PR1,
-};
-
-static const unsigned kb_row2_pr2_pins[] = {
- TEGRA_PIN_KB_ROW2_PR2,
-};
-
-static const unsigned kb_row3_pr3_pins[] = {
- TEGRA_PIN_KB_ROW3_PR3,
-};
-
-static const unsigned kb_row4_pr4_pins[] = {
- TEGRA_PIN_KB_ROW4_PR4,
-};
-
-static const unsigned kb_row5_pr5_pins[] = {
- TEGRA_PIN_KB_ROW5_PR5,
-};
-
-static const unsigned kb_row6_pr6_pins[] = {
- TEGRA_PIN_KB_ROW6_PR6,
-};
-
-static const unsigned kb_row7_pr7_pins[] = {
- TEGRA_PIN_KB_ROW7_PR7,
-};
-
-static const unsigned kb_row8_ps0_pins[] = {
- TEGRA_PIN_KB_ROW8_PS0,
-};
-
-static const unsigned kb_row9_ps1_pins[] = {
- TEGRA_PIN_KB_ROW9_PS1,
-};
-
-static const unsigned kb_row10_ps2_pins[] = {
- TEGRA_PIN_KB_ROW10_PS2,
-};
-
-static const unsigned kb_row11_ps3_pins[] = {
- TEGRA_PIN_KB_ROW11_PS3,
-};
-
-static const unsigned kb_row12_ps4_pins[] = {
- TEGRA_PIN_KB_ROW12_PS4,
-};
-
-static const unsigned kb_row13_ps5_pins[] = {
- TEGRA_PIN_KB_ROW13_PS5,
-};
-
-static const unsigned kb_row14_ps6_pins[] = {
- TEGRA_PIN_KB_ROW14_PS6,
-};
-
-static const unsigned kb_row15_ps7_pins[] = {
- TEGRA_PIN_KB_ROW15_PS7,
-};
-
-static const unsigned kb_row16_pt0_pins[] = {
- TEGRA_PIN_KB_ROW16_PT0,
-};
-
-static const unsigned kb_row17_pt1_pins[] = {
- TEGRA_PIN_KB_ROW17_PT1,
-};
-
-static const unsigned gen2_i2c_scl_pt5_pins[] = {
- TEGRA_PIN_GEN2_I2C_SCL_PT5,
-};
-
-static const unsigned gen2_i2c_sda_pt6_pins[] = {
- TEGRA_PIN_GEN2_I2C_SDA_PT6,
-};
-
-static const unsigned sdmmc4_cmd_pt7_pins[] = {
- TEGRA_PIN_SDMMC4_CMD_PT7,
-};
-
-static const unsigned pu0_pins[] = {
- TEGRA_PIN_PU0,
-};
-
-static const unsigned pu1_pins[] = {
- TEGRA_PIN_PU1,
-};
-
-static const unsigned pu2_pins[] = {
- TEGRA_PIN_PU2,
-};
-
-static const unsigned pu3_pins[] = {
- TEGRA_PIN_PU3,
-};
-
-static const unsigned pu4_pins[] = {
- TEGRA_PIN_PU4,
-};
-
-static const unsigned pu5_pins[] = {
- TEGRA_PIN_PU5,
-};
-
-static const unsigned pu6_pins[] = {
- TEGRA_PIN_PU6,
-};
-
-static const unsigned pv0_pins[] = {
- TEGRA_PIN_PV0,
-};
-
-static const unsigned pv1_pins[] = {
- TEGRA_PIN_PV1,
-};
-
-static const unsigned sdmmc3_cd_n_pv2_pins[] = {
- TEGRA_PIN_SDMMC3_CD_N_PV2,
-};
-
-static const unsigned sdmmc1_wp_n_pv3_pins[] = {
- TEGRA_PIN_SDMMC1_WP_N_PV3,
-};
-
-static const unsigned ddc_scl_pv4_pins[] = {
- TEGRA_PIN_DDC_SCL_PV4,
-};
-
-static const unsigned ddc_sda_pv5_pins[] = {
- TEGRA_PIN_DDC_SDA_PV5,
-};
-
-static const unsigned gpio_w2_aud_pw2_pins[] = {
- TEGRA_PIN_GPIO_W2_AUD_PW2,
-};
-
-static const unsigned gpio_w3_aud_pw3_pins[] = {
- TEGRA_PIN_GPIO_W3_AUD_PW3,
-};
-
-static const unsigned dap_mclk1_pw4_pins[] = {
- TEGRA_PIN_DAP_MCLK1_PW4,
-};
-
-static const unsigned clk2_out_pw5_pins[] = {
- TEGRA_PIN_CLK2_OUT_PW5,
-};
-
-static const unsigned uart3_txd_pw6_pins[] = {
- TEGRA_PIN_UART3_TXD_PW6,
-};
-
-static const unsigned uart3_rxd_pw7_pins[] = {
- TEGRA_PIN_UART3_RXD_PW7,
-};
-
-static const unsigned dvfs_pwm_px0_pins[] = {
- TEGRA_PIN_DVFS_PWM_PX0,
-};
-
-static const unsigned gpio_x1_aud_px1_pins[] = {
- TEGRA_PIN_GPIO_X1_AUD_PX1,
-};
-
-static const unsigned dvfs_clk_px2_pins[] = {
- TEGRA_PIN_DVFS_CLK_PX2,
-};
-
-static const unsigned gpio_x3_aud_px3_pins[] = {
- TEGRA_PIN_GPIO_X3_AUD_PX3,
-};
-
-static const unsigned gpio_x4_aud_px4_pins[] = {
- TEGRA_PIN_GPIO_X4_AUD_PX4,
-};
-
-static const unsigned gpio_x5_aud_px5_pins[] = {
- TEGRA_PIN_GPIO_X5_AUD_PX5,
-};
-
-static const unsigned gpio_x6_aud_px6_pins[] = {
- TEGRA_PIN_GPIO_X6_AUD_PX6,
-};
-
-static const unsigned gpio_x7_aud_px7_pins[] = {
- TEGRA_PIN_GPIO_X7_AUD_PX7,
-};
-
-static const unsigned ulpi_clk_py0_pins[] = {
- TEGRA_PIN_ULPI_CLK_PY0,
-};
-
-static const unsigned ulpi_dir_py1_pins[] = {
- TEGRA_PIN_ULPI_DIR_PY1,
-};
-
-static const unsigned ulpi_nxt_py2_pins[] = {
- TEGRA_PIN_ULPI_NXT_PY2,
-};
-
-static const unsigned ulpi_stp_py3_pins[] = {
- TEGRA_PIN_ULPI_STP_PY3,
-};
-
-static const unsigned sdmmc1_dat3_py4_pins[] = {
- TEGRA_PIN_SDMMC1_DAT3_PY4,
-};
-
-static const unsigned sdmmc1_dat2_py5_pins[] = {
- TEGRA_PIN_SDMMC1_DAT2_PY5,
-};
-
-static const unsigned sdmmc1_dat1_py6_pins[] = {
- TEGRA_PIN_SDMMC1_DAT1_PY6,
-};
-
-static const unsigned sdmmc1_dat0_py7_pins[] = {
- TEGRA_PIN_SDMMC1_DAT0_PY7,
-};
-
-static const unsigned sdmmc1_clk_pz0_pins[] = {
- TEGRA_PIN_SDMMC1_CLK_PZ0,
-};
-
-static const unsigned sdmmc1_cmd_pz1_pins[] = {
- TEGRA_PIN_SDMMC1_CMD_PZ1,
-};
-
-static const unsigned pwr_i2c_scl_pz6_pins[] = {
- TEGRA_PIN_PWR_I2C_SCL_PZ6,
-};
-
-static const unsigned pwr_i2c_sda_pz7_pins[] = {
- TEGRA_PIN_PWR_I2C_SDA_PZ7,
-};
-
-static const unsigned sdmmc4_dat0_paa0_pins[] = {
- TEGRA_PIN_SDMMC4_DAT0_PAA0,
-};
-
-static const unsigned sdmmc4_dat1_paa1_pins[] = {
- TEGRA_PIN_SDMMC4_DAT1_PAA1,
-};
-
-static const unsigned sdmmc4_dat2_paa2_pins[] = {
- TEGRA_PIN_SDMMC4_DAT2_PAA2,
-};
-
-static const unsigned sdmmc4_dat3_paa3_pins[] = {
- TEGRA_PIN_SDMMC4_DAT3_PAA3,
-};
-
-static const unsigned sdmmc4_dat4_paa4_pins[] = {
- TEGRA_PIN_SDMMC4_DAT4_PAA4,
-};
-
-static const unsigned sdmmc4_dat5_paa5_pins[] = {
- TEGRA_PIN_SDMMC4_DAT5_PAA5,
-};
-
-static const unsigned sdmmc4_dat6_paa6_pins[] = {
- TEGRA_PIN_SDMMC4_DAT6_PAA6,
-};
-
-static const unsigned sdmmc4_dat7_paa7_pins[] = {
- TEGRA_PIN_SDMMC4_DAT7_PAA7,
-};
-
-static const unsigned pbb0_pins[] = {
- TEGRA_PIN_PBB0,
-};
-
-static const unsigned cam_i2c_scl_pbb1_pins[] = {
- TEGRA_PIN_CAM_I2C_SCL_PBB1,
-};
-
-static const unsigned cam_i2c_sda_pbb2_pins[] = {
- TEGRA_PIN_CAM_I2C_SDA_PBB2,
-};
-
-static const unsigned pbb3_pins[] = {
- TEGRA_PIN_PBB3,
-};
-
-static const unsigned pbb4_pins[] = {
- TEGRA_PIN_PBB4,
-};
-
-static const unsigned pbb5_pins[] = {
- TEGRA_PIN_PBB5,
-};
-
-static const unsigned pbb6_pins[] = {
- TEGRA_PIN_PBB6,
-};
-
-static const unsigned pbb7_pins[] = {
- TEGRA_PIN_PBB7,
-};
-
-static const unsigned cam_mclk_pcc0_pins[] = {
- TEGRA_PIN_CAM_MCLK_PCC0,
-};
-
-static const unsigned pcc1_pins[] = {
- TEGRA_PIN_PCC1,
-};
-
-static const unsigned pcc2_pins[] = {
- TEGRA_PIN_PCC2,
-};
-
-static const unsigned sdmmc4_clk_pcc4_pins[] = {
- TEGRA_PIN_SDMMC4_CLK_PCC4,
-};
-
-static const unsigned clk2_req_pcc5_pins[] = {
- TEGRA_PIN_CLK2_REQ_PCC5,
-};
-
-static const unsigned pex_l0_rst_n_pdd1_pins[] = {
- TEGRA_PIN_PEX_L0_RST_N_PDD1,
-};
-
-static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
- TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
-};
-
-static const unsigned pex_wake_n_pdd3_pins[] = {
- TEGRA_PIN_PEX_WAKE_N_PDD3,
-};
-
-static const unsigned pex_l1_rst_n_pdd5_pins[] = {
- TEGRA_PIN_PEX_L1_RST_N_PDD5,
-};
-
-static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
- TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
-};
-
-static const unsigned clk3_out_pee0_pins[] = {
- TEGRA_PIN_CLK3_OUT_PEE0,
-};
-
-static const unsigned clk3_req_pee1_pins[] = {
- TEGRA_PIN_CLK3_REQ_PEE1,
-};
-
-static const unsigned dap_mclk1_req_pee2_pins[] = {
- TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
-};
-
-static const unsigned hdmi_cec_pee3_pins[] = {
- TEGRA_PIN_HDMI_CEC_PEE3,
-};
-
-static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
- TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
-};
-
-static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
- TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
-};
-
-static const unsigned dp_hpd_pff0_pins[] = {
- TEGRA_PIN_DP_HPD_PFF0,
-};
-
-static const unsigned usb_vbus_en2_pff1_pins[] = {
- TEGRA_PIN_USB_VBUS_EN2_PFF1,
-};
-
-static const unsigned pff2_pins[] = {
- TEGRA_PIN_PFF2,
-};
-
-static const unsigned core_pwr_req_pins[] = {
- TEGRA_PIN_CORE_PWR_REQ,
-};
-
-static const unsigned cpu_pwr_req_pins[] = {
- TEGRA_PIN_CPU_PWR_REQ,
-};
-
-static const unsigned pwr_int_n_pins[] = {
- TEGRA_PIN_PWR_INT_N,
-};
-
-static const unsigned gmi_clk_lb_pins[] = {
- TEGRA_PIN_GMI_CLK_LB,
-};
-
-static const unsigned reset_out_n_pins[] = {
- TEGRA_PIN_RESET_OUT_N,
-};
-
-static const unsigned owr_pins[] = {
- TEGRA_PIN_OWR,
-};
-
-static const unsigned clk_32k_in_pins[] = {
- TEGRA_PIN_CLK_32K_IN,
-};
-
-static const unsigned jtag_rtck_pins[] = {
- TEGRA_PIN_JTAG_RTCK,
-};
-
-static const unsigned drive_ao1_pins[] = {
- TEGRA_PIN_KB_ROW0_PR0,
- TEGRA_PIN_KB_ROW1_PR1,
- TEGRA_PIN_KB_ROW2_PR2,
- TEGRA_PIN_KB_ROW3_PR3,
- TEGRA_PIN_KB_ROW4_PR4,
- TEGRA_PIN_KB_ROW5_PR5,
- TEGRA_PIN_KB_ROW6_PR6,
- TEGRA_PIN_KB_ROW7_PR7,
- TEGRA_PIN_PWR_I2C_SCL_PZ6,
- TEGRA_PIN_PWR_I2C_SDA_PZ7,
-};
-
-static const unsigned drive_ao2_pins[] = {
- TEGRA_PIN_CLK_32K_OUT_PA0,
- TEGRA_PIN_CLK_32K_IN,
- TEGRA_PIN_KB_COL0_PQ0,
- TEGRA_PIN_KB_COL1_PQ1,
- TEGRA_PIN_KB_COL2_PQ2,
- TEGRA_PIN_KB_COL3_PQ3,
- TEGRA_PIN_KB_COL4_PQ4,
- TEGRA_PIN_KB_COL5_PQ5,
- TEGRA_PIN_KB_COL6_PQ6,
- TEGRA_PIN_KB_COL7_PQ7,
- TEGRA_PIN_KB_ROW8_PS0,
- TEGRA_PIN_KB_ROW9_PS1,
- TEGRA_PIN_KB_ROW10_PS2,
- TEGRA_PIN_KB_ROW11_PS3,
- TEGRA_PIN_KB_ROW12_PS4,
- TEGRA_PIN_KB_ROW13_PS5,
- TEGRA_PIN_KB_ROW14_PS6,
- TEGRA_PIN_KB_ROW15_PS7,
- TEGRA_PIN_KB_ROW16_PT0,
- TEGRA_PIN_KB_ROW17_PT1,
- TEGRA_PIN_SDMMC3_CD_N_PV2,
- TEGRA_PIN_CORE_PWR_REQ,
- TEGRA_PIN_CPU_PWR_REQ,
- TEGRA_PIN_PWR_INT_N,
-};
-
-static const unsigned drive_at1_pins[] = {
- TEGRA_PIN_PH0,
- TEGRA_PIN_PH1,
- TEGRA_PIN_PH2,
- TEGRA_PIN_PH3,
-};
-
-static const unsigned drive_at2_pins[] = {
- TEGRA_PIN_PG0,
- TEGRA_PIN_PG1,
- TEGRA_PIN_PG2,
- TEGRA_PIN_PG3,
- TEGRA_PIN_PG4,
- TEGRA_PIN_PG5,
- TEGRA_PIN_PG6,
- TEGRA_PIN_PG7,
- TEGRA_PIN_PI0,
- TEGRA_PIN_PI1,
- TEGRA_PIN_PI3,
- TEGRA_PIN_PI4,
- TEGRA_PIN_PI7,
- TEGRA_PIN_PK0,
- TEGRA_PIN_PK2,
-};
-
-static const unsigned drive_at3_pins[] = {
- TEGRA_PIN_PC7,
- TEGRA_PIN_PJ0,
-};
-
-static const unsigned drive_at4_pins[] = {
- TEGRA_PIN_PB0,
- TEGRA_PIN_PB1,
- TEGRA_PIN_PJ0,
- TEGRA_PIN_PJ7,
- TEGRA_PIN_PK7,
-};
-
-static const unsigned drive_at5_pins[] = {
- TEGRA_PIN_GEN2_I2C_SCL_PT5,
- TEGRA_PIN_GEN2_I2C_SDA_PT6,
-};
-
-static const unsigned drive_cdev1_pins[] = {
- TEGRA_PIN_DAP_MCLK1_PW4,
- TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
-};
-
-static const unsigned drive_cdev2_pins[] = {
- TEGRA_PIN_CLK2_OUT_PW5,
- TEGRA_PIN_CLK2_REQ_PCC5,
-};
-
-static const unsigned drive_dap1_pins[] = {
- TEGRA_PIN_DAP1_FS_PN0,
- TEGRA_PIN_DAP1_DIN_PN1,
- TEGRA_PIN_DAP1_DOUT_PN2,
- TEGRA_PIN_DAP1_SCLK_PN3,
-};
-
-static const unsigned drive_dap2_pins[] = {
- TEGRA_PIN_DAP2_FS_PA2,
- TEGRA_PIN_DAP2_SCLK_PA3,
- TEGRA_PIN_DAP2_DIN_PA4,
- TEGRA_PIN_DAP2_DOUT_PA5,
-};
-
-static const unsigned drive_dap3_pins[] = {
- TEGRA_PIN_DAP3_FS_PP0,
- TEGRA_PIN_DAP3_DIN_PP1,
- TEGRA_PIN_DAP3_DOUT_PP2,
- TEGRA_PIN_DAP3_SCLK_PP3,
-};
-
-static const unsigned drive_dap4_pins[] = {
- TEGRA_PIN_DAP4_FS_PP4,
- TEGRA_PIN_DAP4_DIN_PP5,
- TEGRA_PIN_DAP4_DOUT_PP6,
- TEGRA_PIN_DAP4_SCLK_PP7,
-};
-
-static const unsigned drive_dbg_pins[] = {
- TEGRA_PIN_GEN1_I2C_SCL_PC4,
- TEGRA_PIN_GEN1_I2C_SDA_PC5,
- TEGRA_PIN_PU0,
- TEGRA_PIN_PU1,
- TEGRA_PIN_PU2,
- TEGRA_PIN_PU3,
- TEGRA_PIN_PU4,
- TEGRA_PIN_PU5,
- TEGRA_PIN_PU6,
-};
-
-static const unsigned drive_sdio3_pins[] = {
- TEGRA_PIN_SDMMC3_CLK_PA6,
- TEGRA_PIN_SDMMC3_CMD_PA7,
- TEGRA_PIN_SDMMC3_DAT3_PB4,
- TEGRA_PIN_SDMMC3_DAT2_PB5,
- TEGRA_PIN_SDMMC3_DAT1_PB6,
- TEGRA_PIN_SDMMC3_DAT0_PB7,
- TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
- TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
-};
-
-static const unsigned drive_spi_pins[] = {
- TEGRA_PIN_DVFS_PWM_PX0,
- TEGRA_PIN_GPIO_X1_AUD_PX1,
- TEGRA_PIN_DVFS_CLK_PX2,
- TEGRA_PIN_GPIO_X3_AUD_PX3,
- TEGRA_PIN_GPIO_X4_AUD_PX4,
- TEGRA_PIN_GPIO_X5_AUD_PX5,
- TEGRA_PIN_GPIO_X6_AUD_PX6,
- TEGRA_PIN_GPIO_X7_AUD_PX7,
- TEGRA_PIN_GPIO_W2_AUD_PW2,
- TEGRA_PIN_GPIO_W3_AUD_PW3,
-};
-
-static const unsigned drive_uaa_pins[] = {
- TEGRA_PIN_ULPI_DATA0_PO1,
- TEGRA_PIN_ULPI_DATA1_PO2,
- TEGRA_PIN_ULPI_DATA2_PO3,
- TEGRA_PIN_ULPI_DATA3_PO4,
-};
-
-static const unsigned drive_uab_pins[] = {
- TEGRA_PIN_ULPI_DATA7_PO0,
- TEGRA_PIN_ULPI_DATA4_PO5,
- TEGRA_PIN_ULPI_DATA5_PO6,
- TEGRA_PIN_ULPI_DATA6_PO7,
- TEGRA_PIN_PV0,
- TEGRA_PIN_PV1,
-};
-
-static const unsigned drive_uart2_pins[] = {
- TEGRA_PIN_UART2_TXD_PC2,
- TEGRA_PIN_UART2_RXD_PC3,
- TEGRA_PIN_UART2_CTS_N_PJ5,
- TEGRA_PIN_UART2_RTS_N_PJ6,
-};
-
-static const unsigned drive_uart3_pins[] = {
- TEGRA_PIN_UART3_CTS_N_PA1,
- TEGRA_PIN_UART3_RTS_N_PC0,
- TEGRA_PIN_UART3_TXD_PW6,
- TEGRA_PIN_UART3_RXD_PW7,
-};
-
-static const unsigned drive_sdio1_pins[] = {
- TEGRA_PIN_SDMMC1_DAT3_PY4,
- TEGRA_PIN_SDMMC1_DAT2_PY5,
- TEGRA_PIN_SDMMC1_DAT1_PY6,
- TEGRA_PIN_SDMMC1_DAT0_PY7,
- TEGRA_PIN_SDMMC1_CLK_PZ0,
- TEGRA_PIN_SDMMC1_CMD_PZ1,
-};
-
-static const unsigned drive_ddc_pins[] = {
- TEGRA_PIN_DDC_SCL_PV4,
- TEGRA_PIN_DDC_SDA_PV5,
-};
-
-static const unsigned drive_gma_pins[] = {
- TEGRA_PIN_SDMMC4_CLK_PCC4,
- TEGRA_PIN_SDMMC4_CMD_PT7,
- TEGRA_PIN_SDMMC4_DAT0_PAA0,
- TEGRA_PIN_SDMMC4_DAT1_PAA1,
- TEGRA_PIN_SDMMC4_DAT2_PAA2,
- TEGRA_PIN_SDMMC4_DAT3_PAA3,
- TEGRA_PIN_SDMMC4_DAT4_PAA4,
- TEGRA_PIN_SDMMC4_DAT5_PAA5,
- TEGRA_PIN_SDMMC4_DAT6_PAA6,
- TEGRA_PIN_SDMMC4_DAT7_PAA7,
-};
-
-static const unsigned drive_gme_pins[] = {
- TEGRA_PIN_PBB0,
- TEGRA_PIN_CAM_I2C_SCL_PBB1,
- TEGRA_PIN_CAM_I2C_SDA_PBB2,
- TEGRA_PIN_PBB3,
- TEGRA_PIN_PCC2,
-};
-
-static const unsigned drive_gmf_pins[] = {
- TEGRA_PIN_PBB4,
- TEGRA_PIN_PBB5,
- TEGRA_PIN_PBB6,
- TEGRA_PIN_PBB7,
-};
-
-static const unsigned drive_gmg_pins[] = {
- TEGRA_PIN_CAM_MCLK_PCC0,
-};
-
-static const unsigned drive_gmh_pins[] = {
- TEGRA_PIN_PCC1,
-};
-
-static const unsigned drive_owr_pins[] = {
- TEGRA_PIN_SDMMC3_CD_N_PV2,
- TEGRA_PIN_OWR,
-};
-
-static const unsigned drive_uda_pins[] = {
- TEGRA_PIN_ULPI_CLK_PY0,
- TEGRA_PIN_ULPI_DIR_PY1,
- TEGRA_PIN_ULPI_NXT_PY2,
- TEGRA_PIN_ULPI_STP_PY3,
-};
-
-static const unsigned drive_gpv_pins[] = {
- TEGRA_PIN_PEX_L0_RST_N_PDD1,
- TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
- TEGRA_PIN_PEX_WAKE_N_PDD3,
- TEGRA_PIN_PEX_L1_RST_N_PDD5,
- TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
- TEGRA_PIN_USB_VBUS_EN2_PFF1,
- TEGRA_PIN_PFF2,
-};
-
-static const unsigned drive_dev3_pins[] = {
- TEGRA_PIN_CLK3_OUT_PEE0,
- TEGRA_PIN_CLK3_REQ_PEE1,
-};
-
-static const unsigned drive_cec_pins[] = {
- TEGRA_PIN_HDMI_CEC_PEE3,
-};
-
-static const unsigned drive_at6_pins[] = {
- TEGRA_PIN_PK1,
- TEGRA_PIN_PK3,
- TEGRA_PIN_PK4,
- TEGRA_PIN_PI2,
- TEGRA_PIN_PI5,
- TEGRA_PIN_PI6,
- TEGRA_PIN_PH4,
- TEGRA_PIN_PH5,
- TEGRA_PIN_PH6,
- TEGRA_PIN_PH7,
-};
-
-static const unsigned drive_dap5_pins[] = {
- TEGRA_PIN_SPDIF_IN_PK6,
- TEGRA_PIN_SPDIF_OUT_PK5,
- TEGRA_PIN_DP_HPD_PFF0,
-};
-
-static const unsigned drive_usb_vbus_en_pins[] = {
- TEGRA_PIN_USB_VBUS_EN0_PN4,
- TEGRA_PIN_USB_VBUS_EN1_PN5,
-};
-
-static const unsigned drive_ao3_pins[] = {
- TEGRA_PIN_RESET_OUT_N,
-};
-
-static const unsigned drive_ao0_pins[] = {
- TEGRA_PIN_JTAG_RTCK,
-};
-
-static const unsigned drive_hv0_pins[] = {
- TEGRA_PIN_HDMI_INT_PN7,
-};
-
-static const unsigned drive_sdio4_pins[] = {
- TEGRA_PIN_SDMMC1_WP_N_PV3,
-};
-
-static const unsigned drive_ao4_pins[] = {
- TEGRA_PIN_JTAG_RTCK,
-};
-
-static const unsigned mipi_pad_ctrl_dsi_b_pins[] = {
- TEGRA_PIN_DSI_B_CLK_P,
- TEGRA_PIN_DSI_B_CLK_N,
- TEGRA_PIN_DSI_B_D0_P,
- TEGRA_PIN_DSI_B_D0_N,
- TEGRA_PIN_DSI_B_D1_P,
- TEGRA_PIN_DSI_B_D1_N,
- TEGRA_PIN_DSI_B_D2_P,
- TEGRA_PIN_DSI_B_D2_N,
- TEGRA_PIN_DSI_B_D3_P,
- TEGRA_PIN_DSI_B_D3_N,
-};
-
-enum tegra_mux {
- TEGRA_MUX_BLINK,
- TEGRA_MUX_CCLA,
- TEGRA_MUX_CEC,
- TEGRA_MUX_CLDVFS,
- TEGRA_MUX_CLK,
- TEGRA_MUX_CLK12,
- TEGRA_MUX_CPU,
- TEGRA_MUX_CSI,
- TEGRA_MUX_DAP,
- TEGRA_MUX_DAP1,
- TEGRA_MUX_DAP2,
- TEGRA_MUX_DEV3,
- TEGRA_MUX_DISPLAYA,
- TEGRA_MUX_DISPLAYA_ALT,
- TEGRA_MUX_DISPLAYB,
- TEGRA_MUX_DP,
- TEGRA_MUX_DSI_B,
- TEGRA_MUX_DTV,
- TEGRA_MUX_EXTPERIPH1,
- TEGRA_MUX_EXTPERIPH2,
- TEGRA_MUX_EXTPERIPH3,
- TEGRA_MUX_GMI,
- TEGRA_MUX_GMI_ALT,
- TEGRA_MUX_HDA,
- TEGRA_MUX_HSI,
- TEGRA_MUX_I2C1,
- TEGRA_MUX_I2C2,
- TEGRA_MUX_I2C3,
- TEGRA_MUX_I2C4,
- TEGRA_MUX_I2CPWR,
- TEGRA_MUX_I2S0,
- TEGRA_MUX_I2S1,
- TEGRA_MUX_I2S2,
- TEGRA_MUX_I2S3,
- TEGRA_MUX_I2S4,
- TEGRA_MUX_IRDA,
- TEGRA_MUX_KBC,
- TEGRA_MUX_OWR,
- TEGRA_MUX_PE,
- TEGRA_MUX_PE0,
- TEGRA_MUX_PE1,
- TEGRA_MUX_PMI,
- TEGRA_MUX_PWM0,
- TEGRA_MUX_PWM1,
- TEGRA_MUX_PWM2,
- TEGRA_MUX_PWM3,
- TEGRA_MUX_PWRON,
- TEGRA_MUX_RESET_OUT_N,
- TEGRA_MUX_RSVD1,
- TEGRA_MUX_RSVD2,
- TEGRA_MUX_RSVD3,
- TEGRA_MUX_RSVD4,
- TEGRA_MUX_RTCK,
- TEGRA_MUX_SATA,
- TEGRA_MUX_SDMMC1,
- TEGRA_MUX_SDMMC2,
- TEGRA_MUX_SDMMC3,
- TEGRA_MUX_SDMMC4,
- TEGRA_MUX_SOC,
- TEGRA_MUX_SPDIF,
- TEGRA_MUX_SPI1,
- TEGRA_MUX_SPI2,
- TEGRA_MUX_SPI3,
- TEGRA_MUX_SPI4,
- TEGRA_MUX_SPI5,
- TEGRA_MUX_SPI6,
- TEGRA_MUX_SYS,
- TEGRA_MUX_TMDS,
- TEGRA_MUX_TRACE,
- TEGRA_MUX_UARTA,
- TEGRA_MUX_UARTB,
- TEGRA_MUX_UARTC,
- TEGRA_MUX_UARTD,
- TEGRA_MUX_ULPI,
- TEGRA_MUX_USB,
- TEGRA_MUX_VGP1,
- TEGRA_MUX_VGP2,
- TEGRA_MUX_VGP3,
- TEGRA_MUX_VGP4,
- TEGRA_MUX_VGP5,
- TEGRA_MUX_VGP6,
- TEGRA_MUX_VI,
- TEGRA_MUX_VI_ALT1,
- TEGRA_MUX_VI_ALT3,
- TEGRA_MUX_VIMCLK2,
- TEGRA_MUX_VIMCLK2_ALT,
-};
-
-#define FUNCTION(fname) \
- { \
- .name = #fname, \
- }
-
-static struct tegra_function tegra124_functions[] = {
- FUNCTION(blink),
- FUNCTION(ccla),
- FUNCTION(cec),
- FUNCTION(cldvfs),
- FUNCTION(clk),
- FUNCTION(clk12),
- FUNCTION(cpu),
- FUNCTION(csi),
- FUNCTION(dap),
- FUNCTION(dap1),
- FUNCTION(dap2),
- FUNCTION(dev3),
- FUNCTION(displaya),
- FUNCTION(displaya_alt),
- FUNCTION(displayb),
- FUNCTION(dp),
- FUNCTION(dsi_b),
- FUNCTION(dtv),
- FUNCTION(extperiph1),
- FUNCTION(extperiph2),
- FUNCTION(extperiph3),
- FUNCTION(gmi),
- FUNCTION(gmi_alt),
- FUNCTION(hda),
- FUNCTION(hsi),
- FUNCTION(i2c1),
- FUNCTION(i2c2),
- FUNCTION(i2c3),
- FUNCTION(i2c4),
- FUNCTION(i2cpwr),
- FUNCTION(i2s0),
- FUNCTION(i2s1),
- FUNCTION(i2s2),
- FUNCTION(i2s3),
- FUNCTION(i2s4),
- FUNCTION(irda),
- FUNCTION(kbc),
- FUNCTION(owr),
- FUNCTION(pe),
- FUNCTION(pe0),
- FUNCTION(pe1),
- FUNCTION(pmi),
- FUNCTION(pwm0),
- FUNCTION(pwm1),
- FUNCTION(pwm2),
- FUNCTION(pwm3),
- FUNCTION(pwron),
- FUNCTION(reset_out_n),
- FUNCTION(rsvd1),
- FUNCTION(rsvd2),
- FUNCTION(rsvd3),
- FUNCTION(rsvd4),
- FUNCTION(rtck),
- FUNCTION(sata),
- FUNCTION(sdmmc1),
- FUNCTION(sdmmc2),
- FUNCTION(sdmmc3),
- FUNCTION(sdmmc4),
- FUNCTION(soc),
- FUNCTION(spdif),
- FUNCTION(spi1),
- FUNCTION(spi2),
- FUNCTION(spi3),
- FUNCTION(spi4),
- FUNCTION(spi5),
- FUNCTION(spi6),
- FUNCTION(sys),
- FUNCTION(tmds),
- FUNCTION(trace),
- FUNCTION(uarta),
- FUNCTION(uartb),
- FUNCTION(uartc),
- FUNCTION(uartd),
- FUNCTION(ulpi),
- FUNCTION(usb),
- FUNCTION(vgp1),
- FUNCTION(vgp2),
- FUNCTION(vgp3),
- FUNCTION(vgp4),
- FUNCTION(vgp5),
- FUNCTION(vgp6),
- FUNCTION(vi),
- FUNCTION(vi_alt1),
- FUNCTION(vi_alt3),
- FUNCTION(vimclk2),
- FUNCTION(vimclk2_alt),
-};
-
-#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
-#define PINGROUP_REG_A 0x3000 /* bank 1 */
-#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
-
-#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
-#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
-#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
-
-#define PINGROUP_BIT_Y(b) (b)
-#define PINGROUP_BIT_N(b) (-1)
-
-#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \
- { \
- .name = #pg_name, \
- .pins = pg_name##_pins, \
- .npins = ARRAY_SIZE(pg_name##_pins), \
- .funcs = { \
- TEGRA_MUX_##f0, \
- TEGRA_MUX_##f1, \
- TEGRA_MUX_##f2, \
- TEGRA_MUX_##f3, \
- }, \
- .mux_reg = PINGROUP_REG(r), \
- .mux_bank = 1, \
- .mux_bit = 0, \
- .pupd_reg = PINGROUP_REG(r), \
- .pupd_bank = 1, \
- .pupd_bit = 2, \
- .tri_reg = PINGROUP_REG(r), \
- .tri_bank = 1, \
- .tri_bit = 4, \
- .einput_bit = 5, \
- .odrain_bit = PINGROUP_BIT_##od(6), \
- .lock_bit = 7, \
- .ioreset_bit = PINGROUP_BIT_##ior(8), \
- .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
- .drv_reg = -1, \
- }
-
-#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
- drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
- slwf_b, slwf_w, drvtype) \
- { \
- .name = "drive_" #pg_name, \
- .pins = drive_##pg_name##_pins, \
- .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
- .mux_reg = -1, \
- .pupd_reg = -1, \
- .tri_reg = -1, \
- .einput_bit = -1, \
- .odrain_bit = -1, \
- .lock_bit = -1, \
- .ioreset_bit = -1, \
- .rcv_sel_bit = -1, \
- .drv_reg = DRV_PINGROUP_REG(r), \
- .drv_bank = 0, \
- .hsm_bit = hsm_b, \
- .schmitt_bit = schmitt_b, \
- .lpmd_bit = lpmd_b, \
- .drvdn_bit = drvdn_b, \
- .drvdn_width = drvdn_w, \
- .drvup_bit = drvup_b, \
- .drvup_width = drvup_w, \
- .slwr_bit = slwr_b, \
- .slwr_width = slwr_w, \
- .slwf_bit = slwf_b, \
- .slwf_width = slwf_w, \
- .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
- }
-
-#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \
- { \
- .name = "mipi_pad_ctrl_" #pg_name, \
- .pins = mipi_pad_ctrl_##pg_name##_pins, \
- .npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins), \
- .funcs = { \
- TEGRA_MUX_ ## f0, \
- TEGRA_MUX_ ## f1, \
- TEGRA_MUX_RSVD3, \
- TEGRA_MUX_RSVD4, \
- }, \
- .mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r), \
- .mux_bank = 2, \
- .mux_bit = b, \
- .pupd_reg = -1, \
- .tri_reg = -1, \
- .einput_bit = -1, \
- .odrain_bit = -1, \
- .lock_bit = -1, \
- .ioreset_bit = -1, \
- .rcv_sel_bit = -1, \
- .drv_reg = -1, \
- }
-
-static const struct tegra_pingroup tegra124_groups[] = {
- /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
- PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
- PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N),
- PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N),
- PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N),
- PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N),
- PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N),
- PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N),
- PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N),
- PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N),
- PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N),
- PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N),
- PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N),
- PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N),
- PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N),
- PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, RSVD4, 0x3038, N, N, N),
- PINGROUP(dap3_sclk_pp3, I2S2, SPI5, RSVD3, DISPLAYB, 0x303c, N, N, N),
- PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N),
- PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N),
- PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N),
- PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N),
- PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N),
- PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N),
- PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N),
- PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N),
- PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N),
- PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N),
- PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y),
- PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y),
- PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y),
- PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N),
- PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N),
- PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, 0x316c, N, N, N),
- PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, 0x3170, N, N, N),
- PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, SPI4, 0x3174, N, N, N),
- PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, SPI4, 0x3178, N, N, N),
- PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, GMI, 0x317c, N, N, N),
- PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, GMI, 0x3180, N, N, N),
- PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, 0x3184, N, N, N),
- PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, 0x3188, N, N, N),
- PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, 0x318c, N, N, N),
- PINGROUP(pu3, PWM0, UARTA, GMI, DISPLAYB, 0x3190, N, N, N),
- PINGROUP(pu4, PWM1, UARTA, GMI, DISPLAYB, 0x3194, N, N, N),
- PINGROUP(pu5, PWM2, UARTA, GMI, DISPLAYB, 0x3198, N, N, N),
- PINGROUP(pu6, PWM3, UARTA, RSVD3, GMI, 0x319c, N, N, N),
- PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N),
- PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N),
- PINGROUP(dap4_fs_pp4, I2S3, GMI, DTV, RSVD4, 0x31a8, N, N, N),
- PINGROUP(dap4_din_pp5, I2S3, GMI, RSVD3, RSVD4, 0x31ac, N, N, N),
- PINGROUP(dap4_dout_pp6, I2S3, GMI, DTV, RSVD4, 0x31b0, N, N, N),
- PINGROUP(dap4_sclk_pp7, I2S3, GMI, RSVD3, RSVD4, 0x31b4, N, N, N),
- PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N),
- PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N),
- PINGROUP(pc7, RSVD1, RSVD2, GMI, GMI_ALT, 0x31c0, N, N, N),
- PINGROUP(pi5, SDMMC2, RSVD2, GMI, RSVD4, 0x31c4, N, N, N),
- PINGROUP(pi7, RSVD1, TRACE, GMI, DTV, 0x31c8, N, N, N),
- PINGROUP(pk0, RSVD1, SDMMC3, GMI, SOC, 0x31cc, N, N, N),
- PINGROUP(pk1, SDMMC2, TRACE, GMI, RSVD4, 0x31d0, N, N, N),
- PINGROUP(pj0, RSVD1, RSVD2, GMI, USB, 0x31d4, N, N, N),
- PINGROUP(pj2, RSVD1, RSVD2, GMI, SOC, 0x31d8, N, N, N),
- PINGROUP(pk3, SDMMC2, TRACE, GMI, CCLA, 0x31dc, N, N, N),
- PINGROUP(pk4, SDMMC2, RSVD2, GMI, GMI_ALT, 0x31e0, N, N, N),
- PINGROUP(pk2, RSVD1, RSVD2, GMI, RSVD4, 0x31e4, N, N, N),
- PINGROUP(pi3, RSVD1, RSVD2, GMI, SPI4, 0x31e8, N, N, N),
- PINGROUP(pi6, RSVD1, RSVD2, GMI, SDMMC2, 0x31ec, N, N, N),
- PINGROUP(pg0, RSVD1, RSVD2, GMI, RSVD4, 0x31f0, N, N, N),
- PINGROUP(pg1, RSVD1, RSVD2, GMI, RSVD4, 0x31f4, N, N, N),
- PINGROUP(pg2, RSVD1, TRACE, GMI, RSVD4, 0x31f8, N, N, N),
- PINGROUP(pg3, RSVD1, TRACE, GMI, RSVD4, 0x31fc, N, N, N),
- PINGROUP(pg4, RSVD1, TMDS, GMI, SPI4, 0x3200, N, N, N),
- PINGROUP(pg5, RSVD1, RSVD2, GMI, SPI4, 0x3204, N, N, N),
- PINGROUP(pg6, RSVD1, RSVD2, GMI, SPI4, 0x3208, N, N, N),
- PINGROUP(pg7, RSVD1, RSVD2, GMI, SPI4, 0x320c, N, N, N),
- PINGROUP(ph0, PWM0, TRACE, GMI, DTV, 0x3210, N, N, N),
- PINGROUP(ph1, PWM1, TMDS, GMI, DISPLAYA, 0x3214, N, N, N),
- PINGROUP(ph2, PWM2, TMDS, GMI, CLDVFS, 0x3218, N, N, N),
- PINGROUP(ph3, PWM3, SPI4, GMI, CLDVFS, 0x321c, N, N, N),
- PINGROUP(ph4, SDMMC2, RSVD2, GMI, RSVD4, 0x3220, N, N, N),
- PINGROUP(ph5, SDMMC2, RSVD2, GMI, RSVD4, 0x3224, N, N, N),
- PINGROUP(ph6, SDMMC2, TRACE, GMI, DTV, 0x3228, N, N, N),
- PINGROUP(ph7, SDMMC2, TRACE, GMI, DTV, 0x322c, N, N, N),
- PINGROUP(pj7, UARTD, RSVD2, GMI, GMI_ALT, 0x3230, N, N, N),
- PINGROUP(pb0, UARTD, RSVD2, GMI, RSVD4, 0x3234, N, N, N),
- PINGROUP(pb1, UARTD, RSVD2, GMI, RSVD4, 0x3238, N, N, N),
- PINGROUP(pk7, UARTD, RSVD2, GMI, RSVD4, 0x323c, N, N, N),
- PINGROUP(pi0, RSVD1, RSVD2, GMI, RSVD4, 0x3240, N, N, N),
- PINGROUP(pi1, RSVD1, RSVD2, GMI, RSVD4, 0x3244, N, N, N),
- PINGROUP(pi2, SDMMC2, TRACE, GMI, RSVD4, 0x3248, N, N, N),
- PINGROUP(pi4, SPI4, TRACE, GMI, DISPLAYA, 0x324c, N, N, N),
- PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N),
- PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N),
- PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N),
- PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N),
- PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N),
- PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N),
- PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N),
- PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N),
- PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N),
- PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, 0x3274, N, Y, N),
- PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N),
- PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N),
- PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, 0x3284, N, N, N),
- PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC2, 0x3288, N, N, N),
- PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, 0x328c, N, N, N),
- PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, 0x3290, Y, N, N),
- PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, 0x3294, Y, N, N),
- PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC2, 0x3298, N, N, N),
- PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC2, 0x329c, N, N, N),
- PINGROUP(pbb5, VGP5, DISPLAYA, RSVD3, SDMMC2, 0x32a0, N, N, N),
- PINGROUP(pbb6, I2S4, RSVD2, DISPLAYB, SDMMC2, 0x32a4, N, N, N),
- PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC2, 0x32a8, N, N, N),
- PINGROUP(pcc2, I2S4, RSVD2, SDMMC3, SDMMC2, 0x32ac, N, N, N),
- PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N),
- PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N),
- PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N),
- PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N),
- PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N),
- PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N),
- PINGROUP(kb_row3_pr3, KBC, DISPLAYA, SYS, DISPLAYB, 0x32c8, N, N, N),
- PINGROUP(kb_row4_pr4, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32cc, N, N, N),
- PINGROUP(kb_row5_pr5, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32d0, N, N, N),
- PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N),
- PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N),
- PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N),
- PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N),
- PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N),
- PINGROUP(kb_row11_ps3, KBC, RSVD2, RSVD3, IRDA, 0x32e8, N, N, N),
- PINGROUP(kb_row12_ps4, KBC, RSVD2, RSVD3, IRDA, 0x32ec, N, N, N),
- PINGROUP(kb_row13_ps5, KBC, RSVD2, SPI2, RSVD4, 0x32f0, N, N, N),
- PINGROUP(kb_row14_ps6, KBC, RSVD2, SPI2, RSVD4, 0x32f4, N, N, N),
- PINGROUP(kb_row15_ps7, KBC, SOC, RSVD3, RSVD4, 0x32f8, N, N, N),
- PINGROUP(kb_col0_pq0, KBC, RSVD2, SPI2, RSVD4, 0x32fc, N, N, N),
- PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, RSVD4, 0x3300, N, N, N),
- PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N),
- PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N),
- PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N),
- PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC3, RSVD4, 0x3310, N, N, N),
- PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, UARTD, 0x3314, N, N, N),
- PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, UARTD, 0x3318, N, N, N),
- PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N),
- PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N),
- PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N),
- PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N),
- PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N),
- PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y),
- PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N),
- PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N),
- PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SATA, 0x3340, N, N, N),
- PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N),
- PINGROUP(dap_mclk1_req_pee2, DAP, DAP1, SATA, RSVD4, 0x3348, N, N, N),
- PINGROUP(dap_mclk1_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N),
- PINGROUP(spdif_in_pk6, SPDIF, RSVD2, RSVD3, I2C3, 0x3350, N, N, N),
- PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, I2C3, 0x3354, N, N, N),
- PINGROUP(dap2_fs_pa2, I2S1, HDA, GMI, RSVD4, 0x3358, N, N, N),
- PINGROUP(dap2_din_pa4, I2S1, HDA, GMI, RSVD4, 0x335c, N, N, N),
- PINGROUP(dap2_dout_pa5, I2S1, HDA, GMI, RSVD4, 0x3360, N, N, N),
- PINGROUP(dap2_sclk_pa3, I2S1, HDA, GMI, RSVD4, 0x3364, N, N, N),
- PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, GMI, RSVD4, 0x3368, N, N, N),
- PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, GMI, RSVD4, 0x336c, N, N, N),
- PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, GMI, RSVD4, 0x3370, N, N, N),
- PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, GMI, RSVD4, 0x3374, N, N, N),
- PINGROUP(gpio_x4_aud_px4, GMI, SPI1, SPI2, DAP2, 0x3378, N, N, N),
- PINGROUP(gpio_x5_aud_px5, GMI, SPI1, SPI2, RSVD4, 0x337c, N, N, N),
- PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, GMI, 0x3380, N, N, N),
- PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N),
- PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N),
- PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N),
- PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N),
- PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N),
- PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N),
- PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N),
- PINGROUP(pex_l0_rst_n_pdd1, PE0, RSVD2, RSVD3, RSVD4, 0x33bc, N, N, N),
- PINGROUP(pex_l0_clkreq_n_pdd2, PE0, RSVD2, RSVD3, RSVD4, 0x33c0, N, N, N),
- PINGROUP(pex_wake_n_pdd3, PE, RSVD2, RSVD3, RSVD4, 0x33c4, N, N, N),
- PINGROUP(pex_l1_rst_n_pdd5, PE1, RSVD2, RSVD3, RSVD4, 0x33cc, N, N, N),
- PINGROUP(pex_l1_clkreq_n_pdd6, PE1, RSVD2, RSVD3, RSVD4, 0x33d0, N, N, N),
- PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, 0x33e0, Y, N, N),
- PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N),
- PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N),
- PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N),
- PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N),
- PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N),
- PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N),
- PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N),
- PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N),
- PINGROUP(gmi_clk_lb, SDMMC2, RSVD2, GMI, RSVD4, 0x3404, N, N, N),
- PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N),
- PINGROUP(kb_row16_pt0, KBC, RSVD2, RSVD3, UARTC, 0x340c, N, N, N),
- PINGROUP(kb_row17_pt1, KBC, RSVD2, RSVD3, UARTC, 0x3410, N, N, N),
- PINGROUP(usb_vbus_en2_pff1, USB, RSVD2, RSVD3, RSVD4, 0x3414, Y, N, N),
- PINGROUP(pff2, SATA, RSVD2, RSVD3, RSVD4, 0x3418, Y, N, N),
- PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, 0x3430, N, N, N),
-
- /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
- DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
- DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
- DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
- DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
- DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
- DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
- DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y),
- DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
- DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(ao3, 0x9a8, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
- DRV_PINGROUP(ao0, 0x9b0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
- DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
- DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
-
- /* pg_name, r, b, f0, f1 */
- MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B),
-};
-
-static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
- .ngpios = NUM_GPIOS,
- .pins = tegra124_pins,
- .npins = ARRAY_SIZE(tegra124_pins),
- .functions = tegra124_functions,
- .nfunctions = ARRAY_SIZE(tegra124_functions),
- .groups = tegra124_groups,
- .ngroups = ARRAY_SIZE(tegra124_groups),
- .hsm_in_mux = false,
- .schmitt_in_mux = false,
- .drvtype_in_mux = false,
-};
-
-static int tegra124_pinctrl_probe(struct platform_device *pdev)
-{
- return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
-}
-
-static const struct of_device_id tegra124_pinctrl_of_match[] = {
- { .compatible = "nvidia,tegra124-pinmux", },
- { },
-};
-MODULE_DEVICE_TABLE(of, tegra124_pinctrl_of_match);
-
-static struct platform_driver tegra124_pinctrl_driver = {
- .driver = {
- .name = "tegra124-pinctrl",
- .of_match_table = tegra124_pinctrl_of_match,
- },
- .probe = tegra124_pinctrl_probe,
- .remove = tegra_pinctrl_remove,
-};
-module_platform_driver(tegra124_pinctrl_driver);
-
-MODULE_AUTHOR("Ashwini Ghuge <aghuge@nvidia.com>");
-MODULE_DESCRIPTION("NVIDIA Tegra124 pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * Pinctrl data for the NVIDIA Tegra20 pinmux
- *
- * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
- *
- * Derived from code:
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2010 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-
-#include "pinctrl-tegra.h"
-
-/*
- * Most pins affected by the pinmux can also be GPIOs. Define these first.
- * These must match how the GPIO driver names/numbers its pins.
- */
-#define _GPIO(offset) (offset)
-
-#define TEGRA_PIN_VI_GP6_PA0 _GPIO(0)
-#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
-#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
-#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
-#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
-#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
-#define TEGRA_PIN_SDIO3_CLK_PA6 _GPIO(6)
-#define TEGRA_PIN_SDIO3_CMD_PA7 _GPIO(7)
-#define TEGRA_PIN_GMI_AD17_PB0 _GPIO(8)
-#define TEGRA_PIN_GMI_AD18_PB1 _GPIO(9)
-#define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10)
-#define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11)
-#define TEGRA_PIN_SDIO3_DAT3_PB4 _GPIO(12)
-#define TEGRA_PIN_SDIO3_DAT2_PB5 _GPIO(13)
-#define TEGRA_PIN_SDIO3_DAT1_PB6 _GPIO(14)
-#define TEGRA_PIN_SDIO3_DAT0_PB7 _GPIO(15)
-#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
-#define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17)
-#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
-#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
-#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
-#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
-#define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22)
-#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
-#define TEGRA_PIN_SDIO3_DAT5_PD0 _GPIO(24)
-#define TEGRA_PIN_SDIO3_DAT4_PD1 _GPIO(25)
-#define TEGRA_PIN_VI_GP5_PD2 _GPIO(26)
-#define TEGRA_PIN_SDIO3_DAT6_PD3 _GPIO(27)
-#define TEGRA_PIN_SDIO3_DAT7_PD4 _GPIO(28)
-#define TEGRA_PIN_VI_D1_PD5 _GPIO(29)
-#define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30)
-#define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31)
-#define TEGRA_PIN_LCD_D0_PE0 _GPIO(32)
-#define TEGRA_PIN_LCD_D1_PE1 _GPIO(33)
-#define TEGRA_PIN_LCD_D2_PE2 _GPIO(34)
-#define TEGRA_PIN_LCD_D3_PE3 _GPIO(35)
-#define TEGRA_PIN_LCD_D4_PE4 _GPIO(36)
-#define TEGRA_PIN_LCD_D5_PE5 _GPIO(37)
-#define TEGRA_PIN_LCD_D6_PE6 _GPIO(38)
-#define TEGRA_PIN_LCD_D7_PE7 _GPIO(39)
-#define TEGRA_PIN_LCD_D8_PF0 _GPIO(40)
-#define TEGRA_PIN_LCD_D9_PF1 _GPIO(41)
-#define TEGRA_PIN_LCD_D10_PF2 _GPIO(42)
-#define TEGRA_PIN_LCD_D11_PF3 _GPIO(43)
-#define TEGRA_PIN_LCD_D12_PF4 _GPIO(44)
-#define TEGRA_PIN_LCD_D13_PF5 _GPIO(45)
-#define TEGRA_PIN_LCD_D14_PF6 _GPIO(46)
-#define TEGRA_PIN_LCD_D15_PF7 _GPIO(47)
-#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
-#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
-#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
-#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
-#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
-#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
-#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
-#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
-#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
-#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
-#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
-#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
-#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
-#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
-#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
-#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
-#define TEGRA_PIN_GMI_HIOW_N_PI0 _GPIO(64)
-#define TEGRA_PIN_GMI_HIOR_N_PI1 _GPIO(65)
-#define TEGRA_PIN_GMI_CS5_N_PI2 _GPIO(66)
-#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
-#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
-#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
-#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
-#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
-#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
-#define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73)
-#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
-#define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75)
-#define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76)
-#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
-#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
-#define TEGRA_PIN_GMI_AD16_PJ7 _GPIO(79)
-#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
-#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
-#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
-#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
-#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
-#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
-#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
-#define TEGRA_PIN_GMI_AD19_PK7 _GPIO(87)
-#define TEGRA_PIN_VI_D2_PL0 _GPIO(88)
-#define TEGRA_PIN_VI_D3_PL1 _GPIO(89)
-#define TEGRA_PIN_VI_D4_PL2 _GPIO(90)
-#define TEGRA_PIN_VI_D5_PL3 _GPIO(91)
-#define TEGRA_PIN_VI_D6_PL4 _GPIO(92)
-#define TEGRA_PIN_VI_D7_PL5 _GPIO(93)
-#define TEGRA_PIN_VI_D8_PL6 _GPIO(94)
-#define TEGRA_PIN_VI_D9_PL7 _GPIO(95)
-#define TEGRA_PIN_LCD_D16_PM0 _GPIO(96)
-#define TEGRA_PIN_LCD_D17_PM1 _GPIO(97)
-#define TEGRA_PIN_LCD_D18_PM2 _GPIO(98)
-#define TEGRA_PIN_LCD_D19_PM3 _GPIO(99)
-#define TEGRA_PIN_LCD_D20_PM4 _GPIO(100)
-#define TEGRA_PIN_LCD_D21_PM5 _GPIO(101)
-#define TEGRA_PIN_LCD_D22_PM6 _GPIO(102)
-#define TEGRA_PIN_LCD_D23_PM7 _GPIO(103)
-#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
-#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
-#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
-#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
-#define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108)
-#define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109)
-#define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110)
-#define TEGRA_PIN_HDMI_INT_N_PN7 _GPIO(111)
-#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
-#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
-#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
-#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
-#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
-#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
-#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
-#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
-#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
-#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
-#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
-#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
-#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
-#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
-#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
-#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
-#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
-#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
-#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
-#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
-#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
-#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
-#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
-#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
-#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
-#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
-#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
-#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
-#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
-#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
-#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
-#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
-#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
-#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
-#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
-#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
-#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
-#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
-#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
-#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
-#define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152)
-#define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153)
-#define TEGRA_PIN_VI_D10_PT2 _GPIO(154)
-#define TEGRA_PIN_VI_D11_PT3 _GPIO(155)
-#define TEGRA_PIN_VI_D0_PT4 _GPIO(156)
-#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
-#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
-#define TEGRA_PIN_GMI_DPD_PT7 _GPIO(159)
-#define TEGRA_PIN_PU0 _GPIO(160)
-#define TEGRA_PIN_PU1 _GPIO(161)
-#define TEGRA_PIN_PU2 _GPIO(162)
-#define TEGRA_PIN_PU3 _GPIO(163)
-#define TEGRA_PIN_PU4 _GPIO(164)
-#define TEGRA_PIN_PU5 _GPIO(165)
-#define TEGRA_PIN_PU6 _GPIO(166)
-#define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167)
-#define TEGRA_PIN_PV0 _GPIO(168)
-#define TEGRA_PIN_PV1 _GPIO(169)
-#define TEGRA_PIN_PV2 _GPIO(170)
-#define TEGRA_PIN_PV3 _GPIO(171)
-#define TEGRA_PIN_PV4 _GPIO(172)
-#define TEGRA_PIN_PV5 _GPIO(173)
-#define TEGRA_PIN_PV6 _GPIO(174)
-#define TEGRA_PIN_LCD_DC1_PV7 _GPIO(175)
-#define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176)
-#define TEGRA_PIN_LCD_M1_PW1 _GPIO(177)
-#define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178)
-#define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179)
-#define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
-#define TEGRA_PIN_DAP_MCLK2_PW5 _GPIO(181)
-#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
-#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
-#define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184)
-#define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185)
-#define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186)
-#define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187)
-#define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188)
-#define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189)
-#define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190)
-#define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191)
-#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
-#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
-#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
-#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
-#define TEGRA_PIN_SDIO1_DAT3_PY4 _GPIO(196)
-#define TEGRA_PIN_SDIO1_DAT2_PY5 _GPIO(197)
-#define TEGRA_PIN_SDIO1_DAT1_PY6 _GPIO(198)
-#define TEGRA_PIN_SDIO1_DAT0_PY7 _GPIO(199)
-#define TEGRA_PIN_SDIO1_CLK_PZ0 _GPIO(200)
-#define TEGRA_PIN_SDIO1_CMD_PZ1 _GPIO(201)
-#define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202)
-#define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203)
-#define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204)
-#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
-#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
-#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
-#define TEGRA_PIN_GMI_AD20_PAA0 _GPIO(208)
-#define TEGRA_PIN_GMI_AD21_PAA1 _GPIO(209)
-#define TEGRA_PIN_GMI_AD22_PAA2 _GPIO(210)
-#define TEGRA_PIN_GMI_AD23_PAA3 _GPIO(211)
-#define TEGRA_PIN_GMI_AD24_PAA4 _GPIO(212)
-#define TEGRA_PIN_GMI_AD25_PAA5 _GPIO(213)
-#define TEGRA_PIN_GMI_AD26_PAA6 _GPIO(214)
-#define TEGRA_PIN_GMI_AD27_PAA7 _GPIO(215)
-#define TEGRA_PIN_LED_BLINK_PBB0 _GPIO(216)
-#define TEGRA_PIN_VI_GP0_PBB1 _GPIO(217)
-#define TEGRA_PIN_CAM_I2C_SCL_PBB2 _GPIO(218)
-#define TEGRA_PIN_CAM_I2C_SDA_PBB3 _GPIO(219)
-#define TEGRA_PIN_VI_GP3_PBB4 _GPIO(220)
-#define TEGRA_PIN_VI_GP4_PBB5 _GPIO(221)
-#define TEGRA_PIN_PBB6 _GPIO(222)
-#define TEGRA_PIN_PBB7 _GPIO(223)
-
-/* All non-GPIO pins follow */
-#define NUM_GPIOS (TEGRA_PIN_PBB7 + 1)
-#define _PIN(offset) (NUM_GPIOS + (offset))
-
-#define TEGRA_PIN_CRT_HSYNC _PIN(30)
-#define TEGRA_PIN_CRT_VSYNC _PIN(31)
-#define TEGRA_PIN_DDC_SCL _PIN(32)
-#define TEGRA_PIN_DDC_SDA _PIN(33)
-#define TEGRA_PIN_OWC _PIN(34)
-#define TEGRA_PIN_CORE_PWR_REQ _PIN(35)
-#define TEGRA_PIN_CPU_PWR_REQ _PIN(36)
-#define TEGRA_PIN_PWR_INT_N _PIN(37)
-#define TEGRA_PIN_CLK_32_K_IN _PIN(38)
-#define TEGRA_PIN_DDR_COMP_PD _PIN(39)
-#define TEGRA_PIN_DDR_COMP_PU _PIN(40)
-#define TEGRA_PIN_DDR_A0 _PIN(41)
-#define TEGRA_PIN_DDR_A1 _PIN(42)
-#define TEGRA_PIN_DDR_A2 _PIN(43)
-#define TEGRA_PIN_DDR_A3 _PIN(44)
-#define TEGRA_PIN_DDR_A4 _PIN(45)
-#define TEGRA_PIN_DDR_A5 _PIN(46)
-#define TEGRA_PIN_DDR_A6 _PIN(47)
-#define TEGRA_PIN_DDR_A7 _PIN(48)
-#define TEGRA_PIN_DDR_A8 _PIN(49)
-#define TEGRA_PIN_DDR_A9 _PIN(50)
-#define TEGRA_PIN_DDR_A10 _PIN(51)
-#define TEGRA_PIN_DDR_A11 _PIN(52)
-#define TEGRA_PIN_DDR_A12 _PIN(53)
-#define TEGRA_PIN_DDR_A13 _PIN(54)
-#define TEGRA_PIN_DDR_A14 _PIN(55)
-#define TEGRA_PIN_DDR_CAS_N _PIN(56)
-#define TEGRA_PIN_DDR_BA0 _PIN(57)
-#define TEGRA_PIN_DDR_BA1 _PIN(58)
-#define TEGRA_PIN_DDR_BA2 _PIN(59)
-#define TEGRA_PIN_DDR_DQS0P _PIN(60)
-#define TEGRA_PIN_DDR_DQS0N _PIN(61)
-#define TEGRA_PIN_DDR_DQS1P _PIN(62)
-#define TEGRA_PIN_DDR_DQS1N _PIN(63)
-#define TEGRA_PIN_DDR_DQS2P _PIN(64)
-#define TEGRA_PIN_DDR_DQS2N _PIN(65)
-#define TEGRA_PIN_DDR_DQS3P _PIN(66)
-#define TEGRA_PIN_DDR_DQS3N _PIN(67)
-#define TEGRA_PIN_DDR_CKE0 _PIN(68)
-#define TEGRA_PIN_DDR_CKE1 _PIN(69)
-#define TEGRA_PIN_DDR_CLK _PIN(70)
-#define TEGRA_PIN_DDR_CLK_N _PIN(71)
-#define TEGRA_PIN_DDR_DM0 _PIN(72)
-#define TEGRA_PIN_DDR_DM1 _PIN(73)
-#define TEGRA_PIN_DDR_DM2 _PIN(74)
-#define TEGRA_PIN_DDR_DM3 _PIN(75)
-#define TEGRA_PIN_DDR_ODT _PIN(76)
-#define TEGRA_PIN_DDR_QUSE0 _PIN(77)
-#define TEGRA_PIN_DDR_QUSE1 _PIN(78)
-#define TEGRA_PIN_DDR_QUSE2 _PIN(79)
-#define TEGRA_PIN_DDR_QUSE3 _PIN(80)
-#define TEGRA_PIN_DDR_RAS_N _PIN(81)
-#define TEGRA_PIN_DDR_WE_N _PIN(82)
-#define TEGRA_PIN_DDR_DQ0 _PIN(83)
-#define TEGRA_PIN_DDR_DQ1 _PIN(84)
-#define TEGRA_PIN_DDR_DQ2 _PIN(85)
-#define TEGRA_PIN_DDR_DQ3 _PIN(86)
-#define TEGRA_PIN_DDR_DQ4 _PIN(87)
-#define TEGRA_PIN_DDR_DQ5 _PIN(88)
-#define TEGRA_PIN_DDR_DQ6 _PIN(89)
-#define TEGRA_PIN_DDR_DQ7 _PIN(90)
-#define TEGRA_PIN_DDR_DQ8 _PIN(91)
-#define TEGRA_PIN_DDR_DQ9 _PIN(92)
-#define TEGRA_PIN_DDR_DQ10 _PIN(93)
-#define TEGRA_PIN_DDR_DQ11 _PIN(94)
-#define TEGRA_PIN_DDR_DQ12 _PIN(95)
-#define TEGRA_PIN_DDR_DQ13 _PIN(96)
-#define TEGRA_PIN_DDR_DQ14 _PIN(97)
-#define TEGRA_PIN_DDR_DQ15 _PIN(98)
-#define TEGRA_PIN_DDR_DQ16 _PIN(99)
-#define TEGRA_PIN_DDR_DQ17 _PIN(100)
-#define TEGRA_PIN_DDR_DQ18 _PIN(101)
-#define TEGRA_PIN_DDR_DQ19 _PIN(102)
-#define TEGRA_PIN_DDR_DQ20 _PIN(103)
-#define TEGRA_PIN_DDR_DQ21 _PIN(104)
-#define TEGRA_PIN_DDR_DQ22 _PIN(105)
-#define TEGRA_PIN_DDR_DQ23 _PIN(106)
-#define TEGRA_PIN_DDR_DQ24 _PIN(107)
-#define TEGRA_PIN_DDR_DQ25 _PIN(108)
-#define TEGRA_PIN_DDR_DQ26 _PIN(109)
-#define TEGRA_PIN_DDR_DQ27 _PIN(110)
-#define TEGRA_PIN_DDR_DQ28 _PIN(111)
-#define TEGRA_PIN_DDR_DQ29 _PIN(112)
-#define TEGRA_PIN_DDR_DQ30 _PIN(113)
-#define TEGRA_PIN_DDR_DQ31 _PIN(114)
-#define TEGRA_PIN_DDR_CS0_N _PIN(115)
-#define TEGRA_PIN_DDR_CS1_N _PIN(116)
-#define TEGRA_PIN_SYS_RESET _PIN(117)
-#define TEGRA_PIN_JTAG_TRST_N _PIN(118)
-#define TEGRA_PIN_JTAG_TDO _PIN(119)
-#define TEGRA_PIN_JTAG_TMS _PIN(120)
-#define TEGRA_PIN_JTAG_TCK _PIN(121)
-#define TEGRA_PIN_JTAG_TDI _PIN(122)
-#define TEGRA_PIN_TEST_MODE_EN _PIN(123)
-
-static const struct pinctrl_pin_desc tegra20_pins[] = {
- PINCTRL_PIN(TEGRA_PIN_VI_GP6_PA0, "VI_GP6 PA0"),
- PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
- PINCTRL_PIN(TEGRA_PIN_SDIO3_CLK_PA6, "SDIO3_CLK PA6"),
- PINCTRL_PIN(TEGRA_PIN_SDIO3_CMD_PA7, "SDIO3_CMD PA7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD17_PB0, "GMI_AD17 PB0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD18_PB1, "GMI_AD18 PB1"),
- PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
- PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
- PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT3_PB4, "SDIO3_DAT3 PB4"),
- PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT2_PB5, "SDIO3_DAT2 PB5"),
- PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT1_PB6, "SDIO3_DAT1 PB6"),
- PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT0_PB7, "SDIO3_DAT0 PB7"),
- PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
- PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
- PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
- PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
- PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
- PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
- PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
- PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT5_PD0, "SDIO3_DAT5 PD0"),
- PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT4_PD1, "SDIO3_DAT4 PD1"),
- PINCTRL_PIN(TEGRA_PIN_VI_GP5_PD2, "VI_GP5 PD2"),
- PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT6_PD3, "SDIO3_DAT6 PD3"),
- PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT7_PD4, "SDIO3_DAT7 PD4"),
- PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
- PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
- PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_HIOW_N_PI0, "GMI_HIOW_N PI0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_HIOR_N_PI1, "GMI_HIOR_N PI1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS5_N_PI2, "GMI_CS5_N PI2"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
- PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
- PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
- PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
- PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
- PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
- PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD16_PJ7, "GMI_AD16 PJ7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
- PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
- PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD19_PK7, "GMI_AD19 PK7"),
- PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
- PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
- PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
- PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
- PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
- PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
- PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
- PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
- PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
- PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
- PINCTRL_PIN(TEGRA_PIN_HDMI_INT_N_PN7, "HDMI_INT_N PN7"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
- PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
- PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
- PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VD_D10 PT2"),
- PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
- PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
- PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
- PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_DPD_PT7, "GMI_DPD PT7"),
- /* PU0..6: GPIO only */
- PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
- PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
- PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
- PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
- PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
- PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
- PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
- /* PV0..1: GPIO only */
- PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
- PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
- /* PV2..3: Balls are named after GPIO not function */
- PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
- PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
- /* PV4..6: GPIO only */
- PINCTRL_PIN(TEGRA_PIN_PV4, "PV4"),
- PINCTRL_PIN(TEGRA_PIN_PV5, "PV5"),
- PINCTRL_PIN(TEGRA_PIN_PV6, "PV6"),
- PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PV7, "LCD_DC1 PV7"),
- PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
- PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
- PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
- PINCTRL_PIN(TEGRA_PIN_DAP_MCLK2_PW5, "DAP_MCLK2 PW5"),
- PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
- PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
- PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
- PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
- PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
- PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
- PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT3_PY4, "SDIO1_DAT3 PY4"),
- PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT2_PY5, "SDIO1_DAT2 PY5"),
- PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT1_PY6, "SDIO1_DAT1 PY6"),
- PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT0_PY7, "SDIO1_DAT0 PY7"),
- PINCTRL_PIN(TEGRA_PIN_SDIO1_CLK_PZ0, "SDIO1_CLK PZ0"),
- PINCTRL_PIN(TEGRA_PIN_SDIO1_CMD_PZ1, "SDIO1_CMD PZ1"),
- PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
- PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
- PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
- PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
- PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD20_PAA0, "GMI_AD20 PAA0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD21_PAA1, "GMI_AD21 PAA1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD22_PAA2, "GMI_AD22 PAA2"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD23_PAA3, "GMI_AD23 PAA3"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD24_PAA4, "GMI_AD24 PAA4"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD25_PAA5, "GMI_AD25 PAA5"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD26_PAA6, "GMI_AD26 PAA6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD27_PAA7, "GMI_AD27 PAA7"),
- PINCTRL_PIN(TEGRA_PIN_LED_BLINK_PBB0, "LED_BLINK PBB0"),
- PINCTRL_PIN(TEGRA_PIN_VI_GP0_PBB1, "VI_GP0 PBB1"),
- PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB2, "CAM_I2C_SCL PBB2"),
- PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB3, "CAM_I2C_SDA PBB3"),
- PINCTRL_PIN(TEGRA_PIN_VI_GP3_PBB4, "VI_GP3 PBB4"),
- PINCTRL_PIN(TEGRA_PIN_VI_GP4_PBB5, "VI_GP4 PBB5"),
- PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
- PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
- PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC, "CRT_HSYNC"),
- PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC, "CRT_VSYNC"),
- PINCTRL_PIN(TEGRA_PIN_DDC_SCL, "DDC_SCL"),
- PINCTRL_PIN(TEGRA_PIN_DDC_SDA, "DDC_SDA"),
- PINCTRL_PIN(TEGRA_PIN_OWC, "OWC"),
- PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
- PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
- PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
- PINCTRL_PIN(TEGRA_PIN_CLK_32_K_IN, "CLK_32_K_IN"),
- PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PD, "DDR_COMP_PD"),
- PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PU, "DDR_COMP_PU"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A0, "DDR_A0"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A1, "DDR_A1"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A2, "DDR_A2"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A3, "DDR_A3"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A4, "DDR_A4"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A5, "DDR_A5"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A6, "DDR_A6"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A7, "DDR_A7"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A8, "DDR_A8"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A9, "DDR_A9"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A10, "DDR_A10"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A11, "DDR_A11"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A12, "DDR_A12"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A13, "DDR_A13"),
- PINCTRL_PIN(TEGRA_PIN_DDR_A14, "DDR_A14"),
- PINCTRL_PIN(TEGRA_PIN_DDR_CAS_N, "DDR_CAS_N"),
- PINCTRL_PIN(TEGRA_PIN_DDR_BA0, "DDR_BA0"),
- PINCTRL_PIN(TEGRA_PIN_DDR_BA1, "DDR_BA1"),
- PINCTRL_PIN(TEGRA_PIN_DDR_BA2, "DDR_BA2"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQS0P, "DDR_DQS0P"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQS0N, "DDR_DQS0N"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQS1P, "DDR_DQS1P"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQS1N, "DDR_DQS1N"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQS2P, "DDR_DQS2P"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQS2N, "DDR_DQS2N"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQS3P, "DDR_DQS3P"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQS3N, "DDR_DQS3N"),
- PINCTRL_PIN(TEGRA_PIN_DDR_CKE0, "DDR_CKE0"),
- PINCTRL_PIN(TEGRA_PIN_DDR_CKE1, "DDR_CKE1"),
- PINCTRL_PIN(TEGRA_PIN_DDR_CLK, "DDR_CLK"),
- PINCTRL_PIN(TEGRA_PIN_DDR_CLK_N, "DDR_CLK_N"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DM0, "DDR_DM0"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DM1, "DDR_DM1"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DM2, "DDR_DM2"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DM3, "DDR_DM3"),
- PINCTRL_PIN(TEGRA_PIN_DDR_ODT, "DDR_ODT"),
- PINCTRL_PIN(TEGRA_PIN_DDR_QUSE0, "DDR_QUSE0"),
- PINCTRL_PIN(TEGRA_PIN_DDR_QUSE1, "DDR_QUSE1"),
- PINCTRL_PIN(TEGRA_PIN_DDR_QUSE2, "DDR_QUSE2"),
- PINCTRL_PIN(TEGRA_PIN_DDR_QUSE3, "DDR_QUSE3"),
- PINCTRL_PIN(TEGRA_PIN_DDR_RAS_N, "DDR_RAS_N"),
- PINCTRL_PIN(TEGRA_PIN_DDR_WE_N, "DDR_WE_N"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ0, "DDR_DQ0"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ1, "DDR_DQ1"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ2, "DDR_DQ2"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ3, "DDR_DQ3"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ4, "DDR_DQ4"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ5, "DDR_DQ5"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ6, "DDR_DQ6"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ7, "DDR_DQ7"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ8, "DDR_DQ8"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ9, "DDR_DQ9"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ10, "DDR_DQ10"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ11, "DDR_DQ11"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ12, "DDR_DQ12"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ13, "DDR_DQ13"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ14, "DDR_DQ14"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ15, "DDR_DQ15"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ16, "DDR_DQ16"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ17, "DDR_DQ17"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ18, "DDR_DQ18"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ19, "DDR_DQ19"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ20, "DDR_DQ20"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ21, "DDR_DQ21"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ22, "DDR_DQ22"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ23, "DDR_DQ23"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ24, "DDR_DQ24"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ25, "DDR_DQ25"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ26, "DDR_DQ26"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ27, "DDR_DQ27"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ28, "DDR_DQ28"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ29, "DDR_DQ29"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ30, "DDR_DQ30"),
- PINCTRL_PIN(TEGRA_PIN_DDR_DQ31, "DDR_DQ31"),
- PINCTRL_PIN(TEGRA_PIN_DDR_CS0_N, "DDR_CS0_N"),
- PINCTRL_PIN(TEGRA_PIN_DDR_CS1_N, "DDR_CS1_N"),
- PINCTRL_PIN(TEGRA_PIN_SYS_RESET, "SYS_RESET"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
- PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
-};
-
-static const unsigned ata_pins[] = {
- TEGRA_PIN_GMI_CS6_N_PI3,
- TEGRA_PIN_GMI_CS7_N_PI6,
- TEGRA_PIN_GMI_RST_N_PI4,
-};
-
-static const unsigned atb_pins[] = {
- TEGRA_PIN_GMI_CS5_N_PI2,
- TEGRA_PIN_GMI_DPD_PT7,
-};
-
-static const unsigned atc_pins[] = {
- TEGRA_PIN_GMI_IORDY_PI5,
- TEGRA_PIN_GMI_WAIT_PI7,
- TEGRA_PIN_GMI_ADV_N_PK0,
- TEGRA_PIN_GMI_CLK_PK1,
- TEGRA_PIN_GMI_CS2_N_PK3,
- TEGRA_PIN_GMI_CS3_N_PK4,
- TEGRA_PIN_GMI_CS4_N_PK2,
- TEGRA_PIN_GMI_AD0_PG0,
- TEGRA_PIN_GMI_AD1_PG1,
- TEGRA_PIN_GMI_AD2_PG2,
- TEGRA_PIN_GMI_AD3_PG3,
- TEGRA_PIN_GMI_AD4_PG4,
- TEGRA_PIN_GMI_AD5_PG5,
- TEGRA_PIN_GMI_AD6_PG6,
- TEGRA_PIN_GMI_AD7_PG7,
- TEGRA_PIN_GMI_HIOW_N_PI0,
- TEGRA_PIN_GMI_HIOR_N_PI1,
-};
-
-static const unsigned atd_pins[] = {
- TEGRA_PIN_GMI_AD8_PH0,
- TEGRA_PIN_GMI_AD9_PH1,
- TEGRA_PIN_GMI_AD10_PH2,
- TEGRA_PIN_GMI_AD11_PH3,
-};
-
-static const unsigned ate_pins[] = {
- TEGRA_PIN_GMI_AD12_PH4,
- TEGRA_PIN_GMI_AD13_PH5,
- TEGRA_PIN_GMI_AD14_PH6,
- TEGRA_PIN_GMI_AD15_PH7,
-};
-
-static const unsigned cdev1_pins[] = {
- TEGRA_PIN_DAP_MCLK1_PW4,
-};
-
-static const unsigned cdev2_pins[] = {
- TEGRA_PIN_DAP_MCLK2_PW5,
-};
-
-static const unsigned crtp_pins[] = {
- TEGRA_PIN_CRT_HSYNC,
- TEGRA_PIN_CRT_VSYNC,
-};
-
-static const unsigned csus_pins[] = {
- TEGRA_PIN_VI_MCLK_PT1,
-};
-
-static const unsigned dap1_pins[] = {
- TEGRA_PIN_DAP1_FS_PN0,
- TEGRA_PIN_DAP1_DIN_PN1,
- TEGRA_PIN_DAP1_DOUT_PN2,
- TEGRA_PIN_DAP1_SCLK_PN3,
-};
-
-static const unsigned dap2_pins[] = {
- TEGRA_PIN_DAP2_FS_PA2,
- TEGRA_PIN_DAP2_SCLK_PA3,
- TEGRA_PIN_DAP2_DIN_PA4,
- TEGRA_PIN_DAP2_DOUT_PA5,
-};
-
-static const unsigned dap3_pins[] = {
- TEGRA_PIN_DAP3_FS_PP0,
- TEGRA_PIN_DAP3_DIN_PP1,
- TEGRA_PIN_DAP3_DOUT_PP2,
- TEGRA_PIN_DAP3_SCLK_PP3,
-};
-
-static const unsigned dap4_pins[] = {
- TEGRA_PIN_DAP4_FS_PP4,
- TEGRA_PIN_DAP4_DIN_PP5,
- TEGRA_PIN_DAP4_DOUT_PP6,
- TEGRA_PIN_DAP4_SCLK_PP7,
-};
-
-static const unsigned ddc_pins[] = {
- TEGRA_PIN_DDC_SCL,
- TEGRA_PIN_DDC_SDA,
-};
-
-static const unsigned dta_pins[] = {
- TEGRA_PIN_VI_D0_PT4,
- TEGRA_PIN_VI_D1_PD5,
-};
-
-static const unsigned dtb_pins[] = {
- TEGRA_PIN_VI_D10_PT2,
- TEGRA_PIN_VI_D11_PT3,
-};
-
-static const unsigned dtc_pins[] = {
- TEGRA_PIN_VI_HSYNC_PD7,
- TEGRA_PIN_VI_VSYNC_PD6,
-};
-
-static const unsigned dtd_pins[] = {
- TEGRA_PIN_VI_PCLK_PT0,
- TEGRA_PIN_VI_D2_PL0,
- TEGRA_PIN_VI_D3_PL1,
- TEGRA_PIN_VI_D4_PL2,
- TEGRA_PIN_VI_D5_PL3,
- TEGRA_PIN_VI_D6_PL4,
- TEGRA_PIN_VI_D7_PL5,
- TEGRA_PIN_VI_D8_PL6,
- TEGRA_PIN_VI_D9_PL7,
-};
-
-static const unsigned dte_pins[] = {
- TEGRA_PIN_VI_GP0_PBB1,
- TEGRA_PIN_VI_GP3_PBB4,
- TEGRA_PIN_VI_GP4_PBB5,
- TEGRA_PIN_VI_GP5_PD2,
- TEGRA_PIN_VI_GP6_PA0,
-};
-
-static const unsigned dtf_pins[] = {
- TEGRA_PIN_CAM_I2C_SCL_PBB2,
- TEGRA_PIN_CAM_I2C_SDA_PBB3,
-};
-
-static const unsigned gma_pins[] = {
- TEGRA_PIN_GMI_AD20_PAA0,
- TEGRA_PIN_GMI_AD21_PAA1,
- TEGRA_PIN_GMI_AD22_PAA2,
- TEGRA_PIN_GMI_AD23_PAA3,
-};
-
-static const unsigned gmb_pins[] = {
- TEGRA_PIN_GMI_WP_N_PC7,
-};
-
-static const unsigned gmc_pins[] = {
- TEGRA_PIN_GMI_AD16_PJ7,
- TEGRA_PIN_GMI_AD17_PB0,
- TEGRA_PIN_GMI_AD18_PB1,
- TEGRA_PIN_GMI_AD19_PK7,
-};
-
-static const unsigned gmd_pins[] = {
- TEGRA_PIN_GMI_CS0_N_PJ0,
- TEGRA_PIN_GMI_CS1_N_PJ2,
-};
-
-static const unsigned gme_pins[] = {
- TEGRA_PIN_GMI_AD24_PAA4,
- TEGRA_PIN_GMI_AD25_PAA5,
- TEGRA_PIN_GMI_AD26_PAA6,
- TEGRA_PIN_GMI_AD27_PAA7,
-};
-
-static const unsigned gpu_pins[] = {
- TEGRA_PIN_PU0,
- TEGRA_PIN_PU1,
- TEGRA_PIN_PU2,
- TEGRA_PIN_PU3,
- TEGRA_PIN_PU4,
- TEGRA_PIN_PU5,
- TEGRA_PIN_PU6,
-};
-
-static const unsigned gpu7_pins[] = {
- TEGRA_PIN_JTAG_RTCK_PU7,
-};
-
-static const unsigned gpv_pins[] = {
- TEGRA_PIN_PV4,
- TEGRA_PIN_PV5,
- TEGRA_PIN_PV6,
-};
-
-static const unsigned hdint_pins[] = {
- TEGRA_PIN_HDMI_INT_N_PN7,
-};
-
-static const unsigned i2cp_pins[] = {
- TEGRA_PIN_PWR_I2C_SCL_PZ6,
- TEGRA_PIN_PWR_I2C_SDA_PZ7,
-};
-
-static const unsigned irrx_pins[] = {
- TEGRA_PIN_UART2_RTS_N_PJ6,
-};
-
-static const unsigned irtx_pins[] = {
- TEGRA_PIN_UART2_CTS_N_PJ5,
-};
-
-static const unsigned kbca_pins[] = {
- TEGRA_PIN_KB_ROW0_PR0,
- TEGRA_PIN_KB_ROW1_PR1,
- TEGRA_PIN_KB_ROW2_PR2,
-};
-
-static const unsigned kbcb_pins[] = {
- TEGRA_PIN_KB_ROW7_PR7,
- TEGRA_PIN_KB_ROW8_PS0,
- TEGRA_PIN_KB_ROW9_PS1,
- TEGRA_PIN_KB_ROW10_PS2,
- TEGRA_PIN_KB_ROW11_PS3,
- TEGRA_PIN_KB_ROW12_PS4,
- TEGRA_PIN_KB_ROW13_PS5,
- TEGRA_PIN_KB_ROW14_PS6,
- TEGRA_PIN_KB_ROW15_PS7,
-};
-
-static const unsigned kbcc_pins[] = {
- TEGRA_PIN_KB_COL0_PQ0,
- TEGRA_PIN_KB_COL1_PQ1,
-};
-
-static const unsigned kbcd_pins[] = {
- TEGRA_PIN_KB_ROW3_PR3,
- TEGRA_PIN_KB_ROW4_PR4,
- TEGRA_PIN_KB_ROW5_PR5,
- TEGRA_PIN_KB_ROW6_PR6,
-};
-
-static const unsigned kbce_pins[] = {
- TEGRA_PIN_KB_COL7_PQ7,
-};
-
-static const unsigned kbcf_pins[] = {
- TEGRA_PIN_KB_COL2_PQ2,
- TEGRA_PIN_KB_COL3_PQ3,
- TEGRA_PIN_KB_COL4_PQ4,
- TEGRA_PIN_KB_COL5_PQ5,
- TEGRA_PIN_KB_COL6_PQ6,
-};
-
-static const unsigned lcsn_pins[] = {
- TEGRA_PIN_LCD_CS0_N_PN4,
-};
-
-static const unsigned ld0_pins[] = {
- TEGRA_PIN_LCD_D0_PE0,
-};
-
-static const unsigned ld1_pins[] = {
- TEGRA_PIN_LCD_D1_PE1,
-};
-
-static const unsigned ld2_pins[] = {
- TEGRA_PIN_LCD_D2_PE2,
-};
-
-static const unsigned ld3_pins[] = {
- TEGRA_PIN_LCD_D3_PE3,
-};
-
-static const unsigned ld4_pins[] = {
- TEGRA_PIN_LCD_D4_PE4,
-};
-
-static const unsigned ld5_pins[] = {
- TEGRA_PIN_LCD_D5_PE5,
-};
-
-static const unsigned ld6_pins[] = {
- TEGRA_PIN_LCD_D6_PE6,
-};
-
-static const unsigned ld7_pins[] = {
- TEGRA_PIN_LCD_D7_PE7,
-};
-
-static const unsigned ld8_pins[] = {
- TEGRA_PIN_LCD_D8_PF0,
-};
-
-static const unsigned ld9_pins[] = {
- TEGRA_PIN_LCD_D9_PF1,
-};
-
-static const unsigned ld10_pins[] = {
- TEGRA_PIN_LCD_D10_PF2,
-};
-
-static const unsigned ld11_pins[] = {
- TEGRA_PIN_LCD_D11_PF3,
-};
-
-static const unsigned ld12_pins[] = {
- TEGRA_PIN_LCD_D12_PF4,
-};
-
-static const unsigned ld13_pins[] = {
- TEGRA_PIN_LCD_D13_PF5,
-};
-
-static const unsigned ld14_pins[] = {
- TEGRA_PIN_LCD_D14_PF6,
-};
-
-static const unsigned ld15_pins[] = {
- TEGRA_PIN_LCD_D15_PF7,
-};
-
-static const unsigned ld16_pins[] = {
- TEGRA_PIN_LCD_D16_PM0,
-};
-
-static const unsigned ld17_pins[] = {
- TEGRA_PIN_LCD_D17_PM1,
-};
-
-static const unsigned ldc_pins[] = {
- TEGRA_PIN_LCD_DC0_PN6,
-};
-
-static const unsigned ldi_pins[] = {
- TEGRA_PIN_LCD_D22_PM6,
-};
-
-static const unsigned lhp0_pins[] = {
- TEGRA_PIN_LCD_D21_PM5,
-};
-
-static const unsigned lhp1_pins[] = {
- TEGRA_PIN_LCD_D18_PM2,
-};
-
-static const unsigned lhp2_pins[] = {
- TEGRA_PIN_LCD_D19_PM3,
-};
-
-static const unsigned lhs_pins[] = {
- TEGRA_PIN_LCD_HSYNC_PJ3,
-};
-
-static const unsigned lm0_pins[] = {
- TEGRA_PIN_LCD_CS1_N_PW0,
-};
-
-static const unsigned lm1_pins[] = {
- TEGRA_PIN_LCD_M1_PW1,
-};
-
-static const unsigned lpp_pins[] = {
- TEGRA_PIN_LCD_D23_PM7,
-};
-
-static const unsigned lpw0_pins[] = {
- TEGRA_PIN_LCD_PWR0_PB2,
-};
-
-static const unsigned lpw1_pins[] = {
- TEGRA_PIN_LCD_PWR1_PC1,
-};
-
-static const unsigned lpw2_pins[] = {
- TEGRA_PIN_LCD_PWR2_PC6,
-};
-
-static const unsigned lsc0_pins[] = {
- TEGRA_PIN_LCD_PCLK_PB3,
-};
-
-static const unsigned lsc1_pins[] = {
- TEGRA_PIN_LCD_WR_N_PZ3,
-};
-
-static const unsigned lsck_pins[] = {
- TEGRA_PIN_LCD_SCK_PZ4,
-};
-
-static const unsigned lsda_pins[] = {
- TEGRA_PIN_LCD_SDOUT_PN5,
-};
-
-static const unsigned lsdi_pins[] = {
- TEGRA_PIN_LCD_SDIN_PZ2,
-};
-
-static const unsigned lspi_pins[] = {
- TEGRA_PIN_LCD_DE_PJ1,
-};
-
-static const unsigned lvp0_pins[] = {
- TEGRA_PIN_LCD_DC1_PV7,
-};
-
-static const unsigned lvp1_pins[] = {
- TEGRA_PIN_LCD_D20_PM4,
-};
-
-static const unsigned lvs_pins[] = {
- TEGRA_PIN_LCD_VSYNC_PJ4,
-};
-
-static const unsigned ls_pins[] = {
- TEGRA_PIN_LCD_PWR0_PB2,
- TEGRA_PIN_LCD_PWR1_PC1,
- TEGRA_PIN_LCD_PWR2_PC6,
- TEGRA_PIN_LCD_SDIN_PZ2,
- TEGRA_PIN_LCD_SDOUT_PN5,
- TEGRA_PIN_LCD_WR_N_PZ3,
- TEGRA_PIN_LCD_CS0_N_PN4,
- TEGRA_PIN_LCD_DC0_PN6,
- TEGRA_PIN_LCD_SCK_PZ4,
-};
-
-static const unsigned lc_pins[] = {
- TEGRA_PIN_LCD_PCLK_PB3,
- TEGRA_PIN_LCD_DE_PJ1,
- TEGRA_PIN_LCD_HSYNC_PJ3,
- TEGRA_PIN_LCD_VSYNC_PJ4,
- TEGRA_PIN_LCD_CS1_N_PW0,
- TEGRA_PIN_LCD_M1_PW1,
- TEGRA_PIN_LCD_DC1_PV7,
- TEGRA_PIN_HDMI_INT_N_PN7,
-};
-
-static const unsigned ld17_0_pins[] = {
- TEGRA_PIN_LCD_D0_PE0,
- TEGRA_PIN_LCD_D1_PE1,
- TEGRA_PIN_LCD_D2_PE2,
- TEGRA_PIN_LCD_D3_PE3,
- TEGRA_PIN_LCD_D4_PE4,
- TEGRA_PIN_LCD_D5_PE5,
- TEGRA_PIN_LCD_D6_PE6,
- TEGRA_PIN_LCD_D7_PE7,
- TEGRA_PIN_LCD_D8_PF0,
- TEGRA_PIN_LCD_D9_PF1,
- TEGRA_PIN_LCD_D10_PF2,
- TEGRA_PIN_LCD_D11_PF3,
- TEGRA_PIN_LCD_D12_PF4,
- TEGRA_PIN_LCD_D13_PF5,
- TEGRA_PIN_LCD_D14_PF6,
- TEGRA_PIN_LCD_D15_PF7,
- TEGRA_PIN_LCD_D16_PM0,
- TEGRA_PIN_LCD_D17_PM1,
-};
-
-static const unsigned ld19_18_pins[] = {
- TEGRA_PIN_LCD_D18_PM2,
- TEGRA_PIN_LCD_D19_PM3,
-};
-
-static const unsigned ld21_20_pins[] = {
- TEGRA_PIN_LCD_D20_PM4,
- TEGRA_PIN_LCD_D21_PM5,
-};
-
-static const unsigned ld23_22_pins[] = {
- TEGRA_PIN_LCD_D22_PM6,
- TEGRA_PIN_LCD_D23_PM7,
-};
-
-static const unsigned owc_pins[] = {
- TEGRA_PIN_OWC,
-};
-
-static const unsigned pmc_pins[] = {
- TEGRA_PIN_LED_BLINK_PBB0,
- TEGRA_PIN_SYS_CLK_REQ_PZ5,
- TEGRA_PIN_CORE_PWR_REQ,
- TEGRA_PIN_CPU_PWR_REQ,
- TEGRA_PIN_PWR_INT_N,
-};
-
-static const unsigned pta_pins[] = {
- TEGRA_PIN_GEN2_I2C_SCL_PT5,
- TEGRA_PIN_GEN2_I2C_SDA_PT6,
-};
-
-static const unsigned rm_pins[] = {
- TEGRA_PIN_GEN1_I2C_SCL_PC4,
- TEGRA_PIN_GEN1_I2C_SDA_PC5,
-};
-
-static const unsigned sdb_pins[] = {
- TEGRA_PIN_SDIO3_CMD_PA7,
-};
-
-static const unsigned sdc_pins[] = {
- TEGRA_PIN_SDIO3_DAT0_PB7,
- TEGRA_PIN_SDIO3_DAT1_PB6,
- TEGRA_PIN_SDIO3_DAT2_PB5,
- TEGRA_PIN_SDIO3_DAT3_PB4,
-};
-
-static const unsigned sdd_pins[] = {
- TEGRA_PIN_SDIO3_CLK_PA6,
-};
-
-static const unsigned sdio1_pins[] = {
- TEGRA_PIN_SDIO1_CLK_PZ0,
- TEGRA_PIN_SDIO1_CMD_PZ1,
- TEGRA_PIN_SDIO1_DAT0_PY7,
- TEGRA_PIN_SDIO1_DAT1_PY6,
- TEGRA_PIN_SDIO1_DAT2_PY5,
- TEGRA_PIN_SDIO1_DAT3_PY4,
-};
-
-static const unsigned slxa_pins[] = {
- TEGRA_PIN_SDIO3_DAT4_PD1,
-};
-
-static const unsigned slxc_pins[] = {
- TEGRA_PIN_SDIO3_DAT6_PD3,
-};
-
-static const unsigned slxd_pins[] = {
- TEGRA_PIN_SDIO3_DAT7_PD4,
-};
-
-static const unsigned slxk_pins[] = {
- TEGRA_PIN_SDIO3_DAT5_PD0,
-};
-
-static const unsigned spdi_pins[] = {
- TEGRA_PIN_SPDIF_IN_PK6,
-};
-
-static const unsigned spdo_pins[] = {
- TEGRA_PIN_SPDIF_OUT_PK5,
-};
-
-static const unsigned spia_pins[] = {
- TEGRA_PIN_SPI2_MOSI_PX0,
-};
-
-static const unsigned spib_pins[] = {
- TEGRA_PIN_SPI2_MISO_PX1,
-};
-
-static const unsigned spic_pins[] = {
- TEGRA_PIN_SPI2_CS0_N_PX3,
- TEGRA_PIN_SPI2_SCK_PX2,
-};
-
-static const unsigned spid_pins[] = {
- TEGRA_PIN_SPI1_MOSI_PX4,
-};
-
-static const unsigned spie_pins[] = {
- TEGRA_PIN_SPI1_CS0_N_PX6,
- TEGRA_PIN_SPI1_SCK_PX5,
-};
-
-static const unsigned spif_pins[] = {
- TEGRA_PIN_SPI1_MISO_PX7,
-};
-
-static const unsigned spig_pins[] = {
- TEGRA_PIN_SPI2_CS1_N_PW2,
-};
-
-static const unsigned spih_pins[] = {
- TEGRA_PIN_SPI2_CS2_N_PW3,
-};
-
-static const unsigned uaa_pins[] = {
- TEGRA_PIN_ULPI_DATA0_PO1,
- TEGRA_PIN_ULPI_DATA1_PO2,
- TEGRA_PIN_ULPI_DATA2_PO3,
- TEGRA_PIN_ULPI_DATA3_PO4,
-};
-
-static const unsigned uab_pins[] = {
- TEGRA_PIN_ULPI_DATA4_PO5,
- TEGRA_PIN_ULPI_DATA5_PO6,
- TEGRA_PIN_ULPI_DATA6_PO7,
- TEGRA_PIN_ULPI_DATA7_PO0,
-};
-
-static const unsigned uac_pins[] = {
- TEGRA_PIN_PV0,
- TEGRA_PIN_PV1,
- TEGRA_PIN_PV2,
- TEGRA_PIN_PV3,
-};
-
-static const unsigned ck32_pins[] = {
- TEGRA_PIN_CLK_32_K_IN,
-};
-
-static const unsigned uad_pins[] = {
- TEGRA_PIN_UART2_RXD_PC3,
- TEGRA_PIN_UART2_TXD_PC2,
-};
-
-static const unsigned uca_pins[] = {
- TEGRA_PIN_UART3_RXD_PW7,
- TEGRA_PIN_UART3_TXD_PW6,
-};
-
-static const unsigned ucb_pins[] = {
- TEGRA_PIN_UART3_CTS_N_PA1,
- TEGRA_PIN_UART3_RTS_N_PC0,
-};
-
-static const unsigned uda_pins[] = {
- TEGRA_PIN_ULPI_CLK_PY0,
- TEGRA_PIN_ULPI_DIR_PY1,
- TEGRA_PIN_ULPI_NXT_PY2,
- TEGRA_PIN_ULPI_STP_PY3,
-};
-
-static const unsigned ddrc_pins[] = {
- TEGRA_PIN_DDR_COMP_PD,
- TEGRA_PIN_DDR_COMP_PU,
-};
-
-static const unsigned pmca_pins[] = {
- TEGRA_PIN_LED_BLINK_PBB0,
-};
-
-static const unsigned pmcb_pins[] = {
- TEGRA_PIN_SYS_CLK_REQ_PZ5,
-};
-
-static const unsigned pmcc_pins[] = {
- TEGRA_PIN_CORE_PWR_REQ,
-};
-
-static const unsigned pmcd_pins[] = {
- TEGRA_PIN_CPU_PWR_REQ,
-};
-
-static const unsigned pmce_pins[] = {
- TEGRA_PIN_PWR_INT_N,
-};
-
-static const unsigned xm2c_pins[] = {
- TEGRA_PIN_DDR_A0,
- TEGRA_PIN_DDR_A1,
- TEGRA_PIN_DDR_A2,
- TEGRA_PIN_DDR_A3,
- TEGRA_PIN_DDR_A4,
- TEGRA_PIN_DDR_A5,
- TEGRA_PIN_DDR_A6,
- TEGRA_PIN_DDR_A7,
- TEGRA_PIN_DDR_A8,
- TEGRA_PIN_DDR_A9,
- TEGRA_PIN_DDR_A10,
- TEGRA_PIN_DDR_A11,
- TEGRA_PIN_DDR_A12,
- TEGRA_PIN_DDR_A13,
- TEGRA_PIN_DDR_A14,
- TEGRA_PIN_DDR_CAS_N,
- TEGRA_PIN_DDR_BA0,
- TEGRA_PIN_DDR_BA1,
- TEGRA_PIN_DDR_BA2,
- TEGRA_PIN_DDR_DQS0P,
- TEGRA_PIN_DDR_DQS0N,
- TEGRA_PIN_DDR_DQS1P,
- TEGRA_PIN_DDR_DQS1N,
- TEGRA_PIN_DDR_DQS2P,
- TEGRA_PIN_DDR_DQS2N,
- TEGRA_PIN_DDR_DQS3P,
- TEGRA_PIN_DDR_DQS3N,
- TEGRA_PIN_DDR_CS0_N,
- TEGRA_PIN_DDR_CS1_N,
- TEGRA_PIN_DDR_CKE0,
- TEGRA_PIN_DDR_CKE1,
- TEGRA_PIN_DDR_CLK,
- TEGRA_PIN_DDR_CLK_N,
- TEGRA_PIN_DDR_DM0,
- TEGRA_PIN_DDR_DM1,
- TEGRA_PIN_DDR_DM2,
- TEGRA_PIN_DDR_DM3,
- TEGRA_PIN_DDR_ODT,
- TEGRA_PIN_DDR_RAS_N,
- TEGRA_PIN_DDR_WE_N,
- TEGRA_PIN_DDR_QUSE0,
- TEGRA_PIN_DDR_QUSE1,
- TEGRA_PIN_DDR_QUSE2,
- TEGRA_PIN_DDR_QUSE3,
-};
-
-static const unsigned xm2d_pins[] = {
- TEGRA_PIN_DDR_DQ0,
- TEGRA_PIN_DDR_DQ1,
- TEGRA_PIN_DDR_DQ2,
- TEGRA_PIN_DDR_DQ3,
- TEGRA_PIN_DDR_DQ4,
- TEGRA_PIN_DDR_DQ5,
- TEGRA_PIN_DDR_DQ6,
- TEGRA_PIN_DDR_DQ7,
- TEGRA_PIN_DDR_DQ8,
- TEGRA_PIN_DDR_DQ9,
- TEGRA_PIN_DDR_DQ10,
- TEGRA_PIN_DDR_DQ11,
- TEGRA_PIN_DDR_DQ12,
- TEGRA_PIN_DDR_DQ13,
- TEGRA_PIN_DDR_DQ14,
- TEGRA_PIN_DDR_DQ15,
- TEGRA_PIN_DDR_DQ16,
- TEGRA_PIN_DDR_DQ17,
- TEGRA_PIN_DDR_DQ18,
- TEGRA_PIN_DDR_DQ19,
- TEGRA_PIN_DDR_DQ20,
- TEGRA_PIN_DDR_DQ21,
- TEGRA_PIN_DDR_DQ22,
- TEGRA_PIN_DDR_DQ23,
- TEGRA_PIN_DDR_DQ24,
- TEGRA_PIN_DDR_DQ25,
- TEGRA_PIN_DDR_DQ26,
- TEGRA_PIN_DDR_DQ27,
- TEGRA_PIN_DDR_DQ28,
- TEGRA_PIN_DDR_DQ29,
- TEGRA_PIN_DDR_DQ30,
- TEGRA_PIN_DDR_DQ31,
-};
-
-static const unsigned drive_ao1_pins[] = {
- TEGRA_PIN_SYS_RESET,
- TEGRA_PIN_PWR_I2C_SCL_PZ6,
- TEGRA_PIN_PWR_I2C_SDA_PZ7,
- TEGRA_PIN_KB_ROW0_PR0,
- TEGRA_PIN_KB_ROW1_PR1,
- TEGRA_PIN_KB_ROW2_PR2,
- TEGRA_PIN_KB_ROW3_PR3,
- TEGRA_PIN_KB_ROW4_PR4,
- TEGRA_PIN_KB_ROW5_PR5,
- TEGRA_PIN_KB_ROW6_PR6,
- TEGRA_PIN_KB_ROW7_PR7,
-};
-
-static const unsigned drive_ao2_pins[] = {
- TEGRA_PIN_KB_ROW8_PS0,
- TEGRA_PIN_KB_ROW9_PS1,
- TEGRA_PIN_KB_ROW10_PS2,
- TEGRA_PIN_KB_ROW11_PS3,
- TEGRA_PIN_KB_ROW12_PS4,
- TEGRA_PIN_KB_ROW13_PS5,
- TEGRA_PIN_KB_ROW14_PS6,
- TEGRA_PIN_KB_ROW15_PS7,
- TEGRA_PIN_KB_COL0_PQ0,
- TEGRA_PIN_KB_COL1_PQ1,
- TEGRA_PIN_KB_COL2_PQ2,
- TEGRA_PIN_KB_COL3_PQ3,
- TEGRA_PIN_KB_COL4_PQ4,
- TEGRA_PIN_KB_COL5_PQ5,
- TEGRA_PIN_KB_COL6_PQ6,
- TEGRA_PIN_KB_COL7_PQ7,
- TEGRA_PIN_LED_BLINK_PBB0,
- TEGRA_PIN_SYS_CLK_REQ_PZ5,
- TEGRA_PIN_CORE_PWR_REQ,
- TEGRA_PIN_CPU_PWR_REQ,
- TEGRA_PIN_PWR_INT_N,
- TEGRA_PIN_CLK_32_K_IN,
-};
-
-static const unsigned drive_at1_pins[] = {
- TEGRA_PIN_GMI_IORDY_PI5,
- TEGRA_PIN_GMI_AD8_PH0,
- TEGRA_PIN_GMI_AD9_PH1,
- TEGRA_PIN_GMI_AD10_PH2,
- TEGRA_PIN_GMI_AD11_PH3,
- TEGRA_PIN_GMI_AD12_PH4,
- TEGRA_PIN_GMI_AD13_PH5,
- TEGRA_PIN_GMI_AD14_PH6,
- TEGRA_PIN_GMI_AD15_PH7,
- TEGRA_PIN_GMI_CS7_N_PI6,
- TEGRA_PIN_GMI_DPD_PT7,
- TEGRA_PIN_GEN2_I2C_SCL_PT5,
- TEGRA_PIN_GEN2_I2C_SDA_PT6,
-};
-
-static const unsigned drive_at2_pins[] = {
- TEGRA_PIN_GMI_WAIT_PI7,
- TEGRA_PIN_GMI_ADV_N_PK0,
- TEGRA_PIN_GMI_CLK_PK1,
- TEGRA_PIN_GMI_CS6_N_PI3,
- TEGRA_PIN_GMI_CS5_N_PI2,
- TEGRA_PIN_GMI_CS4_N_PK2,
- TEGRA_PIN_GMI_CS3_N_PK4,
- TEGRA_PIN_GMI_CS2_N_PK3,
- TEGRA_PIN_GMI_AD0_PG0,
- TEGRA_PIN_GMI_AD1_PG1,
- TEGRA_PIN_GMI_AD2_PG2,
- TEGRA_PIN_GMI_AD3_PG3,
- TEGRA_PIN_GMI_AD4_PG4,
- TEGRA_PIN_GMI_AD5_PG5,
- TEGRA_PIN_GMI_AD6_PG6,
- TEGRA_PIN_GMI_AD7_PG7,
- TEGRA_PIN_GMI_HIOW_N_PI0,
- TEGRA_PIN_GMI_HIOR_N_PI1,
- TEGRA_PIN_GMI_RST_N_PI4,
-};
-
-static const unsigned drive_cdev1_pins[] = {
- TEGRA_PIN_DAP_MCLK1_PW4,
-};
-
-static const unsigned drive_cdev2_pins[] = {
- TEGRA_PIN_DAP_MCLK2_PW5,
-};
-
-static const unsigned drive_csus_pins[] = {
- TEGRA_PIN_VI_MCLK_PT1,
-};
-
-static const unsigned drive_dap1_pins[] = {
- TEGRA_PIN_DAP1_FS_PN0,
- TEGRA_PIN_DAP1_DIN_PN1,
- TEGRA_PIN_DAP1_DOUT_PN2,
- TEGRA_PIN_DAP1_SCLK_PN3,
- TEGRA_PIN_SPDIF_OUT_PK5,
- TEGRA_PIN_SPDIF_IN_PK6,
-};
-
-static const unsigned drive_dap2_pins[] = {
- TEGRA_PIN_DAP2_FS_PA2,
- TEGRA_PIN_DAP2_SCLK_PA3,
- TEGRA_PIN_DAP2_DIN_PA4,
- TEGRA_PIN_DAP2_DOUT_PA5,
-};
-
-static const unsigned drive_dap3_pins[] = {
- TEGRA_PIN_DAP3_FS_PP0,
- TEGRA_PIN_DAP3_DIN_PP1,
- TEGRA_PIN_DAP3_DOUT_PP2,
- TEGRA_PIN_DAP3_SCLK_PP3,
-};
-
-static const unsigned drive_dap4_pins[] = {
- TEGRA_PIN_DAP4_FS_PP4,
- TEGRA_PIN_DAP4_DIN_PP5,
- TEGRA_PIN_DAP4_DOUT_PP6,
- TEGRA_PIN_DAP4_SCLK_PP7,
-};
-
-static const unsigned drive_dbg_pins[] = {
- TEGRA_PIN_PU0,
- TEGRA_PIN_PU1,
- TEGRA_PIN_PU2,
- TEGRA_PIN_PU3,
- TEGRA_PIN_PU4,
- TEGRA_PIN_PU5,
- TEGRA_PIN_PU6,
- TEGRA_PIN_JTAG_RTCK_PU7,
- TEGRA_PIN_GEN1_I2C_SDA_PC5,
- TEGRA_PIN_GEN1_I2C_SCL_PC4,
- TEGRA_PIN_JTAG_TRST_N,
- TEGRA_PIN_JTAG_TDO,
- TEGRA_PIN_JTAG_TMS,
- TEGRA_PIN_JTAG_TCK,
- TEGRA_PIN_JTAG_TDI,
- TEGRA_PIN_TEST_MODE_EN,
-};
-
-static const unsigned drive_lcd1_pins[] = {
- TEGRA_PIN_LCD_PWR1_PC1,
- TEGRA_PIN_LCD_PWR2_PC6,
- TEGRA_PIN_LCD_SDIN_PZ2,
- TEGRA_PIN_LCD_SDOUT_PN5,
- TEGRA_PIN_LCD_WR_N_PZ3,
- TEGRA_PIN_LCD_CS0_N_PN4,
- TEGRA_PIN_LCD_DC0_PN6,
- TEGRA_PIN_LCD_SCK_PZ4,
-};
-
-static const unsigned drive_lcd2_pins[] = {
- TEGRA_PIN_LCD_PWR0_PB2,
- TEGRA_PIN_LCD_PCLK_PB3,
- TEGRA_PIN_LCD_DE_PJ1,
- TEGRA_PIN_LCD_HSYNC_PJ3,
- TEGRA_PIN_LCD_VSYNC_PJ4,
- TEGRA_PIN_LCD_D0_PE0,
- TEGRA_PIN_LCD_D1_PE1,
- TEGRA_PIN_LCD_D2_PE2,
- TEGRA_PIN_LCD_D3_PE3,
- TEGRA_PIN_LCD_D4_PE4,
- TEGRA_PIN_LCD_D5_PE5,
- TEGRA_PIN_LCD_D6_PE6,
- TEGRA_PIN_LCD_D7_PE7,
- TEGRA_PIN_LCD_D8_PF0,
- TEGRA_PIN_LCD_D9_PF1,
- TEGRA_PIN_LCD_D10_PF2,
- TEGRA_PIN_LCD_D11_PF3,
- TEGRA_PIN_LCD_D12_PF4,
- TEGRA_PIN_LCD_D13_PF5,
- TEGRA_PIN_LCD_D14_PF6,
- TEGRA_PIN_LCD_D15_PF7,
- TEGRA_PIN_LCD_D16_PM0,
- TEGRA_PIN_LCD_D17_PM1,
- TEGRA_PIN_LCD_D18_PM2,
- TEGRA_PIN_LCD_D19_PM3,
- TEGRA_PIN_LCD_D20_PM4,
- TEGRA_PIN_LCD_D21_PM5,
- TEGRA_PIN_LCD_D22_PM6,
- TEGRA_PIN_LCD_D23_PM7,
- TEGRA_PIN_LCD_CS1_N_PW0,
- TEGRA_PIN_LCD_M1_PW1,
- TEGRA_PIN_LCD_DC1_PV7,
- TEGRA_PIN_HDMI_INT_N_PN7,
-};
-
-static const unsigned drive_sdmmc2_pins[] = {
- TEGRA_PIN_SDIO3_DAT4_PD1,
- TEGRA_PIN_SDIO3_DAT5_PD0,
- TEGRA_PIN_SDIO3_DAT6_PD3,
- TEGRA_PIN_SDIO3_DAT7_PD4,
-};
-
-static const unsigned drive_sdmmc3_pins[] = {
- TEGRA_PIN_SDIO3_CLK_PA6,
- TEGRA_PIN_SDIO3_CMD_PA7,
- TEGRA_PIN_SDIO3_DAT0_PB7,
- TEGRA_PIN_SDIO3_DAT1_PB6,
- TEGRA_PIN_SDIO3_DAT2_PB5,
- TEGRA_PIN_SDIO3_DAT3_PB4,
- TEGRA_PIN_PV4,
- TEGRA_PIN_PV5,
- TEGRA_PIN_PV6,
-};
-
-static const unsigned drive_spi_pins[] = {
- TEGRA_PIN_SPI2_MOSI_PX0,
- TEGRA_PIN_SPI2_MISO_PX1,
- TEGRA_PIN_SPI2_SCK_PX2,
- TEGRA_PIN_SPI2_CS0_N_PX3,
- TEGRA_PIN_SPI1_MOSI_PX4,
- TEGRA_PIN_SPI1_SCK_PX5,
- TEGRA_PIN_SPI1_CS0_N_PX6,
- TEGRA_PIN_SPI1_MISO_PX7,
- TEGRA_PIN_SPI2_CS1_N_PW2,
- TEGRA_PIN_SPI2_CS2_N_PW3,
-};
-
-static const unsigned drive_uaa_pins[] = {
- TEGRA_PIN_ULPI_DATA0_PO1,
- TEGRA_PIN_ULPI_DATA1_PO2,
- TEGRA_PIN_ULPI_DATA2_PO3,
- TEGRA_PIN_ULPI_DATA3_PO4,
-};
-
-static const unsigned drive_uab_pins[] = {
- TEGRA_PIN_ULPI_DATA4_PO5,
- TEGRA_PIN_ULPI_DATA5_PO6,
- TEGRA_PIN_ULPI_DATA6_PO7,
- TEGRA_PIN_ULPI_DATA7_PO0,
- TEGRA_PIN_PV0,
- TEGRA_PIN_PV1,
- TEGRA_PIN_PV2,
- TEGRA_PIN_PV3,
-};
-
-static const unsigned drive_uart2_pins[] = {
- TEGRA_PIN_UART2_TXD_PC2,
- TEGRA_PIN_UART2_RXD_PC3,
- TEGRA_PIN_UART2_RTS_N_PJ6,
- TEGRA_PIN_UART2_CTS_N_PJ5,
-};
-
-static const unsigned drive_uart3_pins[] = {
- TEGRA_PIN_UART3_TXD_PW6,
- TEGRA_PIN_UART3_RXD_PW7,
- TEGRA_PIN_UART3_RTS_N_PC0,
- TEGRA_PIN_UART3_CTS_N_PA1,
-};
-
-static const unsigned drive_vi1_pins[] = {
- TEGRA_PIN_VI_D0_PT4,
- TEGRA_PIN_VI_D1_PD5,
- TEGRA_PIN_VI_D2_PL0,
- TEGRA_PIN_VI_D3_PL1,
- TEGRA_PIN_VI_D4_PL2,
- TEGRA_PIN_VI_D5_PL3,
- TEGRA_PIN_VI_D6_PL4,
- TEGRA_PIN_VI_D7_PL5,
- TEGRA_PIN_VI_D8_PL6,
- TEGRA_PIN_VI_D9_PL7,
- TEGRA_PIN_VI_D10_PT2,
- TEGRA_PIN_VI_D11_PT3,
- TEGRA_PIN_VI_PCLK_PT0,
- TEGRA_PIN_VI_VSYNC_PD6,
- TEGRA_PIN_VI_HSYNC_PD7,
-};
-
-static const unsigned drive_vi2_pins[] = {
- TEGRA_PIN_VI_GP0_PBB1,
- TEGRA_PIN_CAM_I2C_SCL_PBB2,
- TEGRA_PIN_CAM_I2C_SDA_PBB3,
- TEGRA_PIN_VI_GP3_PBB4,
- TEGRA_PIN_VI_GP4_PBB5,
- TEGRA_PIN_VI_GP5_PD2,
- TEGRA_PIN_VI_GP6_PA0,
-};
-
-static const unsigned drive_xm2a_pins[] = {
- TEGRA_PIN_DDR_A0,
- TEGRA_PIN_DDR_A1,
- TEGRA_PIN_DDR_A2,
- TEGRA_PIN_DDR_A3,
- TEGRA_PIN_DDR_A4,
- TEGRA_PIN_DDR_A5,
- TEGRA_PIN_DDR_A6,
- TEGRA_PIN_DDR_A7,
- TEGRA_PIN_DDR_A8,
- TEGRA_PIN_DDR_A9,
- TEGRA_PIN_DDR_A10,
- TEGRA_PIN_DDR_A11,
- TEGRA_PIN_DDR_A12,
- TEGRA_PIN_DDR_A13,
- TEGRA_PIN_DDR_A14,
- TEGRA_PIN_DDR_BA0,
- TEGRA_PIN_DDR_BA1,
- TEGRA_PIN_DDR_BA2,
- TEGRA_PIN_DDR_CS0_N,
- TEGRA_PIN_DDR_CS1_N,
- TEGRA_PIN_DDR_ODT,
- TEGRA_PIN_DDR_RAS_N,
- TEGRA_PIN_DDR_CAS_N,
- TEGRA_PIN_DDR_WE_N,
- TEGRA_PIN_DDR_CKE0,
- TEGRA_PIN_DDR_CKE1,
-};
-
-static const unsigned drive_xm2c_pins[] = {
- TEGRA_PIN_DDR_DQS0P,
- TEGRA_PIN_DDR_DQS0N,
- TEGRA_PIN_DDR_DQS1P,
- TEGRA_PIN_DDR_DQS1N,
- TEGRA_PIN_DDR_DQS2P,
- TEGRA_PIN_DDR_DQS2N,
- TEGRA_PIN_DDR_DQS3P,
- TEGRA_PIN_DDR_DQS3N,
- TEGRA_PIN_DDR_QUSE0,
- TEGRA_PIN_DDR_QUSE1,
- TEGRA_PIN_DDR_QUSE2,
- TEGRA_PIN_DDR_QUSE3,
-};
-
-static const unsigned drive_xm2d_pins[] = {
- TEGRA_PIN_DDR_DQ0,
- TEGRA_PIN_DDR_DQ1,
- TEGRA_PIN_DDR_DQ2,
- TEGRA_PIN_DDR_DQ3,
- TEGRA_PIN_DDR_DQ4,
- TEGRA_PIN_DDR_DQ5,
- TEGRA_PIN_DDR_DQ6,
- TEGRA_PIN_DDR_DQ7,
- TEGRA_PIN_DDR_DQ8,
- TEGRA_PIN_DDR_DQ9,
- TEGRA_PIN_DDR_DQ10,
- TEGRA_PIN_DDR_DQ11,
- TEGRA_PIN_DDR_DQ12,
- TEGRA_PIN_DDR_DQ13,
- TEGRA_PIN_DDR_DQ14,
- TEGRA_PIN_DDR_DQ15,
- TEGRA_PIN_DDR_DQ16,
- TEGRA_PIN_DDR_DQ17,
- TEGRA_PIN_DDR_DQ18,
- TEGRA_PIN_DDR_DQ19,
- TEGRA_PIN_DDR_DQ20,
- TEGRA_PIN_DDR_DQ21,
- TEGRA_PIN_DDR_DQ22,
- TEGRA_PIN_DDR_DQ23,
- TEGRA_PIN_DDR_DQ24,
- TEGRA_PIN_DDR_DQ25,
- TEGRA_PIN_DDR_DQ26,
- TEGRA_PIN_DDR_DQ27,
- TEGRA_PIN_DDR_DQ28,
- TEGRA_PIN_DDR_DQ29,
- TEGRA_PIN_DDR_DQ30,
- TEGRA_PIN_DDR_DQ31,
- TEGRA_PIN_DDR_DM0,
- TEGRA_PIN_DDR_DM1,
- TEGRA_PIN_DDR_DM2,
- TEGRA_PIN_DDR_DM3,
-};
-
-static const unsigned drive_xm2clk_pins[] = {
- TEGRA_PIN_DDR_CLK,
- TEGRA_PIN_DDR_CLK_N,
-};
-
-static const unsigned drive_sdio1_pins[] = {
- TEGRA_PIN_SDIO1_CLK_PZ0,
- TEGRA_PIN_SDIO1_CMD_PZ1,
- TEGRA_PIN_SDIO1_DAT0_PY7,
- TEGRA_PIN_SDIO1_DAT1_PY6,
- TEGRA_PIN_SDIO1_DAT2_PY5,
- TEGRA_PIN_SDIO1_DAT3_PY4,
-};
-
-static const unsigned drive_crt_pins[] = {
- TEGRA_PIN_CRT_HSYNC,
- TEGRA_PIN_CRT_VSYNC,
-};
-
-static const unsigned drive_ddc_pins[] = {
- TEGRA_PIN_DDC_SCL,
- TEGRA_PIN_DDC_SDA,
-};
-
-static const unsigned drive_gma_pins[] = {
- TEGRA_PIN_GMI_AD20_PAA0,
- TEGRA_PIN_GMI_AD21_PAA1,
- TEGRA_PIN_GMI_AD22_PAA2,
- TEGRA_PIN_GMI_AD23_PAA3,
-};
-
-static const unsigned drive_gmb_pins[] = {
- TEGRA_PIN_GMI_WP_N_PC7,
-};
-
-static const unsigned drive_gmc_pins[] = {
- TEGRA_PIN_GMI_AD16_PJ7,
- TEGRA_PIN_GMI_AD17_PB0,
- TEGRA_PIN_GMI_AD18_PB1,
- TEGRA_PIN_GMI_AD19_PK7,
-};
-
-static const unsigned drive_gmd_pins[] = {
- TEGRA_PIN_GMI_CS0_N_PJ0,
- TEGRA_PIN_GMI_CS1_N_PJ2,
-};
-
-static const unsigned drive_gme_pins[] = {
- TEGRA_PIN_GMI_AD24_PAA4,
- TEGRA_PIN_GMI_AD25_PAA5,
- TEGRA_PIN_GMI_AD26_PAA6,
- TEGRA_PIN_GMI_AD27_PAA7,
-};
-
-static const unsigned drive_owr_pins[] = {
- TEGRA_PIN_OWC,
-};
-
-static const unsigned drive_uda_pins[] = {
- TEGRA_PIN_ULPI_CLK_PY0,
- TEGRA_PIN_ULPI_DIR_PY1,
- TEGRA_PIN_ULPI_NXT_PY2,
- TEGRA_PIN_ULPI_STP_PY3,
-};
-
-enum tegra_mux {
- TEGRA_MUX_AHB_CLK,
- TEGRA_MUX_APB_CLK,
- TEGRA_MUX_AUDIO_SYNC,
- TEGRA_MUX_CRT,
- TEGRA_MUX_DAP1,
- TEGRA_MUX_DAP2,
- TEGRA_MUX_DAP3,
- TEGRA_MUX_DAP4,
- TEGRA_MUX_DAP5,
- TEGRA_MUX_DISPLAYA,
- TEGRA_MUX_DISPLAYB,
- TEGRA_MUX_EMC_TEST0_DLL,
- TEGRA_MUX_EMC_TEST1_DLL,
- TEGRA_MUX_GMI,
- TEGRA_MUX_GMI_INT,
- TEGRA_MUX_HDMI,
- TEGRA_MUX_I2CP,
- TEGRA_MUX_I2C1,
- TEGRA_MUX_I2C2,
- TEGRA_MUX_I2C3,
- TEGRA_MUX_IDE,
- TEGRA_MUX_IRDA,
- TEGRA_MUX_KBC,
- TEGRA_MUX_MIO,
- TEGRA_MUX_MIPI_HS,
- TEGRA_MUX_NAND,
- TEGRA_MUX_OSC,
- TEGRA_MUX_OWR,
- TEGRA_MUX_PCIE,
- TEGRA_MUX_PLLA_OUT,
- TEGRA_MUX_PLLC_OUT1,
- TEGRA_MUX_PLLM_OUT1,
- TEGRA_MUX_PLLP_OUT2,
- TEGRA_MUX_PLLP_OUT3,
- TEGRA_MUX_PLLP_OUT4,
- TEGRA_MUX_PWM,
- TEGRA_MUX_PWR_INTR,
- TEGRA_MUX_PWR_ON,
- TEGRA_MUX_RSVD1,
- TEGRA_MUX_RSVD2,
- TEGRA_MUX_RSVD3,
- TEGRA_MUX_RSVD4,
- TEGRA_MUX_RTCK,
- TEGRA_MUX_SDIO1,
- TEGRA_MUX_SDIO2,
- TEGRA_MUX_SDIO3,
- TEGRA_MUX_SDIO4,
- TEGRA_MUX_SFLASH,
- TEGRA_MUX_SPDIF,
- TEGRA_MUX_SPI1,
- TEGRA_MUX_SPI2,
- TEGRA_MUX_SPI2_ALT,
- TEGRA_MUX_SPI3,
- TEGRA_MUX_SPI4,
- TEGRA_MUX_TRACE,
- TEGRA_MUX_TWC,
- TEGRA_MUX_UARTA,
- TEGRA_MUX_UARTB,
- TEGRA_MUX_UARTC,
- TEGRA_MUX_UARTD,
- TEGRA_MUX_UARTE,
- TEGRA_MUX_ULPI,
- TEGRA_MUX_VI,
- TEGRA_MUX_VI_SENSOR_CLK,
- TEGRA_MUX_XIO,
-};
-
-#define FUNCTION(fname) \
- { \
- .name = #fname, \
- }
-
-static struct tegra_function tegra20_functions[] = {
- FUNCTION(ahb_clk),
- FUNCTION(apb_clk),
- FUNCTION(audio_sync),
- FUNCTION(crt),
- FUNCTION(dap1),
- FUNCTION(dap2),
- FUNCTION(dap3),
- FUNCTION(dap4),
- FUNCTION(dap5),
- FUNCTION(displaya),
- FUNCTION(displayb),
- FUNCTION(emc_test0_dll),
- FUNCTION(emc_test1_dll),
- FUNCTION(gmi),
- FUNCTION(gmi_int),
- FUNCTION(hdmi),
- FUNCTION(i2cp),
- FUNCTION(i2c1),
- FUNCTION(i2c2),
- FUNCTION(i2c3),
- FUNCTION(ide),
- FUNCTION(irda),
- FUNCTION(kbc),
- FUNCTION(mio),
- FUNCTION(mipi_hs),
- FUNCTION(nand),
- FUNCTION(osc),
- FUNCTION(owr),
- FUNCTION(pcie),
- FUNCTION(plla_out),
- FUNCTION(pllc_out1),
- FUNCTION(pllm_out1),
- FUNCTION(pllp_out2),
- FUNCTION(pllp_out3),
- FUNCTION(pllp_out4),
- FUNCTION(pwm),
- FUNCTION(pwr_intr),
- FUNCTION(pwr_on),
- FUNCTION(rsvd1),
- FUNCTION(rsvd2),
- FUNCTION(rsvd3),
- FUNCTION(rsvd4),
- FUNCTION(rtck),
- FUNCTION(sdio1),
- FUNCTION(sdio2),
- FUNCTION(sdio3),
- FUNCTION(sdio4),
- FUNCTION(sflash),
- FUNCTION(spdif),
- FUNCTION(spi1),
- FUNCTION(spi2),
- FUNCTION(spi2_alt),
- FUNCTION(spi3),
- FUNCTION(spi4),
- FUNCTION(trace),
- FUNCTION(twc),
- FUNCTION(uarta),
- FUNCTION(uartb),
- FUNCTION(uartc),
- FUNCTION(uartd),
- FUNCTION(uarte),
- FUNCTION(ulpi),
- FUNCTION(vi),
- FUNCTION(vi_sensor_clk),
- FUNCTION(xio),
-};
-
-#define TRISTATE_REG_A 0x14
-#define PIN_MUX_CTL_REG_A 0x80
-#define PULLUPDOWN_REG_A 0xa0
-#define PINGROUP_REG_A 0x868
-
-/* Pin group with mux control, and typically tri-state and pull-up/down too */
-#define MUX_PG(pg_name, f0, f1, f2, f3, \
- tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
- { \
- .name = #pg_name, \
- .pins = pg_name##_pins, \
- .npins = ARRAY_SIZE(pg_name##_pins), \
- .funcs = { \
- TEGRA_MUX_ ## f0, \
- TEGRA_MUX_ ## f1, \
- TEGRA_MUX_ ## f2, \
- TEGRA_MUX_ ## f3, \
- }, \
- .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
- .mux_bank = 1, \
- .mux_bit = mux_b, \
- .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
- .pupd_bank = 2, \
- .pupd_bit = pupd_b, \
- .tri_reg = ((tri_r) - TRISTATE_REG_A), \
- .tri_bank = 0, \
- .tri_bit = tri_b, \
- .einput_bit = -1, \
- .odrain_bit = -1, \
- .lock_bit = -1, \
- .ioreset_bit = -1, \
- .rcv_sel_bit = -1, \
- .drv_reg = -1, \
- }
-
-/* Pin groups with only pull up and pull down control */
-#define PULL_PG(pg_name, pupd_r, pupd_b) \
- { \
- .name = #pg_name, \
- .pins = pg_name##_pins, \
- .npins = ARRAY_SIZE(pg_name##_pins), \
- .mux_reg = -1, \
- .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
- .pupd_bank = 2, \
- .pupd_bit = pupd_b, \
- .drv_reg = -1, \
- }
-
-/* Pin groups for drive strength registers (configurable version) */
-#define DRV_PG_EXT(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
- drvdn_b, drvup_b, \
- slwr_b, slwr_w, slwf_b, slwf_w) \
- { \
- .name = "drive_" #pg_name, \
- .pins = drive_##pg_name##_pins, \
- .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
- .mux_reg = -1, \
- .pupd_reg = -1, \
- .tri_reg = -1, \
- .drv_reg = ((r) - PINGROUP_REG_A), \
- .drv_bank = 3, \
- .hsm_bit = hsm_b, \
- .schmitt_bit = schmitt_b, \
- .lpmd_bit = lpmd_b, \
- .drvdn_bit = drvdn_b, \
- .drvdn_width = 5, \
- .drvup_bit = drvup_b, \
- .drvup_width = 5, \
- .slwr_bit = slwr_b, \
- .slwr_width = slwr_w, \
- .slwf_bit = slwf_b, \
- .slwf_width = slwf_w, \
- .drvtype_bit = -1, \
- }
-
-/* Pin groups for drive strength registers (simple version) */
-#define DRV_PG(pg_name, r) \
- DRV_PG_EXT(pg_name, r, 2, 3, 4, 12, 20, 28, 2, 30, 2)
-
-static const struct tegra_pingroup tegra20_groups[] = {
- /* name, f0, f1, f2, f3, tri r/b, mux r/b, pupd r/b */
- MUX_PG(ata, IDE, NAND, GMI, RSVD4, 0x14, 0, 0x80, 24, 0xa0, 0),
- MUX_PG(atb, IDE, NAND, GMI, SDIO4, 0x14, 1, 0x80, 16, 0xa0, 2),
- MUX_PG(atc, IDE, NAND, GMI, SDIO4, 0x14, 2, 0x80, 22, 0xa0, 4),
- MUX_PG(atd, IDE, NAND, GMI, SDIO4, 0x14, 3, 0x80, 20, 0xa0, 6),
- MUX_PG(ate, IDE, NAND, GMI, RSVD4, 0x18, 25, 0x80, 12, 0xa0, 8),
- MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, 0x14, 4, 0x88, 2, 0xa8, 0),
- MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, 0x14, 5, 0x88, 4, 0xa8, 2),
- MUX_PG(crtp, CRT, RSVD2, RSVD3, RSVD4, 0x20, 14, 0x98, 20, 0xa4, 24),
- MUX_PG(csus, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, 0x14, 6, 0x88, 6, 0xac, 24),
- MUX_PG(dap1, DAP1, RSVD2, GMI, SDIO2, 0x14, 7, 0x88, 20, 0xa0, 10),
- MUX_PG(dap2, DAP2, TWC, RSVD3, GMI, 0x14, 8, 0x88, 22, 0xa0, 12),
- MUX_PG(dap3, DAP3, RSVD2, RSVD3, RSVD4, 0x14, 9, 0x88, 24, 0xa0, 14),
- MUX_PG(dap4, DAP4, RSVD2, GMI, RSVD4, 0x14, 10, 0x88, 26, 0xa0, 16),
- MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28),
- MUX_PG(dta, RSVD1, SDIO2, VI, RSVD4, 0x14, 11, 0x84, 20, 0xa0, 18),
- MUX_PG(dtb, RSVD1, RSVD2, VI, SPI1, 0x14, 12, 0x84, 22, 0xa0, 20),
- MUX_PG(dtc, RSVD1, RSVD2, VI, RSVD4, 0x14, 13, 0x84, 26, 0xa0, 22),
- MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, 0x14, 14, 0x84, 28, 0xa0, 24),
- MUX_PG(dte, RSVD1, RSVD2, VI, SPI1, 0x14, 15, 0x84, 30, 0xa0, 26),
- MUX_PG(dtf, I2C3, RSVD2, VI, RSVD4, 0x20, 12, 0x98, 30, 0xa0, 28),
- MUX_PG(gma, UARTE, SPI3, GMI, SDIO4, 0x14, 28, 0x84, 0, 0xb0, 20),
- MUX_PG(gmb, IDE, NAND, GMI, GMI_INT, 0x18, 29, 0x88, 28, 0xb0, 22),
- MUX_PG(gmc, UARTD, SPI4, GMI, SFLASH, 0x14, 29, 0x84, 2, 0xb0, 24),
- MUX_PG(gmd, RSVD1, NAND, GMI, SFLASH, 0x18, 30, 0x88, 30, 0xb0, 26),
- MUX_PG(gme, RSVD1, DAP5, GMI, SDIO4, 0x18, 0, 0x8c, 0, 0xa8, 24),
- MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20),
- MUX_PG(gpu7, RTCK, RSVD2, RSVD3, RSVD4, 0x20, 11, 0x98, 28, 0xa4, 6),
- MUX_PG(gpv, PCIE, RSVD2, RSVD3, RSVD4, 0x14, 17, 0x8c, 2, 0xa0, 30),
- MUX_PG(hdint, HDMI, RSVD2, RSVD3, RSVD4, 0x1c, 23, 0x84, 4, -1, -1),
- MUX_PG(i2cp, I2CP, RSVD2, RSVD3, RSVD4, 0x14, 18, 0x88, 8, 0xa4, 2),
- MUX_PG(irrx, UARTA, UARTB, GMI, SPI4, 0x14, 20, 0x88, 18, 0xa8, 22),
- MUX_PG(irtx, UARTA, UARTB, GMI, SPI4, 0x14, 19, 0x88, 16, 0xa8, 20),
- MUX_PG(kbca, KBC, NAND, SDIO2, EMC_TEST0_DLL, 0x14, 22, 0x88, 10, 0xa4, 8),
- MUX_PG(kbcb, KBC, NAND, SDIO2, MIO, 0x14, 21, 0x88, 12, 0xa4, 10),
- MUX_PG(kbcc, KBC, NAND, TRACE, EMC_TEST1_DLL, 0x18, 26, 0x88, 14, 0xa4, 12),
- MUX_PG(kbcd, KBC, NAND, SDIO2, MIO, 0x20, 10, 0x98, 26, 0xa4, 14),
- MUX_PG(kbce, KBC, NAND, OWR, RSVD4, 0x14, 26, 0x80, 28, 0xb0, 2),
- MUX_PG(kbcf, KBC, NAND, TRACE, MIO, 0x14, 27, 0x80, 26, 0xb0, 0),
- MUX_PG(lcsn, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 31, 0x90, 12, -1, -1),
- MUX_PG(ld0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 0, 0x94, 0, -1, -1),
- MUX_PG(ld1, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 1, 0x94, 2, -1, -1),
- MUX_PG(ld2, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 2, 0x94, 4, -1, -1),
- MUX_PG(ld3, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 3, 0x94, 6, -1, -1),
- MUX_PG(ld4, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 4, 0x94, 8, -1, -1),
- MUX_PG(ld5, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 5, 0x94, 10, -1, -1),
- MUX_PG(ld6, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 6, 0x94, 12, -1, -1),
- MUX_PG(ld7, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 7, 0x94, 14, -1, -1),
- MUX_PG(ld8, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 8, 0x94, 16, -1, -1),
- MUX_PG(ld9, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 9, 0x94, 18, -1, -1),
- MUX_PG(ld10, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 10, 0x94, 20, -1, -1),
- MUX_PG(ld11, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 11, 0x94, 22, -1, -1),
- MUX_PG(ld12, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 12, 0x94, 24, -1, -1),
- MUX_PG(ld13, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 13, 0x94, 26, -1, -1),
- MUX_PG(ld14, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 14, 0x94, 28, -1, -1),
- MUX_PG(ld15, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 15, 0x94, 30, -1, -1),
- MUX_PG(ld16, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 16, 0x98, 0, -1, -1),
- MUX_PG(ld17, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 17, 0x98, 2, -1, -1),
- MUX_PG(ldc, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 30, 0x90, 14, -1, -1),
- MUX_PG(ldi, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 6, 0x98, 16, -1, -1),
- MUX_PG(lhp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 18, 0x98, 10, -1, -1),
- MUX_PG(lhp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 19, 0x98, 4, -1, -1),
- MUX_PG(lhp2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 20, 0x98, 6, -1, -1),
- MUX_PG(lhs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x20, 7, 0x90, 22, -1, -1),
- MUX_PG(lm0, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 24, 0x90, 26, -1, -1),
- MUX_PG(lm1, DISPLAYA, DISPLAYB, RSVD3, CRT, 0x1c, 25, 0x90, 28, -1, -1),
- MUX_PG(lpp, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 8, 0x98, 14, -1, -1),
- MUX_PG(lpw0, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 3, 0x90, 0, -1, -1),
- MUX_PG(lpw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 4, 0x90, 2, -1, -1),
- MUX_PG(lpw2, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 5, 0x90, 4, -1, -1),
- MUX_PG(lsc0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 27, 0x90, 18, -1, -1),
- MUX_PG(lsc1, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 28, 0x90, 20, -1, -1),
- MUX_PG(lsck, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 29, 0x90, 16, -1, -1),
- MUX_PG(lsda, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 1, 0x90, 8, -1, -1),
- MUX_PG(lsdi, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x20, 2, 0x90, 6, -1, -1),
- MUX_PG(lspi, DISPLAYA, DISPLAYB, XIO, HDMI, 0x20, 0, 0x90, 10, -1, -1),
- MUX_PG(lvp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 21, 0x90, 30, -1, -1),
- MUX_PG(lvp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 22, 0x98, 8, -1, -1),
- MUX_PG(lvs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 26, 0x90, 24, -1, -1),
- MUX_PG(owc, OWR, RSVD2, RSVD3, RSVD4, 0x14, 31, 0x84, 8, 0xb0, 30),
- MUX_PG(pmc, PWR_ON, PWR_INTR, RSVD3, RSVD4, 0x14, 23, 0x98, 18, -1, -1),
- MUX_PG(pta, I2C2, HDMI, GMI, RSVD4, 0x14, 24, 0x98, 22, 0xa4, 4),
- MUX_PG(rm, I2C1, RSVD2, RSVD3, RSVD4, 0x14, 25, 0x80, 14, 0xa4, 0),
- MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, 0x20, 15, 0x8c, 10, -1, -1),
- MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, 0x18, 1, 0x8c, 12, 0xac, 28),
- MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, 0x18, 2, 0x8c, 14, 0xac, 30),
- MUX_PG(sdio1, SDIO1, RSVD2, UARTE, UARTA, 0x14, 30, 0x80, 30, 0xb0, 18),
- MUX_PG(slxa, PCIE, SPI4, SDIO3, SPI2, 0x18, 3, 0x84, 6, 0xa4, 22),
- MUX_PG(slxc, SPDIF, SPI4, SDIO3, SPI2, 0x18, 5, 0x84, 10, 0xa4, 26),
- MUX_PG(slxd, SPDIF, SPI4, SDIO3, SPI2, 0x18, 6, 0x84, 12, 0xa4, 28),
- MUX_PG(slxk, PCIE, SPI4, SDIO3, SPI2, 0x18, 7, 0x84, 14, 0xa4, 30),
- MUX_PG(spdi, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 8, 0x8c, 8, 0xa4, 16),
- MUX_PG(spdo, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 9, 0x8c, 6, 0xa4, 18),
- MUX_PG(spia, SPI1, SPI2, SPI3, GMI, 0x18, 10, 0x8c, 30, 0xa8, 4),
- MUX_PG(spib, SPI1, SPI2, SPI3, GMI, 0x18, 11, 0x8c, 28, 0xa8, 6),
- MUX_PG(spic, SPI1, SPI2, SPI3, GMI, 0x18, 12, 0x8c, 26, 0xa8, 8),
- MUX_PG(spid, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 13, 0x8c, 24, 0xa8, 10),
- MUX_PG(spie, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 14, 0x8c, 22, 0xa8, 12),
- MUX_PG(spif, SPI3, SPI1, SPI2, RSVD4, 0x18, 15, 0x8c, 20, 0xa8, 14),
- MUX_PG(spig, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 16, 0x8c, 18, 0xa8, 16),
- MUX_PG(spih, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 17, 0x8c, 16, 0xa8, 18),
- MUX_PG(uaa, SPI3, MIPI_HS, UARTA, ULPI, 0x18, 18, 0x80, 0, 0xac, 0),
- MUX_PG(uab, SPI2, MIPI_HS, UARTA, ULPI, 0x18, 19, 0x80, 2, 0xac, 2),
- MUX_PG(uac, OWR, RSVD2, RSVD3, RSVD4, 0x18, 20, 0x80, 4, 0xac, 4),
- MUX_PG(uad, IRDA, SPDIF, UARTA, SPI4, 0x18, 21, 0x80, 6, 0xac, 6),
- MUX_PG(uca, UARTC, RSVD2, GMI, RSVD4, 0x18, 22, 0x84, 16, 0xac, 8),
- MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10),
- MUX_PG(uda, SPI1, RSVD2, UARTD, ULPI, 0x20, 13, 0x80, 8, 0xb0, 16),
- /* pg_name, pupd_r/b */
- PULL_PG(ck32, 0xb0, 14),
- PULL_PG(ddrc, 0xac, 26),
- PULL_PG(pmca, 0xb0, 4),
- PULL_PG(pmcb, 0xb0, 6),
- PULL_PG(pmcc, 0xb0, 8),
- PULL_PG(pmcd, 0xb0, 10),
- PULL_PG(pmce, 0xb0, 12),
- PULL_PG(xm2c, 0xa8, 30),
- PULL_PG(xm2d, 0xa8, 28),
- PULL_PG(ls, 0xac, 20),
- PULL_PG(lc, 0xac, 22),
- PULL_PG(ld17_0, 0xac, 12),
- PULL_PG(ld19_18, 0xac, 14),
- PULL_PG(ld21_20, 0xac, 16),
- PULL_PG(ld23_22, 0xac, 18),
- /* pg_name, r */
- DRV_PG(ao1, 0x868),
- DRV_PG(ao2, 0x86c),
- DRV_PG(at1, 0x870),
- DRV_PG(at2, 0x874),
- DRV_PG(cdev1, 0x878),
- DRV_PG(cdev2, 0x87c),
- DRV_PG(csus, 0x880),
- DRV_PG(dap1, 0x884),
- DRV_PG(dap2, 0x888),
- DRV_PG(dap3, 0x88c),
- DRV_PG(dap4, 0x890),
- DRV_PG(dbg, 0x894),
- DRV_PG(lcd1, 0x898),
- DRV_PG(lcd2, 0x89c),
- DRV_PG(sdmmc2, 0x8a0),
- DRV_PG(sdmmc3, 0x8a4),
- DRV_PG(spi, 0x8a8),
- DRV_PG(uaa, 0x8ac),
- DRV_PG(uab, 0x8b0),
- DRV_PG(uart2, 0x8b4),
- DRV_PG(uart3, 0x8b8),
- DRV_PG(vi1, 0x8bc),
- DRV_PG(vi2, 0x8c0),
- /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvup_b, slwr_b, slwr_w, slwf_b, slwf_w */
- DRV_PG_EXT(xm2a, 0x8c4, -1, -1, 4, 14, 19, 24, 4, 28, 4),
- DRV_PG_EXT(xm2c, 0x8c8, -1, 3, -1, 14, 19, 24, 4, 28, 4),
- DRV_PG_EXT(xm2d, 0x8cc, -1, 3, -1, 14, 19, 24, 4, 28, 4),
- DRV_PG_EXT(xm2clk, 0x8d0, -1, -1, -1, 14, 19, 24, 4, 28, 4),
- /* pg_name, r */
- DRV_PG(sdio1, 0x8e0),
- DRV_PG(crt, 0x8ec),
- DRV_PG(ddc, 0x8f0),
- DRV_PG(gma, 0x8f4),
- DRV_PG(gmb, 0x8f8),
- DRV_PG(gmc, 0x8fc),
- DRV_PG(gmd, 0x900),
- DRV_PG(gme, 0x904),
- DRV_PG(owr, 0x908),
- DRV_PG(uda, 0x90c),
-};
-
-static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
- .ngpios = NUM_GPIOS,
- .pins = tegra20_pins,
- .npins = ARRAY_SIZE(tegra20_pins),
- .functions = tegra20_functions,
- .nfunctions = ARRAY_SIZE(tegra20_functions),
- .groups = tegra20_groups,
- .ngroups = ARRAY_SIZE(tegra20_groups),
- .hsm_in_mux = false,
- .schmitt_in_mux = false,
- .drvtype_in_mux = false,
-};
-
-static int tegra20_pinctrl_probe(struct platform_device *pdev)
-{
- return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
-}
-
-static const struct of_device_id tegra20_pinctrl_of_match[] = {
- { .compatible = "nvidia,tegra20-pinmux", },
- { },
-};
-
-static struct platform_driver tegra20_pinctrl_driver = {
- .driver = {
- .name = "tegra20-pinctrl",
- .of_match_table = tegra20_pinctrl_of_match,
- },
- .probe = tegra20_pinctrl_probe,
- .remove = tegra_pinctrl_remove,
-};
-module_platform_driver(tegra20_pinctrl_driver);
-
-MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
-MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver");
-MODULE_LICENSE("GPL v2");
-MODULE_DEVICE_TABLE(of, tegra20_pinctrl_of_match);
+++ /dev/null
-/*
- * Pinctrl data for the NVIDIA Tegra210 pinmux
- *
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-
-#include "pinctrl-tegra.h"
-
-/*
- * Most pins affected by the pinmux can also be GPIOs. Define these first.
- * These must match how the GPIO driver names/numbers its pins.
- */
-#define _GPIO(offset) (offset)
-
-#define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0)
-#define TEGRA_PIN_PEX_L0_CLKREQ_N_PA1 _GPIO(1)
-#define TEGRA_PIN_PEX_WAKE_N_PA2 _GPIO(2)
-#define TEGRA_PIN_PEX_L1_RST_N_PA3 _GPIO(3)
-#define TEGRA_PIN_PEX_L1_CLKREQ_N_PA4 _GPIO(4)
-#define TEGRA_PIN_SATA_LED_ACTIVE_PA5 _GPIO(5)
-#define TEGRA_PIN_PA6 _GPIO(6)
-#define TEGRA_PIN_DAP1_FS_PB0 _GPIO(8)
-#define TEGRA_PIN_DAP1_DIN_PB1 _GPIO(9)
-#define TEGRA_PIN_DAP1_DOUT_PB2 _GPIO(10)
-#define TEGRA_PIN_DAP1_SCLK_PB3 _GPIO(11)
-#define TEGRA_PIN_SPI2_MOSI_PB4 _GPIO(12)
-#define TEGRA_PIN_SPI2_MISO_PB5 _GPIO(13)
-#define TEGRA_PIN_SPI2_SCK_PB6 _GPIO(14)
-#define TEGRA_PIN_SPI2_CS0_PB7 _GPIO(15)
-#define TEGRA_PIN_SPI1_MOSI_PC0 _GPIO(16)
-#define TEGRA_PIN_SPI1_MISO_PC1 _GPIO(17)
-#define TEGRA_PIN_SPI1_SCK_PC2 _GPIO(18)
-#define TEGRA_PIN_SPI1_CS0_PC3 _GPIO(19)
-#define TEGRA_PIN_SPI1_CS1_PC4 _GPIO(20)
-#define TEGRA_PIN_SPI4_SCK_PC5 _GPIO(21)
-#define TEGRA_PIN_SPI4_CS0_PC6 _GPIO(22)
-#define TEGRA_PIN_SPI4_MOSI_PC7 _GPIO(23)
-#define TEGRA_PIN_SPI4_MISO_PD0 _GPIO(24)
-#define TEGRA_PIN_UART3_TX_PD1 _GPIO(25)
-#define TEGRA_PIN_UART3_RX_PD2 _GPIO(26)
-#define TEGRA_PIN_UART3_RTS_PD3 _GPIO(27)
-#define TEGRA_PIN_UART3_CTS_PD4 _GPIO(28)
-#define TEGRA_PIN_DMIC1_CLK_PE0 _GPIO(32)
-#define TEGRA_PIN_DMIC1_DAT_PE1 _GPIO(33)
-#define TEGRA_PIN_DMIC2_CLK_PE2 _GPIO(34)
-#define TEGRA_PIN_DMIC2_DAT_PE3 _GPIO(35)
-#define TEGRA_PIN_DMIC3_CLK_PE4 _GPIO(36)
-#define TEGRA_PIN_DMIC3_DAT_PE5 _GPIO(37)
-#define TEGRA_PIN_PE6 _GPIO(38)
-#define TEGRA_PIN_PE7 _GPIO(39)
-#define TEGRA_PIN_GEN3_I2C_SCL_PF0 _GPIO(40)
-#define TEGRA_PIN_GEN3_I2C_SDA_PF1 _GPIO(41)
-#define TEGRA_PIN_UART2_TX_PG0 _GPIO(48)
-#define TEGRA_PIN_UART2_RX_PG1 _GPIO(49)
-#define TEGRA_PIN_UART2_RTS_PG2 _GPIO(50)
-#define TEGRA_PIN_UART2_CTS_PG3 _GPIO(51)
-#define TEGRA_PIN_WIFI_EN_PH0 _GPIO(56)
-#define TEGRA_PIN_WIFI_RST_PH1 _GPIO(57)
-#define TEGRA_PIN_WIFI_WAKE_AP_PH2 _GPIO(58)
-#define TEGRA_PIN_AP_WAKE_BT_PH3 _GPIO(59)
-#define TEGRA_PIN_BT_RST_PH4 _GPIO(60)
-#define TEGRA_PIN_BT_WAKE_AP_PH5 _GPIO(61)
-#define TEGRA_PIN_PH6 _GPIO(62)
-#define TEGRA_PIN_AP_WAKE_NFC_PH7 _GPIO(63)
-#define TEGRA_PIN_NFC_EN_PI0 _GPIO(64)
-#define TEGRA_PIN_NFC_INT_PI1 _GPIO(65)
-#define TEGRA_PIN_GPS_EN_PI2 _GPIO(66)
-#define TEGRA_PIN_GPS_RST_PI3 _GPIO(67)
-#define TEGRA_PIN_UART4_TX_PI4 _GPIO(68)
-#define TEGRA_PIN_UART4_RX_PI5 _GPIO(69)
-#define TEGRA_PIN_UART4_RTS_PI6 _GPIO(70)
-#define TEGRA_PIN_UART4_CTS_PI7 _GPIO(71)
-#define TEGRA_PIN_GEN1_I2C_SDA_PJ0 _GPIO(72)
-#define TEGRA_PIN_GEN1_I2C_SCL_PJ1 _GPIO(73)
-#define TEGRA_PIN_GEN2_I2C_SCL_PJ2 _GPIO(74)
-#define TEGRA_PIN_GEN2_I2C_SDA_PJ3 _GPIO(75)
-#define TEGRA_PIN_DAP4_FS_PJ4 _GPIO(76)
-#define TEGRA_PIN_DAP4_DIN_PJ5 _GPIO(77)
-#define TEGRA_PIN_DAP4_DOUT_PJ6 _GPIO(78)
-#define TEGRA_PIN_DAP4_SCLK_PJ7 _GPIO(79)
-#define TEGRA_PIN_PK0 _GPIO(80)
-#define TEGRA_PIN_PK1 _GPIO(81)
-#define TEGRA_PIN_PK2 _GPIO(82)
-#define TEGRA_PIN_PK3 _GPIO(83)
-#define TEGRA_PIN_PK4 _GPIO(84)
-#define TEGRA_PIN_PK5 _GPIO(85)
-#define TEGRA_PIN_PK6 _GPIO(86)
-#define TEGRA_PIN_PK7 _GPIO(87)
-#define TEGRA_PIN_PL0 _GPIO(88)
-#define TEGRA_PIN_PL1 _GPIO(89)
-#define TEGRA_PIN_SDMMC1_CLK_PM0 _GPIO(96)
-#define TEGRA_PIN_SDMMC1_CMD_PM1 _GPIO(97)
-#define TEGRA_PIN_SDMMC1_DAT3_PM2 _GPIO(98)
-#define TEGRA_PIN_SDMMC1_DAT2_PM3 _GPIO(99)
-#define TEGRA_PIN_SDMMC1_DAT1_PM4 _GPIO(100)
-#define TEGRA_PIN_SDMMC1_DAT0_PM5 _GPIO(101)
-#define TEGRA_PIN_SDMMC3_CLK_PP0 _GPIO(120)
-#define TEGRA_PIN_SDMMC3_CMD_PP1 _GPIO(121)
-#define TEGRA_PIN_SDMMC3_DAT3_PP2 _GPIO(122)
-#define TEGRA_PIN_SDMMC3_DAT2_PP3 _GPIO(123)
-#define TEGRA_PIN_SDMMC3_DAT1_PP4 _GPIO(124)
-#define TEGRA_PIN_SDMMC3_DAT0_PP5 _GPIO(125)
-#define TEGRA_PIN_CAM1_MCLK_PS0 _GPIO(144)
-#define TEGRA_PIN_CAM2_MCLK_PS1 _GPIO(145)
-#define TEGRA_PIN_CAM_I2C_SCL_PS2 _GPIO(146)
-#define TEGRA_PIN_CAM_I2C_SDA_PS3 _GPIO(147)
-#define TEGRA_PIN_CAM_RST_PS4 _GPIO(148)
-#define TEGRA_PIN_CAM_AF_EN_PS5 _GPIO(149)
-#define TEGRA_PIN_CAM_FLASH_EN_PS6 _GPIO(150)
-#define TEGRA_PIN_CAM1_PWDN_PS7 _GPIO(151)
-#define TEGRA_PIN_CAM2_PWDN_PT0 _GPIO(152)
-#define TEGRA_PIN_CAM1_STROBE_PT1 _GPIO(153)
-#define TEGRA_PIN_UART1_TX_PU0 _GPIO(160)
-#define TEGRA_PIN_UART1_RX_PU1 _GPIO(161)
-#define TEGRA_PIN_UART1_RTS_PU2 _GPIO(162)
-#define TEGRA_PIN_UART1_CTS_PU3 _GPIO(163)
-#define TEGRA_PIN_LCD_BL_PWM_PV0 _GPIO(168)
-#define TEGRA_PIN_LCD_BL_EN_PV1 _GPIO(169)
-#define TEGRA_PIN_LCD_RST_PV2 _GPIO(170)
-#define TEGRA_PIN_LCD_GPIO1_PV3 _GPIO(171)
-#define TEGRA_PIN_LCD_GPIO2_PV4 _GPIO(172)
-#define TEGRA_PIN_AP_READY_PV5 _GPIO(173)
-#define TEGRA_PIN_TOUCH_RST_PV6 _GPIO(174)
-#define TEGRA_PIN_TOUCH_CLK_PV7 _GPIO(175)
-#define TEGRA_PIN_MODEM_WAKE_AP_PX0 _GPIO(184)
-#define TEGRA_PIN_TOUCH_INT_PX1 _GPIO(185)
-#define TEGRA_PIN_MOTION_INT_PX2 _GPIO(186)
-#define TEGRA_PIN_ALS_PROX_INT_PX3 _GPIO(187)
-#define TEGRA_PIN_TEMP_ALERT_PX4 _GPIO(188)
-#define TEGRA_PIN_BUTTON_POWER_ON_PX5 _GPIO(189)
-#define TEGRA_PIN_BUTTON_VOL_UP_PX6 _GPIO(190)
-#define TEGRA_PIN_BUTTON_VOL_DOWN_PX7 _GPIO(191)
-#define TEGRA_PIN_BUTTON_SLIDE_SW_PY0 _GPIO(192)
-#define TEGRA_PIN_BUTTON_HOME_PY1 _GPIO(193)
-#define TEGRA_PIN_LCD_TE_PY2 _GPIO(194)
-#define TEGRA_PIN_PWR_I2C_SCL_PY3 _GPIO(195)
-#define TEGRA_PIN_PWR_I2C_SDA_PY4 _GPIO(196)
-#define TEGRA_PIN_CLK_32K_OUT_PY5 _GPIO(197)
-#define TEGRA_PIN_PZ0 _GPIO(200)
-#define TEGRA_PIN_PZ1 _GPIO(201)
-#define TEGRA_PIN_PZ2 _GPIO(202)
-#define TEGRA_PIN_PZ3 _GPIO(203)
-#define TEGRA_PIN_PZ4 _GPIO(204)
-#define TEGRA_PIN_PZ5 _GPIO(205)
-#define TEGRA_PIN_DAP2_FS_PAA0 _GPIO(208)
-#define TEGRA_PIN_DAP2_SCLK_PAA1 _GPIO(209)
-#define TEGRA_PIN_DAP2_DIN_PAA2 _GPIO(210)
-#define TEGRA_PIN_DAP2_DOUT_PAA3 _GPIO(211)
-#define TEGRA_PIN_AUD_MCLK_PBB0 _GPIO(216)
-#define TEGRA_PIN_DVFS_PWM_PBB1 _GPIO(217)
-#define TEGRA_PIN_DVFS_CLK_PBB2 _GPIO(218)
-#define TEGRA_PIN_GPIO_X1_AUD_PBB3 _GPIO(219)
-#define TEGRA_PIN_GPIO_X3_AUD_PBB4 _GPIO(220)
-#define TEGRA_PIN_HDMI_CEC_PCC0 _GPIO(224)
-#define TEGRA_PIN_HDMI_INT_DP_HPD_PCC1 _GPIO(225)
-#define TEGRA_PIN_SPDIF_OUT_PCC2 _GPIO(226)
-#define TEGRA_PIN_SPDIF_IN_PCC3 _GPIO(227)
-#define TEGRA_PIN_USB_VBUS_EN0_PCC4 _GPIO(228)
-#define TEGRA_PIN_USB_VBUS_EN1_PCC5 _GPIO(229)
-#define TEGRA_PIN_DP_HPD0_PCC6 _GPIO(230)
-#define TEGRA_PIN_PCC7 _GPIO(231)
-#define TEGRA_PIN_SPI2_CS1_PDD0 _GPIO(232)
-#define TEGRA_PIN_QSPI_SCK_PEE0 _GPIO(240)
-#define TEGRA_PIN_QSPI_CS_N_PEE1 _GPIO(241)
-#define TEGRA_PIN_QSPI_IO0_PEE2 _GPIO(242)
-#define TEGRA_PIN_QSPI_IO1_PEE3 _GPIO(243)
-#define TEGRA_PIN_QSPI_IO2_PEE4 _GPIO(244)
-#define TEGRA_PIN_QSPI_IO3_PEE5 _GPIO(245)
-
-/* All non-GPIO pins follow */
-#define NUM_GPIOS (TEGRA_PIN_QSPI_IO3_PEE5 + 1)
-#define _PIN(offset) (NUM_GPIOS + (offset))
-
-/* Non-GPIO pins */
-#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
-#define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
-#define TEGRA_PIN_PWR_INT_N _PIN(2)
-#define TEGRA_PIN_CLK_32K_IN _PIN(3)
-#define TEGRA_PIN_JTAG_RTCK _PIN(4)
-#define TEGRA_PIN_BATT_BCL _PIN(5)
-#define TEGRA_PIN_CLK_REQ _PIN(6)
-#define TEGRA_PIN_SHUTDOWN _PIN(7)
-
-static const struct pinctrl_pin_desc tegra210_pins[] = {
- PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PA0, "PEX_L0_RST_N PA0"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, "PEX_L0_CLKREQ_N PA1"),
- PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PA2, "PEX_WAKE_N PA2"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PA3, "PEX_L1_RST_N PA3"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, "PEX_L1_CLKREQ_N PA4"),
- PINCTRL_PIN(TEGRA_PIN_SATA_LED_ACTIVE_PA5, "SATA_LED_ACTIVE PA5"),
- PINCTRL_PIN(TEGRA_PIN_PA6, "PA6"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PB0, "DAP1_FS PB0"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PB1, "DAP1_DIN PB1"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PB2, "DAP1_DOUT PB2"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PB3, "DAP1_SCLK PB3"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PB4, "SPI2_MOSI PB4"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PB5, "SPI2_MISO PB5"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PB6, "SPI2_SCK PB6"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PB7, "SPI2_CS0 PB7"),
- PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PC0, "SPI1_MOSI PC0"),
- PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PC1, "SPI1_MISO PC1"),
- PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PC2, "SPI1_SCK PC2"),
- PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PC3, "SPI1_CS0 PC3"),
- PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PC4, "SPI1_CS1 PC4"),
- PINCTRL_PIN(TEGRA_PIN_SPI4_SCK_PC5, "SPI4_SCK PC5"),
- PINCTRL_PIN(TEGRA_PIN_SPI4_CS0_PC6, "SPI4_CS0 PC6"),
- PINCTRL_PIN(TEGRA_PIN_SPI4_MOSI_PC7, "SPI4_MOSI PC7"),
- PINCTRL_PIN(TEGRA_PIN_SPI4_MISO_PD0, "SPI4_MISO PD0"),
- PINCTRL_PIN(TEGRA_PIN_UART3_TX_PD1, "UART3_TX PD1"),
- PINCTRL_PIN(TEGRA_PIN_UART3_RX_PD2, "UART3_RX PD2"),
- PINCTRL_PIN(TEGRA_PIN_UART3_RTS_PD3, "UART3_RTS PD3"),
- PINCTRL_PIN(TEGRA_PIN_UART3_CTS_PD4, "UART3_CTS PD4"),
- PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PE0, "DMIC1_CLK PE0"),
- PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PE1, "DMIC1_DAT PE1"),
- PINCTRL_PIN(TEGRA_PIN_DMIC2_CLK_PE2, "DMIC2_CLK PE2"),
- PINCTRL_PIN(TEGRA_PIN_DMIC2_DAT_PE3, "DMIC2_DAT PE3"),
- PINCTRL_PIN(TEGRA_PIN_DMIC3_CLK_PE4, "DMIC3_CLK PE4"),
- PINCTRL_PIN(TEGRA_PIN_DMIC3_DAT_PE5, "DMIC3_DAT PE5"),
- PINCTRL_PIN(TEGRA_PIN_PE6, "PE6"),
- PINCTRL_PIN(TEGRA_PIN_PE7, "PE7"),
- PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SCL_PF0, "GEN3_I2C_SCL PF0"),
- PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SDA_PF1, "GEN3_I2C_SDA PF1"),
- PINCTRL_PIN(TEGRA_PIN_UART2_TX_PG0, "UART2_TX PG0"),
- PINCTRL_PIN(TEGRA_PIN_UART2_RX_PG1, "UART2_RX PG1"),
- PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PG2, "UART2_RTS PG2"),
- PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PG3, "UART2_CTS PG3"),
- PINCTRL_PIN(TEGRA_PIN_WIFI_EN_PH0, "WIFI_EN PH0"),
- PINCTRL_PIN(TEGRA_PIN_WIFI_RST_PH1, "WIFI_RST PH1"),
- PINCTRL_PIN(TEGRA_PIN_WIFI_WAKE_AP_PH2, "WIFI_WAKE_AP PH2"),
- PINCTRL_PIN(TEGRA_PIN_AP_WAKE_BT_PH3, "AP_WAKE_BT PH3"),
- PINCTRL_PIN(TEGRA_PIN_BT_RST_PH4, "BT_RST PH4"),
- PINCTRL_PIN(TEGRA_PIN_BT_WAKE_AP_PH5, "BT_WAKE_AP PH5"),
- PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
- PINCTRL_PIN(TEGRA_PIN_AP_WAKE_NFC_PH7, "AP_WAKE_NFC PH7"),
- PINCTRL_PIN(TEGRA_PIN_NFC_EN_PI0, "NFC_EN PI0"),
- PINCTRL_PIN(TEGRA_PIN_NFC_INT_PI1, "NFC_INT PI1"),
- PINCTRL_PIN(TEGRA_PIN_GPS_EN_PI2, "GPS_EN PI2"),
- PINCTRL_PIN(TEGRA_PIN_GPS_RST_PI3, "GPS_RST PI3"),
- PINCTRL_PIN(TEGRA_PIN_UART4_TX_PI4, "UART4_TX PI4"),
- PINCTRL_PIN(TEGRA_PIN_UART4_RX_PI5, "UART4_RX PI5"),
- PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PI6, "UART4_RTS PI6"),
- PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PI7, "UART4_CTS PI7"),
- PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PJ0, "GEN1_I2C_SDA PJ0"),
- PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PJ1, "GEN1_I2C_SCL PJ1"),
- PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PJ2, "GEN2_I2C_SCL PJ2"),
- PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PJ3, "GEN2_I2C_SDA PJ3"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PJ4, "DAP4_FS PJ4"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PJ5, "DAP4_DIN PJ5"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PJ6, "DAP4_DOUT PJ6"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PJ7, "DAP4_SCLK PJ7"),
- PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
- PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
- PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
- PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
- PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
- PINCTRL_PIN(TEGRA_PIN_PK5, "PK5"),
- PINCTRL_PIN(TEGRA_PIN_PK6, "PK6"),
- PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
- PINCTRL_PIN(TEGRA_PIN_PL0, "PL0"),
- PINCTRL_PIN(TEGRA_PIN_PL1, "PL1"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PM0, "SDMMC1_CLK PM0"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PM1, "SDMMC1_CMD PM1"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PM2, "SDMMC1_DAT3 PM2"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PM3, "SDMMC1_DAT2 PM3"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PM4, "SDMMC1_DAT1 PM4"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PM5, "SDMMC1_DAT0 PM5"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PP0, "SDMMC3_CLK PP0"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PP1, "SDMMC3_CMD PP1"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PP2, "SDMMC3_DAT3 PP2"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PP3, "SDMMC3_DAT2 PP3"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PP4, "SDMMC3_DAT1 PP4"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PP5, "SDMMC3_DAT0 PP5"),
- PINCTRL_PIN(TEGRA_PIN_CAM1_MCLK_PS0, "CAM1_MCLK PS0"),
- PINCTRL_PIN(TEGRA_PIN_CAM2_MCLK_PS1, "CAM2_MCLK PS1"),
- PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PS2, "CAM_I2C_SCL PS2"),
- PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PS3, "CAM_I2C_SDA PS3"),
- PINCTRL_PIN(TEGRA_PIN_CAM_RST_PS4, "CAM_RST PS4"),
- PINCTRL_PIN(TEGRA_PIN_CAM_AF_EN_PS5, "CAM_AF_EN PS5"),
- PINCTRL_PIN(TEGRA_PIN_CAM_FLASH_EN_PS6, "CAM_FLASH_EN PS6"),
- PINCTRL_PIN(TEGRA_PIN_CAM1_PWDN_PS7, "CAM1_PWDN PS7"),
- PINCTRL_PIN(TEGRA_PIN_CAM2_PWDN_PT0, "CAM2_PWDN PT0"),
- PINCTRL_PIN(TEGRA_PIN_CAM1_STROBE_PT1, "CAM1_STROBE PT1"),
- PINCTRL_PIN(TEGRA_PIN_UART1_TX_PU0, "UART1_TX PU0"),
- PINCTRL_PIN(TEGRA_PIN_UART1_RX_PU1, "UART1_RX PU1"),
- PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PU2, "UART1_RTS PU2"),
- PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PU3, "UART1_CTS PU3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_BL_PWM_PV0, "LCD_BL_PWM PV0"),
- PINCTRL_PIN(TEGRA_PIN_LCD_BL_EN_PV1, "LCD_BL_EN PV1"),
- PINCTRL_PIN(TEGRA_PIN_LCD_RST_PV2, "LCD_RST PV2"),
- PINCTRL_PIN(TEGRA_PIN_LCD_GPIO1_PV3, "LCD_GPIO1 PV3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_GPIO2_PV4, "LCD_GPIO2 PV4"),
- PINCTRL_PIN(TEGRA_PIN_AP_READY_PV5, "AP_READY PV5"),
- PINCTRL_PIN(TEGRA_PIN_TOUCH_RST_PV6, "TOUCH_RST PV6"),
- PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PV7, "TOUCH_CLK PV7"),
- PINCTRL_PIN(TEGRA_PIN_MODEM_WAKE_AP_PX0, "MODEM_WAKE_AP PX0"),
- PINCTRL_PIN(TEGRA_PIN_TOUCH_INT_PX1, "TOUCH_INT PX1"),
- PINCTRL_PIN(TEGRA_PIN_MOTION_INT_PX2, "MOTION_INT PX2"),
- PINCTRL_PIN(TEGRA_PIN_ALS_PROX_INT_PX3, "ALS_PROX_INT PX3"),
- PINCTRL_PIN(TEGRA_PIN_TEMP_ALERT_PX4, "TEMP_ALERT PX4"),
- PINCTRL_PIN(TEGRA_PIN_BUTTON_POWER_ON_PX5, "BUTTON_POWER_ON PX5"),
- PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_UP_PX6, "BUTTON_VOL_UP PX6"),
- PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_DOWN_PX7, "BUTTON_VOL_DOWN PX7"),
- PINCTRL_PIN(TEGRA_PIN_BUTTON_SLIDE_SW_PY0, "BUTTON_SLIDE_SW PY0"),
- PINCTRL_PIN(TEGRA_PIN_BUTTON_HOME_PY1, "BUTTON_HOME PY1"),
- PINCTRL_PIN(TEGRA_PIN_LCD_TE_PY2, "LCD_TE PY2"),
- PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PY3, "PWR_I2C_SCL PY3"),
- PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PY4, "PWR_I2C_SDA PY4"),
- PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PY5, "CLK_32K_OUT PY5"),
- PINCTRL_PIN(TEGRA_PIN_PZ0, "PZ0"),
- PINCTRL_PIN(TEGRA_PIN_PZ1, "PZ1"),
- PINCTRL_PIN(TEGRA_PIN_PZ2, "PZ2"),
- PINCTRL_PIN(TEGRA_PIN_PZ3, "PZ3"),
- PINCTRL_PIN(TEGRA_PIN_PZ4, "PZ4"),
- PINCTRL_PIN(TEGRA_PIN_PZ5, "PZ5"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PAA0, "DAP2_FS PAA0"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PAA1, "DAP2_SCLK PAA1"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PAA2, "DAP2_DIN PAA2"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PAA3, "DAP2_DOUT PAA3"),
- PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PBB0, "AUD_MCLK PBB0"),
- PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PBB1, "DVFS_PWM PBB1"),
- PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PBB2, "DVFS_CLK PBB2"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PBB3, "GPIO_X1_AUD PBB3"),
- PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PBB4, "GPIO_X3_AUD PBB4"),
- PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PCC0, "HDMI_CEC PCC0"),
- PINCTRL_PIN(TEGRA_PIN_HDMI_INT_DP_HPD_PCC1, "HDMI_INT_DP_HPD PCC1"),
- PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PCC2, "SPDIF_OUT PCC2"),
- PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PCC3, "SPDIF_IN PCC3"),
- PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PCC4, "USB_VBUS_EN0 PCC4"),
- PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PCC5, "USB_VBUS_EN1 PCC5"),
- PINCTRL_PIN(TEGRA_PIN_DP_HPD0_PCC6, "DP_HPD0 PCC6"),
- PINCTRL_PIN(TEGRA_PIN_PCC7, "PCC7"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_PDD0, "SPI2_CS1 PDD0"),
- PINCTRL_PIN(TEGRA_PIN_QSPI_SCK_PEE0, "QSPI_SCK PEE0"),
- PINCTRL_PIN(TEGRA_PIN_QSPI_CS_N_PEE1, "QSPI_CS_N PEE1"),
- PINCTRL_PIN(TEGRA_PIN_QSPI_IO0_PEE2, "QSPI_IO0 PEE2"),
- PINCTRL_PIN(TEGRA_PIN_QSPI_IO1_PEE3, "QSPI_IO1 PEE3"),
- PINCTRL_PIN(TEGRA_PIN_QSPI_IO2_PEE4, "QSPI_IO2 PEE4"),
- PINCTRL_PIN(TEGRA_PIN_QSPI_IO3_PEE5, "QSPI_IO3 PEE5"),
- PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
- PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
- PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
- PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
- PINCTRL_PIN(TEGRA_PIN_BATT_BCL, "BATT_BCL"),
- PINCTRL_PIN(TEGRA_PIN_CLK_REQ, "CLK_REQ"),
- PINCTRL_PIN(TEGRA_PIN_SHUTDOWN, "SHUTDOWN"),
-};
-
-static const unsigned pex_l0_rst_n_pa0_pins[] = {
- TEGRA_PIN_PEX_L0_RST_N_PA0,
-};
-
-static const unsigned pex_l0_clkreq_n_pa1_pins[] = {
- TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
-};
-
-static const unsigned pex_wake_n_pa2_pins[] = {
- TEGRA_PIN_PEX_WAKE_N_PA2,
-};
-
-static const unsigned pex_l1_rst_n_pa3_pins[] = {
- TEGRA_PIN_PEX_L1_RST_N_PA3,
-};
-
-static const unsigned pex_l1_clkreq_n_pa4_pins[] = {
- TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
-};
-
-static const unsigned sata_led_active_pa5_pins[] = {
- TEGRA_PIN_SATA_LED_ACTIVE_PA5,
-};
-
-static const unsigned pa6_pins[] = {
- TEGRA_PIN_PA6,
-};
-
-static const unsigned dap1_fs_pb0_pins[] = {
- TEGRA_PIN_DAP1_FS_PB0,
-};
-
-static const unsigned dap1_din_pb1_pins[] = {
- TEGRA_PIN_DAP1_DIN_PB1,
-};
-
-static const unsigned dap1_dout_pb2_pins[] = {
- TEGRA_PIN_DAP1_DOUT_PB2,
-};
-
-static const unsigned dap1_sclk_pb3_pins[] = {
- TEGRA_PIN_DAP1_SCLK_PB3,
-};
-
-static const unsigned spi2_mosi_pb4_pins[] = {
- TEGRA_PIN_SPI2_MOSI_PB4,
-};
-
-static const unsigned spi2_miso_pb5_pins[] = {
- TEGRA_PIN_SPI2_MISO_PB5,
-};
-
-static const unsigned spi2_sck_pb6_pins[] = {
- TEGRA_PIN_SPI2_SCK_PB6,
-};
-
-static const unsigned spi2_cs0_pb7_pins[] = {
- TEGRA_PIN_SPI2_CS0_PB7,
-};
-
-static const unsigned spi1_mosi_pc0_pins[] = {
- TEGRA_PIN_SPI1_MOSI_PC0,
-};
-
-static const unsigned spi1_miso_pc1_pins[] = {
- TEGRA_PIN_SPI1_MISO_PC1,
-};
-
-static const unsigned spi1_sck_pc2_pins[] = {
- TEGRA_PIN_SPI1_SCK_PC2,
-};
-
-static const unsigned spi1_cs0_pc3_pins[] = {
- TEGRA_PIN_SPI1_CS0_PC3,
-};
-
-static const unsigned spi1_cs1_pc4_pins[] = {
- TEGRA_PIN_SPI1_CS1_PC4,
-};
-
-static const unsigned spi4_sck_pc5_pins[] = {
- TEGRA_PIN_SPI4_SCK_PC5,
-};
-
-static const unsigned spi4_cs0_pc6_pins[] = {
- TEGRA_PIN_SPI4_CS0_PC6,
-};
-
-static const unsigned spi4_mosi_pc7_pins[] = {
- TEGRA_PIN_SPI4_MOSI_PC7,
-};
-
-static const unsigned spi4_miso_pd0_pins[] = {
- TEGRA_PIN_SPI4_MISO_PD0,
-};
-
-static const unsigned uart3_tx_pd1_pins[] = {
- TEGRA_PIN_UART3_TX_PD1,
-};
-
-static const unsigned uart3_rx_pd2_pins[] = {
- TEGRA_PIN_UART3_RX_PD2,
-};
-
-static const unsigned uart3_rts_pd3_pins[] = {
- TEGRA_PIN_UART3_RTS_PD3,
-};
-
-static const unsigned uart3_cts_pd4_pins[] = {
- TEGRA_PIN_UART3_CTS_PD4,
-};
-
-static const unsigned dmic1_clk_pe0_pins[] = {
- TEGRA_PIN_DMIC1_CLK_PE0,
-};
-
-static const unsigned dmic1_dat_pe1_pins[] = {
- TEGRA_PIN_DMIC1_DAT_PE1,
-};
-
-static const unsigned dmic2_clk_pe2_pins[] = {
- TEGRA_PIN_DMIC2_CLK_PE2,
-};
-
-static const unsigned dmic2_dat_pe3_pins[] = {
- TEGRA_PIN_DMIC2_DAT_PE3,
-};
-
-static const unsigned dmic3_clk_pe4_pins[] = {
- TEGRA_PIN_DMIC3_CLK_PE4,
-};
-
-static const unsigned dmic3_dat_pe5_pins[] = {
- TEGRA_PIN_DMIC3_DAT_PE5,
-};
-
-static const unsigned pe6_pins[] = {
- TEGRA_PIN_PE6,
-};
-
-static const unsigned pe7_pins[] = {
- TEGRA_PIN_PE7,
-};
-
-static const unsigned gen3_i2c_scl_pf0_pins[] = {
- TEGRA_PIN_GEN3_I2C_SCL_PF0,
-};
-
-static const unsigned gen3_i2c_sda_pf1_pins[] = {
- TEGRA_PIN_GEN3_I2C_SDA_PF1,
-};
-
-static const unsigned uart2_tx_pg0_pins[] = {
- TEGRA_PIN_UART2_TX_PG0,
-};
-
-static const unsigned uart2_rx_pg1_pins[] = {
- TEGRA_PIN_UART2_RX_PG1,
-};
-
-static const unsigned uart2_rts_pg2_pins[] = {
- TEGRA_PIN_UART2_RTS_PG2,
-};
-
-static const unsigned uart2_cts_pg3_pins[] = {
- TEGRA_PIN_UART2_CTS_PG3,
-};
-
-static const unsigned wifi_en_ph0_pins[] = {
- TEGRA_PIN_WIFI_EN_PH0,
-};
-
-static const unsigned wifi_rst_ph1_pins[] = {
- TEGRA_PIN_WIFI_RST_PH1,
-};
-
-static const unsigned wifi_wake_ap_ph2_pins[] = {
- TEGRA_PIN_WIFI_WAKE_AP_PH2,
-};
-
-static const unsigned ap_wake_bt_ph3_pins[] = {
- TEGRA_PIN_AP_WAKE_BT_PH3,
-};
-
-static const unsigned bt_rst_ph4_pins[] = {
- TEGRA_PIN_BT_RST_PH4,
-};
-
-static const unsigned bt_wake_ap_ph5_pins[] = {
- TEGRA_PIN_BT_WAKE_AP_PH5,
-};
-
-static const unsigned ph6_pins[] = {
- TEGRA_PIN_PH6,
-};
-
-static const unsigned ap_wake_nfc_ph7_pins[] = {
- TEGRA_PIN_AP_WAKE_NFC_PH7,
-};
-
-static const unsigned nfc_en_pi0_pins[] = {
- TEGRA_PIN_NFC_EN_PI0,
-};
-
-static const unsigned nfc_int_pi1_pins[] = {
- TEGRA_PIN_NFC_INT_PI1,
-};
-
-static const unsigned gps_en_pi2_pins[] = {
- TEGRA_PIN_GPS_EN_PI2,
-};
-
-static const unsigned gps_rst_pi3_pins[] = {
- TEGRA_PIN_GPS_RST_PI3,
-};
-
-static const unsigned uart4_tx_pi4_pins[] = {
- TEGRA_PIN_UART4_TX_PI4,
-};
-
-static const unsigned uart4_rx_pi5_pins[] = {
- TEGRA_PIN_UART4_RX_PI5,
-};
-
-static const unsigned uart4_rts_pi6_pins[] = {
- TEGRA_PIN_UART4_RTS_PI6,
-};
-
-static const unsigned uart4_cts_pi7_pins[] = {
- TEGRA_PIN_UART4_CTS_PI7,
-};
-
-static const unsigned gen1_i2c_sda_pj0_pins[] = {
- TEGRA_PIN_GEN1_I2C_SDA_PJ0,
-};
-
-static const unsigned gen1_i2c_scl_pj1_pins[] = {
- TEGRA_PIN_GEN1_I2C_SCL_PJ1,
-};
-
-static const unsigned gen2_i2c_scl_pj2_pins[] = {
- TEGRA_PIN_GEN2_I2C_SCL_PJ2,
-};
-
-static const unsigned gen2_i2c_sda_pj3_pins[] = {
- TEGRA_PIN_GEN2_I2C_SDA_PJ3,
-};
-
-static const unsigned dap4_fs_pj4_pins[] = {
- TEGRA_PIN_DAP4_FS_PJ4,
-};
-
-static const unsigned dap4_din_pj5_pins[] = {
- TEGRA_PIN_DAP4_DIN_PJ5,
-};
-
-static const unsigned dap4_dout_pj6_pins[] = {
- TEGRA_PIN_DAP4_DOUT_PJ6,
-};
-
-static const unsigned dap4_sclk_pj7_pins[] = {
- TEGRA_PIN_DAP4_SCLK_PJ7,
-};
-
-static const unsigned pk0_pins[] = {
- TEGRA_PIN_PK0,
-};
-
-static const unsigned pk1_pins[] = {
- TEGRA_PIN_PK1,
-};
-
-static const unsigned pk2_pins[] = {
- TEGRA_PIN_PK2,
-};
-
-static const unsigned pk3_pins[] = {
- TEGRA_PIN_PK3,
-};
-
-static const unsigned pk4_pins[] = {
- TEGRA_PIN_PK4,
-};
-
-static const unsigned pk5_pins[] = {
- TEGRA_PIN_PK5,
-};
-
-static const unsigned pk6_pins[] = {
- TEGRA_PIN_PK6,
-};
-
-static const unsigned pk7_pins[] = {
- TEGRA_PIN_PK7,
-};
-
-static const unsigned pl0_pins[] = {
- TEGRA_PIN_PL0,
-};
-
-static const unsigned pl1_pins[] = {
- TEGRA_PIN_PL1,
-};
-
-static const unsigned sdmmc1_clk_pm0_pins[] = {
- TEGRA_PIN_SDMMC1_CLK_PM0,
-};
-
-static const unsigned sdmmc1_cmd_pm1_pins[] = {
- TEGRA_PIN_SDMMC1_CMD_PM1,
-};
-
-static const unsigned sdmmc1_dat3_pm2_pins[] = {
- TEGRA_PIN_SDMMC1_DAT3_PM2,
-};
-
-static const unsigned sdmmc1_dat2_pm3_pins[] = {
- TEGRA_PIN_SDMMC1_DAT2_PM3,
-};
-
-static const unsigned sdmmc1_dat1_pm4_pins[] = {
- TEGRA_PIN_SDMMC1_DAT1_PM4,
-};
-
-static const unsigned sdmmc1_dat0_pm5_pins[] = {
- TEGRA_PIN_SDMMC1_DAT0_PM5,
-};
-
-static const unsigned sdmmc3_clk_pp0_pins[] = {
- TEGRA_PIN_SDMMC3_CLK_PP0,
-};
-
-static const unsigned sdmmc3_cmd_pp1_pins[] = {
- TEGRA_PIN_SDMMC3_CMD_PP1,
-};
-
-static const unsigned sdmmc3_dat3_pp2_pins[] = {
- TEGRA_PIN_SDMMC3_DAT3_PP2,
-};
-
-static const unsigned sdmmc3_dat2_pp3_pins[] = {
- TEGRA_PIN_SDMMC3_DAT2_PP3,
-};
-
-static const unsigned sdmmc3_dat1_pp4_pins[] = {
- TEGRA_PIN_SDMMC3_DAT1_PP4,
-};
-
-static const unsigned sdmmc3_dat0_pp5_pins[] = {
- TEGRA_PIN_SDMMC3_DAT0_PP5,
-};
-
-static const unsigned cam1_mclk_ps0_pins[] = {
- TEGRA_PIN_CAM1_MCLK_PS0,
-};
-
-static const unsigned cam2_mclk_ps1_pins[] = {
- TEGRA_PIN_CAM2_MCLK_PS1,
-};
-
-static const unsigned cam_i2c_scl_ps2_pins[] = {
- TEGRA_PIN_CAM_I2C_SCL_PS2,
-};
-
-static const unsigned cam_i2c_sda_ps3_pins[] = {
- TEGRA_PIN_CAM_I2C_SDA_PS3,
-};
-
-static const unsigned cam_rst_ps4_pins[] = {
- TEGRA_PIN_CAM_RST_PS4,
-};
-
-static const unsigned cam_af_en_ps5_pins[] = {
- TEGRA_PIN_CAM_AF_EN_PS5,
-};
-
-static const unsigned cam_flash_en_ps6_pins[] = {
- TEGRA_PIN_CAM_FLASH_EN_PS6,
-};
-
-static const unsigned cam1_pwdn_ps7_pins[] = {
- TEGRA_PIN_CAM1_PWDN_PS7,
-};
-
-static const unsigned cam2_pwdn_pt0_pins[] = {
- TEGRA_PIN_CAM2_PWDN_PT0,
-};
-
-static const unsigned cam1_strobe_pt1_pins[] = {
- TEGRA_PIN_CAM1_STROBE_PT1,
-};
-
-static const unsigned uart1_tx_pu0_pins[] = {
- TEGRA_PIN_UART1_TX_PU0,
-};
-
-static const unsigned uart1_rx_pu1_pins[] = {
- TEGRA_PIN_UART1_RX_PU1,
-};
-
-static const unsigned uart1_rts_pu2_pins[] = {
- TEGRA_PIN_UART1_RTS_PU2,
-};
-
-static const unsigned uart1_cts_pu3_pins[] = {
- TEGRA_PIN_UART1_CTS_PU3,
-};
-
-static const unsigned lcd_bl_pwm_pv0_pins[] = {
- TEGRA_PIN_LCD_BL_PWM_PV0,
-};
-
-static const unsigned lcd_bl_en_pv1_pins[] = {
- TEGRA_PIN_LCD_BL_EN_PV1,
-};
-
-static const unsigned lcd_rst_pv2_pins[] = {
- TEGRA_PIN_LCD_RST_PV2,
-};
-
-static const unsigned lcd_gpio1_pv3_pins[] = {
- TEGRA_PIN_LCD_GPIO1_PV3,
-};
-
-static const unsigned lcd_gpio2_pv4_pins[] = {
- TEGRA_PIN_LCD_GPIO2_PV4,
-};
-
-static const unsigned ap_ready_pv5_pins[] = {
- TEGRA_PIN_AP_READY_PV5,
-};
-
-static const unsigned touch_rst_pv6_pins[] = {
- TEGRA_PIN_TOUCH_RST_PV6,
-};
-
-static const unsigned touch_clk_pv7_pins[] = {
- TEGRA_PIN_TOUCH_CLK_PV7,
-};
-
-static const unsigned modem_wake_ap_px0_pins[] = {
- TEGRA_PIN_MODEM_WAKE_AP_PX0,
-};
-
-static const unsigned touch_int_px1_pins[] = {
- TEGRA_PIN_TOUCH_INT_PX1,
-};
-
-static const unsigned motion_int_px2_pins[] = {
- TEGRA_PIN_MOTION_INT_PX2,
-};
-
-static const unsigned als_prox_int_px3_pins[] = {
- TEGRA_PIN_ALS_PROX_INT_PX3,
-};
-
-static const unsigned temp_alert_px4_pins[] = {
- TEGRA_PIN_TEMP_ALERT_PX4,
-};
-
-static const unsigned button_power_on_px5_pins[] = {
- TEGRA_PIN_BUTTON_POWER_ON_PX5,
-};
-
-static const unsigned button_vol_up_px6_pins[] = {
- TEGRA_PIN_BUTTON_VOL_UP_PX6,
-};
-
-static const unsigned button_vol_down_px7_pins[] = {
- TEGRA_PIN_BUTTON_VOL_DOWN_PX7,
-};
-
-static const unsigned button_slide_sw_py0_pins[] = {
- TEGRA_PIN_BUTTON_SLIDE_SW_PY0,
-};
-
-static const unsigned button_home_py1_pins[] = {
- TEGRA_PIN_BUTTON_HOME_PY1,
-};
-
-static const unsigned lcd_te_py2_pins[] = {
- TEGRA_PIN_LCD_TE_PY2,
-};
-
-static const unsigned pwr_i2c_scl_py3_pins[] = {
- TEGRA_PIN_PWR_I2C_SCL_PY3,
-};
-
-static const unsigned pwr_i2c_sda_py4_pins[] = {
- TEGRA_PIN_PWR_I2C_SDA_PY4,
-};
-
-static const unsigned clk_32k_out_py5_pins[] = {
- TEGRA_PIN_CLK_32K_OUT_PY5,
-};
-
-static const unsigned pz0_pins[] = {
- TEGRA_PIN_PZ0,
-};
-
-static const unsigned pz1_pins[] = {
- TEGRA_PIN_PZ1,
-};
-
-static const unsigned pz2_pins[] = {
- TEGRA_PIN_PZ2,
-};
-
-static const unsigned pz3_pins[] = {
- TEGRA_PIN_PZ3,
-};
-
-static const unsigned pz4_pins[] = {
- TEGRA_PIN_PZ4,
-};
-
-static const unsigned pz5_pins[] = {
- TEGRA_PIN_PZ5,
-};
-
-static const unsigned dap2_fs_paa0_pins[] = {
- TEGRA_PIN_DAP2_FS_PAA0,
-};
-
-static const unsigned dap2_sclk_paa1_pins[] = {
- TEGRA_PIN_DAP2_SCLK_PAA1,
-};
-
-static const unsigned dap2_din_paa2_pins[] = {
- TEGRA_PIN_DAP2_DIN_PAA2,
-};
-
-static const unsigned dap2_dout_paa3_pins[] = {
- TEGRA_PIN_DAP2_DOUT_PAA3,
-};
-
-static const unsigned aud_mclk_pbb0_pins[] = {
- TEGRA_PIN_AUD_MCLK_PBB0,
-};
-
-static const unsigned dvfs_pwm_pbb1_pins[] = {
- TEGRA_PIN_DVFS_PWM_PBB1,
-};
-
-static const unsigned dvfs_clk_pbb2_pins[] = {
- TEGRA_PIN_DVFS_CLK_PBB2,
-};
-
-static const unsigned gpio_x1_aud_pbb3_pins[] = {
- TEGRA_PIN_GPIO_X1_AUD_PBB3,
-};
-
-static const unsigned gpio_x3_aud_pbb4_pins[] = {
- TEGRA_PIN_GPIO_X3_AUD_PBB4,
-};
-
-static const unsigned hdmi_cec_pcc0_pins[] = {
- TEGRA_PIN_HDMI_CEC_PCC0,
-};
-
-static const unsigned hdmi_int_dp_hpd_pcc1_pins[] = {
- TEGRA_PIN_HDMI_INT_DP_HPD_PCC1,
-};
-
-static const unsigned spdif_out_pcc2_pins[] = {
- TEGRA_PIN_SPDIF_OUT_PCC2,
-};
-
-static const unsigned spdif_in_pcc3_pins[] = {
- TEGRA_PIN_SPDIF_IN_PCC3,
-};
-
-static const unsigned usb_vbus_en0_pcc4_pins[] = {
- TEGRA_PIN_USB_VBUS_EN0_PCC4,
-};
-
-static const unsigned usb_vbus_en1_pcc5_pins[] = {
- TEGRA_PIN_USB_VBUS_EN1_PCC5,
-};
-
-static const unsigned dp_hpd0_pcc6_pins[] = {
- TEGRA_PIN_DP_HPD0_PCC6,
-};
-
-static const unsigned pcc7_pins[] = {
- TEGRA_PIN_PCC7,
-};
-
-static const unsigned spi2_cs1_pdd0_pins[] = {
- TEGRA_PIN_SPI2_CS1_PDD0,
-};
-
-static const unsigned qspi_sck_pee0_pins[] = {
- TEGRA_PIN_QSPI_SCK_PEE0,
-};
-
-static const unsigned qspi_cs_n_pee1_pins[] = {
- TEGRA_PIN_QSPI_CS_N_PEE1,
-};
-
-static const unsigned qspi_io0_pee2_pins[] = {
- TEGRA_PIN_QSPI_IO0_PEE2,
-};
-
-static const unsigned qspi_io1_pee3_pins[] = {
- TEGRA_PIN_QSPI_IO1_PEE3,
-};
-
-static const unsigned qspi_io2_pee4_pins[] = {
- TEGRA_PIN_QSPI_IO2_PEE4,
-};
-
-static const unsigned qspi_io3_pee5_pins[] = {
- TEGRA_PIN_QSPI_IO3_PEE5,
-};
-
-static const unsigned core_pwr_req_pins[] = {
- TEGRA_PIN_CORE_PWR_REQ,
-};
-
-static const unsigned cpu_pwr_req_pins[] = {
- TEGRA_PIN_CPU_PWR_REQ,
-};
-
-static const unsigned pwr_int_n_pins[] = {
- TEGRA_PIN_PWR_INT_N,
-};
-
-static const unsigned clk_32k_in_pins[] = {
- TEGRA_PIN_CLK_32K_IN,
-};
-
-static const unsigned jtag_rtck_pins[] = {
- TEGRA_PIN_JTAG_RTCK,
-};
-
-static const unsigned batt_bcl_pins[] = {
- TEGRA_PIN_BATT_BCL,
-};
-
-static const unsigned clk_req_pins[] = {
- TEGRA_PIN_CLK_REQ,
-};
-
-static const unsigned shutdown_pins[] = {
- TEGRA_PIN_SHUTDOWN,
-};
-
-static const unsigned drive_pa6_pins[] = {
- TEGRA_PIN_PA6,
-};
-
-static const unsigned drive_pcc7_pins[] = {
- TEGRA_PIN_PCC7,
-};
-
-static const unsigned drive_pe6_pins[] = {
- TEGRA_PIN_PE6,
-};
-
-static const unsigned drive_pe7_pins[] = {
- TEGRA_PIN_PE7,
-};
-
-static const unsigned drive_ph6_pins[] = {
- TEGRA_PIN_PH6,
-};
-
-static const unsigned drive_pk0_pins[] = {
- TEGRA_PIN_PK0,
-};
-
-static const unsigned drive_pk1_pins[] = {
- TEGRA_PIN_PK1,
-};
-
-static const unsigned drive_pk2_pins[] = {
- TEGRA_PIN_PK2,
-};
-
-static const unsigned drive_pk3_pins[] = {
- TEGRA_PIN_PK3,
-};
-
-static const unsigned drive_pk4_pins[] = {
- TEGRA_PIN_PK4,
-};
-
-static const unsigned drive_pk5_pins[] = {
- TEGRA_PIN_PK5,
-};
-
-static const unsigned drive_pk6_pins[] = {
- TEGRA_PIN_PK6,
-};
-
-static const unsigned drive_pk7_pins[] = {
- TEGRA_PIN_PK7,
-};
-
-static const unsigned drive_pl0_pins[] = {
- TEGRA_PIN_PL0,
-};
-
-static const unsigned drive_pl1_pins[] = {
- TEGRA_PIN_PL1,
-};
-
-static const unsigned drive_pz0_pins[] = {
- TEGRA_PIN_PZ0,
-};
-
-static const unsigned drive_pz1_pins[] = {
- TEGRA_PIN_PZ1,
-};
-
-static const unsigned drive_pz2_pins[] = {
- TEGRA_PIN_PZ2,
-};
-
-static const unsigned drive_pz3_pins[] = {
- TEGRA_PIN_PZ3,
-};
-
-static const unsigned drive_pz4_pins[] = {
- TEGRA_PIN_PZ4,
-};
-
-static const unsigned drive_pz5_pins[] = {
- TEGRA_PIN_PZ5,
-};
-
-static const unsigned drive_sdmmc1_pins[] = {
- TEGRA_PIN_SDMMC1_CLK_PM0,
- TEGRA_PIN_SDMMC1_CMD_PM1,
- TEGRA_PIN_SDMMC1_DAT3_PM2,
- TEGRA_PIN_SDMMC1_DAT2_PM3,
- TEGRA_PIN_SDMMC1_DAT1_PM4,
- TEGRA_PIN_SDMMC1_DAT0_PM5,
-};
-
-static const unsigned drive_sdmmc2_pins[] = {
-};
-
-static const unsigned drive_sdmmc3_pins[] = {
- TEGRA_PIN_SDMMC3_CLK_PP0,
- TEGRA_PIN_SDMMC3_CMD_PP1,
- TEGRA_PIN_SDMMC3_DAT3_PP2,
- TEGRA_PIN_SDMMC3_DAT2_PP3,
- TEGRA_PIN_SDMMC3_DAT1_PP4,
- TEGRA_PIN_SDMMC3_DAT0_PP5,
-};
-
-static const unsigned drive_sdmmc4_pins[] = {
-};
-
-enum tegra_mux {
- TEGRA_MUX_AUD,
- TEGRA_MUX_BCL,
- TEGRA_MUX_BLINK,
- TEGRA_MUX_CCLA,
- TEGRA_MUX_CEC,
- TEGRA_MUX_CLDVFS,
- TEGRA_MUX_CLK,
- TEGRA_MUX_CORE,
- TEGRA_MUX_CPU,
- TEGRA_MUX_DISPLAYA,
- TEGRA_MUX_DISPLAYB,
- TEGRA_MUX_DMIC1,
- TEGRA_MUX_DMIC2,
- TEGRA_MUX_DMIC3,
- TEGRA_MUX_DP,
- TEGRA_MUX_DTV,
- TEGRA_MUX_EXTPERIPH3,
- TEGRA_MUX_I2C1,
- TEGRA_MUX_I2C2,
- TEGRA_MUX_I2C3,
- TEGRA_MUX_I2CPMU,
- TEGRA_MUX_I2CVI,
- TEGRA_MUX_I2S1,
- TEGRA_MUX_I2S2,
- TEGRA_MUX_I2S3,
- TEGRA_MUX_I2S4A,
- TEGRA_MUX_I2S4B,
- TEGRA_MUX_I2S5A,
- TEGRA_MUX_I2S5B,
- TEGRA_MUX_IQC0,
- TEGRA_MUX_IQC1,
- TEGRA_MUX_JTAG,
- TEGRA_MUX_PE,
- TEGRA_MUX_PE0,
- TEGRA_MUX_PE1,
- TEGRA_MUX_PMI,
- TEGRA_MUX_PWM0,
- TEGRA_MUX_PWM1,
- TEGRA_MUX_PWM2,
- TEGRA_MUX_PWM3,
- TEGRA_MUX_QSPI,
- TEGRA_MUX_RSVD0,
- TEGRA_MUX_RSVD1,
- TEGRA_MUX_RSVD2,
- TEGRA_MUX_RSVD3,
- TEGRA_MUX_SATA,
- TEGRA_MUX_SDMMC1,
- TEGRA_MUX_SDMMC3,
- TEGRA_MUX_SHUTDOWN,
- TEGRA_MUX_SOC,
- TEGRA_MUX_SOR0,
- TEGRA_MUX_SOR1,
- TEGRA_MUX_SPDIF,
- TEGRA_MUX_SPI1,
- TEGRA_MUX_SPI2,
- TEGRA_MUX_SPI3,
- TEGRA_MUX_SPI4,
- TEGRA_MUX_SYS,
- TEGRA_MUX_TOUCH,
- TEGRA_MUX_UART,
- TEGRA_MUX_UARTA,
- TEGRA_MUX_UARTB,
- TEGRA_MUX_UARTC,
- TEGRA_MUX_UARTD,
- TEGRA_MUX_USB,
- TEGRA_MUX_VGP1,
- TEGRA_MUX_VGP2,
- TEGRA_MUX_VGP3,
- TEGRA_MUX_VGP4,
- TEGRA_MUX_VGP5,
- TEGRA_MUX_VGP6,
- TEGRA_MUX_VIMCLK,
- TEGRA_MUX_VIMCLK2,
-};
-
-#define FUNCTION(fname) \
- { \
- .name = #fname, \
- }
-
-static struct tegra_function tegra210_functions[] = {
- FUNCTION(aud),
- FUNCTION(bcl),
- FUNCTION(blink),
- FUNCTION(ccla),
- FUNCTION(cec),
- FUNCTION(cldvfs),
- FUNCTION(clk),
- FUNCTION(core),
- FUNCTION(cpu),
- FUNCTION(displaya),
- FUNCTION(displayb),
- FUNCTION(dmic1),
- FUNCTION(dmic2),
- FUNCTION(dmic3),
- FUNCTION(dp),
- FUNCTION(dtv),
- FUNCTION(extperiph3),
- FUNCTION(i2c1),
- FUNCTION(i2c2),
- FUNCTION(i2c3),
- FUNCTION(i2cpmu),
- FUNCTION(i2cvi),
- FUNCTION(i2s1),
- FUNCTION(i2s2),
- FUNCTION(i2s3),
- FUNCTION(i2s4a),
- FUNCTION(i2s4b),
- FUNCTION(i2s5a),
- FUNCTION(i2s5b),
- FUNCTION(iqc0),
- FUNCTION(iqc1),
- FUNCTION(jtag),
- FUNCTION(pe),
- FUNCTION(pe0),
- FUNCTION(pe1),
- FUNCTION(pmi),
- FUNCTION(pwm0),
- FUNCTION(pwm1),
- FUNCTION(pwm2),
- FUNCTION(pwm3),
- FUNCTION(qspi),
- FUNCTION(rsvd0),
- FUNCTION(rsvd1),
- FUNCTION(rsvd2),
- FUNCTION(rsvd3),
- FUNCTION(sata),
- FUNCTION(sdmmc1),
- FUNCTION(sdmmc3),
- FUNCTION(shutdown),
- FUNCTION(soc),
- FUNCTION(sor0),
- FUNCTION(sor1),
- FUNCTION(spdif),
- FUNCTION(spi1),
- FUNCTION(spi2),
- FUNCTION(spi3),
- FUNCTION(spi4),
- FUNCTION(sys),
- FUNCTION(touch),
- FUNCTION(uart),
- FUNCTION(uarta),
- FUNCTION(uartb),
- FUNCTION(uartc),
- FUNCTION(uartd),
- FUNCTION(usb),
- FUNCTION(vgp1),
- FUNCTION(vgp2),
- FUNCTION(vgp3),
- FUNCTION(vgp4),
- FUNCTION(vgp5),
- FUNCTION(vgp6),
- FUNCTION(vimclk),
- FUNCTION(vimclk2),
-};
-
-#define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */
-#define PINGROUP_REG_A 0x3000 /* bank 1 */
-
-#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
-#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
-
-#define PINGROUP_BIT_Y(b) (b)
-#define PINGROUP_BIT_N(b) (-1)
-
-#define PINGROUP(pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, \
- rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, \
- slwr_w, slwf_b, slwf_w) \
- { \
- .name = #pg_name, \
- .pins = pg_name##_pins, \
- .npins = ARRAY_SIZE(pg_name##_pins), \
- .funcs = { \
- TEGRA_MUX_##f0, \
- TEGRA_MUX_##f1, \
- TEGRA_MUX_##f2, \
- TEGRA_MUX_##f3, \
- }, \
- .mux_reg = PINGROUP_REG(r), \
- .mux_bank = 1, \
- .mux_bit = 0, \
- .pupd_reg = PINGROUP_REG(r), \
- .pupd_bank = 1, \
- .pupd_bit = 2, \
- .tri_reg = PINGROUP_REG(r), \
- .tri_bank = 1, \
- .tri_bit = 4, \
- .einput_bit = 6, \
- .odrain_bit = 11, \
- .lock_bit = 7, \
- .ioreset_bit = -1, \
- .rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10), \
- .hsm_bit = PINGROUP_BIT_##hsm(9), \
- .schmitt_bit = 12, \
- .drvtype_bit = PINGROUP_BIT_##drvtype(13), \
- .drv_reg = DRV_PINGROUP_REG(rdrv), \
- .drv_bank = 0, \
- .lpmd_bit = -1, \
- .drvdn_bit = drvdn_b, \
- .drvdn_width = drvdn_w, \
- .drvup_bit = drvup_b, \
- .drvup_width = drvup_w, \
- .slwr_bit = slwr_b, \
- .slwr_width = slwr_w, \
- .slwf_bit = slwf_b, \
- .slwf_width = slwf_w, \
- }
-
-#define DRV_PINGROUP(pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, \
- slwr_b, slwr_w, slwf_b, slwf_w) \
- { \
- .name = "drive_" #pg_name, \
- .pins = drive_##pg_name##_pins, \
- .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
- .mux_reg = -1, \
- .pupd_reg = -1, \
- .tri_reg = -1, \
- .einput_bit = -1, \
- .odrain_bit = -1, \
- .lock_bit = -1, \
- .ioreset_bit = -1, \
- .rcv_sel_bit = -1, \
- .drv_reg = DRV_PINGROUP_REG(r), \
- .drv_bank = 0, \
- .hsm_bit = -1, \
- .schmitt_bit = -1, \
- .lpmd_bit = -1, \
- .drvdn_bit = drvdn_b, \
- .drvdn_width = drvdn_w, \
- .drvup_bit = drvup_b, \
- .drvup_width = drvup_w, \
- .slwr_bit = slwr_b, \
- .slwr_width = slwr_w, \
- .slwf_bit = slwf_b, \
- .slwf_width = slwf_w, \
- .drvtype_bit = -1, \
- }
-
-static const struct tegra_pingroup tegra210_groups[] = {
- /* pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
- PINGROUP(sdmmc1_clk_pm0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3000, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(sdmmc1_cmd_pm1, SDMMC1, SPI3, RSVD2, RSVD3, 0x3004, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(sdmmc1_dat3_pm2, SDMMC1, SPI3, RSVD2, RSVD3, 0x3008, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(sdmmc1_dat2_pm3, SDMMC1, SPI3, RSVD2, RSVD3, 0x300c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(sdmmc1_dat1_pm4, SDMMC1, SPI3, RSVD2, RSVD3, 0x3010, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(sdmmc1_dat0_pm5, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3014, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(sdmmc3_clk_pp0, SDMMC3, RSVD1, RSVD2, RSVD3, 0x301c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(sdmmc3_cmd_pp1, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3020, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(sdmmc3_dat0_pp5, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3024, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(sdmmc3_dat1_pp4, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3028, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(sdmmc3_dat2_pp3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x302c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(sdmmc3_dat3_pp2, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3030, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pex_l0_rst_n_pa0, PE0, RSVD1, RSVD2, RSVD3, 0x3038, N, N, Y, 0xa5c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(pex_l0_clkreq_n_pa1, PE0, RSVD1, RSVD2, RSVD3, 0x303c, N, N, Y, 0xa58, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(pex_wake_n_pa2, PE, RSVD1, RSVD2, RSVD3, 0x3040, N, N, Y, 0xa68, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(pex_l1_rst_n_pa3, PE1, RSVD1, RSVD2, RSVD3, 0x3044, N, N, Y, 0xa64, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(pex_l1_clkreq_n_pa4, PE1, RSVD1, RSVD2, RSVD3, 0x3048, N, N, Y, 0xa60, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(sata_led_active_pa5, SATA, RSVD1, RSVD2, RSVD3, 0x304c, N, N, N, 0xa94, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(spi1_mosi_pc0, SPI1, RSVD1, RSVD2, RSVD3, 0x3050, Y, Y, N, 0xae0, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(spi1_miso_pc1, SPI1, RSVD1, RSVD2, RSVD3, 0x3054, Y, Y, N, 0xadc, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(spi1_sck_pc2, SPI1, RSVD1, RSVD2, RSVD3, 0x3058, Y, Y, N, 0xae4, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(spi1_cs0_pc3, SPI1, RSVD1, RSVD2, RSVD3, 0x305c, Y, Y, N, 0xad4, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(spi1_cs1_pc4, SPI1, RSVD1, RSVD2, RSVD3, 0x3060, Y, Y, N, 0xad8, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(spi2_mosi_pb4, SPI2, DTV, RSVD2, RSVD3, 0x3064, Y, Y, N, 0xaf4, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(spi2_miso_pb5, SPI2, DTV, RSVD2, RSVD3, 0x3068, Y, Y, N, 0xaf0, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(spi2_sck_pb6, SPI2, DTV, RSVD2, RSVD3, 0x306c, Y, Y, N, 0xaf8, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(spi2_cs0_pb7, SPI2, DTV, RSVD2, RSVD3, 0x3070, Y, Y, N, 0xae8, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(spi2_cs1_pdd0, SPI2, RSVD1, RSVD2, RSVD3, 0x3074, Y, Y, N, 0xaec, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(spi4_mosi_pc7, SPI4, RSVD1, RSVD2, RSVD3, 0x3078, Y, Y, N, 0xb04, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(spi4_miso_pd0, SPI4, RSVD1, RSVD2, RSVD3, 0x307c, Y, Y, N, 0xb00, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(spi4_sck_pc5, SPI4, RSVD1, RSVD2, RSVD3, 0x3080, Y, Y, N, 0xb08, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(spi4_cs0_pc6, SPI4, RSVD1, RSVD2, RSVD3, 0x3084, Y, Y, N, 0xafc, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(qspi_sck_pee0, QSPI, RSVD1, RSVD2, RSVD3, 0x3088, Y, Y, N, 0xa90, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(qspi_cs_n_pee1, QSPI, RSVD1, RSVD2, RSVD3, 0x308c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(qspi_io0_pee2, QSPI, RSVD1, RSVD2, RSVD3, 0x3090, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(qspi_io1_pee3, QSPI, RSVD1, RSVD2, RSVD3, 0x3094, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(qspi_io2_pee4, QSPI, RSVD1, RSVD2, RSVD3, 0x3098, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(qspi_io3_pee5, QSPI, RSVD1, RSVD2, RSVD3, 0x309c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(dmic1_clk_pe0, DMIC1, I2S3, RSVD2, RSVD3, 0x30a4, N, N, N, 0x984, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(dmic1_dat_pe1, DMIC1, I2S3, RSVD2, RSVD3, 0x30a8, N, N, N, 0x988, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(dmic2_clk_pe2, DMIC2, I2S3, RSVD2, RSVD3, 0x30ac, N, N, N, 0x98c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(dmic2_dat_pe3, DMIC2, I2S3, RSVD2, RSVD3, 0x30b0, N, N, N, 0x990, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(dmic3_clk_pe4, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b4, N, N, N, 0x994, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(dmic3_dat_pe5, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b8, N, N, N, 0x998, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(gen1_i2c_scl_pj1, I2C1, RSVD1, RSVD2, RSVD3, 0x30bc, N, N, Y, 0x9a8, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(gen1_i2c_sda_pj0, I2C1, RSVD1, RSVD2, RSVD3, 0x30c0, N, N, Y, 0x9ac, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(gen2_i2c_scl_pj2, I2C2, RSVD1, RSVD2, RSVD3, 0x30c4, N, N, Y, 0x9b0, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(gen2_i2c_sda_pj3, I2C2, RSVD1, RSVD2, RSVD3, 0x30c8, N, N, Y, 0x9b4, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(gen3_i2c_scl_pf0, I2C3, RSVD1, RSVD2, RSVD3, 0x30cc, N, N, Y, 0x9b8, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(gen3_i2c_sda_pf1, I2C3, RSVD1, RSVD2, RSVD3, 0x30d0, N, N, Y, 0x9bc, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(cam_i2c_scl_ps2, I2C3, I2CVI, RSVD2, RSVD3, 0x30d4, N, N, Y, 0x934, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(cam_i2c_sda_ps3, I2C3, I2CVI, RSVD2, RSVD3, 0x30d8, N, N, Y, 0x938, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(pwr_i2c_scl_py3, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30dc, N, N, Y, 0xa6c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(pwr_i2c_sda_py4, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30e0, N, N, Y, 0xa70, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart1_tx_pu0, UARTA, RSVD1, RSVD2, RSVD3, 0x30e4, N, N, N, 0xb28, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart1_rx_pu1, UARTA, RSVD1, RSVD2, RSVD3, 0x30e8, N, N, N, 0xb24, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart1_rts_pu2, UARTA, RSVD1, RSVD2, RSVD3, 0x30ec, N, N, N, 0xb20, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart1_cts_pu3, UARTA, RSVD1, RSVD2, RSVD3, 0x30f0, N, N, N, 0xb1c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart2_tx_pg0, UARTB, I2S4A, SPDIF, UART, 0x30f4, N, N, N, 0xb38, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart2_rx_pg1, UARTB, I2S4A, SPDIF, UART, 0x30f8, N, N, N, 0xb34, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart2_rts_pg2, UARTB, I2S4A, RSVD2, UART, 0x30fc, N, N, N, 0xb30, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart2_cts_pg3, UARTB, I2S4A, RSVD2, UART, 0x3100, N, N, N, 0xb2c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart3_tx_pd1, UARTC, SPI4, RSVD2, RSVD3, 0x3104, N, N, N, 0xb48, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart3_rx_pd2, UARTC, SPI4, RSVD2, RSVD3, 0x3108, N, N, N, 0xb44, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart3_rts_pd3, UARTC, SPI4, RSVD2, RSVD3, 0x310c, N, N, N, 0xb40, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart3_cts_pd4, UARTC, SPI4, RSVD2, RSVD3, 0x3110, N, N, N, 0xb3c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart4_tx_pi4, UARTD, UART, RSVD2, RSVD3, 0x3114, N, N, N, 0xb58, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart4_rx_pi5, UARTD, UART, RSVD2, RSVD3, 0x3118, N, N, N, 0xb54, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart4_rts_pi6, UARTD, UART, RSVD2, RSVD3, 0x311c, N, N, N, 0xb50, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(uart4_cts_pi7, UARTD, UART, RSVD2, RSVD3, 0x3120, N, N, N, 0xb4c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(dap1_fs_pb0, I2S1, RSVD1, RSVD2, RSVD3, 0x3124, Y, Y, N, 0x95c, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(dap1_din_pb1, I2S1, RSVD1, RSVD2, RSVD3, 0x3128, Y, Y, N, 0x954, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(dap1_dout_pb2, I2S1, RSVD1, RSVD2, RSVD3, 0x312c, Y, Y, N, 0x958, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(dap1_sclk_pb3, I2S1, RSVD1, RSVD2, RSVD3, 0x3130, Y, Y, N, 0x960, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(dap2_fs_paa0, I2S2, RSVD1, RSVD2, RSVD3, 0x3134, Y, Y, N, 0x96c, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(dap2_din_paa2, I2S2, RSVD1, RSVD2, RSVD3, 0x3138, Y, Y, N, 0x964, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(dap2_dout_paa3, I2S2, RSVD1, RSVD2, RSVD3, 0x313c, Y, Y, N, 0x968, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(dap2_sclk_paa1, I2S2, RSVD1, RSVD2, RSVD3, 0x3140, Y, Y, N, 0x970, -1, -1, -1, -1, 28, 2, 30, 2),
- PINGROUP(dap4_fs_pj4, I2S4B, RSVD1, RSVD2, RSVD3, 0x3144, N, N, N, 0x97c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(dap4_din_pj5, I2S4B, RSVD1, RSVD2, RSVD3, 0x3148, N, N, N, 0x974, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(dap4_dout_pj6, I2S4B, RSVD1, RSVD2, RSVD3, 0x314c, N, N, N, 0x978, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(dap4_sclk_pj7, I2S4B, RSVD1, RSVD2, RSVD3, 0x3150, N, N, N, 0x980, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(cam1_mclk_ps0, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3154, N, N, N, 0x918, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(cam2_mclk_ps1, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3158, N, N, N, 0x924, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(jtag_rtck, JTAG, RSVD1, RSVD2, RSVD3, 0x315c, N, N, N, 0xa2c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(clk_32k_in, CLK, RSVD1, RSVD2, RSVD3, 0x3160, N, N, N, 0x940, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(clk_32k_out_py5, SOC, BLINK, RSVD2, RSVD3, 0x3164, N, N, N, 0x944, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(batt_bcl, BCL, RSVD1, RSVD2, RSVD3, 0x3168, N, N, Y, 0x8f8, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(clk_req, SYS, RSVD1, RSVD2, RSVD3, 0x316c, N, N, N, 0x948, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(cpu_pwr_req, CPU, RSVD1, RSVD2, RSVD3, 0x3170, N, N, N, 0x950, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(pwr_int_n, PMI, RSVD1, RSVD2, RSVD3, 0x3174, N, N, N, 0xa74, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(shutdown, SHUTDOWN, RSVD1, RSVD2, RSVD3, 0x3178, N, N, N, 0xac8, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(core_pwr_req, CORE, RSVD1, RSVD2, RSVD3, 0x317c, N, N, N, 0x94c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(aud_mclk_pbb0, AUD, RSVD1, RSVD2, RSVD3, 0x3180, N, N, N, 0x8f4, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(dvfs_pwm_pbb1, RSVD0, CLDVFS, SPI3, RSVD3, 0x3184, N, N, N, 0x9a4, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(dvfs_clk_pbb2, RSVD0, CLDVFS, SPI3, RSVD3, 0x3188, N, N, N, 0x9a0, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(gpio_x1_aud_pbb3, RSVD0, RSVD1, SPI3, RSVD3, 0x318c, N, N, N, 0xa14, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(gpio_x3_aud_pbb4, RSVD0, RSVD1, SPI3, RSVD3, 0x3190, N, N, N, 0xa18, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(pcc7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3194, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(hdmi_cec_pcc0, CEC, RSVD1, RSVD2, RSVD3, 0x3198, N, N, Y, 0xa24, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(hdmi_int_dp_hpd_pcc1, DP, RSVD1, RSVD2, RSVD3, 0x319c, N, N, Y, 0xa28, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(spdif_out_pcc2, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a0, N, N, N, 0xad0, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(spdif_in_pcc3, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a4, N, N, N, 0xacc, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(usb_vbus_en0_pcc4, USB, RSVD1, RSVD2, RSVD3, 0x31a8, N, N, Y, 0xb5c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(usb_vbus_en1_pcc5, USB, RSVD1, RSVD2, RSVD3, 0x31ac, N, N, Y, 0xb60, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(dp_hpd0_pcc6, DP, RSVD1, RSVD2, RSVD3, 0x31b0, N, N, N, 0x99c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(wifi_en_ph0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b4, N, N, N, 0xb64, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(wifi_rst_ph1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b8, N, N, N, 0xb68, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(wifi_wake_ap_ph2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31bc, N, N, N, 0xb6c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(ap_wake_bt_ph3, RSVD0, UARTB, SPDIF, RSVD3, 0x31c0, N, N, N, 0x8ec, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(bt_rst_ph4, RSVD0, UARTB, SPDIF, RSVD3, 0x31c4, N, N, N, 0x8fc, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(bt_wake_ap_ph5, RSVD0, RSVD1, RSVD2, RSVD3, 0x31c8, N, N, N, 0x900, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(ap_wake_nfc_ph7, RSVD0, RSVD1, RSVD2, RSVD3, 0x31cc, N, N, N, 0x8f0, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(nfc_en_pi0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d0, N, N, N, 0xa50, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(nfc_int_pi1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d4, N, N, N, 0xa54, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(gps_en_pi2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d8, N, N, N, 0xa1c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(gps_rst_pi3, RSVD0, RSVD1, RSVD2, RSVD3, 0x31dc, N, N, N, 0xa20, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(cam_rst_ps4, VGP1, RSVD1, RSVD2, RSVD3, 0x31e0, N, N, N, 0x93c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(cam_af_en_ps5, VIMCLK, VGP2, RSVD2, RSVD3, 0x31e4, N, N, N, 0x92c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(cam_flash_en_ps6, VIMCLK, VGP3, RSVD2, RSVD3, 0x31e8, N, N, N, 0x930, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(cam1_pwdn_ps7, VGP4, RSVD1, RSVD2, RSVD3, 0x31ec, N, N, N, 0x91c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(cam2_pwdn_pt0, VGP5, RSVD1, RSVD2, RSVD3, 0x31f0, N, N, N, 0x928, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(cam1_strobe_pt1, VGP6, RSVD1, RSVD2, RSVD3, 0x31f4, N, N, N, 0x920, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(lcd_te_py2, DISPLAYA, RSVD1, RSVD2, RSVD3, 0x31f8, N, N, N, 0xa44, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(lcd_bl_pwm_pv0, DISPLAYA, PWM0, SOR0, RSVD3, 0x31fc, N, N, N, 0xa34, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(lcd_bl_en_pv1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3200, N, N, N, 0xa30, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(lcd_rst_pv2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3204, N, N, N, 0xa40, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(lcd_gpio1_pv3, DISPLAYB, RSVD1, RSVD2, RSVD3, 0x3208, N, N, N, 0xa38, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(lcd_gpio2_pv4, DISPLAYB, PWM1, RSVD2, SOR1, 0x320c, N, N, N, 0xa3c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(ap_ready_pv5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3210, N, N, N, 0x8e8, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(touch_rst_pv6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3214, N, N, N, 0xb18, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(touch_clk_pv7, TOUCH, RSVD1, RSVD2, RSVD3, 0x3218, N, N, N, 0xb10, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(modem_wake_ap_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0x321c, N, N, N, 0xa48, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(touch_int_px1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3220, N, N, N, 0xb14, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(motion_int_px2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3224, N, N, N, 0xa4c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(als_prox_int_px3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3228, N, N, N, 0x8e4, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(temp_alert_px4, RSVD0, RSVD1, RSVD2, RSVD3, 0x322c, N, N, N, 0xb0c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(button_power_on_px5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3230, N, N, N, 0x908, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(button_vol_up_px6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3234, N, N, N, 0x914, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(button_vol_down_px7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3238, N, N, N, 0x910, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(button_slide_sw_py0, RSVD0, RSVD1, RSVD2, RSVD3, 0x323c, N, N, N, 0x90c, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(button_home_py1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3240, N, N, N, 0x904, 12, 5, 20, 5, -1, -1, -1, -1),
- PINGROUP(pa6, SATA, RSVD1, RSVD2, RSVD3, 0x3244, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pe6, RSVD0, I2S5A, PWM2, RSVD3, 0x3248, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pe7, RSVD0, I2S5A, PWM3, RSVD3, 0x324c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(ph6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3250, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pk0, IQC0, I2S5B, RSVD2, RSVD3, 0x3254, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pk1, IQC0, I2S5B, RSVD2, RSVD3, 0x3258, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pk2, IQC0, I2S5B, RSVD2, RSVD3, 0x325c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pk3, IQC0, I2S5B, RSVD2, RSVD3, 0x3260, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pk4, IQC1, RSVD1, RSVD2, RSVD3, 0x3264, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pk5, IQC1, RSVD1, RSVD2, RSVD3, 0x3268, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pk6, IQC1, RSVD1, RSVD2, RSVD3, 0x326c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pk7, IQC1, RSVD1, RSVD2, RSVD3, 0x3270, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pl0, RSVD0, RSVD1, RSVD2, RSVD3, 0x3274, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pl1, SOC, RSVD1, RSVD2, RSVD3, 0x3278, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pz0, VIMCLK2, RSVD1, RSVD2, RSVD3, 0x327c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pz1, VIMCLK2, SDMMC1, RSVD2, RSVD3, 0x3280, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pz2, SDMMC3, CCLA, RSVD2, RSVD3, 0x3284, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pz3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3288, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pz4, SDMMC1, RSVD1, RSVD2, RSVD3, 0x328c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
- PINGROUP(pz5, SOC, RSVD1, RSVD2, RSVD3, 0x3290, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
-
- /* pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
- DRV_PINGROUP(pa6, 0x9c0, 12, 5, 20, 5, -1, -1, -1, -1),
- DRV_PINGROUP(pcc7, 0x9c4, 12, 5, 20, 5, -1, -1, -1, -1),
- DRV_PINGROUP(pe6, 0x9c8, 12, 5, 20, 5, -1, -1, -1, -1),
- DRV_PINGROUP(pe7, 0x9cc, 12, 5, 20, 5, -1, -1, -1, -1),
- DRV_PINGROUP(ph6, 0x9d0, 12, 5, 20, 5, -1, -1, -1, -1),
- DRV_PINGROUP(pk0, 0x9d4, -1, -1, -1, -1, 28, 2, 30, 2),
- DRV_PINGROUP(pk1, 0x9d8, -1, -1, -1, -1, 28, 2, 30, 2),
- DRV_PINGROUP(pk2, 0x9dc, -1, -1, -1, -1, 28, 2, 30, 2),
- DRV_PINGROUP(pk3, 0x9e0, -1, -1, -1, -1, 28, 2, 30, 2),
- DRV_PINGROUP(pk4, 0x9e4, -1, -1, -1, -1, 28, 2, 30, 2),
- DRV_PINGROUP(pk5, 0x9e8, -1, -1, -1, -1, 28, 2, 30, 2),
- DRV_PINGROUP(pk6, 0x9ec, -1, -1, -1, -1, 28, 2, 30, 2),
- DRV_PINGROUP(pk7, 0x9f0, -1, -1, -1, -1, 28, 2, 30, 2),
- DRV_PINGROUP(pl0, 0x9f4, -1, -1, -1, -1, 28, 2, 30, 2),
- DRV_PINGROUP(pl1, 0x9f8, -1, -1, -1, -1, 28, 2, 30, 2),
- DRV_PINGROUP(pz0, 0x9fc, 12, 7, 20, 7, -1, -1, -1, -1),
- DRV_PINGROUP(pz1, 0xa00, 12, 7, 20, 7, -1, -1, -1, -1),
- DRV_PINGROUP(pz2, 0xa04, 12, 7, 20, 7, -1, -1, -1, -1),
- DRV_PINGROUP(pz3, 0xa08, 12, 7, 20, 7, -1, -1, -1, -1),
- DRV_PINGROUP(pz4, 0xa0c, 12, 7, 20, 7, -1, -1, -1, -1),
- DRV_PINGROUP(pz5, 0xa10, 12, 7, 20, 7, -1, -1, -1, -1),
- DRV_PINGROUP(sdmmc1, 0xa98, 12, 7, 20, 7, 28, 2, 30, 2),
- DRV_PINGROUP(sdmmc2, 0xa9c, 2, 6, 8, 6, 28, 2, 30, 2),
- DRV_PINGROUP(sdmmc3, 0xab0, 12, 7, 20, 7, 28, 2, 30, 2),
- DRV_PINGROUP(sdmmc4, 0xab4, 2, 6, 8, 6, 28, 2, 30, 2),
-};
-
-static const struct tegra_pinctrl_soc_data tegra210_pinctrl = {
- .ngpios = NUM_GPIOS,
- .pins = tegra210_pins,
- .npins = ARRAY_SIZE(tegra210_pins),
- .functions = tegra210_functions,
- .nfunctions = ARRAY_SIZE(tegra210_functions),
- .groups = tegra210_groups,
- .ngroups = ARRAY_SIZE(tegra210_groups),
- .hsm_in_mux = true,
- .schmitt_in_mux = true,
- .drvtype_in_mux = true,
-};
-
-static int tegra210_pinctrl_probe(struct platform_device *pdev)
-{
- return tegra_pinctrl_probe(pdev, &tegra210_pinctrl);
-}
-
-static const struct of_device_id tegra210_pinctrl_of_match[] = {
- { .compatible = "nvidia,tegra210-pinmux", },
- { },
-};
-MODULE_DEVICE_TABLE(of, tegra210_pinctrl_of_match);
-
-static struct platform_driver tegra210_pinctrl_driver = {
- .driver = {
- .name = "tegra210-pinctrl",
- .of_match_table = tegra210_pinctrl_of_match,
- },
- .probe = tegra210_pinctrl_probe,
- .remove = tegra_pinctrl_remove,
-};
-module_platform_driver(tegra210_pinctrl_driver);
-
-MODULE_AUTHOR("NVIDIA");
-MODULE_DESCRIPTION("NVIDIA Tegra210 pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * Pinctrl data for the NVIDIA Tegra30 pinmux
- *
- * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-
-#include "pinctrl-tegra.h"
-
-/*
- * Most pins affected by the pinmux can also be GPIOs. Define these first.
- * These must match how the GPIO driver names/numbers its pins.
- */
-#define _GPIO(offset) (offset)
-
-#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
-#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
-#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
-#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
-#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
-#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
-#define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
-#define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
-#define TEGRA_PIN_GMI_A17_PB0 _GPIO(8)
-#define TEGRA_PIN_GMI_A18_PB1 _GPIO(9)
-#define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10)
-#define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11)
-#define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
-#define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
-#define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
-#define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
-#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
-#define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17)
-#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
-#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
-#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
-#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
-#define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22)
-#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
-#define TEGRA_PIN_SDMMC3_DAT5_PD0 _GPIO(24)
-#define TEGRA_PIN_SDMMC3_DAT4_PD1 _GPIO(25)
-#define TEGRA_PIN_LCD_DC1_PD2 _GPIO(26)
-#define TEGRA_PIN_SDMMC3_DAT6_PD3 _GPIO(27)
-#define TEGRA_PIN_SDMMC3_DAT7_PD4 _GPIO(28)
-#define TEGRA_PIN_VI_D1_PD5 _GPIO(29)
-#define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30)
-#define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31)
-#define TEGRA_PIN_LCD_D0_PE0 _GPIO(32)
-#define TEGRA_PIN_LCD_D1_PE1 _GPIO(33)
-#define TEGRA_PIN_LCD_D2_PE2 _GPIO(34)
-#define TEGRA_PIN_LCD_D3_PE3 _GPIO(35)
-#define TEGRA_PIN_LCD_D4_PE4 _GPIO(36)
-#define TEGRA_PIN_LCD_D5_PE5 _GPIO(37)
-#define TEGRA_PIN_LCD_D6_PE6 _GPIO(38)
-#define TEGRA_PIN_LCD_D7_PE7 _GPIO(39)
-#define TEGRA_PIN_LCD_D8_PF0 _GPIO(40)
-#define TEGRA_PIN_LCD_D9_PF1 _GPIO(41)
-#define TEGRA_PIN_LCD_D10_PF2 _GPIO(42)
-#define TEGRA_PIN_LCD_D11_PF3 _GPIO(43)
-#define TEGRA_PIN_LCD_D12_PF4 _GPIO(44)
-#define TEGRA_PIN_LCD_D13_PF5 _GPIO(45)
-#define TEGRA_PIN_LCD_D14_PF6 _GPIO(46)
-#define TEGRA_PIN_LCD_D15_PF7 _GPIO(47)
-#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
-#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
-#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
-#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
-#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
-#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
-#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
-#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
-#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
-#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
-#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
-#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
-#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
-#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
-#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
-#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
-#define TEGRA_PIN_GMI_WR_N_PI0 _GPIO(64)
-#define TEGRA_PIN_GMI_OE_N_PI1 _GPIO(65)
-#define TEGRA_PIN_GMI_DQS_PI2 _GPIO(66)
-#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
-#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
-#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
-#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
-#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
-#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
-#define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73)
-#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
-#define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75)
-#define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76)
-#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
-#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
-#define TEGRA_PIN_GMI_A16_PJ7 _GPIO(79)
-#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
-#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
-#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
-#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
-#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
-#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
-#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
-#define TEGRA_PIN_GMI_A19_PK7 _GPIO(87)
-#define TEGRA_PIN_VI_D2_PL0 _GPIO(88)
-#define TEGRA_PIN_VI_D3_PL1 _GPIO(89)
-#define TEGRA_PIN_VI_D4_PL2 _GPIO(90)
-#define TEGRA_PIN_VI_D5_PL3 _GPIO(91)
-#define TEGRA_PIN_VI_D6_PL4 _GPIO(92)
-#define TEGRA_PIN_VI_D7_PL5 _GPIO(93)
-#define TEGRA_PIN_VI_D8_PL6 _GPIO(94)
-#define TEGRA_PIN_VI_D9_PL7 _GPIO(95)
-#define TEGRA_PIN_LCD_D16_PM0 _GPIO(96)
-#define TEGRA_PIN_LCD_D17_PM1 _GPIO(97)
-#define TEGRA_PIN_LCD_D18_PM2 _GPIO(98)
-#define TEGRA_PIN_LCD_D19_PM3 _GPIO(99)
-#define TEGRA_PIN_LCD_D20_PM4 _GPIO(100)
-#define TEGRA_PIN_LCD_D21_PM5 _GPIO(101)
-#define TEGRA_PIN_LCD_D22_PM6 _GPIO(102)
-#define TEGRA_PIN_LCD_D23_PM7 _GPIO(103)
-#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
-#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
-#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
-#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
-#define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108)
-#define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109)
-#define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110)
-#define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
-#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
-#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
-#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
-#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
-#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
-#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
-#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
-#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
-#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
-#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
-#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
-#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
-#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
-#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
-#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
-#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
-#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
-#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
-#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
-#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
-#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
-#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
-#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
-#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
-#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
-#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
-#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
-#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
-#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
-#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
-#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
-#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
-#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
-#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
-#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
-#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
-#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
-#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
-#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
-#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
-#define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152)
-#define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153)
-#define TEGRA_PIN_VI_D10_PT2 _GPIO(154)
-#define TEGRA_PIN_VI_D11_PT3 _GPIO(155)
-#define TEGRA_PIN_VI_D0_PT4 _GPIO(156)
-#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
-#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
-#define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
-#define TEGRA_PIN_PU0 _GPIO(160)
-#define TEGRA_PIN_PU1 _GPIO(161)
-#define TEGRA_PIN_PU2 _GPIO(162)
-#define TEGRA_PIN_PU3 _GPIO(163)
-#define TEGRA_PIN_PU4 _GPIO(164)
-#define TEGRA_PIN_PU5 _GPIO(165)
-#define TEGRA_PIN_PU6 _GPIO(166)
-#define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167)
-#define TEGRA_PIN_PV0 _GPIO(168)
-#define TEGRA_PIN_PV1 _GPIO(169)
-#define TEGRA_PIN_PV2 _GPIO(170)
-#define TEGRA_PIN_PV3 _GPIO(171)
-#define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
-#define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
-#define TEGRA_PIN_CRT_HSYNC_PV6 _GPIO(174)
-#define TEGRA_PIN_CRT_VSYNC_PV7 _GPIO(175)
-#define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176)
-#define TEGRA_PIN_LCD_M1_PW1 _GPIO(177)
-#define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178)
-#define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179)
-#define TEGRA_PIN_CLK1_OUT_PW4 _GPIO(180)
-#define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
-#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
-#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
-#define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184)
-#define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185)
-#define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186)
-#define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187)
-#define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188)
-#define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189)
-#define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190)
-#define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191)
-#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
-#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
-#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
-#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
-#define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
-#define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
-#define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
-#define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
-#define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
-#define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
-#define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202)
-#define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203)
-#define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204)
-#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
-#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
-#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
-#define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
-#define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
-#define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
-#define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
-#define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
-#define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
-#define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
-#define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
-#define TEGRA_PIN_PBB0 _GPIO(216)
-#define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
-#define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
-#define TEGRA_PIN_PBB3 _GPIO(219)
-#define TEGRA_PIN_PBB4 _GPIO(220)
-#define TEGRA_PIN_PBB5 _GPIO(221)
-#define TEGRA_PIN_PBB6 _GPIO(222)
-#define TEGRA_PIN_PBB7 _GPIO(223)
-#define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
-#define TEGRA_PIN_PCC1 _GPIO(225)
-#define TEGRA_PIN_PCC2 _GPIO(226)
-#define TEGRA_PIN_SDMMC4_RST_N_PCC3 _GPIO(227)
-#define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
-#define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
-#define TEGRA_PIN_PEX_L2_RST_N_PCC6 _GPIO(230)
-#define TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7 _GPIO(231)
-#define TEGRA_PIN_PEX_L0_PRSNT_N_PDD0 _GPIO(232)
-#define TEGRA_PIN_PEX_L0_RST_N_PDD1 _GPIO(233)
-#define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2 _GPIO(234)
-#define TEGRA_PIN_PEX_WAKE_N_PDD3 _GPIO(235)
-#define TEGRA_PIN_PEX_L1_PRSNT_N_PDD4 _GPIO(236)
-#define TEGRA_PIN_PEX_L1_RST_N_PDD5 _GPIO(237)
-#define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6 _GPIO(238)
-#define TEGRA_PIN_PEX_L2_PRSNT_N_PDD7 _GPIO(239)
-#define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
-#define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
-#define TEGRA_PIN_CLK1_REQ_PEE2 _GPIO(242)
-#define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
-#define TEGRA_PIN_PEE4 _GPIO(244)
-#define TEGRA_PIN_PEE5 _GPIO(245)
-#define TEGRA_PIN_PEE6 _GPIO(246)
-#define TEGRA_PIN_PEE7 _GPIO(247)
-
-/* All non-GPIO pins follow */
-#define NUM_GPIOS (TEGRA_PIN_PEE7 + 1)
-#define _PIN(offset) (NUM_GPIOS + (offset))
-
-/* Non-GPIO pins */
-#define TEGRA_PIN_CLK_32K_IN _PIN(0)
-#define TEGRA_PIN_CORE_PWR_REQ _PIN(1)
-#define TEGRA_PIN_CPU_PWR_REQ _PIN(2)
-#define TEGRA_PIN_JTAG_TCK _PIN(3)
-#define TEGRA_PIN_JTAG_TDI _PIN(4)
-#define TEGRA_PIN_JTAG_TDO _PIN(5)
-#define TEGRA_PIN_JTAG_TMS _PIN(6)
-#define TEGRA_PIN_JTAG_TRST_N _PIN(7)
-#define TEGRA_PIN_OWR _PIN(8)
-#define TEGRA_PIN_PWR_INT_N _PIN(9)
-#define TEGRA_PIN_SYS_RESET_N _PIN(10)
-#define TEGRA_PIN_TEST_MODE_EN _PIN(11)
-
-static const struct pinctrl_pin_desc tegra30_pins[] = {
- PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
- PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
- PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
- PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
- PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
- PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
- PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
- PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
- PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
- PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
- PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
- PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT5_PD0, "SDMMC3_DAT5 PD0"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, "SDMMC3_DAT4 PD1"),
- PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, "LCD_DC1 PD2"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, "SDMMC3_DAT6 PD3"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, "SDMMC3_DAT7 PD4"),
- PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
- PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
- PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_DQS_PI2, "GMI_DQS PI2"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
- PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
- PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
- PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
- PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
- PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
- PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
- PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
- PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
- PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
- PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
- PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
- PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
- PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
- PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
- PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
- PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
- PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
- PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
- PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
- PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
- PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
- PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
- PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
- PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
- PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
- PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
- PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
- PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
- PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
- PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
- PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VI_D10 PT2"),
- PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
- PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
- PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
- PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
- PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
- PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
- PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
- PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
- PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
- PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
- PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
- PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
- PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
- PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
- PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
- PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
- PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
- PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC_PV6, "CRT_HSYNC PV6"),
- PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC_PV7, "CRT_VSYNC PV7"),
- PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
- PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
- PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
- PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
- PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
- PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
- PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
- PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
- PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
- PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
- PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
- PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
- PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
- PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
- PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
- PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
- PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
- PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
- PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
- PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
- PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
- PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
- PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
- PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
- PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
- PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
- PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
- PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_RST_N_PCC3, "SDMMC4_RST_N PCC3"),
- PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
- PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PCC6, "PEX_L2_RST_N PCC6"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7, "PEX_L2_CLKREQ_N PCC7"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L0_PRSNT_N_PDD0, "PEX_L0_PRSNT_N PDD0"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
- PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L1_PRSNT_N_PDD4, "PEX_L1_PRSNT_N PDD4"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
- PINCTRL_PIN(TEGRA_PIN_PEX_L2_PRSNT_N_PDD7, "PEX_L2_PRSNT_N PDD7"),
- PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
- PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
- PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
- PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
- PINCTRL_PIN(TEGRA_PIN_PEE4, "PEE4"),
- PINCTRL_PIN(TEGRA_PIN_PEE5, "PEE5"),
- PINCTRL_PIN(TEGRA_PIN_PEE6, "PEE6"),
- PINCTRL_PIN(TEGRA_PIN_PEE7, "PEE7"),
- PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
- PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
- PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
- PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
- PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
- PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
- PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
- PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
-};
-
-static const unsigned clk_32k_out_pa0_pins[] = {
- TEGRA_PIN_CLK_32K_OUT_PA0,
-};
-
-static const unsigned uart3_cts_n_pa1_pins[] = {
- TEGRA_PIN_UART3_CTS_N_PA1,
-};
-
-static const unsigned dap2_fs_pa2_pins[] = {
- TEGRA_PIN_DAP2_FS_PA2,
-};
-
-static const unsigned dap2_sclk_pa3_pins[] = {
- TEGRA_PIN_DAP2_SCLK_PA3,
-};
-
-static const unsigned dap2_din_pa4_pins[] = {
- TEGRA_PIN_DAP2_DIN_PA4,
-};
-
-static const unsigned dap2_dout_pa5_pins[] = {
- TEGRA_PIN_DAP2_DOUT_PA5,
-};
-
-static const unsigned sdmmc3_clk_pa6_pins[] = {
- TEGRA_PIN_SDMMC3_CLK_PA6,
-};
-
-static const unsigned sdmmc3_cmd_pa7_pins[] = {
- TEGRA_PIN_SDMMC3_CMD_PA7,
-};
-
-static const unsigned gmi_a17_pb0_pins[] = {
- TEGRA_PIN_GMI_A17_PB0,
-};
-
-static const unsigned gmi_a18_pb1_pins[] = {
- TEGRA_PIN_GMI_A18_PB1,
-};
-
-static const unsigned lcd_pwr0_pb2_pins[] = {
- TEGRA_PIN_LCD_PWR0_PB2,
-};
-
-static const unsigned lcd_pclk_pb3_pins[] = {
- TEGRA_PIN_LCD_PCLK_PB3,
-};
-
-static const unsigned sdmmc3_dat3_pb4_pins[] = {
- TEGRA_PIN_SDMMC3_DAT3_PB4,
-};
-
-static const unsigned sdmmc3_dat2_pb5_pins[] = {
- TEGRA_PIN_SDMMC3_DAT2_PB5,
-};
-
-static const unsigned sdmmc3_dat1_pb6_pins[] = {
- TEGRA_PIN_SDMMC3_DAT1_PB6,
-};
-
-static const unsigned sdmmc3_dat0_pb7_pins[] = {
- TEGRA_PIN_SDMMC3_DAT0_PB7,
-};
-
-static const unsigned uart3_rts_n_pc0_pins[] = {
- TEGRA_PIN_UART3_RTS_N_PC0,
-};
-
-static const unsigned lcd_pwr1_pc1_pins[] = {
- TEGRA_PIN_LCD_PWR1_PC1,
-};
-
-static const unsigned uart2_txd_pc2_pins[] = {
- TEGRA_PIN_UART2_TXD_PC2,
-};
-
-static const unsigned uart2_rxd_pc3_pins[] = {
- TEGRA_PIN_UART2_RXD_PC3,
-};
-
-static const unsigned gen1_i2c_scl_pc4_pins[] = {
- TEGRA_PIN_GEN1_I2C_SCL_PC4,
-};
-
-static const unsigned gen1_i2c_sda_pc5_pins[] = {
- TEGRA_PIN_GEN1_I2C_SDA_PC5,
-};
-
-static const unsigned lcd_pwr2_pc6_pins[] = {
- TEGRA_PIN_LCD_PWR2_PC6,
-};
-
-static const unsigned gmi_wp_n_pc7_pins[] = {
- TEGRA_PIN_GMI_WP_N_PC7,
-};
-
-static const unsigned sdmmc3_dat5_pd0_pins[] = {
- TEGRA_PIN_SDMMC3_DAT5_PD0,
-};
-
-static const unsigned sdmmc3_dat4_pd1_pins[] = {
- TEGRA_PIN_SDMMC3_DAT4_PD1,
-};
-
-static const unsigned lcd_dc1_pd2_pins[] = {
- TEGRA_PIN_LCD_DC1_PD2,
-};
-
-static const unsigned sdmmc3_dat6_pd3_pins[] = {
- TEGRA_PIN_SDMMC3_DAT6_PD3,
-};
-
-static const unsigned sdmmc3_dat7_pd4_pins[] = {
- TEGRA_PIN_SDMMC3_DAT7_PD4,
-};
-
-static const unsigned vi_d1_pd5_pins[] = {
- TEGRA_PIN_VI_D1_PD5,
-};
-
-static const unsigned vi_vsync_pd6_pins[] = {
- TEGRA_PIN_VI_VSYNC_PD6,
-};
-
-static const unsigned vi_hsync_pd7_pins[] = {
- TEGRA_PIN_VI_HSYNC_PD7,
-};
-
-static const unsigned lcd_d0_pe0_pins[] = {
- TEGRA_PIN_LCD_D0_PE0,
-};
-
-static const unsigned lcd_d1_pe1_pins[] = {
- TEGRA_PIN_LCD_D1_PE1,
-};
-
-static const unsigned lcd_d2_pe2_pins[] = {
- TEGRA_PIN_LCD_D2_PE2,
-};
-
-static const unsigned lcd_d3_pe3_pins[] = {
- TEGRA_PIN_LCD_D3_PE3,
-};
-
-static const unsigned lcd_d4_pe4_pins[] = {
- TEGRA_PIN_LCD_D4_PE4,
-};
-
-static const unsigned lcd_d5_pe5_pins[] = {
- TEGRA_PIN_LCD_D5_PE5,
-};
-
-static const unsigned lcd_d6_pe6_pins[] = {
- TEGRA_PIN_LCD_D6_PE6,
-};
-
-static const unsigned lcd_d7_pe7_pins[] = {
- TEGRA_PIN_LCD_D7_PE7,
-};
-
-static const unsigned lcd_d8_pf0_pins[] = {
- TEGRA_PIN_LCD_D8_PF0,
-};
-
-static const unsigned lcd_d9_pf1_pins[] = {
- TEGRA_PIN_LCD_D9_PF1,
-};
-
-static const unsigned lcd_d10_pf2_pins[] = {
- TEGRA_PIN_LCD_D10_PF2,
-};
-
-static const unsigned lcd_d11_pf3_pins[] = {
- TEGRA_PIN_LCD_D11_PF3,
-};
-
-static const unsigned lcd_d12_pf4_pins[] = {
- TEGRA_PIN_LCD_D12_PF4,
-};
-
-static const unsigned lcd_d13_pf5_pins[] = {
- TEGRA_PIN_LCD_D13_PF5,
-};
-
-static const unsigned lcd_d14_pf6_pins[] = {
- TEGRA_PIN_LCD_D14_PF6,
-};
-
-static const unsigned lcd_d15_pf7_pins[] = {
- TEGRA_PIN_LCD_D15_PF7,
-};
-
-static const unsigned gmi_ad0_pg0_pins[] = {
- TEGRA_PIN_GMI_AD0_PG0,
-};
-
-static const unsigned gmi_ad1_pg1_pins[] = {
- TEGRA_PIN_GMI_AD1_PG1,
-};
-
-static const unsigned gmi_ad2_pg2_pins[] = {
- TEGRA_PIN_GMI_AD2_PG2,
-};
-
-static const unsigned gmi_ad3_pg3_pins[] = {
- TEGRA_PIN_GMI_AD3_PG3,
-};
-
-static const unsigned gmi_ad4_pg4_pins[] = {
- TEGRA_PIN_GMI_AD4_PG4,
-};
-
-static const unsigned gmi_ad5_pg5_pins[] = {
- TEGRA_PIN_GMI_AD5_PG5,
-};
-
-static const unsigned gmi_ad6_pg6_pins[] = {
- TEGRA_PIN_GMI_AD6_PG6,
-};
-
-static const unsigned gmi_ad7_pg7_pins[] = {
- TEGRA_PIN_GMI_AD7_PG7,
-};
-
-static const unsigned gmi_ad8_ph0_pins[] = {
- TEGRA_PIN_GMI_AD8_PH0,
-};
-
-static const unsigned gmi_ad9_ph1_pins[] = {
- TEGRA_PIN_GMI_AD9_PH1,
-};
-
-static const unsigned gmi_ad10_ph2_pins[] = {
- TEGRA_PIN_GMI_AD10_PH2,
-};
-
-static const unsigned gmi_ad11_ph3_pins[] = {
- TEGRA_PIN_GMI_AD11_PH3,
-};
-
-static const unsigned gmi_ad12_ph4_pins[] = {
- TEGRA_PIN_GMI_AD12_PH4,
-};
-
-static const unsigned gmi_ad13_ph5_pins[] = {
- TEGRA_PIN_GMI_AD13_PH5,
-};
-
-static const unsigned gmi_ad14_ph6_pins[] = {
- TEGRA_PIN_GMI_AD14_PH6,
-};
-
-static const unsigned gmi_ad15_ph7_pins[] = {
- TEGRA_PIN_GMI_AD15_PH7,
-};
-
-static const unsigned gmi_wr_n_pi0_pins[] = {
- TEGRA_PIN_GMI_WR_N_PI0,
-};
-
-static const unsigned gmi_oe_n_pi1_pins[] = {
- TEGRA_PIN_GMI_OE_N_PI1,
-};
-
-static const unsigned gmi_dqs_pi2_pins[] = {
- TEGRA_PIN_GMI_DQS_PI2,
-};
-
-static const unsigned gmi_cs6_n_pi3_pins[] = {
- TEGRA_PIN_GMI_CS6_N_PI3,
-};
-
-static const unsigned gmi_rst_n_pi4_pins[] = {
- TEGRA_PIN_GMI_RST_N_PI4,
-};
-
-static const unsigned gmi_iordy_pi5_pins[] = {
- TEGRA_PIN_GMI_IORDY_PI5,
-};
-
-static const unsigned gmi_cs7_n_pi6_pins[] = {
- TEGRA_PIN_GMI_CS7_N_PI6,
-};
-
-static const unsigned gmi_wait_pi7_pins[] = {
- TEGRA_PIN_GMI_WAIT_PI7,
-};
-
-static const unsigned gmi_cs0_n_pj0_pins[] = {
- TEGRA_PIN_GMI_CS0_N_PJ0,
-};
-
-static const unsigned lcd_de_pj1_pins[] = {
- TEGRA_PIN_LCD_DE_PJ1,
-};
-
-static const unsigned gmi_cs1_n_pj2_pins[] = {
- TEGRA_PIN_GMI_CS1_N_PJ2,
-};
-
-static const unsigned lcd_hsync_pj3_pins[] = {
- TEGRA_PIN_LCD_HSYNC_PJ3,
-};
-
-static const unsigned lcd_vsync_pj4_pins[] = {
- TEGRA_PIN_LCD_VSYNC_PJ4,
-};
-
-static const unsigned uart2_cts_n_pj5_pins[] = {
- TEGRA_PIN_UART2_CTS_N_PJ5,
-};
-
-static const unsigned uart2_rts_n_pj6_pins[] = {
- TEGRA_PIN_UART2_RTS_N_PJ6,
-};
-
-static const unsigned gmi_a16_pj7_pins[] = {
- TEGRA_PIN_GMI_A16_PJ7,
-};
-
-static const unsigned gmi_adv_n_pk0_pins[] = {
- TEGRA_PIN_GMI_ADV_N_PK0,
-};
-
-static const unsigned gmi_clk_pk1_pins[] = {
- TEGRA_PIN_GMI_CLK_PK1,
-};
-
-static const unsigned gmi_cs4_n_pk2_pins[] = {
- TEGRA_PIN_GMI_CS4_N_PK2,
-};
-
-static const unsigned gmi_cs2_n_pk3_pins[] = {
- TEGRA_PIN_GMI_CS2_N_PK3,
-};
-
-static const unsigned gmi_cs3_n_pk4_pins[] = {
- TEGRA_PIN_GMI_CS3_N_PK4,
-};
-
-static const unsigned spdif_out_pk5_pins[] = {
- TEGRA_PIN_SPDIF_OUT_PK5,
-};
-
-static const unsigned spdif_in_pk6_pins[] = {
- TEGRA_PIN_SPDIF_IN_PK6,
-};
-
-static const unsigned gmi_a19_pk7_pins[] = {
- TEGRA_PIN_GMI_A19_PK7,
-};
-
-static const unsigned vi_d2_pl0_pins[] = {
- TEGRA_PIN_VI_D2_PL0,
-};
-
-static const unsigned vi_d3_pl1_pins[] = {
- TEGRA_PIN_VI_D3_PL1,
-};
-
-static const unsigned vi_d4_pl2_pins[] = {
- TEGRA_PIN_VI_D4_PL2,
-};
-
-static const unsigned vi_d5_pl3_pins[] = {
- TEGRA_PIN_VI_D5_PL3,
-};
-
-static const unsigned vi_d6_pl4_pins[] = {
- TEGRA_PIN_VI_D6_PL4,
-};
-
-static const unsigned vi_d7_pl5_pins[] = {
- TEGRA_PIN_VI_D7_PL5,
-};
-
-static const unsigned vi_d8_pl6_pins[] = {
- TEGRA_PIN_VI_D8_PL6,
-};
-
-static const unsigned vi_d9_pl7_pins[] = {
- TEGRA_PIN_VI_D9_PL7,
-};
-
-static const unsigned lcd_d16_pm0_pins[] = {
- TEGRA_PIN_LCD_D16_PM0,
-};
-
-static const unsigned lcd_d17_pm1_pins[] = {
- TEGRA_PIN_LCD_D17_PM1,
-};
-
-static const unsigned lcd_d18_pm2_pins[] = {
- TEGRA_PIN_LCD_D18_PM2,
-};
-
-static const unsigned lcd_d19_pm3_pins[] = {
- TEGRA_PIN_LCD_D19_PM3,
-};
-
-static const unsigned lcd_d20_pm4_pins[] = {
- TEGRA_PIN_LCD_D20_PM4,
-};
-
-static const unsigned lcd_d21_pm5_pins[] = {
- TEGRA_PIN_LCD_D21_PM5,
-};
-
-static const unsigned lcd_d22_pm6_pins[] = {
- TEGRA_PIN_LCD_D22_PM6,
-};
-
-static const unsigned lcd_d23_pm7_pins[] = {
- TEGRA_PIN_LCD_D23_PM7,
-};
-
-static const unsigned dap1_fs_pn0_pins[] = {
- TEGRA_PIN_DAP1_FS_PN0,
-};
-
-static const unsigned dap1_din_pn1_pins[] = {
- TEGRA_PIN_DAP1_DIN_PN1,
-};
-
-static const unsigned dap1_dout_pn2_pins[] = {
- TEGRA_PIN_DAP1_DOUT_PN2,
-};
-
-static const unsigned dap1_sclk_pn3_pins[] = {
- TEGRA_PIN_DAP1_SCLK_PN3,
-};
-
-static const unsigned lcd_cs0_n_pn4_pins[] = {
- TEGRA_PIN_LCD_CS0_N_PN4,
-};
-
-static const unsigned lcd_sdout_pn5_pins[] = {
- TEGRA_PIN_LCD_SDOUT_PN5,
-};
-
-static const unsigned lcd_dc0_pn6_pins[] = {
- TEGRA_PIN_LCD_DC0_PN6,
-};
-
-static const unsigned hdmi_int_pn7_pins[] = {
- TEGRA_PIN_HDMI_INT_PN7,
-};
-
-static const unsigned ulpi_data7_po0_pins[] = {
- TEGRA_PIN_ULPI_DATA7_PO0,
-};
-
-static const unsigned ulpi_data0_po1_pins[] = {
- TEGRA_PIN_ULPI_DATA0_PO1,
-};
-
-static const unsigned ulpi_data1_po2_pins[] = {
- TEGRA_PIN_ULPI_DATA1_PO2,
-};
-
-static const unsigned ulpi_data2_po3_pins[] = {
- TEGRA_PIN_ULPI_DATA2_PO3,
-};
-
-static const unsigned ulpi_data3_po4_pins[] = {
- TEGRA_PIN_ULPI_DATA3_PO4,
-};
-
-static const unsigned ulpi_data4_po5_pins[] = {
- TEGRA_PIN_ULPI_DATA4_PO5,
-};
-
-static const unsigned ulpi_data5_po6_pins[] = {
- TEGRA_PIN_ULPI_DATA5_PO6,
-};
-
-static const unsigned ulpi_data6_po7_pins[] = {
- TEGRA_PIN_ULPI_DATA6_PO7,
-};
-
-static const unsigned dap3_fs_pp0_pins[] = {
- TEGRA_PIN_DAP3_FS_PP0,
-};
-
-static const unsigned dap3_din_pp1_pins[] = {
- TEGRA_PIN_DAP3_DIN_PP1,
-};
-
-static const unsigned dap3_dout_pp2_pins[] = {
- TEGRA_PIN_DAP3_DOUT_PP2,
-};
-
-static const unsigned dap3_sclk_pp3_pins[] = {
- TEGRA_PIN_DAP3_SCLK_PP3,
-};
-
-static const unsigned dap4_fs_pp4_pins[] = {
- TEGRA_PIN_DAP4_FS_PP4,
-};
-
-static const unsigned dap4_din_pp5_pins[] = {
- TEGRA_PIN_DAP4_DIN_PP5,
-};
-
-static const unsigned dap4_dout_pp6_pins[] = {
- TEGRA_PIN_DAP4_DOUT_PP6,
-};
-
-static const unsigned dap4_sclk_pp7_pins[] = {
- TEGRA_PIN_DAP4_SCLK_PP7,
-};
-
-static const unsigned kb_col0_pq0_pins[] = {
- TEGRA_PIN_KB_COL0_PQ0,
-};
-
-static const unsigned kb_col1_pq1_pins[] = {
- TEGRA_PIN_KB_COL1_PQ1,
-};
-
-static const unsigned kb_col2_pq2_pins[] = {
- TEGRA_PIN_KB_COL2_PQ2,
-};
-
-static const unsigned kb_col3_pq3_pins[] = {
- TEGRA_PIN_KB_COL3_PQ3,
-};
-
-static const unsigned kb_col4_pq4_pins[] = {
- TEGRA_PIN_KB_COL4_PQ4,
-};
-
-static const unsigned kb_col5_pq5_pins[] = {
- TEGRA_PIN_KB_COL5_PQ5,
-};
-
-static const unsigned kb_col6_pq6_pins[] = {
- TEGRA_PIN_KB_COL6_PQ6,
-};
-
-static const unsigned kb_col7_pq7_pins[] = {
- TEGRA_PIN_KB_COL7_PQ7,
-};
-
-static const unsigned kb_row0_pr0_pins[] = {
- TEGRA_PIN_KB_ROW0_PR0,
-};
-
-static const unsigned kb_row1_pr1_pins[] = {
- TEGRA_PIN_KB_ROW1_PR1,
-};
-
-static const unsigned kb_row2_pr2_pins[] = {
- TEGRA_PIN_KB_ROW2_PR2,
-};
-
-static const unsigned kb_row3_pr3_pins[] = {
- TEGRA_PIN_KB_ROW3_PR3,
-};
-
-static const unsigned kb_row4_pr4_pins[] = {
- TEGRA_PIN_KB_ROW4_PR4,
-};
-
-static const unsigned kb_row5_pr5_pins[] = {
- TEGRA_PIN_KB_ROW5_PR5,
-};
-
-static const unsigned kb_row6_pr6_pins[] = {
- TEGRA_PIN_KB_ROW6_PR6,
-};
-
-static const unsigned kb_row7_pr7_pins[] = {
- TEGRA_PIN_KB_ROW7_PR7,
-};
-
-static const unsigned kb_row8_ps0_pins[] = {
- TEGRA_PIN_KB_ROW8_PS0,
-};
-
-static const unsigned kb_row9_ps1_pins[] = {
- TEGRA_PIN_KB_ROW9_PS1,
-};
-
-static const unsigned kb_row10_ps2_pins[] = {
- TEGRA_PIN_KB_ROW10_PS2,
-};
-
-static const unsigned kb_row11_ps3_pins[] = {
- TEGRA_PIN_KB_ROW11_PS3,
-};
-
-static const unsigned kb_row12_ps4_pins[] = {
- TEGRA_PIN_KB_ROW12_PS4,
-};
-
-static const unsigned kb_row13_ps5_pins[] = {
- TEGRA_PIN_KB_ROW13_PS5,
-};
-
-static const unsigned kb_row14_ps6_pins[] = {
- TEGRA_PIN_KB_ROW14_PS6,
-};
-
-static const unsigned kb_row15_ps7_pins[] = {
- TEGRA_PIN_KB_ROW15_PS7,
-};
-
-static const unsigned vi_pclk_pt0_pins[] = {
- TEGRA_PIN_VI_PCLK_PT0,
-};
-
-static const unsigned vi_mclk_pt1_pins[] = {
- TEGRA_PIN_VI_MCLK_PT1,
-};
-
-static const unsigned vi_d10_pt2_pins[] = {
- TEGRA_PIN_VI_D10_PT2,
-};
-
-static const unsigned vi_d11_pt3_pins[] = {
- TEGRA_PIN_VI_D11_PT3,
-};
-
-static const unsigned vi_d0_pt4_pins[] = {
- TEGRA_PIN_VI_D0_PT4,
-};
-
-static const unsigned gen2_i2c_scl_pt5_pins[] = {
- TEGRA_PIN_GEN2_I2C_SCL_PT5,
-};
-
-static const unsigned gen2_i2c_sda_pt6_pins[] = {
- TEGRA_PIN_GEN2_I2C_SDA_PT6,
-};
-
-static const unsigned sdmmc4_cmd_pt7_pins[] = {
- TEGRA_PIN_SDMMC4_CMD_PT7,
-};
-
-static const unsigned pu0_pins[] = {
- TEGRA_PIN_PU0,
-};
-
-static const unsigned pu1_pins[] = {
- TEGRA_PIN_PU1,
-};
-
-static const unsigned pu2_pins[] = {
- TEGRA_PIN_PU2,
-};
-
-static const unsigned pu3_pins[] = {
- TEGRA_PIN_PU3,
-};
-
-static const unsigned pu4_pins[] = {
- TEGRA_PIN_PU4,
-};
-
-static const unsigned pu5_pins[] = {
- TEGRA_PIN_PU5,
-};
-
-static const unsigned pu6_pins[] = {
- TEGRA_PIN_PU6,
-};
-
-static const unsigned jtag_rtck_pu7_pins[] = {
- TEGRA_PIN_JTAG_RTCK_PU7,
-};
-
-static const unsigned pv0_pins[] = {
- TEGRA_PIN_PV0,
-};
-
-static const unsigned pv1_pins[] = {
- TEGRA_PIN_PV1,
-};
-
-static const unsigned pv2_pins[] = {
- TEGRA_PIN_PV2,
-};
-
-static const unsigned pv3_pins[] = {
- TEGRA_PIN_PV3,
-};
-
-static const unsigned ddc_scl_pv4_pins[] = {
- TEGRA_PIN_DDC_SCL_PV4,
-};
-
-static const unsigned ddc_sda_pv5_pins[] = {
- TEGRA_PIN_DDC_SDA_PV5,
-};
-
-static const unsigned crt_hsync_pv6_pins[] = {
- TEGRA_PIN_CRT_HSYNC_PV6,
-};
-
-static const unsigned crt_vsync_pv7_pins[] = {
- TEGRA_PIN_CRT_VSYNC_PV7,
-};
-
-static const unsigned lcd_cs1_n_pw0_pins[] = {
- TEGRA_PIN_LCD_CS1_N_PW0,
-};
-
-static const unsigned lcd_m1_pw1_pins[] = {
- TEGRA_PIN_LCD_M1_PW1,
-};
-
-static const unsigned spi2_cs1_n_pw2_pins[] = {
- TEGRA_PIN_SPI2_CS1_N_PW2,
-};
-
-static const unsigned spi2_cs2_n_pw3_pins[] = {
- TEGRA_PIN_SPI2_CS2_N_PW3,
-};
-
-static const unsigned clk1_out_pw4_pins[] = {
- TEGRA_PIN_CLK1_OUT_PW4,
-};
-
-static const unsigned clk2_out_pw5_pins[] = {
- TEGRA_PIN_CLK2_OUT_PW5,
-};
-
-static const unsigned uart3_txd_pw6_pins[] = {
- TEGRA_PIN_UART3_TXD_PW6,
-};
-
-static const unsigned uart3_rxd_pw7_pins[] = {
- TEGRA_PIN_UART3_RXD_PW7,
-};
-
-static const unsigned spi2_mosi_px0_pins[] = {
- TEGRA_PIN_SPI2_MOSI_PX0,
-};
-
-static const unsigned spi2_miso_px1_pins[] = {
- TEGRA_PIN_SPI2_MISO_PX1,
-};
-
-static const unsigned spi2_sck_px2_pins[] = {
- TEGRA_PIN_SPI2_SCK_PX2,
-};
-
-static const unsigned spi2_cs0_n_px3_pins[] = {
- TEGRA_PIN_SPI2_CS0_N_PX3,
-};
-
-static const unsigned spi1_mosi_px4_pins[] = {
- TEGRA_PIN_SPI1_MOSI_PX4,
-};
-
-static const unsigned spi1_sck_px5_pins[] = {
- TEGRA_PIN_SPI1_SCK_PX5,
-};
-
-static const unsigned spi1_cs0_n_px6_pins[] = {
- TEGRA_PIN_SPI1_CS0_N_PX6,
-};
-
-static const unsigned spi1_miso_px7_pins[] = {
- TEGRA_PIN_SPI1_MISO_PX7,
-};
-
-static const unsigned ulpi_clk_py0_pins[] = {
- TEGRA_PIN_ULPI_CLK_PY0,
-};
-
-static const unsigned ulpi_dir_py1_pins[] = {
- TEGRA_PIN_ULPI_DIR_PY1,
-};
-
-static const unsigned ulpi_nxt_py2_pins[] = {
- TEGRA_PIN_ULPI_NXT_PY2,
-};
-
-static const unsigned ulpi_stp_py3_pins[] = {
- TEGRA_PIN_ULPI_STP_PY3,
-};
-
-static const unsigned sdmmc1_dat3_py4_pins[] = {
- TEGRA_PIN_SDMMC1_DAT3_PY4,
-};
-
-static const unsigned sdmmc1_dat2_py5_pins[] = {
- TEGRA_PIN_SDMMC1_DAT2_PY5,
-};
-
-static const unsigned sdmmc1_dat1_py6_pins[] = {
- TEGRA_PIN_SDMMC1_DAT1_PY6,
-};
-
-static const unsigned sdmmc1_dat0_py7_pins[] = {
- TEGRA_PIN_SDMMC1_DAT0_PY7,
-};
-
-static const unsigned sdmmc1_clk_pz0_pins[] = {
- TEGRA_PIN_SDMMC1_CLK_PZ0,
-};
-
-static const unsigned sdmmc1_cmd_pz1_pins[] = {
- TEGRA_PIN_SDMMC1_CMD_PZ1,
-};
-
-static const unsigned lcd_sdin_pz2_pins[] = {
- TEGRA_PIN_LCD_SDIN_PZ2,
-};
-
-static const unsigned lcd_wr_n_pz3_pins[] = {
- TEGRA_PIN_LCD_WR_N_PZ3,
-};
-
-static const unsigned lcd_sck_pz4_pins[] = {
- TEGRA_PIN_LCD_SCK_PZ4,
-};
-
-static const unsigned sys_clk_req_pz5_pins[] = {
- TEGRA_PIN_SYS_CLK_REQ_PZ5,
-};
-
-static const unsigned pwr_i2c_scl_pz6_pins[] = {
- TEGRA_PIN_PWR_I2C_SCL_PZ6,
-};
-
-static const unsigned pwr_i2c_sda_pz7_pins[] = {
- TEGRA_PIN_PWR_I2C_SDA_PZ7,
-};
-
-static const unsigned sdmmc4_dat0_paa0_pins[] = {
- TEGRA_PIN_SDMMC4_DAT0_PAA0,
-};
-
-static const unsigned sdmmc4_dat1_paa1_pins[] = {
- TEGRA_PIN_SDMMC4_DAT1_PAA1,
-};
-
-static const unsigned sdmmc4_dat2_paa2_pins[] = {
- TEGRA_PIN_SDMMC4_DAT2_PAA2,
-};
-
-static const unsigned sdmmc4_dat3_paa3_pins[] = {
- TEGRA_PIN_SDMMC4_DAT3_PAA3,
-};
-
-static const unsigned sdmmc4_dat4_paa4_pins[] = {
- TEGRA_PIN_SDMMC4_DAT4_PAA4,
-};
-
-static const unsigned sdmmc4_dat5_paa5_pins[] = {
- TEGRA_PIN_SDMMC4_DAT5_PAA5,
-};
-
-static const unsigned sdmmc4_dat6_paa6_pins[] = {
- TEGRA_PIN_SDMMC4_DAT6_PAA6,
-};
-
-static const unsigned sdmmc4_dat7_paa7_pins[] = {
- TEGRA_PIN_SDMMC4_DAT7_PAA7,
-};
-
-static const unsigned pbb0_pins[] = {
- TEGRA_PIN_PBB0,
-};
-
-static const unsigned cam_i2c_scl_pbb1_pins[] = {
- TEGRA_PIN_CAM_I2C_SCL_PBB1,
-};
-
-static const unsigned cam_i2c_sda_pbb2_pins[] = {
- TEGRA_PIN_CAM_I2C_SDA_PBB2,
-};
-
-static const unsigned pbb3_pins[] = {
- TEGRA_PIN_PBB3,
-};
-
-static const unsigned pbb4_pins[] = {
- TEGRA_PIN_PBB4,
-};
-
-static const unsigned pbb5_pins[] = {
- TEGRA_PIN_PBB5,
-};
-
-static const unsigned pbb6_pins[] = {
- TEGRA_PIN_PBB6,
-};
-
-static const unsigned pbb7_pins[] = {
- TEGRA_PIN_PBB7,
-};
-
-static const unsigned cam_mclk_pcc0_pins[] = {
- TEGRA_PIN_CAM_MCLK_PCC0,
-};
-
-static const unsigned pcc1_pins[] = {
- TEGRA_PIN_PCC1,
-};
-
-static const unsigned pcc2_pins[] = {
- TEGRA_PIN_PCC2,
-};
-
-static const unsigned sdmmc4_rst_n_pcc3_pins[] = {
- TEGRA_PIN_SDMMC4_RST_N_PCC3,
-};
-
-static const unsigned sdmmc4_clk_pcc4_pins[] = {
- TEGRA_PIN_SDMMC4_CLK_PCC4,
-};
-
-static const unsigned clk2_req_pcc5_pins[] = {
- TEGRA_PIN_CLK2_REQ_PCC5,
-};
-
-static const unsigned pex_l2_rst_n_pcc6_pins[] = {
- TEGRA_PIN_PEX_L2_RST_N_PCC6,
-};
-
-static const unsigned pex_l2_clkreq_n_pcc7_pins[] = {
- TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
-};
-
-static const unsigned pex_l0_prsnt_n_pdd0_pins[] = {
- TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
-};
-
-static const unsigned pex_l0_rst_n_pdd1_pins[] = {
- TEGRA_PIN_PEX_L0_RST_N_PDD1,
-};
-
-static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
- TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
-};
-
-static const unsigned pex_wake_n_pdd3_pins[] = {
- TEGRA_PIN_PEX_WAKE_N_PDD3,
-};
-
-static const unsigned pex_l1_prsnt_n_pdd4_pins[] = {
- TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
-};
-
-static const unsigned pex_l1_rst_n_pdd5_pins[] = {
- TEGRA_PIN_PEX_L1_RST_N_PDD5,
-};
-
-static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
- TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
-};
-
-static const unsigned pex_l2_prsnt_n_pdd7_pins[] = {
- TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
-};
-
-static const unsigned clk3_out_pee0_pins[] = {
- TEGRA_PIN_CLK3_OUT_PEE0,
-};
-
-static const unsigned clk3_req_pee1_pins[] = {
- TEGRA_PIN_CLK3_REQ_PEE1,
-};
-
-static const unsigned clk1_req_pee2_pins[] = {
- TEGRA_PIN_CLK1_REQ_PEE2,
-};
-
-static const unsigned hdmi_cec_pee3_pins[] = {
- TEGRA_PIN_HDMI_CEC_PEE3,
-};
-
-static const unsigned clk_32k_in_pins[] = {
- TEGRA_PIN_CLK_32K_IN,
-};
-
-static const unsigned core_pwr_req_pins[] = {
- TEGRA_PIN_CORE_PWR_REQ,
-};
-
-static const unsigned cpu_pwr_req_pins[] = {
- TEGRA_PIN_CPU_PWR_REQ,
-};
-
-static const unsigned owr_pins[] = {
- TEGRA_PIN_OWR,
-};
-
-static const unsigned pwr_int_n_pins[] = {
- TEGRA_PIN_PWR_INT_N,
-};
-
-static const unsigned drive_ao1_pins[] = {
- TEGRA_PIN_KB_ROW0_PR0,
- TEGRA_PIN_KB_ROW1_PR1,
- TEGRA_PIN_KB_ROW2_PR2,
- TEGRA_PIN_KB_ROW3_PR3,
- TEGRA_PIN_KB_ROW4_PR4,
- TEGRA_PIN_KB_ROW5_PR5,
- TEGRA_PIN_KB_ROW6_PR6,
- TEGRA_PIN_KB_ROW7_PR7,
- TEGRA_PIN_PWR_I2C_SCL_PZ6,
- TEGRA_PIN_PWR_I2C_SDA_PZ7,
- TEGRA_PIN_SYS_RESET_N,
-};
-
-static const unsigned drive_ao2_pins[] = {
- TEGRA_PIN_CLK_32K_OUT_PA0,
- TEGRA_PIN_KB_COL0_PQ0,
- TEGRA_PIN_KB_COL1_PQ1,
- TEGRA_PIN_KB_COL2_PQ2,
- TEGRA_PIN_KB_COL3_PQ3,
- TEGRA_PIN_KB_COL4_PQ4,
- TEGRA_PIN_KB_COL5_PQ5,
- TEGRA_PIN_KB_COL6_PQ6,
- TEGRA_PIN_KB_COL7_PQ7,
- TEGRA_PIN_KB_ROW8_PS0,
- TEGRA_PIN_KB_ROW9_PS1,
- TEGRA_PIN_KB_ROW10_PS2,
- TEGRA_PIN_KB_ROW11_PS3,
- TEGRA_PIN_KB_ROW12_PS4,
- TEGRA_PIN_KB_ROW13_PS5,
- TEGRA_PIN_KB_ROW14_PS6,
- TEGRA_PIN_KB_ROW15_PS7,
- TEGRA_PIN_SYS_CLK_REQ_PZ5,
- TEGRA_PIN_CLK_32K_IN,
- TEGRA_PIN_CORE_PWR_REQ,
- TEGRA_PIN_CPU_PWR_REQ,
- TEGRA_PIN_PWR_INT_N,
-};
-
-static const unsigned drive_at1_pins[] = {
- TEGRA_PIN_GMI_AD8_PH0,
- TEGRA_PIN_GMI_AD9_PH1,
- TEGRA_PIN_GMI_AD10_PH2,
- TEGRA_PIN_GMI_AD11_PH3,
- TEGRA_PIN_GMI_AD12_PH4,
- TEGRA_PIN_GMI_AD13_PH5,
- TEGRA_PIN_GMI_AD14_PH6,
- TEGRA_PIN_GMI_AD15_PH7,
- TEGRA_PIN_GMI_IORDY_PI5,
- TEGRA_PIN_GMI_CS7_N_PI6,
-};
-
-static const unsigned drive_at2_pins[] = {
- TEGRA_PIN_GMI_AD0_PG0,
- TEGRA_PIN_GMI_AD1_PG1,
- TEGRA_PIN_GMI_AD2_PG2,
- TEGRA_PIN_GMI_AD3_PG3,
- TEGRA_PIN_GMI_AD4_PG4,
- TEGRA_PIN_GMI_AD5_PG5,
- TEGRA_PIN_GMI_AD6_PG6,
- TEGRA_PIN_GMI_AD7_PG7,
- TEGRA_PIN_GMI_WR_N_PI0,
- TEGRA_PIN_GMI_OE_N_PI1,
- TEGRA_PIN_GMI_DQS_PI2,
- TEGRA_PIN_GMI_CS6_N_PI3,
- TEGRA_PIN_GMI_RST_N_PI4,
- TEGRA_PIN_GMI_WAIT_PI7,
- TEGRA_PIN_GMI_ADV_N_PK0,
- TEGRA_PIN_GMI_CLK_PK1,
- TEGRA_PIN_GMI_CS4_N_PK2,
- TEGRA_PIN_GMI_CS2_N_PK3,
- TEGRA_PIN_GMI_CS3_N_PK4,
-};
-
-static const unsigned drive_at3_pins[] = {
- TEGRA_PIN_GMI_WP_N_PC7,
- TEGRA_PIN_GMI_CS0_N_PJ0,
-};
-
-static const unsigned drive_at4_pins[] = {
- TEGRA_PIN_GMI_A17_PB0,
- TEGRA_PIN_GMI_A18_PB1,
- TEGRA_PIN_GMI_CS1_N_PJ2,
- TEGRA_PIN_GMI_A16_PJ7,
- TEGRA_PIN_GMI_A19_PK7,
-};
-
-static const unsigned drive_at5_pins[] = {
- TEGRA_PIN_GEN2_I2C_SCL_PT5,
- TEGRA_PIN_GEN2_I2C_SDA_PT6,
-};
-
-static const unsigned drive_cdev1_pins[] = {
- TEGRA_PIN_CLK1_OUT_PW4,
- TEGRA_PIN_CLK1_REQ_PEE2,
-};
-
-static const unsigned drive_cdev2_pins[] = {
- TEGRA_PIN_CLK2_OUT_PW5,
- TEGRA_PIN_CLK2_REQ_PCC5,
-};
-
-static const unsigned drive_cec_pins[] = {
- TEGRA_PIN_HDMI_CEC_PEE3,
-};
-
-static const unsigned drive_crt_pins[] = {
- TEGRA_PIN_CRT_HSYNC_PV6,
- TEGRA_PIN_CRT_VSYNC_PV7,
-};
-
-static const unsigned drive_csus_pins[] = {
- TEGRA_PIN_VI_MCLK_PT1,
-};
-
-static const unsigned drive_dap1_pins[] = {
- TEGRA_PIN_SPDIF_OUT_PK5,
- TEGRA_PIN_SPDIF_IN_PK6,
- TEGRA_PIN_DAP1_FS_PN0,
- TEGRA_PIN_DAP1_DIN_PN1,
- TEGRA_PIN_DAP1_DOUT_PN2,
- TEGRA_PIN_DAP1_SCLK_PN3,
-};
-
-static const unsigned drive_dap2_pins[] = {
- TEGRA_PIN_DAP2_FS_PA2,
- TEGRA_PIN_DAP2_SCLK_PA3,
- TEGRA_PIN_DAP2_DIN_PA4,
- TEGRA_PIN_DAP2_DOUT_PA5,
-};
-
-static const unsigned drive_dap3_pins[] = {
- TEGRA_PIN_DAP3_FS_PP0,
- TEGRA_PIN_DAP3_DIN_PP1,
- TEGRA_PIN_DAP3_DOUT_PP2,
- TEGRA_PIN_DAP3_SCLK_PP3,
-};
-
-static const unsigned drive_dap4_pins[] = {
- TEGRA_PIN_DAP4_FS_PP4,
- TEGRA_PIN_DAP4_DIN_PP5,
- TEGRA_PIN_DAP4_DOUT_PP6,
- TEGRA_PIN_DAP4_SCLK_PP7,
-};
-
-static const unsigned drive_dbg_pins[] = {
- TEGRA_PIN_GEN1_I2C_SCL_PC4,
- TEGRA_PIN_GEN1_I2C_SDA_PC5,
- TEGRA_PIN_PU0,
- TEGRA_PIN_PU1,
- TEGRA_PIN_PU2,
- TEGRA_PIN_PU3,
- TEGRA_PIN_PU4,
- TEGRA_PIN_PU5,
- TEGRA_PIN_PU6,
- TEGRA_PIN_JTAG_RTCK_PU7,
- TEGRA_PIN_JTAG_TCK,
- TEGRA_PIN_JTAG_TDI,
- TEGRA_PIN_JTAG_TDO,
- TEGRA_PIN_JTAG_TMS,
- TEGRA_PIN_JTAG_TRST_N,
- TEGRA_PIN_TEST_MODE_EN,
-};
-
-static const unsigned drive_ddc_pins[] = {
- TEGRA_PIN_DDC_SCL_PV4,
- TEGRA_PIN_DDC_SDA_PV5,
-};
-
-static const unsigned drive_dev3_pins[] = {
- TEGRA_PIN_CLK3_OUT_PEE0,
- TEGRA_PIN_CLK3_REQ_PEE1,
-};
-
-static const unsigned drive_gma_pins[] = {
- TEGRA_PIN_SDMMC4_DAT0_PAA0,
- TEGRA_PIN_SDMMC4_DAT1_PAA1,
- TEGRA_PIN_SDMMC4_DAT2_PAA2,
- TEGRA_PIN_SDMMC4_DAT3_PAA3,
- TEGRA_PIN_SDMMC4_RST_N_PCC3,
-};
-
-static const unsigned drive_gmb_pins[] = {
- TEGRA_PIN_SDMMC4_DAT4_PAA4,
- TEGRA_PIN_SDMMC4_DAT5_PAA5,
- TEGRA_PIN_SDMMC4_DAT6_PAA6,
- TEGRA_PIN_SDMMC4_DAT7_PAA7,
-};
-
-static const unsigned drive_gmc_pins[] = {
- TEGRA_PIN_SDMMC4_CLK_PCC4,
-};
-
-static const unsigned drive_gmd_pins[] = {
- TEGRA_PIN_SDMMC4_CMD_PT7,
-};
-
-static const unsigned drive_gme_pins[] = {
- TEGRA_PIN_PBB0,
- TEGRA_PIN_CAM_I2C_SCL_PBB1,
- TEGRA_PIN_CAM_I2C_SDA_PBB2,
- TEGRA_PIN_PBB3,
- TEGRA_PIN_PCC2,
-};
-
-static const unsigned drive_gmf_pins[] = {
- TEGRA_PIN_PBB4,
- TEGRA_PIN_PBB5,
- TEGRA_PIN_PBB6,
- TEGRA_PIN_PBB7,
-};
-
-static const unsigned drive_gmg_pins[] = {
- TEGRA_PIN_CAM_MCLK_PCC0,
-};
-
-static const unsigned drive_gmh_pins[] = {
- TEGRA_PIN_PCC1,
-};
-
-static const unsigned drive_gpv_pins[] = {
- TEGRA_PIN_PEX_L2_RST_N_PCC6,
- TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
- TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
- TEGRA_PIN_PEX_L0_RST_N_PDD1,
- TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
- TEGRA_PIN_PEX_WAKE_N_PDD3,
- TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
- TEGRA_PIN_PEX_L1_RST_N_PDD5,
- TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
- TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
-};
-
-static const unsigned drive_lcd1_pins[] = {
- TEGRA_PIN_LCD_PWR1_PC1,
- TEGRA_PIN_LCD_PWR2_PC6,
- TEGRA_PIN_LCD_CS0_N_PN4,
- TEGRA_PIN_LCD_SDOUT_PN5,
- TEGRA_PIN_LCD_DC0_PN6,
- TEGRA_PIN_LCD_SDIN_PZ2,
- TEGRA_PIN_LCD_WR_N_PZ3,
- TEGRA_PIN_LCD_SCK_PZ4,
-};
-
-static const unsigned drive_lcd2_pins[] = {
- TEGRA_PIN_LCD_PWR0_PB2,
- TEGRA_PIN_LCD_PCLK_PB3,
- TEGRA_PIN_LCD_DC1_PD2,
- TEGRA_PIN_LCD_D0_PE0,
- TEGRA_PIN_LCD_D1_PE1,
- TEGRA_PIN_LCD_D2_PE2,
- TEGRA_PIN_LCD_D3_PE3,
- TEGRA_PIN_LCD_D4_PE4,
- TEGRA_PIN_LCD_D5_PE5,
- TEGRA_PIN_LCD_D6_PE6,
- TEGRA_PIN_LCD_D7_PE7,
- TEGRA_PIN_LCD_D8_PF0,
- TEGRA_PIN_LCD_D9_PF1,
- TEGRA_PIN_LCD_D10_PF2,
- TEGRA_PIN_LCD_D11_PF3,
- TEGRA_PIN_LCD_D12_PF4,
- TEGRA_PIN_LCD_D13_PF5,
- TEGRA_PIN_LCD_D14_PF6,
- TEGRA_PIN_LCD_D15_PF7,
- TEGRA_PIN_LCD_DE_PJ1,
- TEGRA_PIN_LCD_HSYNC_PJ3,
- TEGRA_PIN_LCD_VSYNC_PJ4,
- TEGRA_PIN_LCD_D16_PM0,
- TEGRA_PIN_LCD_D17_PM1,
- TEGRA_PIN_LCD_D18_PM2,
- TEGRA_PIN_LCD_D19_PM3,
- TEGRA_PIN_LCD_D20_PM4,
- TEGRA_PIN_LCD_D21_PM5,
- TEGRA_PIN_LCD_D22_PM6,
- TEGRA_PIN_LCD_D23_PM7,
- TEGRA_PIN_HDMI_INT_PN7,
- TEGRA_PIN_LCD_CS1_N_PW0,
- TEGRA_PIN_LCD_M1_PW1,
-};
-
-static const unsigned drive_owr_pins[] = {
- TEGRA_PIN_OWR,
-};
-
-static const unsigned drive_sdio1_pins[] = {
- TEGRA_PIN_SDMMC1_DAT3_PY4,
- TEGRA_PIN_SDMMC1_DAT2_PY5,
- TEGRA_PIN_SDMMC1_DAT1_PY6,
- TEGRA_PIN_SDMMC1_DAT0_PY7,
- TEGRA_PIN_SDMMC1_CLK_PZ0,
- TEGRA_PIN_SDMMC1_CMD_PZ1,
-};
-
-static const unsigned drive_sdio2_pins[] = {
- TEGRA_PIN_SDMMC3_DAT5_PD0,
- TEGRA_PIN_SDMMC3_DAT4_PD1,
- TEGRA_PIN_SDMMC3_DAT6_PD3,
- TEGRA_PIN_SDMMC3_DAT7_PD4,
-};
-
-static const unsigned drive_sdio3_pins[] = {
- TEGRA_PIN_SDMMC3_CLK_PA6,
- TEGRA_PIN_SDMMC3_CMD_PA7,
- TEGRA_PIN_SDMMC3_DAT3_PB4,
- TEGRA_PIN_SDMMC3_DAT2_PB5,
- TEGRA_PIN_SDMMC3_DAT1_PB6,
- TEGRA_PIN_SDMMC3_DAT0_PB7,
-};
-
-static const unsigned drive_spi_pins[] = {
- TEGRA_PIN_SPI2_CS1_N_PW2,
- TEGRA_PIN_SPI2_CS2_N_PW3,
- TEGRA_PIN_SPI2_MOSI_PX0,
- TEGRA_PIN_SPI2_MISO_PX1,
- TEGRA_PIN_SPI2_SCK_PX2,
- TEGRA_PIN_SPI2_CS0_N_PX3,
- TEGRA_PIN_SPI1_MOSI_PX4,
- TEGRA_PIN_SPI1_SCK_PX5,
- TEGRA_PIN_SPI1_CS0_N_PX6,
- TEGRA_PIN_SPI1_MISO_PX7,
-};
-
-static const unsigned drive_uaa_pins[] = {
- TEGRA_PIN_ULPI_DATA0_PO1,
- TEGRA_PIN_ULPI_DATA1_PO2,
- TEGRA_PIN_ULPI_DATA2_PO3,
- TEGRA_PIN_ULPI_DATA3_PO4,
-};
-
-static const unsigned drive_uab_pins[] = {
- TEGRA_PIN_ULPI_DATA7_PO0,
- TEGRA_PIN_ULPI_DATA4_PO5,
- TEGRA_PIN_ULPI_DATA5_PO6,
- TEGRA_PIN_ULPI_DATA6_PO7,
- TEGRA_PIN_PV0,
- TEGRA_PIN_PV1,
- TEGRA_PIN_PV2,
- TEGRA_PIN_PV3,
-};
-
-static const unsigned drive_uart2_pins[] = {
- TEGRA_PIN_UART2_TXD_PC2,
- TEGRA_PIN_UART2_RXD_PC3,
- TEGRA_PIN_UART2_CTS_N_PJ5,
- TEGRA_PIN_UART2_RTS_N_PJ6,
-};
-
-static const unsigned drive_uart3_pins[] = {
- TEGRA_PIN_UART3_CTS_N_PA1,
- TEGRA_PIN_UART3_RTS_N_PC0,
- TEGRA_PIN_UART3_TXD_PW6,
- TEGRA_PIN_UART3_RXD_PW7,
-};
-
-static const unsigned drive_uda_pins[] = {
- TEGRA_PIN_ULPI_CLK_PY0,
- TEGRA_PIN_ULPI_DIR_PY1,
- TEGRA_PIN_ULPI_NXT_PY2,
- TEGRA_PIN_ULPI_STP_PY3,
-};
-
-static const unsigned drive_vi1_pins[] = {
- TEGRA_PIN_VI_D1_PD5,
- TEGRA_PIN_VI_VSYNC_PD6,
- TEGRA_PIN_VI_HSYNC_PD7,
- TEGRA_PIN_VI_D2_PL0,
- TEGRA_PIN_VI_D3_PL1,
- TEGRA_PIN_VI_D4_PL2,
- TEGRA_PIN_VI_D5_PL3,
- TEGRA_PIN_VI_D6_PL4,
- TEGRA_PIN_VI_D7_PL5,
- TEGRA_PIN_VI_D8_PL6,
- TEGRA_PIN_VI_D9_PL7,
- TEGRA_PIN_VI_PCLK_PT0,
- TEGRA_PIN_VI_D10_PT2,
- TEGRA_PIN_VI_D11_PT3,
- TEGRA_PIN_VI_D0_PT4,
-};
-
-enum tegra_mux {
- TEGRA_MUX_BLINK,
- TEGRA_MUX_CEC,
- TEGRA_MUX_CLK_12M_OUT,
- TEGRA_MUX_CLK_32K_IN,
- TEGRA_MUX_CORE_PWR_REQ,
- TEGRA_MUX_CPU_PWR_REQ,
- TEGRA_MUX_CRT,
- TEGRA_MUX_DAP,
- TEGRA_MUX_DDR,
- TEGRA_MUX_DEV3,
- TEGRA_MUX_DISPLAYA,
- TEGRA_MUX_DISPLAYB,
- TEGRA_MUX_DTV,
- TEGRA_MUX_EXTPERIPH1,
- TEGRA_MUX_EXTPERIPH2,
- TEGRA_MUX_EXTPERIPH3,
- TEGRA_MUX_GMI,
- TEGRA_MUX_GMI_ALT,
- TEGRA_MUX_HDA,
- TEGRA_MUX_HDCP,
- TEGRA_MUX_HDMI,
- TEGRA_MUX_HSI,
- TEGRA_MUX_I2C1,
- TEGRA_MUX_I2C2,
- TEGRA_MUX_I2C3,
- TEGRA_MUX_I2C4,
- TEGRA_MUX_I2CPWR,
- TEGRA_MUX_I2S0,
- TEGRA_MUX_I2S1,
- TEGRA_MUX_I2S2,
- TEGRA_MUX_I2S3,
- TEGRA_MUX_I2S4,
- TEGRA_MUX_INVALID,
- TEGRA_MUX_KBC,
- TEGRA_MUX_MIO,
- TEGRA_MUX_NAND,
- TEGRA_MUX_NAND_ALT,
- TEGRA_MUX_OWR,
- TEGRA_MUX_PCIE,
- TEGRA_MUX_PWM0,
- TEGRA_MUX_PWM1,
- TEGRA_MUX_PWM2,
- TEGRA_MUX_PWM3,
- TEGRA_MUX_PWR_INT_N,
- TEGRA_MUX_RSVD1,
- TEGRA_MUX_RSVD2,
- TEGRA_MUX_RSVD3,
- TEGRA_MUX_RSVD4,
- TEGRA_MUX_RTCK,
- TEGRA_MUX_SATA,
- TEGRA_MUX_SDMMC1,
- TEGRA_MUX_SDMMC2,
- TEGRA_MUX_SDMMC3,
- TEGRA_MUX_SDMMC4,
- TEGRA_MUX_SPDIF,
- TEGRA_MUX_SPI1,
- TEGRA_MUX_SPI2,
- TEGRA_MUX_SPI2_ALT,
- TEGRA_MUX_SPI3,
- TEGRA_MUX_SPI4,
- TEGRA_MUX_SPI5,
- TEGRA_MUX_SPI6,
- TEGRA_MUX_SYSCLK,
- TEGRA_MUX_TEST,
- TEGRA_MUX_TRACE,
- TEGRA_MUX_UARTA,
- TEGRA_MUX_UARTB,
- TEGRA_MUX_UARTC,
- TEGRA_MUX_UARTD,
- TEGRA_MUX_UARTE,
- TEGRA_MUX_ULPI,
- TEGRA_MUX_VGP1,
- TEGRA_MUX_VGP2,
- TEGRA_MUX_VGP3,
- TEGRA_MUX_VGP4,
- TEGRA_MUX_VGP5,
- TEGRA_MUX_VGP6,
- TEGRA_MUX_VI,
- TEGRA_MUX_VI_ALT1,
- TEGRA_MUX_VI_ALT2,
- TEGRA_MUX_VI_ALT3,
-};
-
-#define FUNCTION(fname) \
- { \
- .name = #fname, \
- }
-
-static struct tegra_function tegra30_functions[] = {
- FUNCTION(blink),
- FUNCTION(cec),
- FUNCTION(clk_12m_out),
- FUNCTION(clk_32k_in),
- FUNCTION(core_pwr_req),
- FUNCTION(cpu_pwr_req),
- FUNCTION(crt),
- FUNCTION(dap),
- FUNCTION(ddr),
- FUNCTION(dev3),
- FUNCTION(displaya),
- FUNCTION(displayb),
- FUNCTION(dtv),
- FUNCTION(extperiph1),
- FUNCTION(extperiph2),
- FUNCTION(extperiph3),
- FUNCTION(gmi),
- FUNCTION(gmi_alt),
- FUNCTION(hda),
- FUNCTION(hdcp),
- FUNCTION(hdmi),
- FUNCTION(hsi),
- FUNCTION(i2c1),
- FUNCTION(i2c2),
- FUNCTION(i2c3),
- FUNCTION(i2c4),
- FUNCTION(i2cpwr),
- FUNCTION(i2s0),
- FUNCTION(i2s1),
- FUNCTION(i2s2),
- FUNCTION(i2s3),
- FUNCTION(i2s4),
- FUNCTION(invalid),
- FUNCTION(kbc),
- FUNCTION(mio),
- FUNCTION(nand),
- FUNCTION(nand_alt),
- FUNCTION(owr),
- FUNCTION(pcie),
- FUNCTION(pwm0),
- FUNCTION(pwm1),
- FUNCTION(pwm2),
- FUNCTION(pwm3),
- FUNCTION(pwr_int_n),
- FUNCTION(rsvd1),
- FUNCTION(rsvd2),
- FUNCTION(rsvd3),
- FUNCTION(rsvd4),
- FUNCTION(rtck),
- FUNCTION(sata),
- FUNCTION(sdmmc1),
- FUNCTION(sdmmc2),
- FUNCTION(sdmmc3),
- FUNCTION(sdmmc4),
- FUNCTION(spdif),
- FUNCTION(spi1),
- FUNCTION(spi2),
- FUNCTION(spi2_alt),
- FUNCTION(spi3),
- FUNCTION(spi4),
- FUNCTION(spi5),
- FUNCTION(spi6),
- FUNCTION(sysclk),
- FUNCTION(test),
- FUNCTION(trace),
- FUNCTION(uarta),
- FUNCTION(uartb),
- FUNCTION(uartc),
- FUNCTION(uartd),
- FUNCTION(uarte),
- FUNCTION(ulpi),
- FUNCTION(vgp1),
- FUNCTION(vgp2),
- FUNCTION(vgp3),
- FUNCTION(vgp4),
- FUNCTION(vgp5),
- FUNCTION(vgp6),
- FUNCTION(vi),
- FUNCTION(vi_alt1),
- FUNCTION(vi_alt2),
- FUNCTION(vi_alt3),
-};
-
-#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
-#define PINGROUP_REG_A 0x3000 /* bank 1 */
-
-#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
-#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
-
-#define PINGROUP_BIT_Y(b) (b)
-#define PINGROUP_BIT_N(b) (-1)
-
-#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \
- { \
- .name = #pg_name, \
- .pins = pg_name##_pins, \
- .npins = ARRAY_SIZE(pg_name##_pins), \
- .funcs = { \
- TEGRA_MUX_##f0, \
- TEGRA_MUX_##f1, \
- TEGRA_MUX_##f2, \
- TEGRA_MUX_##f3, \
- }, \
- .mux_reg = PINGROUP_REG(r), \
- .mux_bank = 1, \
- .mux_bit = 0, \
- .pupd_reg = PINGROUP_REG(r), \
- .pupd_bank = 1, \
- .pupd_bit = 2, \
- .tri_reg = PINGROUP_REG(r), \
- .tri_bank = 1, \
- .tri_bit = 4, \
- .einput_bit = 5, \
- .odrain_bit = PINGROUP_BIT_##od(6), \
- .lock_bit = 7, \
- .ioreset_bit = PINGROUP_BIT_##ior(8), \
- .rcv_sel_bit = -1, \
- .drv_reg = -1, \
- }
-
-#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
- drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
- slwf_b, slwf_w) \
- { \
- .name = "drive_" #pg_name, \
- .pins = drive_##pg_name##_pins, \
- .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
- .mux_reg = -1, \
- .pupd_reg = -1, \
- .tri_reg = -1, \
- .einput_bit = -1, \
- .odrain_bit = -1, \
- .lock_bit = -1, \
- .ioreset_bit = -1, \
- .rcv_sel_bit = -1, \
- .drv_reg = DRV_PINGROUP_REG(r), \
- .drv_bank = 0, \
- .hsm_bit = hsm_b, \
- .schmitt_bit = schmitt_b, \
- .lpmd_bit = lpmd_b, \
- .drvdn_bit = drvdn_b, \
- .drvdn_width = drvdn_w, \
- .drvup_bit = drvup_b, \
- .drvup_width = drvup_w, \
- .slwr_bit = slwr_b, \
- .slwr_width = slwr_w, \
- .slwf_bit = slwf_b, \
- .slwf_width = slwf_w, \
- .drvtype_bit = -1, \
- }
-
-static const struct tegra_pingroup tegra30_groups[] = {
- /* pg_name, f0, f1, f2, f3, r, od, ior */
- PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, 0x331c, N, N),
- PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, 0x317c, N, N),
- PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, GMI, 0x3358, N, N),
- PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, GMI, 0x3364, N, N),
- PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, GMI, 0x335c, N, N),
- PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, GMI, 0x3360, N, N),
- PINGROUP(sdmmc3_clk_pa6, UARTA, PWM2, SDMMC3, SPI3, 0x3390, N, N),
- PINGROUP(sdmmc3_cmd_pa7, UARTA, PWM3, SDMMC3, SPI2, 0x3394, N, N),
- PINGROUP(gmi_a17_pb0, UARTD, SPI4, GMI, DTV, 0x3234, N, N),
- PINGROUP(gmi_a18_pb1, UARTD, SPI4, GMI, DTV, 0x3238, N, N),
- PINGROUP(lcd_pwr0_pb2, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3090, N, N),
- PINGROUP(lcd_pclk_pb3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3094, N, N),
- PINGROUP(sdmmc3_dat3_pb4, RSVD1, PWM0, SDMMC3, SPI3, 0x33a4, N, N),
- PINGROUP(sdmmc3_dat2_pb5, RSVD1, PWM1, SDMMC3, SPI3, 0x33a0, N, N),
- PINGROUP(sdmmc3_dat1_pb6, RSVD1, RSVD2, SDMMC3, SPI3, 0x339c, N, N),
- PINGROUP(sdmmc3_dat0_pb7, RSVD1, RSVD2, SDMMC3, SPI3, 0x3398, N, N),
- PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, GMI, RSVD4, 0x3180, N, N),
- PINGROUP(lcd_pwr1_pc1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3070, N, N),
- PINGROUP(uart2_txd_pc2, UARTB, SPDIF, UARTA, SPI4, 0x3168, N, N),
- PINGROUP(uart2_rxd_pc3, UARTB, SPDIF, UARTA, SPI4, 0x3164, N, N),
- PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N),
- PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N),
- PINGROUP(lcd_pwr2_pc6, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3074, N, N),
- PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N),
- PINGROUP(sdmmc3_dat5_pd0, PWM0, SPI4, SDMMC3, SPI2, 0x33ac, N, N),
- PINGROUP(sdmmc3_dat4_pd1, PWM1, SPI4, SDMMC3, SPI2, 0x33a8, N, N),
- PINGROUP(lcd_dc1_pd2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x310c, N, N),
- PINGROUP(sdmmc3_dat6_pd3, SPDIF, SPI4, SDMMC3, SPI2, 0x33b0, N, N),
- PINGROUP(sdmmc3_dat7_pd4, SPDIF, SPI4, SDMMC3, SPI2, 0x33b4, N, N),
- PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, Y),
- PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, Y),
- PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, Y),
- PINGROUP(lcd_d0_pe0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a4, N, N),
- PINGROUP(lcd_d1_pe1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a8, N, N),
- PINGROUP(lcd_d2_pe2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30ac, N, N),
- PINGROUP(lcd_d3_pe3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b0, N, N),
- PINGROUP(lcd_d4_pe4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b4, N, N),
- PINGROUP(lcd_d5_pe5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b8, N, N),
- PINGROUP(lcd_d6_pe6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30bc, N, N),
- PINGROUP(lcd_d7_pe7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c0, N, N),
- PINGROUP(lcd_d8_pf0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c4, N, N),
- PINGROUP(lcd_d9_pf1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c8, N, N),
- PINGROUP(lcd_d10_pf2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30cc, N, N),
- PINGROUP(lcd_d11_pf3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d0, N, N),
- PINGROUP(lcd_d12_pf4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d4, N, N),
- PINGROUP(lcd_d13_pf5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d8, N, N),
- PINGROUP(lcd_d14_pf6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30dc, N, N),
- PINGROUP(lcd_d15_pf7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e0, N, N),
- PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, N),
- PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, N),
- PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, N),
- PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, N),
- PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, N),
- PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, 0x3204, N, N),
- PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, 0x3208, N, N),
- PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, 0x320c, N, N),
- PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, N),
- PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, RSVD4, 0x3214, N, N),
- PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, RSVD4, 0x3218, N, N),
- PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, RSVD4, 0x321c, N, N),
- PINGROUP(gmi_ad12_ph4, RSVD1, NAND, GMI, RSVD4, 0x3220, N, N),
- PINGROUP(gmi_ad13_ph5, RSVD1, NAND, GMI, RSVD4, 0x3224, N, N),
- PINGROUP(gmi_ad14_ph6, RSVD1, NAND, GMI, RSVD4, 0x3228, N, N),
- PINGROUP(gmi_ad15_ph7, RSVD1, NAND, GMI, RSVD4, 0x322c, N, N),
- PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, RSVD4, 0x3240, N, N),
- PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, RSVD4, 0x3244, N, N),
- PINGROUP(gmi_dqs_pi2, RSVD1, NAND, GMI, RSVD4, 0x3248, N, N),
- PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SATA, 0x31e8, N, N),
- PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, 0x324c, N, N),
- PINGROUP(gmi_iordy_pi5, RSVD1, NAND, GMI, RSVD4, 0x31c4, N, N),
- PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, GMI_ALT, 0x31ec, N, N),
- PINGROUP(gmi_wait_pi7, RSVD1, NAND, GMI, RSVD4, 0x31c8, N, N),
- PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, DTV, 0x31d4, N, N),
- PINGROUP(lcd_de_pj1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3098, N, N),
- PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, DTV, 0x31d8, N, N),
- PINGROUP(lcd_hsync_pj3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x309c, N, N),
- PINGROUP(lcd_vsync_pj4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a0, N, N),
- PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, 0x3170, N, N),
- PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, 0x316c, N, N),
- PINGROUP(gmi_a16_pj7, UARTD, SPI4, GMI, GMI_ALT, 0x3230, N, N),
- PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, RSVD4, 0x31cc, N, N),
- PINGROUP(gmi_clk_pk1, RSVD1, NAND, GMI, RSVD4, 0x31d0, N, N),
- PINGROUP(gmi_cs4_n_pk2, RSVD1, NAND, GMI, RSVD4, 0x31e4, N, N),
- PINGROUP(gmi_cs2_n_pk3, RSVD1, NAND, GMI, RSVD4, 0x31dc, N, N),
- PINGROUP(gmi_cs3_n_pk4, RSVD1, NAND, GMI, GMI_ALT, 0x31e0, N, N),
- PINGROUP(spdif_out_pk5, SPDIF, RSVD2, I2C1, SDMMC2, 0x3354, N, N),
- PINGROUP(spdif_in_pk6, SPDIF, HDA, I2C1, SDMMC2, 0x3350, N, N),
- PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, RSVD4, 0x323c, N, N),
- PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, Y),
- PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, Y),
- PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, Y),
- PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, Y),
- PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, Y),
- PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, Y),
- PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, 0x3144, N, Y),
- PINGROUP(vi_d9_pl7, DDR, SDMMC2, VI, RSVD4, 0x3148, N, Y),
- PINGROUP(lcd_d16_pm0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e4, N, N),
- PINGROUP(lcd_d17_pm1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e8, N, N),
- PINGROUP(lcd_d18_pm2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30ec, N, N),
- PINGROUP(lcd_d19_pm3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f0, N, N),
- PINGROUP(lcd_d20_pm4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f4, N, N),
- PINGROUP(lcd_d21_pm5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f8, N, N),
- PINGROUP(lcd_d22_pm6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30fc, N, N),
- PINGROUP(lcd_d23_pm7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3100, N, N),
- PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, SDMMC2, 0x3338, N, N),
- PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, SDMMC2, 0x333c, N, N),
- PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SDMMC2, 0x3340, N, N),
- PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, SDMMC2, 0x3344, N, N),
- PINGROUP(lcd_cs0_n_pn4, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3084, N, N),
- PINGROUP(lcd_sdout_pn5, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x307c, N, N),
- PINGROUP(lcd_dc0_pn6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3088, N, N),
- PINGROUP(hdmi_int_pn7, HDMI, RSVD2, RSVD3, RSVD4, 0x3110, N, N),
- PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N),
- PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N),
- PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N),
- PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N),
- PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N),
- PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N),
- PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N),
- PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N),
- PINGROUP(dap3_fs_pp0, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3030, N, N),
- PINGROUP(dap3_din_pp1, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3034, N, N),
- PINGROUP(dap3_dout_pp2, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3038, N, N),
- PINGROUP(dap3_sclk_pp3, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x303c, N, N),
- PINGROUP(dap4_fs_pp4, I2S3, RSVD2, GMI, RSVD4, 0x31a8, N, N),
- PINGROUP(dap4_din_pp5, I2S3, RSVD2, GMI, RSVD4, 0x31ac, N, N),
- PINGROUP(dap4_dout_pp6, I2S3, RSVD2, GMI, RSVD4, 0x31b0, N, N),
- PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, GMI, RSVD4, 0x31b4, N, N),
- PINGROUP(kb_col0_pq0, KBC, NAND, TRACE, TEST, 0x32fc, N, N),
- PINGROUP(kb_col1_pq1, KBC, NAND, TRACE, TEST, 0x3300, N, N),
- PINGROUP(kb_col2_pq2, KBC, NAND, TRACE, RSVD4, 0x3304, N, N),
- PINGROUP(kb_col3_pq3, KBC, NAND, TRACE, RSVD4, 0x3308, N, N),
- PINGROUP(kb_col4_pq4, KBC, NAND, TRACE, RSVD4, 0x330c, N, N),
- PINGROUP(kb_col5_pq5, KBC, NAND, TRACE, RSVD4, 0x3310, N, N),
- PINGROUP(kb_col6_pq6, KBC, NAND, TRACE, MIO, 0x3314, N, N),
- PINGROUP(kb_col7_pq7, KBC, NAND, TRACE, MIO, 0x3318, N, N),
- PINGROUP(kb_row0_pr0, KBC, NAND, RSVD3, RSVD4, 0x32bc, N, N),
- PINGROUP(kb_row1_pr1, KBC, NAND, RSVD3, RSVD4, 0x32c0, N, N),
- PINGROUP(kb_row2_pr2, KBC, NAND, RSVD3, RSVD4, 0x32c4, N, N),
- PINGROUP(kb_row3_pr3, KBC, NAND, RSVD3, INVALID, 0x32c8, N, N),
- PINGROUP(kb_row4_pr4, KBC, NAND, TRACE, RSVD4, 0x32cc, N, N),
- PINGROUP(kb_row5_pr5, KBC, NAND, TRACE, OWR, 0x32d0, N, N),
- PINGROUP(kb_row6_pr6, KBC, NAND, SDMMC2, MIO, 0x32d4, N, N),
- PINGROUP(kb_row7_pr7, KBC, NAND, SDMMC2, MIO, 0x32d8, N, N),
- PINGROUP(kb_row8_ps0, KBC, NAND, SDMMC2, MIO, 0x32dc, N, N),
- PINGROUP(kb_row9_ps1, KBC, NAND, SDMMC2, MIO, 0x32e0, N, N),
- PINGROUP(kb_row10_ps2, KBC, NAND, SDMMC2, MIO, 0x32e4, N, N),
- PINGROUP(kb_row11_ps3, KBC, NAND, SDMMC2, MIO, 0x32e8, N, N),
- PINGROUP(kb_row12_ps4, KBC, NAND, SDMMC2, MIO, 0x32ec, N, N),
- PINGROUP(kb_row13_ps5, KBC, NAND, SDMMC2, MIO, 0x32f0, N, N),
- PINGROUP(kb_row14_ps6, KBC, NAND, SDMMC2, MIO, 0x32f4, N, N),
- PINGROUP(kb_row15_ps7, KBC, NAND, SDMMC2, MIO, 0x32f8, N, N),
- PINGROUP(vi_pclk_pt0, RSVD1, SDMMC2, VI, RSVD4, 0x3154, N, Y),
- PINGROUP(vi_mclk_pt1, VI, VI_ALT1, VI_ALT2, VI_ALT3, 0x3158, N, Y),
- PINGROUP(vi_d10_pt2, DDR, RSVD2, VI, RSVD4, 0x314c, N, Y),
- PINGROUP(vi_d11_pt3, DDR, RSVD2, VI, RSVD4, 0x3150, N, Y),
- PINGROUP(vi_d0_pt4, DDR, RSVD2, VI, RSVD4, 0x3124, N, Y),
- PINGROUP(gen2_i2c_scl_pt5, I2C2, HDCP, GMI, RSVD4, 0x3250, Y, N),
- PINGROUP(gen2_i2c_sda_pt6, I2C2, HDCP, GMI, RSVD4, 0x3254, Y, N),
- PINGROUP(sdmmc4_cmd_pt7, I2C3, NAND, GMI, SDMMC4, 0x325c, N, Y),
- PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, 0x3184, N, N),
- PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, 0x3188, N, N),
- PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, 0x318c, N, N),
- PINGROUP(pu3, PWM0, UARTA, GMI, RSVD4, 0x3190, N, N),
- PINGROUP(pu4, PWM1, UARTA, GMI, RSVD4, 0x3194, N, N),
- PINGROUP(pu5, PWM2, UARTA, GMI, RSVD4, 0x3198, N, N),
- PINGROUP(pu6, PWM3, UARTA, GMI, RSVD4, 0x319c, N, N),
- PINGROUP(jtag_rtck_pu7, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N),
- PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, 0x3040, N, N),
- PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N),
- PINGROUP(pv2, OWR, RSVD2, RSVD3, RSVD4, 0x3060, N, N),
- PINGROUP(pv3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4, 0x3064, N, N),
- PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N),
- PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N),
- PINGROUP(crt_hsync_pv6, CRT, RSVD2, RSVD3, RSVD4, 0x311c, N, N),
- PINGROUP(crt_vsync_pv7, CRT, RSVD2, RSVD3, RSVD4, 0x3120, N, N),
- PINGROUP(lcd_cs1_n_pw0, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3104, N, N),
- PINGROUP(lcd_m1_pw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3108, N, N),
- PINGROUP(spi2_cs1_n_pw2, SPI3, SPI2, SPI2_ALT, I2C1, 0x3388, N, N),
- PINGROUP(spi2_cs2_n_pw3, SPI3, SPI2, SPI2_ALT, I2C1, 0x338c, N, N),
- PINGROUP(clk1_out_pw4, EXTPERIPH1, RSVD2, RSVD3, RSVD4, 0x334c, N, N),
- PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N),
- PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, RSVD4, 0x3174, N, N),
- PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, RSVD4, 0x3178, N, N),
- PINGROUP(spi2_mosi_px0, SPI6, SPI2, SPI3, GMI, 0x3368, N, N),
- PINGROUP(spi2_miso_px1, SPI6, SPI2, SPI3, GMI, 0x336c, N, N),
- PINGROUP(spi2_sck_px2, SPI6, SPI2, SPI3, GMI, 0x3374, N, N),
- PINGROUP(spi2_cs0_n_px3, SPI6, SPI2, SPI3, GMI, 0x3370, N, N),
- PINGROUP(spi1_mosi_px4, SPI2, SPI1, SPI2_ALT, GMI, 0x3378, N, N),
- PINGROUP(spi1_sck_px5, SPI2, SPI1, SPI2_ALT, GMI, 0x337c, N, N),
- PINGROUP(spi1_cs0_n_px6, SPI2, SPI1, SPI2_ALT, GMI, 0x3380, N, N),
- PINGROUP(spi1_miso_px7, SPI3, SPI1, SPI2_ALT, RSVD4, 0x3384, N, N),
- PINGROUP(ulpi_clk_py0, SPI1, RSVD2, UARTD, ULPI, 0x3020, N, N),
- PINGROUP(ulpi_dir_py1, SPI1, RSVD2, UARTD, ULPI, 0x3024, N, N),
- PINGROUP(ulpi_nxt_py2, SPI1, RSVD2, UARTD, ULPI, 0x3028, N, N),
- PINGROUP(ulpi_stp_py3, SPI1, RSVD2, UARTD, ULPI, 0x302c, N, N),
- PINGROUP(sdmmc1_dat3_py4, SDMMC1, RSVD2, UARTE, UARTA, 0x3050, N, N),
- PINGROUP(sdmmc1_dat2_py5, SDMMC1, RSVD2, UARTE, UARTA, 0x3054, N, N),
- PINGROUP(sdmmc1_dat1_py6, SDMMC1, RSVD2, UARTE, UARTA, 0x3058, N, N),
- PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, UARTE, UARTA, 0x305c, N, N),
- PINGROUP(sdmmc1_clk_pz0, SDMMC1, RSVD2, RSVD3, UARTA, 0x3048, N, N),
- PINGROUP(sdmmc1_cmd_pz1, SDMMC1, RSVD2, RSVD3, UARTA, 0x304c, N, N),
- PINGROUP(lcd_sdin_pz2, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3078, N, N),
- PINGROUP(lcd_wr_n_pz3, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3080, N, N),
- PINGROUP(lcd_sck_pz4, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x308c, N, N),
- PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N),
- PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N),
- PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N),
- PINGROUP(sdmmc4_dat0_paa0, UARTE, SPI3, GMI, SDMMC4, 0x3260, N, Y),
- PINGROUP(sdmmc4_dat1_paa1, UARTE, SPI3, GMI, SDMMC4, 0x3264, N, Y),
- PINGROUP(sdmmc4_dat2_paa2, UARTE, SPI3, GMI, SDMMC4, 0x3268, N, Y),
- PINGROUP(sdmmc4_dat3_paa3, UARTE, SPI3, GMI, SDMMC4, 0x326c, N, Y),
- PINGROUP(sdmmc4_dat4_paa4, I2C3, I2S4, GMI, SDMMC4, 0x3270, N, Y),
- PINGROUP(sdmmc4_dat5_paa5, VGP3, I2S4, GMI, SDMMC4, 0x3274, N, Y),
- PINGROUP(sdmmc4_dat6_paa6, VGP4, I2S4, GMI, SDMMC4, 0x3278, N, Y),
- PINGROUP(sdmmc4_dat7_paa7, VGP5, I2S4, GMI, SDMMC4, 0x327c, N, Y),
- PINGROUP(pbb0, I2S4, RSVD2, RSVD3, SDMMC4, 0x328c, N, N),
- PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC4, 0x3290, Y, N),
- PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC4, 0x3294, Y, N),
- PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC4, 0x3298, N, N),
- PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC4, 0x329c, N, N),
- PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, SDMMC4, 0x32a0, N, N),
- PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, SDMMC4, 0x32a4, N, N),
- PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC4, 0x32a8, N, N),
- PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC4, 0x3284, N, N),
- PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC4, 0x3288, N, N),
- PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, 0x32ac, N, N),
- PINGROUP(sdmmc4_rst_n_pcc3, VGP6, RSVD2, RSVD3, SDMMC4, 0x3280, N, Y),
- PINGROUP(sdmmc4_clk_pcc4, INVALID, NAND, GMI, SDMMC4, 0x3258, N, Y),
- PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N),
- PINGROUP(pex_l2_rst_n_pcc6, PCIE, HDA, RSVD3, RSVD4, 0x33d8, N, N),
- PINGROUP(pex_l2_clkreq_n_pcc7, PCIE, HDA, RSVD3, RSVD4, 0x33dc, N, N),
- PINGROUP(pex_l0_prsnt_n_pdd0, PCIE, HDA, RSVD3, RSVD4, 0x33b8, N, N),
- PINGROUP(pex_l0_rst_n_pdd1, PCIE, HDA, RSVD3, RSVD4, 0x33bc, N, N),
- PINGROUP(pex_l0_clkreq_n_pdd2, PCIE, HDA, RSVD3, RSVD4, 0x33c0, N, N),
- PINGROUP(pex_wake_n_pdd3, PCIE, HDA, RSVD3, RSVD4, 0x33c4, N, N),
- PINGROUP(pex_l1_prsnt_n_pdd4, PCIE, HDA, RSVD3, RSVD4, 0x33c8, N, N),
- PINGROUP(pex_l1_rst_n_pdd5, PCIE, HDA, RSVD3, RSVD4, 0x33cc, N, N),
- PINGROUP(pex_l1_clkreq_n_pdd6, PCIE, HDA, RSVD3, RSVD4, 0x33d0, N, N),
- PINGROUP(pex_l2_prsnt_n_pdd7, PCIE, HDA, RSVD3, RSVD4, 0x33d4, N, N),
- PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N),
- PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N),
- PINGROUP(clk1_req_pee2, DAP, HDA, RSVD3, RSVD4, 0x3348, N, N),
- PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, 0x33e0, Y, N),
- PINGROUP(clk_32k_in, CLK_32K_IN, RSVD2, RSVD3, RSVD4, 0x3330, N, N),
- PINGROUP(core_pwr_req, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4, 0x3324, N, N),
- PINGROUP(cpu_pwr_req, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4, 0x3328, N, N),
- PINGROUP(owr, OWR, CEC, RSVD3, RSVD4, 0x3334, N, N),
- PINGROUP(pwr_int_n, PWR_INT_N, RSVD2, RSVD3, RSVD4, 0x332c, N, N),
- /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
- DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(at1, 0x870, 2, 3, 4, 14, 5, 19, 5, 24, 2, 28, 2),
- DRV_PINGROUP(at2, 0x874, 2, 3, 4, 14, 5, 19, 5, 24, 2, 28, 2),
- DRV_PINGROUP(at3, 0x878, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
- DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
- DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
- DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(crt, 0x8f8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(csus, 0x88c, -1, -1, -1, 12, 5, 19, 5, 24, 4, 28, 4),
- DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(gma, 0x900, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
- DRV_PINGROUP(gmb, 0x904, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
- DRV_PINGROUP(gmc, 0x908, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
- DRV_PINGROUP(gmd, 0x90c, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
- DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
- DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
- DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
- DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
- DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(lcd1, 0x8a4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(lcd2, 0x8a8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2),
- DRV_PINGROUP(sdio2, 0x8ac, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2),
- DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2),
- DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
- DRV_PINGROUP(vi1, 0x8c8, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
-};
-
-static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
- .ngpios = NUM_GPIOS,
- .pins = tegra30_pins,
- .npins = ARRAY_SIZE(tegra30_pins),
- .functions = tegra30_functions,
- .nfunctions = ARRAY_SIZE(tegra30_functions),
- .groups = tegra30_groups,
- .ngroups = ARRAY_SIZE(tegra30_groups),
- .hsm_in_mux = false,
- .schmitt_in_mux = false,
- .drvtype_in_mux = false,
-};
-
-static int tegra30_pinctrl_probe(struct platform_device *pdev)
-{
- return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
-}
-
-static const struct of_device_id tegra30_pinctrl_of_match[] = {
- { .compatible = "nvidia,tegra30-pinmux", },
- { },
-};
-MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
-
-static struct platform_driver tegra30_pinctrl_driver = {
- .driver = {
- .name = "tegra30-pinctrl",
- .of_match_table = tegra30_pinctrl_of_match,
- },
- .probe = tegra30_pinctrl_probe,
- .remove = tegra_pinctrl_remove,
-};
-module_platform_driver(tegra30_pinctrl_driver);
-
-MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
-MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver");
-MODULE_LICENSE("GPL v2");
static const char * const mdio0_groups[] = {"mdio0_0_grp"};
static const char * const mdio1_groups[] = {"mdio1_0_grp"};
static const char * const qspi0_groups[] = {"qspi0_0_grp"};
-static const char * const qspi1_groups[] = {"qspi0_1_grp"};
+static const char * const qspi1_groups[] = {"qspi1_0_grp"};
static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"};
static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"};
static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp",
return 0;
}
-EXPORT_SYMBOL(pxa2xx_pinctrl_init);
+EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_init);
int pxa2xx_pinctrl_exit(struct platform_device *pdev)
{
pinctrl_unregister(pctl->pctl_dev);
return 0;
}
+EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_exit);
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
+config PINCTRL_IPQ4019
+ tristate "Qualcomm IPQ4019 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.
+
config PINCTRL_IPQ8064
tristate "Qualcomm IPQ8064 pin controller driver"
depends on GPIOLIB && OF
obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
+obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
--- /dev/null
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+static const struct pinctrl_pin_desc ipq4019_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+};
+
+#define DECLARE_QCA_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_QCA_GPIO_PINS(0);
+DECLARE_QCA_GPIO_PINS(1);
+DECLARE_QCA_GPIO_PINS(2);
+DECLARE_QCA_GPIO_PINS(3);
+DECLARE_QCA_GPIO_PINS(4);
+DECLARE_QCA_GPIO_PINS(5);
+DECLARE_QCA_GPIO_PINS(6);
+DECLARE_QCA_GPIO_PINS(7);
+DECLARE_QCA_GPIO_PINS(8);
+DECLARE_QCA_GPIO_PINS(9);
+DECLARE_QCA_GPIO_PINS(10);
+DECLARE_QCA_GPIO_PINS(11);
+DECLARE_QCA_GPIO_PINS(12);
+DECLARE_QCA_GPIO_PINS(13);
+DECLARE_QCA_GPIO_PINS(14);
+DECLARE_QCA_GPIO_PINS(15);
+DECLARE_QCA_GPIO_PINS(16);
+DECLARE_QCA_GPIO_PINS(17);
+DECLARE_QCA_GPIO_PINS(18);
+DECLARE_QCA_GPIO_PINS(19);
+DECLARE_QCA_GPIO_PINS(20);
+DECLARE_QCA_GPIO_PINS(21);
+DECLARE_QCA_GPIO_PINS(22);
+DECLARE_QCA_GPIO_PINS(23);
+DECLARE_QCA_GPIO_PINS(24);
+DECLARE_QCA_GPIO_PINS(25);
+DECLARE_QCA_GPIO_PINS(26);
+DECLARE_QCA_GPIO_PINS(27);
+DECLARE_QCA_GPIO_PINS(28);
+DECLARE_QCA_GPIO_PINS(29);
+DECLARE_QCA_GPIO_PINS(30);
+DECLARE_QCA_GPIO_PINS(31);
+DECLARE_QCA_GPIO_PINS(32);
+DECLARE_QCA_GPIO_PINS(33);
+DECLARE_QCA_GPIO_PINS(34);
+DECLARE_QCA_GPIO_PINS(35);
+DECLARE_QCA_GPIO_PINS(36);
+DECLARE_QCA_GPIO_PINS(37);
+DECLARE_QCA_GPIO_PINS(38);
+DECLARE_QCA_GPIO_PINS(39);
+DECLARE_QCA_GPIO_PINS(40);
+DECLARE_QCA_GPIO_PINS(41);
+DECLARE_QCA_GPIO_PINS(42);
+DECLARE_QCA_GPIO_PINS(43);
+DECLARE_QCA_GPIO_PINS(44);
+DECLARE_QCA_GPIO_PINS(45);
+DECLARE_QCA_GPIO_PINS(46);
+DECLARE_QCA_GPIO_PINS(47);
+DECLARE_QCA_GPIO_PINS(48);
+DECLARE_QCA_GPIO_PINS(49);
+DECLARE_QCA_GPIO_PINS(50);
+DECLARE_QCA_GPIO_PINS(51);
+DECLARE_QCA_GPIO_PINS(52);
+DECLARE_QCA_GPIO_PINS(53);
+DECLARE_QCA_GPIO_PINS(54);
+DECLARE_QCA_GPIO_PINS(55);
+DECLARE_QCA_GPIO_PINS(56);
+DECLARE_QCA_GPIO_PINS(57);
+DECLARE_QCA_GPIO_PINS(58);
+DECLARE_QCA_GPIO_PINS(59);
+DECLARE_QCA_GPIO_PINS(60);
+DECLARE_QCA_GPIO_PINS(61);
+DECLARE_QCA_GPIO_PINS(62);
+DECLARE_QCA_GPIO_PINS(63);
+DECLARE_QCA_GPIO_PINS(64);
+DECLARE_QCA_GPIO_PINS(65);
+DECLARE_QCA_GPIO_PINS(66);
+DECLARE_QCA_GPIO_PINS(67);
+DECLARE_QCA_GPIO_PINS(68);
+DECLARE_QCA_GPIO_PINS(69);
+DECLARE_QCA_GPIO_PINS(70);
+DECLARE_QCA_GPIO_PINS(71);
+DECLARE_QCA_GPIO_PINS(72);
+DECLARE_QCA_GPIO_PINS(73);
+DECLARE_QCA_GPIO_PINS(74);
+DECLARE_QCA_GPIO_PINS(75);
+DECLARE_QCA_GPIO_PINS(76);
+DECLARE_QCA_GPIO_PINS(77);
+DECLARE_QCA_GPIO_PINS(78);
+DECLARE_QCA_GPIO_PINS(79);
+DECLARE_QCA_GPIO_PINS(80);
+DECLARE_QCA_GPIO_PINS(81);
+DECLARE_QCA_GPIO_PINS(82);
+DECLARE_QCA_GPIO_PINS(83);
+DECLARE_QCA_GPIO_PINS(84);
+DECLARE_QCA_GPIO_PINS(85);
+DECLARE_QCA_GPIO_PINS(86);
+DECLARE_QCA_GPIO_PINS(87);
+DECLARE_QCA_GPIO_PINS(88);
+DECLARE_QCA_GPIO_PINS(89);
+DECLARE_QCA_GPIO_PINS(90);
+DECLARE_QCA_GPIO_PINS(91);
+DECLARE_QCA_GPIO_PINS(92);
+DECLARE_QCA_GPIO_PINS(93);
+DECLARE_QCA_GPIO_PINS(94);
+DECLARE_QCA_GPIO_PINS(95);
+DECLARE_QCA_GPIO_PINS(96);
+DECLARE_QCA_GPIO_PINS(97);
+DECLARE_QCA_GPIO_PINS(98);
+DECLARE_QCA_GPIO_PINS(99);
+
+#define FUNCTION(fname) \
+ [qca_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ qca_mux_NA, /* gpio mode */ \
+ qca_mux_##f1, \
+ qca_mux_##f2, \
+ qca_mux_##f3, \
+ qca_mux_##f4, \
+ qca_mux_##f5, \
+ qca_mux_##f6, \
+ qca_mux_##f7, \
+ qca_mux_##f8, \
+ qca_mux_##f9, \
+ qca_mux_##f10, \
+ qca_mux_##f11, \
+ qca_mux_##f12, \
+ qca_mux_##f13, \
+ qca_mux_##f14 \
+ }, \
+ .nfuncs = 15, \
+ .ctl_reg = 0x1000 + 0x10 * id, \
+ .io_reg = 0x1004 + 0x10 * id, \
+ .intr_cfg_reg = 0x1008 + 0x10 * id, \
+ .intr_status_reg = 0x100c + 0x10 * id, \
+ .intr_target_reg = 0x400 + 0x4 * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+
+enum ipq4019_functions {
+ qca_mux_gpio,
+ qca_mux_blsp_uart1,
+ qca_mux_blsp_i2c0,
+ qca_mux_blsp_i2c1,
+ qca_mux_blsp_uart0,
+ qca_mux_blsp_spi1,
+ qca_mux_blsp_spi0,
+ qca_mux_NA,
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
+ "gpio99",
+};
+
+static const char * const blsp_uart1_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+static const char * const blsp_i2c0_groups[] = {
+ "gpio10", "gpio11", "gpio20", "gpio21", "gpio58", "gpio59",
+};
+static const char * const blsp_spi0_groups[] = {
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio45",
+ "gpio54", "gpio55", "gpio56", "gpio57",
+};
+static const char * const blsp_i2c1_groups[] = {
+ "gpio12", "gpio13", "gpio34", "gpio35",
+};
+static const char * const blsp_uart0_groups[] = {
+ "gpio16", "gpio17", "gpio60", "gpio61",
+};
+static const char * const blsp_spi1_groups[] = {
+ "gpio44", "gpio45", "gpio46", "gpio47",
+};
+
+static const struct msm_function ipq4019_functions[] = {
+ FUNCTION(gpio),
+ FUNCTION(blsp_uart1),
+ FUNCTION(blsp_i2c0),
+ FUNCTION(blsp_i2c1),
+ FUNCTION(blsp_uart0),
+ FUNCTION(blsp_spi1),
+ FUNCTION(blsp_spi0),
+};
+
+static const struct msm_pingroup ipq4019_groups[] = {
+ PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(5, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(6, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(8, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(9, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(16, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(17, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(18, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(19, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(20, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(21, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(22, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(24, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(25, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(27, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(28, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(30, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(33, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(34, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(35, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(37, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(44, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(45, NA, blsp_spi1, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(46, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(47, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(48, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(49, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(50, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(51, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(52, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(53, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(54, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(55, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(56, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(57, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(58, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(59, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(60, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(61, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+};
+
+static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
+ .pins = ipq4019_pins,
+ .npins = ARRAY_SIZE(ipq4019_pins),
+ .functions = ipq4019_functions,
+ .nfunctions = ARRAY_SIZE(ipq4019_functions),
+ .groups = ipq4019_groups,
+ .ngroups = ARRAY_SIZE(ipq4019_groups),
+ .ngpios = 70,
+};
+
+static int ipq4019_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &ipq4019_pinctrl);
+}
+
+static const struct of_device_id ipq4019_pinctrl_of_match[] = {
+ { .compatible = "qcom,ipq4019-pinctrl", },
+ { },
+};
+
+static struct platform_driver ipq4019_pinctrl_driver = {
+ .driver = {
+ .name = "ipq4019-pinctrl",
+ .of_match_table = ipq4019_pinctrl_of_match,
+ },
+ .probe = ipq4019_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init ipq4019_pinctrl_init(void)
+{
+ return platform_driver_register(&ipq4019_pinctrl_driver);
+}
+arch_initcall(ipq4019_pinctrl_init);
+
+static void __exit ipq4019_pinctrl_exit(void)
+{
+ platform_driver_unregister(&ipq4019_pinctrl_driver);
+}
+module_exit(ipq4019_pinctrl_exit);
+
+MODULE_DESCRIPTION("Qualcomm ipq4019 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, ipq4019_pinctrl_of_match);
* @output_enabled: Set to true if MPP output logic is enabled.
* @input_enabled: Set to true if MPP input buffer logic is enabled.
* @paired: Pin operates in paired mode
+ * @has_pullup: Pin has support to configure pullup
* @num_sources: Number of power-sources supported by this MPP.
* @power_source: Current power-source used.
* @amux_input: Set the source for analog input.
bool output_enabled;
bool input_enabled;
bool paired;
+ bool has_pullup;
unsigned int num_sources;
unsigned int power_source;
unsigned int amux_input;
if (ret < 0)
return ret;
- val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT;
+ if (pad->has_pullup) {
+ val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT;
- ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, val);
- if (ret < 0)
- return ret;
+ ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL,
+ val);
+ if (ret < 0)
+ return ret;
+ }
val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK;
seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]);
seq_printf(s, " vin-%d", pad->power_source);
seq_printf(s, " %d", pad->aout_level);
- seq_printf(s, " %-8s", biases[pad->pullup]);
+ if (pad->has_pullup)
+ seq_printf(s, " %-8s", biases[pad->pullup]);
seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
if (pad->dtest)
seq_printf(s, " dtest%d", pad->dtest);
pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT;
pad->power_source &= PMIC_MPP_REG_VIN_MASK;
- val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL);
- if (val < 0)
- return val;
+ if (subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT &&
+ subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK) {
+ val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL);
+ if (val < 0)
+ return val;
- pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT;
- pad->pullup &= PMIC_MPP_REG_PULL_MASK;
+ pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT;
+ pad->pullup &= PMIC_MPP_REG_PULL_MASK;
+ pad->has_pullup = true;
+ }
val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL);
if (val < 0)
# Renesas SH and SH Mobile PINCTRL drivers
#
-if ARCH_SHMOBILE || SUPERH
+if ARCH_RENESAS || SUPERH
config PINCTRL_SH_PFC
- select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
select PINMUX
select PINCONF
select GENERIC_PINCONF
help
This enables pin control drivers for SH and SH Mobile platforms
-config GPIO_SH_PFC
- bool "SuperH PFC GPIO support"
- depends on PINCTRL_SH_PFC && GPIOLIB
+config PINCTRL_SH_PFC_GPIO
+ select GPIOLIB
+ select PINCTRL_SH_PFC
+ bool
help
- This enables support for GPIOs within the SoC's pin function
- controller.
+ This enables pin control and GPIO drivers for SH/SH Mobile platforms
config PINCTRL_PFC_EMEV2
def_bool y
config PINCTRL_PFC_R8A73A4
def_bool y
depends on ARCH_R8A73A4
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A7740
def_bool y
depends on ARCH_R8A7740
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A7778
def_bool y
config PINCTRL_PFC_SH7203
def_bool y
depends on CPU_SUBTYPE_SH7203
- depends on GPIOLIB
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7264
def_bool y
depends on CPU_SUBTYPE_SH7264
- depends on GPIOLIB
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7269
def_bool y
depends on CPU_SUBTYPE_SH7269
- depends on GPIOLIB
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH73A0
def_bool y
depends on ARCH_SH73A0
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
select REGULATOR
config PINCTRL_PFC_SH7720
def_bool y
depends on CPU_SUBTYPE_SH7720
- depends on GPIOLIB
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7722
def_bool y
depends on CPU_SUBTYPE_SH7722
- depends on GPIOLIB
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7723
def_bool y
depends on CPU_SUBTYPE_SH7723
- depends on GPIOLIB
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7724
def_bool y
depends on CPU_SUBTYPE_SH7724
- depends on GPIOLIB
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7734
def_bool y
depends on CPU_SUBTYPE_SH7734
- depends on GPIOLIB
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7757
def_bool y
depends on CPU_SUBTYPE_SH7757
- depends on GPIOLIB
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7785
def_bool y
depends on CPU_SUBTYPE_SH7785
- depends on GPIOLIB
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7786
def_bool y
depends on CPU_SUBTYPE_SH7786
- depends on GPIOLIB
- select PINCTRL_SH_PFC
+ select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SHX3
def_bool y
depends on CPU_SUBTYPE_SHX3
- depends on GPIOLIB
- select PINCTRL_SH_PFC
-
+ select PINCTRL_SH_PFC_GPIO
endif
-sh-pfc-objs = core.o pinctrl.o
-ifeq ($(CONFIG_GPIO_SH_PFC),y)
-sh-pfc-objs += gpio.o
-endif
-obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
+obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o
+obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o
obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
/*
- * SuperH Pin Function Controller support.
+ * Pin Control and GPIO driver for SuperH Pin Function Controller.
+ *
+ * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
*
* Copyright (C) 2008 Magnus Damm
* Copyright (C) 2009 - 2012 Paul Mundt
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
#endif
{ },
};
-MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
#endif
static int sh_pfc_probe(struct platform_device *pdev)
#ifdef CONFIG_OF
if (np)
- info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
+ info = of_device_get_match_data(&pdev->dev);
else
#endif
info = platid ? (const void *)platid->driver_data : NULL;
if (unlikely(ret != 0))
return ret;
-#ifdef CONFIG_GPIO_SH_PFC
+#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
/*
* Then the GPIO chip
*/
{
struct sh_pfc *pfc = platform_get_drvdata(pdev);
-#ifdef CONFIG_GPIO_SH_PFC
+#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
sh_pfc_unregister_gpiochip(pfc);
#endif
sh_pfc_unregister_pinctrl(pfc);
{ "sh-pfc", 0 },
{ },
};
-MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
static struct platform_driver sh_pfc_driver = {
.probe = sh_pfc_probe,
return platform_driver_register(&sh_pfc_driver);
}
postcore_initcall(sh_pfc_init);
-
-static void __exit sh_pfc_exit(void)
-{
- platform_driver_unregister(&sh_pfc_driver);
-}
-module_exit(sh_pfc_exit);
-
-MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
-MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
-MODULE_LICENSE("GPL v2");
PINMUX_SINGLE(AVS2),
/* IPSR0 */
- PINMUX_IPSR_DATA(IP0_1_0, PRESETOUT),
- PINMUX_IPSR_DATA(IP0_1_0, PWM1),
+ PINMUX_IPSR_GPSR(IP0_1_0, PRESETOUT),
+ PINMUX_IPSR_GPSR(IP0_1_0, PWM1),
- PINMUX_IPSR_DATA(IP0_4_2, AUDATA0),
- PINMUX_IPSR_DATA(IP0_4_2, ARM_TRACEDATA_0),
+ PINMUX_IPSR_GPSR(IP0_4_2, AUDATA0),
+ PINMUX_IPSR_GPSR(IP0_4_2, ARM_TRACEDATA_0),
PINMUX_IPSR_MSEL(IP0_4_2, GPSCLK_C, SEL_GPS_C),
- PINMUX_IPSR_DATA(IP0_4_2, USB_OVC0),
- PINMUX_IPSR_DATA(IP0_4_2, TX2_E),
+ PINMUX_IPSR_GPSR(IP0_4_2, USB_OVC0),
+ PINMUX_IPSR_GPSR(IP0_4_2, TX2_E),
PINMUX_IPSR_MSEL(IP0_4_2, SDA2_B, SEL_I2C2_B),
- PINMUX_IPSR_DATA(IP0_7_5, AUDATA1),
- PINMUX_IPSR_DATA(IP0_7_5, ARM_TRACEDATA_1),
+ PINMUX_IPSR_GPSR(IP0_7_5, AUDATA1),
+ PINMUX_IPSR_GPSR(IP0_7_5, ARM_TRACEDATA_1),
PINMUX_IPSR_MSEL(IP0_7_5, GPSIN_C, SEL_GPS_C),
- PINMUX_IPSR_DATA(IP0_7_5, USB_OVC1),
+ PINMUX_IPSR_GPSR(IP0_7_5, USB_OVC1),
PINMUX_IPSR_MSEL(IP0_7_5, RX2_E, SEL_SCIF2_E),
PINMUX_IPSR_MSEL(IP0_7_5, SCL2_B, SEL_I2C2_B),
PINMUX_IPSR_MSEL(IP0_11_8, SD1_DAT2_A, SEL_SD1_A),
- PINMUX_IPSR_DATA(IP0_11_8, MMC_D2),
- PINMUX_IPSR_DATA(IP0_11_8, BS),
- PINMUX_IPSR_DATA(IP0_11_8, ATADIR0_A),
- PINMUX_IPSR_DATA(IP0_11_8, SDSELF_A),
- PINMUX_IPSR_DATA(IP0_11_8, PWM4_B),
+ PINMUX_IPSR_GPSR(IP0_11_8, MMC_D2),
+ PINMUX_IPSR_GPSR(IP0_11_8, BS),
+ PINMUX_IPSR_GPSR(IP0_11_8, ATADIR0_A),
+ PINMUX_IPSR_GPSR(IP0_11_8, SDSELF_A),
+ PINMUX_IPSR_GPSR(IP0_11_8, PWM4_B),
PINMUX_IPSR_MSEL(IP0_14_12, SD1_DAT3_A, SEL_SD1_A),
- PINMUX_IPSR_DATA(IP0_14_12, MMC_D3),
- PINMUX_IPSR_DATA(IP0_14_12, A0),
- PINMUX_IPSR_DATA(IP0_14_12, ATAG0_A),
+ PINMUX_IPSR_GPSR(IP0_14_12, MMC_D3),
+ PINMUX_IPSR_GPSR(IP0_14_12, A0),
+ PINMUX_IPSR_GPSR(IP0_14_12, ATAG0_A),
PINMUX_IPSR_MSEL(IP0_14_12, REMOCON_B, SEL_REMOCON_B),
- PINMUX_IPSR_DATA(IP0_15, A4),
- PINMUX_IPSR_DATA(IP0_16, A5),
- PINMUX_IPSR_DATA(IP0_17, A6),
- PINMUX_IPSR_DATA(IP0_18, A7),
- PINMUX_IPSR_DATA(IP0_19, A8),
- PINMUX_IPSR_DATA(IP0_20, A9),
- PINMUX_IPSR_DATA(IP0_21, A10),
- PINMUX_IPSR_DATA(IP0_22, A11),
- PINMUX_IPSR_DATA(IP0_23, A12),
- PINMUX_IPSR_DATA(IP0_24, A13),
- PINMUX_IPSR_DATA(IP0_25, A14),
- PINMUX_IPSR_DATA(IP0_26, A15),
- PINMUX_IPSR_DATA(IP0_27, A16),
- PINMUX_IPSR_DATA(IP0_28, A17),
- PINMUX_IPSR_DATA(IP0_29, A18),
- PINMUX_IPSR_DATA(IP0_30, A19),
+ PINMUX_IPSR_GPSR(IP0_15, A4),
+ PINMUX_IPSR_GPSR(IP0_16, A5),
+ PINMUX_IPSR_GPSR(IP0_17, A6),
+ PINMUX_IPSR_GPSR(IP0_18, A7),
+ PINMUX_IPSR_GPSR(IP0_19, A8),
+ PINMUX_IPSR_GPSR(IP0_20, A9),
+ PINMUX_IPSR_GPSR(IP0_21, A10),
+ PINMUX_IPSR_GPSR(IP0_22, A11),
+ PINMUX_IPSR_GPSR(IP0_23, A12),
+ PINMUX_IPSR_GPSR(IP0_24, A13),
+ PINMUX_IPSR_GPSR(IP0_25, A14),
+ PINMUX_IPSR_GPSR(IP0_26, A15),
+ PINMUX_IPSR_GPSR(IP0_27, A16),
+ PINMUX_IPSR_GPSR(IP0_28, A17),
+ PINMUX_IPSR_GPSR(IP0_29, A18),
+ PINMUX_IPSR_GPSR(IP0_30, A19),
/* IPSR1 */
- PINMUX_IPSR_DATA(IP1_0, A20),
+ PINMUX_IPSR_GPSR(IP1_0, A20),
PINMUX_IPSR_MSEL(IP1_0, HSPI_CS1_B, SEL_HSPI1_B),
- PINMUX_IPSR_DATA(IP1_1, A21),
+ PINMUX_IPSR_GPSR(IP1_1, A21),
PINMUX_IPSR_MSEL(IP1_1, HSPI_CLK1_B, SEL_HSPI1_B),
- PINMUX_IPSR_DATA(IP1_4_2, A22),
+ PINMUX_IPSR_GPSR(IP1_4_2, A22),
PINMUX_IPSR_MSEL(IP1_4_2, HRTS0_B, SEL_HSCIF0_B),
PINMUX_IPSR_MSEL(IP1_4_2, RX2_B, SEL_SCIF2_B),
PINMUX_IPSR_MSEL(IP1_4_2, DREQ2_A, SEL_DREQ2_A),
- PINMUX_IPSR_DATA(IP1_7_5, A23),
- PINMUX_IPSR_DATA(IP1_7_5, HTX0_B),
- PINMUX_IPSR_DATA(IP1_7_5, TX2_B),
- PINMUX_IPSR_DATA(IP1_7_5, DACK2_A),
+ PINMUX_IPSR_GPSR(IP1_7_5, A23),
+ PINMUX_IPSR_GPSR(IP1_7_5, HTX0_B),
+ PINMUX_IPSR_GPSR(IP1_7_5, TX2_B),
+ PINMUX_IPSR_GPSR(IP1_7_5, DACK2_A),
PINMUX_IPSR_MSEL(IP1_7_5, TS_SDEN0_A, SEL_TSIF0_A),
PINMUX_IPSR_MSEL(IP1_10_8, SD1_CD_A, SEL_SD1_A),
- PINMUX_IPSR_DATA(IP1_10_8, MMC_D6),
- PINMUX_IPSR_DATA(IP1_10_8, A24),
+ PINMUX_IPSR_GPSR(IP1_10_8, MMC_D6),
+ PINMUX_IPSR_GPSR(IP1_10_8, A24),
PINMUX_IPSR_MSEL(IP1_10_8, DREQ1_A, SEL_DREQ1_A),
PINMUX_IPSR_MSEL(IP1_10_8, HRX0_B, SEL_HSCIF0_B),
PINMUX_IPSR_MSEL(IP1_10_8, TS_SPSYNC0_A, SEL_TSIF0_A),
PINMUX_IPSR_MSEL(IP1_14_11, SD1_WP_A, SEL_SD1_A),
- PINMUX_IPSR_DATA(IP1_14_11, MMC_D7),
- PINMUX_IPSR_DATA(IP1_14_11, A25),
- PINMUX_IPSR_DATA(IP1_14_11, DACK1_A),
+ PINMUX_IPSR_GPSR(IP1_14_11, MMC_D7),
+ PINMUX_IPSR_GPSR(IP1_14_11, A25),
+ PINMUX_IPSR_GPSR(IP1_14_11, DACK1_A),
PINMUX_IPSR_MSEL(IP1_14_11, HCTS0_B, SEL_HSCIF0_B),
PINMUX_IPSR_MSEL(IP1_14_11, RX3_C, SEL_SCIF3_C),
PINMUX_IPSR_MSEL(IP1_14_11, TS_SDAT0_A, SEL_TSIF0_A),
PINMUX_IPSR_NOGM(IP1_20_18, SDA2_A, SEL_I2C2_A),
PINMUX_IPSR_NOGM(IP1_20_18, SCK2_B, SEL_SCIF2_B),
- PINMUX_IPSR_DATA(IP1_23_21, MMC_D5),
- PINMUX_IPSR_DATA(IP1_23_21, ATADIR0_B),
- PINMUX_IPSR_DATA(IP1_23_21, RD_WR),
+ PINMUX_IPSR_GPSR(IP1_23_21, MMC_D5),
+ PINMUX_IPSR_GPSR(IP1_23_21, ATADIR0_B),
+ PINMUX_IPSR_GPSR(IP1_23_21, RD_WR),
- PINMUX_IPSR_DATA(IP1_24, WE1),
- PINMUX_IPSR_DATA(IP1_24, ATAWR0_B),
+ PINMUX_IPSR_GPSR(IP1_24, WE1),
+ PINMUX_IPSR_GPSR(IP1_24, ATAWR0_B),
PINMUX_IPSR_MSEL(IP1_27_25, SSI_WS1_B, SEL_SSI1_B),
- PINMUX_IPSR_DATA(IP1_27_25, EX_CS0),
+ PINMUX_IPSR_GPSR(IP1_27_25, EX_CS0),
PINMUX_IPSR_MSEL(IP1_27_25, SCL2_A, SEL_I2C2_A),
- PINMUX_IPSR_DATA(IP1_27_25, TX3_C),
+ PINMUX_IPSR_GPSR(IP1_27_25, TX3_C),
PINMUX_IPSR_MSEL(IP1_27_25, TS_SCK0_A, SEL_TSIF0_A),
- PINMUX_IPSR_DATA(IP1_29_28, EX_CS1),
- PINMUX_IPSR_DATA(IP1_29_28, MMC_D4),
+ PINMUX_IPSR_GPSR(IP1_29_28, EX_CS1),
+ PINMUX_IPSR_GPSR(IP1_29_28, MMC_D4),
/* IPSR2 */
- PINMUX_IPSR_DATA(IP2_2_0, SD1_CLK_A),
- PINMUX_IPSR_DATA(IP2_2_0, MMC_CLK),
- PINMUX_IPSR_DATA(IP2_2_0, ATACS00),
- PINMUX_IPSR_DATA(IP2_2_0, EX_CS2),
+ PINMUX_IPSR_GPSR(IP2_2_0, SD1_CLK_A),
+ PINMUX_IPSR_GPSR(IP2_2_0, MMC_CLK),
+ PINMUX_IPSR_GPSR(IP2_2_0, ATACS00),
+ PINMUX_IPSR_GPSR(IP2_2_0, EX_CS2),
PINMUX_IPSR_MSEL(IP2_5_3, SD1_CMD_A, SEL_SD1_A),
- PINMUX_IPSR_DATA(IP2_5_3, MMC_CMD),
- PINMUX_IPSR_DATA(IP2_5_3, ATACS10),
- PINMUX_IPSR_DATA(IP2_5_3, EX_CS3),
+ PINMUX_IPSR_GPSR(IP2_5_3, MMC_CMD),
+ PINMUX_IPSR_GPSR(IP2_5_3, ATACS10),
+ PINMUX_IPSR_GPSR(IP2_5_3, EX_CS3),
PINMUX_IPSR_MSEL(IP2_8_6, SD1_DAT0_A, SEL_SD1_A),
- PINMUX_IPSR_DATA(IP2_8_6, MMC_D0),
- PINMUX_IPSR_DATA(IP2_8_6, ATARD0),
- PINMUX_IPSR_DATA(IP2_8_6, EX_CS4),
+ PINMUX_IPSR_GPSR(IP2_8_6, MMC_D0),
+ PINMUX_IPSR_GPSR(IP2_8_6, ATARD0),
+ PINMUX_IPSR_GPSR(IP2_8_6, EX_CS4),
PINMUX_IPSR_MSEL(IP2_8_6, EX_WAIT1_A, SEL_WAIT1_A),
PINMUX_IPSR_MSEL(IP2_11_9, SD1_DAT1_A, SEL_SD1_A),
- PINMUX_IPSR_DATA(IP2_11_9, MMC_D1),
- PINMUX_IPSR_DATA(IP2_11_9, ATAWR0_A),
- PINMUX_IPSR_DATA(IP2_11_9, EX_CS5),
+ PINMUX_IPSR_GPSR(IP2_11_9, MMC_D1),
+ PINMUX_IPSR_GPSR(IP2_11_9, ATAWR0_A),
+ PINMUX_IPSR_GPSR(IP2_11_9, EX_CS5),
PINMUX_IPSR_MSEL(IP2_11_9, EX_WAIT2_A, SEL_WAIT2_A),
PINMUX_IPSR_MSEL(IP2_13_12, DREQ0_A, SEL_DREQ0_A),
PINMUX_IPSR_MSEL(IP2_13_12, RX3_A, SEL_SCIF3_A),
- PINMUX_IPSR_DATA(IP2_16_14, DACK0),
- PINMUX_IPSR_DATA(IP2_16_14, TX3_A),
- PINMUX_IPSR_DATA(IP2_16_14, DRACK0),
+ PINMUX_IPSR_GPSR(IP2_16_14, DACK0),
+ PINMUX_IPSR_GPSR(IP2_16_14, TX3_A),
+ PINMUX_IPSR_GPSR(IP2_16_14, DRACK0),
- PINMUX_IPSR_DATA(IP2_17, EX_WAIT0),
- PINMUX_IPSR_DATA(IP2_17, PWM0_C),
+ PINMUX_IPSR_GPSR(IP2_17, EX_WAIT0),
+ PINMUX_IPSR_GPSR(IP2_17, PWM0_C),
PINMUX_IPSR_NOGP(IP2_18, D0),
PINMUX_IPSR_NOGP(IP2_19, D1),
PINMUX_IPSR_NOGP(IP2_28, D10),
PINMUX_IPSR_NOGP(IP2_29, D11),
- PINMUX_IPSR_DATA(IP2_30, RD_WR_B),
- PINMUX_IPSR_DATA(IP2_30, IRQ0),
+ PINMUX_IPSR_GPSR(IP2_30, RD_WR_B),
+ PINMUX_IPSR_GPSR(IP2_30, IRQ0),
- PINMUX_IPSR_DATA(IP2_31, MLB_CLK),
+ PINMUX_IPSR_GPSR(IP2_31, MLB_CLK),
PINMUX_IPSR_MSEL(IP2_31, IRQ1_A, SEL_IRQ1_A),
/* IPSR3 */
- PINMUX_IPSR_DATA(IP3_1_0, MLB_SIG),
+ PINMUX_IPSR_GPSR(IP3_1_0, MLB_SIG),
PINMUX_IPSR_MSEL(IP3_1_0, RX5_B, SEL_SCIF5_B),
PINMUX_IPSR_MSEL(IP3_1_0, SDA3_A, SEL_I2C3_A),
PINMUX_IPSR_MSEL(IP3_1_0, IRQ2_A, SEL_IRQ2_A),
- PINMUX_IPSR_DATA(IP3_4_2, MLB_DAT),
- PINMUX_IPSR_DATA(IP3_4_2, TX5_B),
+ PINMUX_IPSR_GPSR(IP3_4_2, MLB_DAT),
+ PINMUX_IPSR_GPSR(IP3_4_2, TX5_B),
PINMUX_IPSR_MSEL(IP3_4_2, SCL3_A, SEL_I2C3_A),
PINMUX_IPSR_MSEL(IP3_4_2, IRQ3_A, SEL_IRQ3_A),
- PINMUX_IPSR_DATA(IP3_4_2, SDSELF_B),
+ PINMUX_IPSR_GPSR(IP3_4_2, SDSELF_B),
PINMUX_IPSR_MSEL(IP3_7_5, SD1_CMD_B, SEL_SD1_B),
- PINMUX_IPSR_DATA(IP3_7_5, SCIF_CLK),
- PINMUX_IPSR_DATA(IP3_7_5, AUDIO_CLKOUT_B),
+ PINMUX_IPSR_GPSR(IP3_7_5, SCIF_CLK),
+ PINMUX_IPSR_GPSR(IP3_7_5, AUDIO_CLKOUT_B),
PINMUX_IPSR_MSEL(IP3_7_5, CAN_CLK_B, SEL_CANCLK_B),
PINMUX_IPSR_MSEL(IP3_7_5, SDA3_B, SEL_I2C3_B),
- PINMUX_IPSR_DATA(IP3_9_8, SD1_CLK_B),
- PINMUX_IPSR_DATA(IP3_9_8, HTX0_A),
- PINMUX_IPSR_DATA(IP3_9_8, TX0_A),
+ PINMUX_IPSR_GPSR(IP3_9_8, SD1_CLK_B),
+ PINMUX_IPSR_GPSR(IP3_9_8, HTX0_A),
+ PINMUX_IPSR_GPSR(IP3_9_8, TX0_A),
PINMUX_IPSR_MSEL(IP3_12_10, SD1_DAT0_B, SEL_SD1_B),
PINMUX_IPSR_MSEL(IP3_12_10, HRX0_A, SEL_HSCIF0_A),
PINMUX_IPSR_MSEL(IP3_15_13, SD1_DAT1_B, SEL_SD1_B),
PINMUX_IPSR_MSEL(IP3_15_13, HSCK0, SEL_HSCIF0_A),
- PINMUX_IPSR_DATA(IP3_15_13, SCK0),
+ PINMUX_IPSR_GPSR(IP3_15_13, SCK0),
PINMUX_IPSR_MSEL(IP3_15_13, SCL3_B, SEL_I2C3_B),
PINMUX_IPSR_MSEL(IP3_18_16, SD1_DAT2_B, SEL_SD1_B),
PINMUX_IPSR_MSEL(IP3_18_16, HCTS0_A, SEL_HSCIF0_A),
- PINMUX_IPSR_DATA(IP3_18_16, CTS0),
+ PINMUX_IPSR_GPSR(IP3_18_16, CTS0),
PINMUX_IPSR_MSEL(IP3_20_19, SD1_DAT3_B, SEL_SD1_B),
PINMUX_IPSR_MSEL(IP3_20_19, HRTS0_A, SEL_HSCIF0_A),
- PINMUX_IPSR_DATA(IP3_20_19, RTS0),
+ PINMUX_IPSR_GPSR(IP3_20_19, RTS0),
- PINMUX_IPSR_DATA(IP3_23_21, SSI_SCK4),
- PINMUX_IPSR_DATA(IP3_23_21, DU0_DR0),
- PINMUX_IPSR_DATA(IP3_23_21, LCDOUT0),
- PINMUX_IPSR_DATA(IP3_23_21, AUDATA2),
- PINMUX_IPSR_DATA(IP3_23_21, ARM_TRACEDATA_2),
+ PINMUX_IPSR_GPSR(IP3_23_21, SSI_SCK4),
+ PINMUX_IPSR_GPSR(IP3_23_21, DU0_DR0),
+ PINMUX_IPSR_GPSR(IP3_23_21, LCDOUT0),
+ PINMUX_IPSR_GPSR(IP3_23_21, AUDATA2),
+ PINMUX_IPSR_GPSR(IP3_23_21, ARM_TRACEDATA_2),
PINMUX_IPSR_MSEL(IP3_23_21, SDA3_C, SEL_I2C3_C),
- PINMUX_IPSR_DATA(IP3_23_21, ADICHS1),
+ PINMUX_IPSR_GPSR(IP3_23_21, ADICHS1),
PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN0_B, SEL_TSIF0_B),
- PINMUX_IPSR_DATA(IP3_26_24, SSI_WS4),
- PINMUX_IPSR_DATA(IP3_26_24, DU0_DR1),
- PINMUX_IPSR_DATA(IP3_26_24, LCDOUT1),
- PINMUX_IPSR_DATA(IP3_26_24, AUDATA3),
- PINMUX_IPSR_DATA(IP3_26_24, ARM_TRACEDATA_3),
+ PINMUX_IPSR_GPSR(IP3_26_24, SSI_WS4),
+ PINMUX_IPSR_GPSR(IP3_26_24, DU0_DR1),
+ PINMUX_IPSR_GPSR(IP3_26_24, LCDOUT1),
+ PINMUX_IPSR_GPSR(IP3_26_24, AUDATA3),
+ PINMUX_IPSR_GPSR(IP3_26_24, ARM_TRACEDATA_3),
PINMUX_IPSR_MSEL(IP3_26_24, SCL3_C, SEL_I2C3_C),
- PINMUX_IPSR_DATA(IP3_26_24, ADICHS2),
+ PINMUX_IPSR_GPSR(IP3_26_24, ADICHS2),
PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC0_B, SEL_TSIF0_B),
- PINMUX_IPSR_DATA(IP3_27, DU0_DR2),
- PINMUX_IPSR_DATA(IP3_27, LCDOUT2),
+ PINMUX_IPSR_GPSR(IP3_27, DU0_DR2),
+ PINMUX_IPSR_GPSR(IP3_27, LCDOUT2),
- PINMUX_IPSR_DATA(IP3_28, DU0_DR3),
- PINMUX_IPSR_DATA(IP3_28, LCDOUT3),
+ PINMUX_IPSR_GPSR(IP3_28, DU0_DR3),
+ PINMUX_IPSR_GPSR(IP3_28, LCDOUT3),
- PINMUX_IPSR_DATA(IP3_29, DU0_DR4),
- PINMUX_IPSR_DATA(IP3_29, LCDOUT4),
+ PINMUX_IPSR_GPSR(IP3_29, DU0_DR4),
+ PINMUX_IPSR_GPSR(IP3_29, LCDOUT4),
- PINMUX_IPSR_DATA(IP3_30, DU0_DR5),
- PINMUX_IPSR_DATA(IP3_30, LCDOUT5),
+ PINMUX_IPSR_GPSR(IP3_30, DU0_DR5),
+ PINMUX_IPSR_GPSR(IP3_30, LCDOUT5),
- PINMUX_IPSR_DATA(IP3_31, DU0_DR6),
- PINMUX_IPSR_DATA(IP3_31, LCDOUT6),
+ PINMUX_IPSR_GPSR(IP3_31, DU0_DR6),
+ PINMUX_IPSR_GPSR(IP3_31, LCDOUT6),
/* IPSR4 */
- PINMUX_IPSR_DATA(IP4_0, DU0_DR7),
- PINMUX_IPSR_DATA(IP4_0, LCDOUT7),
-
- PINMUX_IPSR_DATA(IP4_3_1, DU0_DG0),
- PINMUX_IPSR_DATA(IP4_3_1, LCDOUT8),
- PINMUX_IPSR_DATA(IP4_3_1, AUDATA4),
- PINMUX_IPSR_DATA(IP4_3_1, ARM_TRACEDATA_4),
- PINMUX_IPSR_DATA(IP4_3_1, TX1_D),
- PINMUX_IPSR_DATA(IP4_3_1, CAN0_TX_A),
- PINMUX_IPSR_DATA(IP4_3_1, ADICHS0),
-
- PINMUX_IPSR_DATA(IP4_6_4, DU0_DG1),
- PINMUX_IPSR_DATA(IP4_6_4, LCDOUT9),
- PINMUX_IPSR_DATA(IP4_6_4, AUDATA5),
- PINMUX_IPSR_DATA(IP4_6_4, ARM_TRACEDATA_5),
+ PINMUX_IPSR_GPSR(IP4_0, DU0_DR7),
+ PINMUX_IPSR_GPSR(IP4_0, LCDOUT7),
+
+ PINMUX_IPSR_GPSR(IP4_3_1, DU0_DG0),
+ PINMUX_IPSR_GPSR(IP4_3_1, LCDOUT8),
+ PINMUX_IPSR_GPSR(IP4_3_1, AUDATA4),
+ PINMUX_IPSR_GPSR(IP4_3_1, ARM_TRACEDATA_4),
+ PINMUX_IPSR_GPSR(IP4_3_1, TX1_D),
+ PINMUX_IPSR_GPSR(IP4_3_1, CAN0_TX_A),
+ PINMUX_IPSR_GPSR(IP4_3_1, ADICHS0),
+
+ PINMUX_IPSR_GPSR(IP4_6_4, DU0_DG1),
+ PINMUX_IPSR_GPSR(IP4_6_4, LCDOUT9),
+ PINMUX_IPSR_GPSR(IP4_6_4, AUDATA5),
+ PINMUX_IPSR_GPSR(IP4_6_4, ARM_TRACEDATA_5),
PINMUX_IPSR_MSEL(IP4_6_4, RX1_D, SEL_SCIF1_D),
PINMUX_IPSR_MSEL(IP4_6_4, CAN0_RX_A, SEL_CAN0_A),
- PINMUX_IPSR_DATA(IP4_6_4, ADIDATA),
+ PINMUX_IPSR_GPSR(IP4_6_4, ADIDATA),
- PINMUX_IPSR_DATA(IP4_7, DU0_DG2),
- PINMUX_IPSR_DATA(IP4_7, LCDOUT10),
+ PINMUX_IPSR_GPSR(IP4_7, DU0_DG2),
+ PINMUX_IPSR_GPSR(IP4_7, LCDOUT10),
- PINMUX_IPSR_DATA(IP4_8, DU0_DG3),
- PINMUX_IPSR_DATA(IP4_8, LCDOUT11),
+ PINMUX_IPSR_GPSR(IP4_8, DU0_DG3),
+ PINMUX_IPSR_GPSR(IP4_8, LCDOUT11),
- PINMUX_IPSR_DATA(IP4_10_9, DU0_DG4),
- PINMUX_IPSR_DATA(IP4_10_9, LCDOUT12),
+ PINMUX_IPSR_GPSR(IP4_10_9, DU0_DG4),
+ PINMUX_IPSR_GPSR(IP4_10_9, LCDOUT12),
PINMUX_IPSR_MSEL(IP4_10_9, RX0_B, SEL_SCIF0_B),
- PINMUX_IPSR_DATA(IP4_12_11, DU0_DG5),
- PINMUX_IPSR_DATA(IP4_12_11, LCDOUT13),
- PINMUX_IPSR_DATA(IP4_12_11, TX0_B),
+ PINMUX_IPSR_GPSR(IP4_12_11, DU0_DG5),
+ PINMUX_IPSR_GPSR(IP4_12_11, LCDOUT13),
+ PINMUX_IPSR_GPSR(IP4_12_11, TX0_B),
- PINMUX_IPSR_DATA(IP4_14_13, DU0_DG6),
- PINMUX_IPSR_DATA(IP4_14_13, LCDOUT14),
+ PINMUX_IPSR_GPSR(IP4_14_13, DU0_DG6),
+ PINMUX_IPSR_GPSR(IP4_14_13, LCDOUT14),
PINMUX_IPSR_MSEL(IP4_14_13, RX4_A, SEL_SCIF4_A),
- PINMUX_IPSR_DATA(IP4_16_15, DU0_DG7),
- PINMUX_IPSR_DATA(IP4_16_15, LCDOUT15),
- PINMUX_IPSR_DATA(IP4_16_15, TX4_A),
+ PINMUX_IPSR_GPSR(IP4_16_15, DU0_DG7),
+ PINMUX_IPSR_GPSR(IP4_16_15, LCDOUT15),
+ PINMUX_IPSR_GPSR(IP4_16_15, TX4_A),
PINMUX_IPSR_MSEL(IP4_20_17, SSI_SCK2_B, SEL_SSI2_B),
PINMUX_DATA(VI0_R0_B_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_B), /* see sel_vi0 */
PINMUX_DATA(VI0_R0_D_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_D), /* see sel_vi0 */
- PINMUX_IPSR_DATA(IP4_20_17, DU0_DB0),
- PINMUX_IPSR_DATA(IP4_20_17, LCDOUT16),
- PINMUX_IPSR_DATA(IP4_20_17, AUDATA6),
- PINMUX_IPSR_DATA(IP4_20_17, ARM_TRACEDATA_6),
+ PINMUX_IPSR_GPSR(IP4_20_17, DU0_DB0),
+ PINMUX_IPSR_GPSR(IP4_20_17, LCDOUT16),
+ PINMUX_IPSR_GPSR(IP4_20_17, AUDATA6),
+ PINMUX_IPSR_GPSR(IP4_20_17, ARM_TRACEDATA_6),
PINMUX_IPSR_MSEL(IP4_20_17, GPSCLK_A, SEL_GPS_A),
- PINMUX_IPSR_DATA(IP4_20_17, PWM0_A),
- PINMUX_IPSR_DATA(IP4_20_17, ADICLK),
+ PINMUX_IPSR_GPSR(IP4_20_17, PWM0_A),
+ PINMUX_IPSR_GPSR(IP4_20_17, ADICLK),
PINMUX_IPSR_MSEL(IP4_20_17, TS_SDAT0_B, SEL_TSIF0_B),
- PINMUX_IPSR_DATA(IP4_24_21, AUDIO_CLKC),
+ PINMUX_IPSR_GPSR(IP4_24_21, AUDIO_CLKC),
PINMUX_DATA(VI0_R1_B_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_B), /* see sel_vi0 */
PINMUX_DATA(VI0_R1_D_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_D), /* see sel_vi0 */
- PINMUX_IPSR_DATA(IP4_24_21, DU0_DB1),
- PINMUX_IPSR_DATA(IP4_24_21, LCDOUT17),
- PINMUX_IPSR_DATA(IP4_24_21, AUDATA7),
- PINMUX_IPSR_DATA(IP4_24_21, ARM_TRACEDATA_7),
+ PINMUX_IPSR_GPSR(IP4_24_21, DU0_DB1),
+ PINMUX_IPSR_GPSR(IP4_24_21, LCDOUT17),
+ PINMUX_IPSR_GPSR(IP4_24_21, AUDATA7),
+ PINMUX_IPSR_GPSR(IP4_24_21, ARM_TRACEDATA_7),
PINMUX_IPSR_MSEL(IP4_24_21, GPSIN_A, SEL_GPS_A),
- PINMUX_IPSR_DATA(IP4_24_21, ADICS_SAMP),
+ PINMUX_IPSR_GPSR(IP4_24_21, ADICS_SAMP),
PINMUX_IPSR_MSEL(IP4_24_21, TS_SCK0_B, SEL_TSIF0_B),
PINMUX_DATA(VI0_R2_B_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_B), /* see sel_vi0 */
PINMUX_DATA(VI0_R2_D_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_D), /* see sel_vi0 */
- PINMUX_IPSR_DATA(IP4_26_25, DU0_DB2),
- PINMUX_IPSR_DATA(IP4_26_25, LCDOUT18),
+ PINMUX_IPSR_GPSR(IP4_26_25, DU0_DB2),
+ PINMUX_IPSR_GPSR(IP4_26_25, LCDOUT18),
PINMUX_IPSR_MSEL(IP4_28_27, VI0_R3_B, SEL_VI0_B),
- PINMUX_IPSR_DATA(IP4_28_27, DU0_DB3),
- PINMUX_IPSR_DATA(IP4_28_27, LCDOUT19),
+ PINMUX_IPSR_GPSR(IP4_28_27, DU0_DB3),
+ PINMUX_IPSR_GPSR(IP4_28_27, LCDOUT19),
PINMUX_DATA(VI0_R4_B_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_B), /* see sel_vi0 */
PINMUX_DATA(VI0_R4_D_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_D), /* see sel_vi0 */
- PINMUX_IPSR_DATA(IP4_30_29, DU0_DB4),
- PINMUX_IPSR_DATA(IP4_30_29, LCDOUT20),
+ PINMUX_IPSR_GPSR(IP4_30_29, DU0_DB4),
+ PINMUX_IPSR_GPSR(IP4_30_29, LCDOUT20),
/* IPSR5 */
PINMUX_DATA(VI0_R5_B_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_B), /* see sel_vi0 */
PINMUX_DATA(VI0_R5_D_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_D), /* see sel_vi0 */
- PINMUX_IPSR_DATA(IP5_1_0, DU0_DB5),
- PINMUX_IPSR_DATA(IP5_1_0, LCDOUT21),
+ PINMUX_IPSR_GPSR(IP5_1_0, DU0_DB5),
+ PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT21),
PINMUX_IPSR_MSEL(IP5_3_2, VI1_DATA10_B, SEL_VI1_B),
- PINMUX_IPSR_DATA(IP5_3_2, DU0_DB6),
- PINMUX_IPSR_DATA(IP5_3_2, LCDOUT22),
+ PINMUX_IPSR_GPSR(IP5_3_2, DU0_DB6),
+ PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT22),
PINMUX_IPSR_MSEL(IP5_5_4, VI1_DATA11_B, SEL_VI1_B),
- PINMUX_IPSR_DATA(IP5_5_4, DU0_DB7),
- PINMUX_IPSR_DATA(IP5_5_4, LCDOUT23),
+ PINMUX_IPSR_GPSR(IP5_5_4, DU0_DB7),
+ PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT23),
- PINMUX_IPSR_DATA(IP5_6, DU0_DOTCLKIN),
- PINMUX_IPSR_DATA(IP5_6, QSTVA_QVS),
+ PINMUX_IPSR_GPSR(IP5_6, DU0_DOTCLKIN),
+ PINMUX_IPSR_GPSR(IP5_6, QSTVA_QVS),
- PINMUX_IPSR_DATA(IP5_7, DU0_DOTCLKO_UT0),
- PINMUX_IPSR_DATA(IP5_7, QCLK),
+ PINMUX_IPSR_GPSR(IP5_7, DU0_DOTCLKO_UT0),
+ PINMUX_IPSR_GPSR(IP5_7, QCLK),
- PINMUX_IPSR_DATA(IP5_9_8, DU0_DOTCLKO_UT1),
- PINMUX_IPSR_DATA(IP5_9_8, QSTVB_QVE),
- PINMUX_IPSR_DATA(IP5_9_8, AUDIO_CLKOUT_A),
+ PINMUX_IPSR_GPSR(IP5_9_8, DU0_DOTCLKO_UT1),
+ PINMUX_IPSR_GPSR(IP5_9_8, QSTVB_QVE),
+ PINMUX_IPSR_GPSR(IP5_9_8, AUDIO_CLKOUT_A),
PINMUX_IPSR_MSEL(IP5_9_8, REMOCON_C, SEL_REMOCON_C),
PINMUX_IPSR_MSEL(IP5_11_10, SSI_WS2_B, SEL_SSI2_B),
- PINMUX_IPSR_DATA(IP5_11_10, DU0_EXHSYNC_DU0_HSYNC),
- PINMUX_IPSR_DATA(IP5_11_10, QSTH_QHS),
+ PINMUX_IPSR_GPSR(IP5_11_10, DU0_EXHSYNC_DU0_HSYNC),
+ PINMUX_IPSR_GPSR(IP5_11_10, QSTH_QHS),
- PINMUX_IPSR_DATA(IP5_12, DU0_EXVSYNC_DU0_VSYNC),
- PINMUX_IPSR_DATA(IP5_12, QSTB_QHE),
+ PINMUX_IPSR_GPSR(IP5_12, DU0_EXVSYNC_DU0_VSYNC),
+ PINMUX_IPSR_GPSR(IP5_12, QSTB_QHE),
- PINMUX_IPSR_DATA(IP5_14_13, DU0_EXODDF_DU0_ODDF_DISP_CDE),
- PINMUX_IPSR_DATA(IP5_14_13, QCPV_QDE),
+ PINMUX_IPSR_GPSR(IP5_14_13, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP5_14_13, QCPV_QDE),
PINMUX_IPSR_MSEL(IP5_14_13, FMCLK_D, SEL_FM_D),
PINMUX_IPSR_MSEL(IP5_17_15, SSI_SCK1_A, SEL_SSI1_A),
- PINMUX_IPSR_DATA(IP5_17_15, DU0_DISP),
- PINMUX_IPSR_DATA(IP5_17_15, QPOLA),
- PINMUX_IPSR_DATA(IP5_17_15, AUDCK),
- PINMUX_IPSR_DATA(IP5_17_15, ARM_TRACECLK),
- PINMUX_IPSR_DATA(IP5_17_15, BPFCLK_D),
+ PINMUX_IPSR_GPSR(IP5_17_15, DU0_DISP),
+ PINMUX_IPSR_GPSR(IP5_17_15, QPOLA),
+ PINMUX_IPSR_GPSR(IP5_17_15, AUDCK),
+ PINMUX_IPSR_GPSR(IP5_17_15, ARM_TRACECLK),
+ PINMUX_IPSR_GPSR(IP5_17_15, BPFCLK_D),
PINMUX_IPSR_MSEL(IP5_20_18, SSI_WS1_A, SEL_SSI1_A),
- PINMUX_IPSR_DATA(IP5_20_18, DU0_CDE),
- PINMUX_IPSR_DATA(IP5_20_18, QPOLB),
- PINMUX_IPSR_DATA(IP5_20_18, AUDSYNC),
- PINMUX_IPSR_DATA(IP5_20_18, ARM_TRACECTL),
+ PINMUX_IPSR_GPSR(IP5_20_18, DU0_CDE),
+ PINMUX_IPSR_GPSR(IP5_20_18, QPOLB),
+ PINMUX_IPSR_GPSR(IP5_20_18, AUDSYNC),
+ PINMUX_IPSR_GPSR(IP5_20_18, ARM_TRACECTL),
PINMUX_IPSR_MSEL(IP5_20_18, FMIN_D, SEL_FM_D),
PINMUX_IPSR_MSEL(IP5_22_21, SD1_CD_B, SEL_SD1_B),
- PINMUX_IPSR_DATA(IP5_22_21, SSI_SCK78),
+ PINMUX_IPSR_GPSR(IP5_22_21, SSI_SCK78),
PINMUX_IPSR_MSEL(IP5_22_21, HSPI_RX0_B, SEL_HSPI0_B),
- PINMUX_IPSR_DATA(IP5_22_21, TX1_B),
+ PINMUX_IPSR_GPSR(IP5_22_21, TX1_B),
PINMUX_IPSR_MSEL(IP5_25_23, SD1_WP_B, SEL_SD1_B),
- PINMUX_IPSR_DATA(IP5_25_23, SSI_WS78),
+ PINMUX_IPSR_GPSR(IP5_25_23, SSI_WS78),
PINMUX_IPSR_MSEL(IP5_25_23, HSPI_CLK0_B, SEL_HSPI0_B),
PINMUX_IPSR_MSEL(IP5_25_23, RX1_B, SEL_SCIF1_B),
PINMUX_IPSR_MSEL(IP5_25_23, CAN_CLK_D, SEL_CANCLK_D),
- PINMUX_IPSR_DATA(IP5_28_26, SSI_SDATA8),
+ PINMUX_IPSR_GPSR(IP5_28_26, SSI_SDATA8),
PINMUX_IPSR_MSEL(IP5_28_26, SSI_SCK2_A, SEL_SSI2_A),
PINMUX_IPSR_MSEL(IP5_28_26, HSPI_CS0_B, SEL_HSPI0_B),
- PINMUX_IPSR_DATA(IP5_28_26, TX2_A),
- PINMUX_IPSR_DATA(IP5_28_26, CAN0_TX_B),
+ PINMUX_IPSR_GPSR(IP5_28_26, TX2_A),
+ PINMUX_IPSR_GPSR(IP5_28_26, CAN0_TX_B),
- PINMUX_IPSR_DATA(IP5_30_29, SSI_SDATA7),
- PINMUX_IPSR_DATA(IP5_30_29, HSPI_TX0_B),
+ PINMUX_IPSR_GPSR(IP5_30_29, SSI_SDATA7),
+ PINMUX_IPSR_GPSR(IP5_30_29, HSPI_TX0_B),
PINMUX_IPSR_MSEL(IP5_30_29, RX2_A, SEL_SCIF2_A),
PINMUX_IPSR_MSEL(IP5_30_29, CAN0_RX_B, SEL_CAN0_B),
/* IPSR6 */
- PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK6),
+ PINMUX_IPSR_GPSR(IP6_1_0, SSI_SCK6),
PINMUX_IPSR_MSEL(IP6_1_0, HSPI_RX2_A, SEL_HSPI2_A),
PINMUX_IPSR_MSEL(IP6_1_0, FMCLK_B, SEL_FM_B),
- PINMUX_IPSR_DATA(IP6_1_0, CAN1_TX_B),
+ PINMUX_IPSR_GPSR(IP6_1_0, CAN1_TX_B),
- PINMUX_IPSR_DATA(IP6_4_2, SSI_WS6),
+ PINMUX_IPSR_GPSR(IP6_4_2, SSI_WS6),
PINMUX_IPSR_MSEL(IP6_4_2, HSPI_CLK2_A, SEL_HSPI2_A),
- PINMUX_IPSR_DATA(IP6_4_2, BPFCLK_B),
+ PINMUX_IPSR_GPSR(IP6_4_2, BPFCLK_B),
PINMUX_IPSR_MSEL(IP6_4_2, CAN1_RX_B, SEL_CAN1_B),
- PINMUX_IPSR_DATA(IP6_6_5, SSI_SDATA6),
- PINMUX_IPSR_DATA(IP6_6_5, HSPI_TX2_A),
+ PINMUX_IPSR_GPSR(IP6_6_5, SSI_SDATA6),
+ PINMUX_IPSR_GPSR(IP6_6_5, HSPI_TX2_A),
PINMUX_IPSR_MSEL(IP6_6_5, FMIN_B, SEL_FM_B),
- PINMUX_IPSR_DATA(IP6_7, SSI_SCK5),
+ PINMUX_IPSR_GPSR(IP6_7, SSI_SCK5),
PINMUX_IPSR_MSEL(IP6_7, RX4_C, SEL_SCIF4_C),
- PINMUX_IPSR_DATA(IP6_8, SSI_WS5),
- PINMUX_IPSR_DATA(IP6_8, TX4_C),
+ PINMUX_IPSR_GPSR(IP6_8, SSI_WS5),
+ PINMUX_IPSR_GPSR(IP6_8, TX4_C),
- PINMUX_IPSR_DATA(IP6_9, SSI_SDATA5),
+ PINMUX_IPSR_GPSR(IP6_9, SSI_SDATA5),
PINMUX_IPSR_MSEL(IP6_9, RX0_D, SEL_SCIF0_D),
- PINMUX_IPSR_DATA(IP6_10, SSI_WS34),
- PINMUX_IPSR_DATA(IP6_10, ARM_TRACEDATA_8),
+ PINMUX_IPSR_GPSR(IP6_10, SSI_WS34),
+ PINMUX_IPSR_GPSR(IP6_10, ARM_TRACEDATA_8),
- PINMUX_IPSR_DATA(IP6_12_11, SSI_SDATA4),
+ PINMUX_IPSR_GPSR(IP6_12_11, SSI_SDATA4),
PINMUX_IPSR_MSEL(IP6_12_11, SSI_WS2_A, SEL_SSI2_A),
- PINMUX_IPSR_DATA(IP6_12_11, ARM_TRACEDATA_9),
+ PINMUX_IPSR_GPSR(IP6_12_11, ARM_TRACEDATA_9),
- PINMUX_IPSR_DATA(IP6_13, SSI_SDATA3),
- PINMUX_IPSR_DATA(IP6_13, ARM_TRACEDATA_10),
+ PINMUX_IPSR_GPSR(IP6_13, SSI_SDATA3),
+ PINMUX_IPSR_GPSR(IP6_13, ARM_TRACEDATA_10),
- PINMUX_IPSR_DATA(IP6_15_14, SSI_SCK012),
- PINMUX_IPSR_DATA(IP6_15_14, ARM_TRACEDATA_11),
- PINMUX_IPSR_DATA(IP6_15_14, TX0_D),
+ PINMUX_IPSR_GPSR(IP6_15_14, SSI_SCK012),
+ PINMUX_IPSR_GPSR(IP6_15_14, ARM_TRACEDATA_11),
+ PINMUX_IPSR_GPSR(IP6_15_14, TX0_D),
- PINMUX_IPSR_DATA(IP6_16, SSI_WS012),
- PINMUX_IPSR_DATA(IP6_16, ARM_TRACEDATA_12),
+ PINMUX_IPSR_GPSR(IP6_16, SSI_WS012),
+ PINMUX_IPSR_GPSR(IP6_16, ARM_TRACEDATA_12),
- PINMUX_IPSR_DATA(IP6_18_17, SSI_SDATA2),
+ PINMUX_IPSR_GPSR(IP6_18_17, SSI_SDATA2),
PINMUX_IPSR_MSEL(IP6_18_17, HSPI_CS2_A, SEL_HSPI2_A),
- PINMUX_IPSR_DATA(IP6_18_17, ARM_TRACEDATA_13),
+ PINMUX_IPSR_GPSR(IP6_18_17, ARM_TRACEDATA_13),
PINMUX_IPSR_MSEL(IP6_18_17, SDA1_A, SEL_I2C1_A),
- PINMUX_IPSR_DATA(IP6_20_19, SSI_SDATA1),
- PINMUX_IPSR_DATA(IP6_20_19, ARM_TRACEDATA_14),
+ PINMUX_IPSR_GPSR(IP6_20_19, SSI_SDATA1),
+ PINMUX_IPSR_GPSR(IP6_20_19, ARM_TRACEDATA_14),
PINMUX_IPSR_MSEL(IP6_20_19, SCL1_A, SEL_I2C1_A),
PINMUX_IPSR_MSEL(IP6_20_19, SCK2_A, SEL_SCIF2_A),
- PINMUX_IPSR_DATA(IP6_21, SSI_SDATA0),
- PINMUX_IPSR_DATA(IP6_21, ARM_TRACEDATA_15),
+ PINMUX_IPSR_GPSR(IP6_21, SSI_SDATA0),
+ PINMUX_IPSR_GPSR(IP6_21, ARM_TRACEDATA_15),
- PINMUX_IPSR_DATA(IP6_23_22, SD0_CLK),
- PINMUX_IPSR_DATA(IP6_23_22, SUB_TDO),
+ PINMUX_IPSR_GPSR(IP6_23_22, SD0_CLK),
+ PINMUX_IPSR_GPSR(IP6_23_22, SUB_TDO),
- PINMUX_IPSR_DATA(IP6_25_24, SD0_CMD),
- PINMUX_IPSR_DATA(IP6_25_24, SUB_TRST),
+ PINMUX_IPSR_GPSR(IP6_25_24, SD0_CMD),
+ PINMUX_IPSR_GPSR(IP6_25_24, SUB_TRST),
- PINMUX_IPSR_DATA(IP6_27_26, SD0_DAT0),
- PINMUX_IPSR_DATA(IP6_27_26, SUB_TMS),
+ PINMUX_IPSR_GPSR(IP6_27_26, SD0_DAT0),
+ PINMUX_IPSR_GPSR(IP6_27_26, SUB_TMS),
- PINMUX_IPSR_DATA(IP6_29_28, SD0_DAT1),
- PINMUX_IPSR_DATA(IP6_29_28, SUB_TCK),
+ PINMUX_IPSR_GPSR(IP6_29_28, SD0_DAT1),
+ PINMUX_IPSR_GPSR(IP6_29_28, SUB_TCK),
- PINMUX_IPSR_DATA(IP6_31_30, SD0_DAT2),
- PINMUX_IPSR_DATA(IP6_31_30, SUB_TDI),
+ PINMUX_IPSR_GPSR(IP6_31_30, SD0_DAT2),
+ PINMUX_IPSR_GPSR(IP6_31_30, SUB_TDI),
/* IPSR7 */
- PINMUX_IPSR_DATA(IP7_1_0, SD0_DAT3),
+ PINMUX_IPSR_GPSR(IP7_1_0, SD0_DAT3),
PINMUX_IPSR_MSEL(IP7_1_0, IRQ1_B, SEL_IRQ1_B),
- PINMUX_IPSR_DATA(IP7_3_2, SD0_CD),
- PINMUX_IPSR_DATA(IP7_3_2, TX5_A),
+ PINMUX_IPSR_GPSR(IP7_3_2, SD0_CD),
+ PINMUX_IPSR_GPSR(IP7_3_2, TX5_A),
- PINMUX_IPSR_DATA(IP7_5_4, SD0_WP),
+ PINMUX_IPSR_GPSR(IP7_5_4, SD0_WP),
PINMUX_IPSR_MSEL(IP7_5_4, RX5_A, SEL_SCIF5_A),
- PINMUX_IPSR_DATA(IP7_8_6, VI1_CLKENB),
+ PINMUX_IPSR_GPSR(IP7_8_6, VI1_CLKENB),
PINMUX_IPSR_MSEL(IP7_8_6, HSPI_CLK0_A, SEL_HSPI0_A),
- PINMUX_IPSR_DATA(IP7_8_6, HTX1_A),
+ PINMUX_IPSR_GPSR(IP7_8_6, HTX1_A),
PINMUX_IPSR_MSEL(IP7_8_6, RTS1_C, SEL_SCIF1_C),
- PINMUX_IPSR_DATA(IP7_11_9, VI1_FIELD),
+ PINMUX_IPSR_GPSR(IP7_11_9, VI1_FIELD),
PINMUX_IPSR_MSEL(IP7_11_9, HSPI_CS0_A, SEL_HSPI0_A),
PINMUX_IPSR_MSEL(IP7_11_9, HRX1_A, SEL_HSCIF1_A),
PINMUX_IPSR_MSEL(IP7_11_9, SCK1_C, SEL_SCIF1_C),
- PINMUX_IPSR_DATA(IP7_14_12, VI1_HSYNC),
+ PINMUX_IPSR_GPSR(IP7_14_12, VI1_HSYNC),
PINMUX_IPSR_MSEL(IP7_14_12, HSPI_RX0_A, SEL_HSPI0_A),
PINMUX_IPSR_MSEL(IP7_14_12, HRTS1_A, SEL_HSCIF1_A),
PINMUX_IPSR_MSEL(IP7_14_12, FMCLK_A, SEL_FM_A),
PINMUX_IPSR_MSEL(IP7_14_12, RX1_C, SEL_SCIF1_C),
- PINMUX_IPSR_DATA(IP7_17_15, VI1_VSYNC),
- PINMUX_IPSR_DATA(IP7_17_15, HSPI_TX0),
+ PINMUX_IPSR_GPSR(IP7_17_15, VI1_VSYNC),
+ PINMUX_IPSR_GPSR(IP7_17_15, HSPI_TX0),
PINMUX_IPSR_MSEL(IP7_17_15, HCTS1_A, SEL_HSCIF1_A),
- PINMUX_IPSR_DATA(IP7_17_15, BPFCLK_A),
- PINMUX_IPSR_DATA(IP7_17_15, TX1_C),
+ PINMUX_IPSR_GPSR(IP7_17_15, BPFCLK_A),
+ PINMUX_IPSR_GPSR(IP7_17_15, TX1_C),
- PINMUX_IPSR_DATA(IP7_20_18, TCLK0),
+ PINMUX_IPSR_GPSR(IP7_20_18, TCLK0),
PINMUX_IPSR_MSEL(IP7_20_18, HSCK1_A, SEL_HSCIF1_A),
PINMUX_IPSR_MSEL(IP7_20_18, FMIN_A, SEL_FM_A),
PINMUX_IPSR_MSEL(IP7_20_18, IRQ2_C, SEL_IRQ2_C),
PINMUX_IPSR_MSEL(IP7_20_18, CTS1_C, SEL_SCIF1_C),
- PINMUX_IPSR_DATA(IP7_20_18, SPEEDIN),
+ PINMUX_IPSR_GPSR(IP7_20_18, SPEEDIN),
- PINMUX_IPSR_DATA(IP7_21, VI0_CLK),
+ PINMUX_IPSR_GPSR(IP7_21, VI0_CLK),
PINMUX_IPSR_MSEL(IP7_21, CAN_CLK_A, SEL_CANCLK_A),
- PINMUX_IPSR_DATA(IP7_24_22, VI0_CLKENB),
+ PINMUX_IPSR_GPSR(IP7_24_22, VI0_CLKENB),
PINMUX_IPSR_MSEL(IP7_24_22, SD2_DAT2_B, SEL_SD2_B),
- PINMUX_IPSR_DATA(IP7_24_22, VI1_DATA0),
- PINMUX_IPSR_DATA(IP7_24_22, DU1_DG6),
+ PINMUX_IPSR_GPSR(IP7_24_22, VI1_DATA0),
+ PINMUX_IPSR_GPSR(IP7_24_22, DU1_DG6),
PINMUX_IPSR_MSEL(IP7_24_22, HSPI_RX1_A, SEL_HSPI1_A),
PINMUX_IPSR_MSEL(IP7_24_22, RX4_B, SEL_SCIF4_B),
- PINMUX_IPSR_DATA(IP7_28_25, VI0_FIELD),
+ PINMUX_IPSR_GPSR(IP7_28_25, VI0_FIELD),
PINMUX_IPSR_MSEL(IP7_28_25, SD2_DAT3_B, SEL_SD2_B),
PINMUX_DATA(VI0_R3_C_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_C), /* see sel_vi0 */
PINMUX_DATA(VI0_R3_D_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_D), /* see sel_vi0 */
- PINMUX_IPSR_DATA(IP7_28_25, VI1_DATA1),
- PINMUX_IPSR_DATA(IP7_28_25, DU1_DG7),
+ PINMUX_IPSR_GPSR(IP7_28_25, VI1_DATA1),
+ PINMUX_IPSR_GPSR(IP7_28_25, DU1_DG7),
PINMUX_IPSR_MSEL(IP7_28_25, HSPI_CLK1_A, SEL_HSPI1_A),
- PINMUX_IPSR_DATA(IP7_28_25, TX4_B),
+ PINMUX_IPSR_GPSR(IP7_28_25, TX4_B),
- PINMUX_IPSR_DATA(IP7_31_29, VI0_HSYNC),
+ PINMUX_IPSR_GPSR(IP7_31_29, VI0_HSYNC),
PINMUX_IPSR_MSEL(IP7_31_29, SD2_CD_B, SEL_SD2_B),
- PINMUX_IPSR_DATA(IP7_31_29, VI1_DATA2),
- PINMUX_IPSR_DATA(IP7_31_29, DU1_DR2),
+ PINMUX_IPSR_GPSR(IP7_31_29, VI1_DATA2),
+ PINMUX_IPSR_GPSR(IP7_31_29, DU1_DR2),
PINMUX_IPSR_MSEL(IP7_31_29, HSPI_CS1_A, SEL_HSPI1_A),
PINMUX_IPSR_MSEL(IP7_31_29, RX3_B, SEL_SCIF3_B),
/* IPSR8 */
- PINMUX_IPSR_DATA(IP8_2_0, VI0_VSYNC),
+ PINMUX_IPSR_GPSR(IP8_2_0, VI0_VSYNC),
PINMUX_IPSR_MSEL(IP8_2_0, SD2_WP_B, SEL_SD2_B),
- PINMUX_IPSR_DATA(IP8_2_0, VI1_DATA3),
- PINMUX_IPSR_DATA(IP8_2_0, DU1_DR3),
- PINMUX_IPSR_DATA(IP8_2_0, HSPI_TX1_A),
- PINMUX_IPSR_DATA(IP8_2_0, TX3_B),
+ PINMUX_IPSR_GPSR(IP8_2_0, VI1_DATA3),
+ PINMUX_IPSR_GPSR(IP8_2_0, DU1_DR3),
+ PINMUX_IPSR_GPSR(IP8_2_0, HSPI_TX1_A),
+ PINMUX_IPSR_GPSR(IP8_2_0, TX3_B),
- PINMUX_IPSR_DATA(IP8_5_3, VI0_DATA0_VI0_B0),
- PINMUX_IPSR_DATA(IP8_5_3, DU1_DG2),
+ PINMUX_IPSR_GPSR(IP8_5_3, VI0_DATA0_VI0_B0),
+ PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG2),
PINMUX_IPSR_MSEL(IP8_5_3, IRQ2_B, SEL_IRQ2_B),
PINMUX_IPSR_MSEL(IP8_5_3, RX3_D, SEL_SCIF3_D),
- PINMUX_IPSR_DATA(IP8_8_6, VI0_DATA1_VI0_B1),
- PINMUX_IPSR_DATA(IP8_8_6, DU1_DG3),
+ PINMUX_IPSR_GPSR(IP8_8_6, VI0_DATA1_VI0_B1),
+ PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG3),
PINMUX_IPSR_MSEL(IP8_8_6, IRQ3_B, SEL_IRQ3_B),
- PINMUX_IPSR_DATA(IP8_8_6, TX3_D),
+ PINMUX_IPSR_GPSR(IP8_8_6, TX3_D),
- PINMUX_IPSR_DATA(IP8_10_9, VI0_DATA2_VI0_B2),
- PINMUX_IPSR_DATA(IP8_10_9, DU1_DG4),
+ PINMUX_IPSR_GPSR(IP8_10_9, VI0_DATA2_VI0_B2),
+ PINMUX_IPSR_GPSR(IP8_10_9, DU1_DG4),
PINMUX_IPSR_MSEL(IP8_10_9, RX0_C, SEL_SCIF0_C),
- PINMUX_IPSR_DATA(IP8_13_11, VI0_DATA3_VI0_B3),
- PINMUX_IPSR_DATA(IP8_13_11, DU1_DG5),
- PINMUX_IPSR_DATA(IP8_13_11, TX1_A),
- PINMUX_IPSR_DATA(IP8_13_11, TX0_C),
+ PINMUX_IPSR_GPSR(IP8_13_11, VI0_DATA3_VI0_B3),
+ PINMUX_IPSR_GPSR(IP8_13_11, DU1_DG5),
+ PINMUX_IPSR_GPSR(IP8_13_11, TX1_A),
+ PINMUX_IPSR_GPSR(IP8_13_11, TX0_C),
- PINMUX_IPSR_DATA(IP8_15_14, VI0_DATA4_VI0_B4),
- PINMUX_IPSR_DATA(IP8_15_14, DU1_DB2),
+ PINMUX_IPSR_GPSR(IP8_15_14, VI0_DATA4_VI0_B4),
+ PINMUX_IPSR_GPSR(IP8_15_14, DU1_DB2),
PINMUX_IPSR_MSEL(IP8_15_14, RX1_A, SEL_SCIF1_A),
- PINMUX_IPSR_DATA(IP8_18_16, VI0_DATA5_VI0_B5),
- PINMUX_IPSR_DATA(IP8_18_16, DU1_DB3),
+ PINMUX_IPSR_GPSR(IP8_18_16, VI0_DATA5_VI0_B5),
+ PINMUX_IPSR_GPSR(IP8_18_16, DU1_DB3),
PINMUX_IPSR_MSEL(IP8_18_16, SCK1_A, SEL_SCIF1_A),
- PINMUX_IPSR_DATA(IP8_18_16, PWM4),
+ PINMUX_IPSR_GPSR(IP8_18_16, PWM4),
PINMUX_IPSR_MSEL(IP8_18_16, HSCK1_B, SEL_HSCIF1_B),
- PINMUX_IPSR_DATA(IP8_21_19, VI0_DATA6_VI0_G0),
- PINMUX_IPSR_DATA(IP8_21_19, DU1_DB4),
+ PINMUX_IPSR_GPSR(IP8_21_19, VI0_DATA6_VI0_G0),
+ PINMUX_IPSR_GPSR(IP8_21_19, DU1_DB4),
PINMUX_IPSR_MSEL(IP8_21_19, CTS1_A, SEL_SCIF1_A),
- PINMUX_IPSR_DATA(IP8_21_19, PWM5),
+ PINMUX_IPSR_GPSR(IP8_21_19, PWM5),
- PINMUX_IPSR_DATA(IP8_23_22, VI0_DATA7_VI0_G1),
- PINMUX_IPSR_DATA(IP8_23_22, DU1_DB5),
+ PINMUX_IPSR_GPSR(IP8_23_22, VI0_DATA7_VI0_G1),
+ PINMUX_IPSR_GPSR(IP8_23_22, DU1_DB5),
PINMUX_IPSR_MSEL(IP8_23_22, RTS1_A, SEL_SCIF1_A),
- PINMUX_IPSR_DATA(IP8_26_24, VI0_G2),
- PINMUX_IPSR_DATA(IP8_26_24, SD2_CLK_B),
- PINMUX_IPSR_DATA(IP8_26_24, VI1_DATA4),
- PINMUX_IPSR_DATA(IP8_26_24, DU1_DR4),
- PINMUX_IPSR_DATA(IP8_26_24, HTX1_B),
+ PINMUX_IPSR_GPSR(IP8_26_24, VI0_G2),
+ PINMUX_IPSR_GPSR(IP8_26_24, SD2_CLK_B),
+ PINMUX_IPSR_GPSR(IP8_26_24, VI1_DATA4),
+ PINMUX_IPSR_GPSR(IP8_26_24, DU1_DR4),
+ PINMUX_IPSR_GPSR(IP8_26_24, HTX1_B),
- PINMUX_IPSR_DATA(IP8_29_27, VI0_G3),
+ PINMUX_IPSR_GPSR(IP8_29_27, VI0_G3),
PINMUX_IPSR_MSEL(IP8_29_27, SD2_CMD_B, SEL_SD2_B),
- PINMUX_IPSR_DATA(IP8_29_27, VI1_DATA5),
- PINMUX_IPSR_DATA(IP8_29_27, DU1_DR5),
+ PINMUX_IPSR_GPSR(IP8_29_27, VI1_DATA5),
+ PINMUX_IPSR_GPSR(IP8_29_27, DU1_DR5),
PINMUX_IPSR_MSEL(IP8_29_27, HRX1_B, SEL_HSCIF1_B),
/* IPSR9 */
- PINMUX_IPSR_DATA(IP9_2_0, VI0_G4),
+ PINMUX_IPSR_GPSR(IP9_2_0, VI0_G4),
PINMUX_IPSR_MSEL(IP9_2_0, SD2_DAT0_B, SEL_SD2_B),
- PINMUX_IPSR_DATA(IP9_2_0, VI1_DATA6),
- PINMUX_IPSR_DATA(IP9_2_0, DU1_DR6),
+ PINMUX_IPSR_GPSR(IP9_2_0, VI1_DATA6),
+ PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR6),
PINMUX_IPSR_MSEL(IP9_2_0, HRTS1_B, SEL_HSCIF1_B),
- PINMUX_IPSR_DATA(IP9_5_3, VI0_G5),
+ PINMUX_IPSR_GPSR(IP9_5_3, VI0_G5),
PINMUX_IPSR_MSEL(IP9_5_3, SD2_DAT1_B, SEL_SD2_B),
- PINMUX_IPSR_DATA(IP9_5_3, VI1_DATA7),
- PINMUX_IPSR_DATA(IP9_5_3, DU1_DR7),
+ PINMUX_IPSR_GPSR(IP9_5_3, VI1_DATA7),
+ PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR7),
PINMUX_IPSR_MSEL(IP9_5_3, HCTS1_B, SEL_HSCIF1_B),
PINMUX_DATA(VI0_R0_A_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_A), /* see sel_vi0 */
PINMUX_DATA(VI0_R0_C_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_C), /* see sel_vi0 */
- PINMUX_IPSR_DATA(IP9_8_6, VI1_CLK),
- PINMUX_IPSR_DATA(IP9_8_6, ETH_REF_CLK),
- PINMUX_IPSR_DATA(IP9_8_6, DU1_DOTCLKIN),
+ PINMUX_IPSR_GPSR(IP9_8_6, VI1_CLK),
+ PINMUX_IPSR_GPSR(IP9_8_6, ETH_REF_CLK),
+ PINMUX_IPSR_GPSR(IP9_8_6, DU1_DOTCLKIN),
PINMUX_DATA(VI0_R1_A_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_A), /* see sel_vi0 */
PINMUX_DATA(VI0_R1_C_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_C), /* see sel_vi0 */
- PINMUX_IPSR_DATA(IP9_11_9, VI1_DATA8),
- PINMUX_IPSR_DATA(IP9_11_9, DU1_DB6),
- PINMUX_IPSR_DATA(IP9_11_9, ETH_TXD0),
- PINMUX_IPSR_DATA(IP9_11_9, PWM2),
- PINMUX_IPSR_DATA(IP9_11_9, TCLK1),
+ PINMUX_IPSR_GPSR(IP9_11_9, VI1_DATA8),
+ PINMUX_IPSR_GPSR(IP9_11_9, DU1_DB6),
+ PINMUX_IPSR_GPSR(IP9_11_9, ETH_TXD0),
+ PINMUX_IPSR_GPSR(IP9_11_9, PWM2),
+ PINMUX_IPSR_GPSR(IP9_11_9, TCLK1),
PINMUX_DATA(VI0_R2_A_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_A), /* see sel_vi0 */
PINMUX_DATA(VI0_R2_C_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_C), /* see sel_vi0 */
- PINMUX_IPSR_DATA(IP9_14_12, VI1_DATA9),
- PINMUX_IPSR_DATA(IP9_14_12, DU1_DB7),
- PINMUX_IPSR_DATA(IP9_14_12, ETH_TXD1),
- PINMUX_IPSR_DATA(IP9_14_12, PWM3),
+ PINMUX_IPSR_GPSR(IP9_14_12, VI1_DATA9),
+ PINMUX_IPSR_GPSR(IP9_14_12, DU1_DB7),
+ PINMUX_IPSR_GPSR(IP9_14_12, ETH_TXD1),
+ PINMUX_IPSR_GPSR(IP9_14_12, PWM3),
PINMUX_IPSR_MSEL(IP9_17_15, VI0_R3_A, SEL_VI0_A),
- PINMUX_IPSR_DATA(IP9_17_15, ETH_CRS_DV),
- PINMUX_IPSR_DATA(IP9_17_15, IECLK),
+ PINMUX_IPSR_GPSR(IP9_17_15, ETH_CRS_DV),
+ PINMUX_IPSR_GPSR(IP9_17_15, IECLK),
PINMUX_IPSR_MSEL(IP9_17_15, SCK2_C, SEL_SCIF2_C),
PINMUX_DATA(VI0_R4_A_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_A), /* see sel_vi0 */
PINMUX_DATA(VI0_R3_C_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_C), /* see sel_vi0 */
- PINMUX_IPSR_DATA(IP9_20_18, ETH_TX_EN),
- PINMUX_IPSR_DATA(IP9_20_18, IETX),
- PINMUX_IPSR_DATA(IP9_20_18, TX2_C),
+ PINMUX_IPSR_GPSR(IP9_20_18, ETH_TX_EN),
+ PINMUX_IPSR_GPSR(IP9_20_18, IETX),
+ PINMUX_IPSR_GPSR(IP9_20_18, TX2_C),
PINMUX_DATA(VI0_R5_A_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_A), /* see sel_vi0 */
PINMUX_DATA(VI0_R5_C_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_C), /* see sel_vi0 */
- PINMUX_IPSR_DATA(IP9_23_21, ETH_RX_ER),
+ PINMUX_IPSR_GPSR(IP9_23_21, ETH_RX_ER),
PINMUX_IPSR_MSEL(IP9_23_21, FMCLK_C, SEL_FM_C),
- PINMUX_IPSR_DATA(IP9_23_21, IERX),
+ PINMUX_IPSR_GPSR(IP9_23_21, IERX),
PINMUX_IPSR_MSEL(IP9_23_21, RX2_C, SEL_SCIF2_C),
PINMUX_IPSR_MSEL(IP9_26_24, VI1_DATA10_A, SEL_VI1_A),
- PINMUX_IPSR_DATA(IP9_26_24, DU1_DOTCLKOUT),
- PINMUX_IPSR_DATA(IP9_26_24, ETH_RXD0),
- PINMUX_IPSR_DATA(IP9_26_24, BPFCLK_C),
- PINMUX_IPSR_DATA(IP9_26_24, TX2_D),
+ PINMUX_IPSR_GPSR(IP9_26_24, DU1_DOTCLKOUT),
+ PINMUX_IPSR_GPSR(IP9_26_24, ETH_RXD0),
+ PINMUX_IPSR_GPSR(IP9_26_24, BPFCLK_C),
+ PINMUX_IPSR_GPSR(IP9_26_24, TX2_D),
PINMUX_IPSR_MSEL(IP9_26_24, SDA2_C, SEL_I2C2_C),
PINMUX_IPSR_MSEL(IP9_29_27, VI1_DATA11_A, SEL_VI1_A),
- PINMUX_IPSR_DATA(IP9_29_27, DU1_EXHSYNC_DU1_HSYNC),
- PINMUX_IPSR_DATA(IP9_29_27, ETH_RXD1),
+ PINMUX_IPSR_GPSR(IP9_29_27, DU1_EXHSYNC_DU1_HSYNC),
+ PINMUX_IPSR_GPSR(IP9_29_27, ETH_RXD1),
PINMUX_IPSR_MSEL(IP9_29_27, FMIN_C, SEL_FM_C),
PINMUX_IPSR_MSEL(IP9_29_27, RX2_D, SEL_SCIF2_D),
PINMUX_IPSR_MSEL(IP9_29_27, SCL2_C, SEL_I2C2_C),
/* IPSR10 */
- PINMUX_IPSR_DATA(IP10_2_0, SD2_CLK_A),
- PINMUX_IPSR_DATA(IP10_2_0, DU1_EXVSYNC_DU1_VSYNC),
- PINMUX_IPSR_DATA(IP10_2_0, ATARD1),
- PINMUX_IPSR_DATA(IP10_2_0, ETH_MDC),
+ PINMUX_IPSR_GPSR(IP10_2_0, SD2_CLK_A),
+ PINMUX_IPSR_GPSR(IP10_2_0, DU1_EXVSYNC_DU1_VSYNC),
+ PINMUX_IPSR_GPSR(IP10_2_0, ATARD1),
+ PINMUX_IPSR_GPSR(IP10_2_0, ETH_MDC),
PINMUX_IPSR_MSEL(IP10_2_0, SDA1_B, SEL_I2C1_B),
PINMUX_IPSR_MSEL(IP10_5_3, SD2_CMD_A, SEL_SD2_A),
- PINMUX_IPSR_DATA(IP10_5_3, DU1_EXODDF_DU1_ODDF_DISP_CDE),
- PINMUX_IPSR_DATA(IP10_5_3, ATAWR1),
- PINMUX_IPSR_DATA(IP10_5_3, ETH_MDIO),
+ PINMUX_IPSR_GPSR(IP10_5_3, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP10_5_3, ATAWR1),
+ PINMUX_IPSR_GPSR(IP10_5_3, ETH_MDIO),
PINMUX_IPSR_MSEL(IP10_5_3, SCL1_B, SEL_I2C1_B),
PINMUX_IPSR_MSEL(IP10_8_6, SD2_DAT0_A, SEL_SD2_A),
- PINMUX_IPSR_DATA(IP10_8_6, DU1_DISP),
- PINMUX_IPSR_DATA(IP10_8_6, ATACS01),
+ PINMUX_IPSR_GPSR(IP10_8_6, DU1_DISP),
+ PINMUX_IPSR_GPSR(IP10_8_6, ATACS01),
PINMUX_IPSR_MSEL(IP10_8_6, DREQ1_B, SEL_DREQ1_B),
- PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
+ PINMUX_IPSR_GPSR(IP10_8_6, ETH_LINK),
PINMUX_IPSR_MSEL(IP10_8_6, CAN1_RX_A, SEL_CAN1_A),
PINMUX_IPSR_MSEL(IP10_12_9, SD2_DAT1_A, SEL_SD2_A),
- PINMUX_IPSR_DATA(IP10_12_9, DU1_CDE),
- PINMUX_IPSR_DATA(IP10_12_9, ATACS11),
- PINMUX_IPSR_DATA(IP10_12_9, DACK1_B),
- PINMUX_IPSR_DATA(IP10_12_9, ETH_MAGIC),
- PINMUX_IPSR_DATA(IP10_12_9, CAN1_TX_A),
- PINMUX_IPSR_DATA(IP10_12_9, PWM6),
+ PINMUX_IPSR_GPSR(IP10_12_9, DU1_CDE),
+ PINMUX_IPSR_GPSR(IP10_12_9, ATACS11),
+ PINMUX_IPSR_GPSR(IP10_12_9, DACK1_B),
+ PINMUX_IPSR_GPSR(IP10_12_9, ETH_MAGIC),
+ PINMUX_IPSR_GPSR(IP10_12_9, CAN1_TX_A),
+ PINMUX_IPSR_GPSR(IP10_12_9, PWM6),
PINMUX_IPSR_MSEL(IP10_15_13, SD2_DAT2_A, SEL_SD2_A),
- PINMUX_IPSR_DATA(IP10_15_13, VI1_DATA12),
+ PINMUX_IPSR_GPSR(IP10_15_13, VI1_DATA12),
PINMUX_IPSR_MSEL(IP10_15_13, DREQ2_B, SEL_DREQ2_B),
- PINMUX_IPSR_DATA(IP10_15_13, ATADIR1),
+ PINMUX_IPSR_GPSR(IP10_15_13, ATADIR1),
PINMUX_IPSR_MSEL(IP10_15_13, HSPI_CLK2_B, SEL_HSPI2_B),
PINMUX_IPSR_MSEL(IP10_15_13, GPSCLK_B, SEL_GPS_B),
PINMUX_IPSR_MSEL(IP10_18_16, SD2_DAT3_A, SEL_SD2_A),
- PINMUX_IPSR_DATA(IP10_18_16, VI1_DATA13),
- PINMUX_IPSR_DATA(IP10_18_16, DACK2_B),
- PINMUX_IPSR_DATA(IP10_18_16, ATAG1),
+ PINMUX_IPSR_GPSR(IP10_18_16, VI1_DATA13),
+ PINMUX_IPSR_GPSR(IP10_18_16, DACK2_B),
+ PINMUX_IPSR_GPSR(IP10_18_16, ATAG1),
PINMUX_IPSR_MSEL(IP10_18_16, HSPI_CS2_B, SEL_HSPI2_B),
PINMUX_IPSR_MSEL(IP10_18_16, GPSIN_B, SEL_GPS_B),
PINMUX_IPSR_MSEL(IP10_21_19, SD2_CD_A, SEL_SD2_A),
- PINMUX_IPSR_DATA(IP10_21_19, VI1_DATA14),
+ PINMUX_IPSR_GPSR(IP10_21_19, VI1_DATA14),
PINMUX_IPSR_MSEL(IP10_21_19, EX_WAIT1_B, SEL_WAIT1_B),
PINMUX_IPSR_MSEL(IP10_21_19, DREQ0_B, SEL_DREQ0_B),
PINMUX_IPSR_MSEL(IP10_21_19, HSPI_RX2_B, SEL_HSPI2_B),
PINMUX_IPSR_MSEL(IP10_21_19, REMOCON_A, SEL_REMOCON_A),
PINMUX_IPSR_MSEL(IP10_24_22, SD2_WP_A, SEL_SD2_A),
- PINMUX_IPSR_DATA(IP10_24_22, VI1_DATA15),
+ PINMUX_IPSR_GPSR(IP10_24_22, VI1_DATA15),
PINMUX_IPSR_MSEL(IP10_24_22, EX_WAIT2_B, SEL_WAIT2_B),
- PINMUX_IPSR_DATA(IP10_24_22, DACK0_B),
- PINMUX_IPSR_DATA(IP10_24_22, HSPI_TX2_B),
+ PINMUX_IPSR_GPSR(IP10_24_22, DACK0_B),
+ PINMUX_IPSR_GPSR(IP10_24_22, HSPI_TX2_B),
PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C),
};
PINMUX_SINGLE(USB_PENC0),
PINMUX_SINGLE(USB_PENC1),
- PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
+ PINMUX_IPSR_GPSR(IP0_2_0, USB_PENC2),
PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0),
- PINMUX_IPSR_DATA(IP0_2_0, PWM1),
+ PINMUX_IPSR_GPSR(IP0_2_0, PWM1),
PINMUX_IPSR_MSEL(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
PINMUX_IPSR_MSEL(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP0_2_0, TCLK0_C, SEL_TMU0_2),
- PINMUX_IPSR_DATA(IP0_5_3, BS),
- PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
- PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
- PINMUX_IPSR_DATA(IP0_5_3, FD2),
- PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
- PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
+ PINMUX_IPSR_GPSR(IP0_5_3, BS),
+ PINMUX_IPSR_GPSR(IP0_5_3, SD1_DAT2),
+ PINMUX_IPSR_GPSR(IP0_5_3, MMC0_D2),
+ PINMUX_IPSR_GPSR(IP0_5_3, FD2),
+ PINMUX_IPSR_GPSR(IP0_5_3, ATADIR0),
+ PINMUX_IPSR_GPSR(IP0_5_3, SDSELF),
PINMUX_IPSR_MSEL(IP0_5_3, HCTS1, SEL_HSCIF1_0),
- PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
- PINMUX_IPSR_DATA(IP0_7_6, A0),
- PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
- PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3),
- PINMUX_IPSR_DATA(IP0_7_6, FD3),
- PINMUX_IPSR_DATA(IP0_9_8, A20),
- PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
- PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
- PINMUX_IPSR_DATA(IP0_11_10, A21),
+ PINMUX_IPSR_GPSR(IP0_5_3, TX4_C),
+ PINMUX_IPSR_GPSR(IP0_7_6, A0),
+ PINMUX_IPSR_GPSR(IP0_7_6, SD1_DAT3),
+ PINMUX_IPSR_GPSR(IP0_7_6, MMC0_D3),
+ PINMUX_IPSR_GPSR(IP0_7_6, FD3),
+ PINMUX_IPSR_GPSR(IP0_9_8, A20),
+ PINMUX_IPSR_GPSR(IP0_9_8, TX5_D),
+ PINMUX_IPSR_GPSR(IP0_9_8, HSPI_TX2_B),
+ PINMUX_IPSR_GPSR(IP0_11_10, A21),
PINMUX_IPSR_MSEL(IP0_11_10, SCK5_D, SEL_SCIF5_3),
PINMUX_IPSR_MSEL(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
- PINMUX_IPSR_DATA(IP0_13_12, A22),
+ PINMUX_IPSR_GPSR(IP0_13_12, A22),
PINMUX_IPSR_MSEL(IP0_13_12, RX5_D, SEL_SCIF5_3),
PINMUX_IPSR_MSEL(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
- PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
- PINMUX_IPSR_DATA(IP0_15_14, A23),
- PINMUX_IPSR_DATA(IP0_15_14, FCLE),
+ PINMUX_IPSR_GPSR(IP0_13_12, VI1_R0),
+ PINMUX_IPSR_GPSR(IP0_15_14, A23),
+ PINMUX_IPSR_GPSR(IP0_15_14, FCLE),
PINMUX_IPSR_MSEL(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
- PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
- PINMUX_IPSR_DATA(IP0_18_16, A24),
- PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
- PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
- PINMUX_IPSR_DATA(IP0_18_16, FD4),
+ PINMUX_IPSR_GPSR(IP0_15_14, VI1_R1),
+ PINMUX_IPSR_GPSR(IP0_18_16, A24),
+ PINMUX_IPSR_GPSR(IP0_18_16, SD1_CD),
+ PINMUX_IPSR_GPSR(IP0_18_16, MMC0_D4),
+ PINMUX_IPSR_GPSR(IP0_18_16, FD4),
PINMUX_IPSR_MSEL(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
- PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
+ PINMUX_IPSR_GPSR(IP0_18_16, VI1_R2),
PINMUX_IPSR_MSEL(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
- PINMUX_IPSR_DATA(IP0_22_19, A25),
- PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
- PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
- PINMUX_IPSR_DATA(IP0_22_19, FD5),
+ PINMUX_IPSR_GPSR(IP0_22_19, A25),
+ PINMUX_IPSR_GPSR(IP0_22_19, SD1_WP),
+ PINMUX_IPSR_GPSR(IP0_22_19, MMC0_D5),
+ PINMUX_IPSR_GPSR(IP0_22_19, FD5),
PINMUX_IPSR_MSEL(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
- PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
- PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
+ PINMUX_IPSR_GPSR(IP0_22_19, VI1_R3),
+ PINMUX_IPSR_GPSR(IP0_22_19, TX5_B),
PINMUX_IPSR_MSEL(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
PINMUX_IPSR_MSEL(IP0_22_19, CTS0_B, SEL_SCIF0_1),
- PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
- PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
- PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
- PINMUX_IPSR_DATA(IP0_25, CS0),
+ PINMUX_IPSR_GPSR(IP0_24_23, CLKOUT),
+ PINMUX_IPSR_GPSR(IP0_24_23, TX3C_IRDA_TX_C),
+ PINMUX_IPSR_GPSR(IP0_24_23, PWM0_B),
+ PINMUX_IPSR_GPSR(IP0_25, CS0),
PINMUX_IPSR_MSEL(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
- PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
- PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
- PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
- PINMUX_IPSR_DATA(IP0_30_28, RD_WR),
- PINMUX_IPSR_DATA(IP0_30_28, FWE),
- PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
- PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
+ PINMUX_IPSR_GPSR(IP0_27_26, CS1_A26),
+ PINMUX_IPSR_GPSR(IP0_27_26, HSPI_TX2),
+ PINMUX_IPSR_GPSR(IP0_27_26, SDSELF_B),
+ PINMUX_IPSR_GPSR(IP0_30_28, RD_WR),
+ PINMUX_IPSR_GPSR(IP0_30_28, FWE),
+ PINMUX_IPSR_GPSR(IP0_30_28, ATAG0),
+ PINMUX_IPSR_GPSR(IP0_30_28, VI1_R7),
PINMUX_IPSR_MSEL(IP0_30_28, HRTS1, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP0_30_28, RX4_C, SEL_SCIF4_2),
- PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
+ PINMUX_IPSR_GPSR(IP1_1_0, EX_CS0),
PINMUX_IPSR_MSEL(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
- PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
- PINMUX_IPSR_DATA(IP1_1_0, FD6),
- PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
- PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7),
- PINMUX_IPSR_DATA(IP1_3_2, FD7),
- PINMUX_IPSR_DATA(IP1_6_4, EX_CS2),
- PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK),
- PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK),
- PINMUX_IPSR_DATA(IP1_6_4, FALE),
- PINMUX_IPSR_DATA(IP1_6_4, ATACS00),
- PINMUX_IPSR_DATA(IP1_10_7, EX_CS3),
- PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD),
- PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD),
- PINMUX_IPSR_DATA(IP1_10_7, FRE),
- PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
- PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
+ PINMUX_IPSR_GPSR(IP1_1_0, MMC0_D6),
+ PINMUX_IPSR_GPSR(IP1_1_0, FD6),
+ PINMUX_IPSR_GPSR(IP1_3_2, EX_CS1),
+ PINMUX_IPSR_GPSR(IP1_3_2, MMC0_D7),
+ PINMUX_IPSR_GPSR(IP1_3_2, FD7),
+ PINMUX_IPSR_GPSR(IP1_6_4, EX_CS2),
+ PINMUX_IPSR_GPSR(IP1_6_4, SD1_CLK),
+ PINMUX_IPSR_GPSR(IP1_6_4, MMC0_CLK),
+ PINMUX_IPSR_GPSR(IP1_6_4, FALE),
+ PINMUX_IPSR_GPSR(IP1_6_4, ATACS00),
+ PINMUX_IPSR_GPSR(IP1_10_7, EX_CS3),
+ PINMUX_IPSR_GPSR(IP1_10_7, SD1_CMD),
+ PINMUX_IPSR_GPSR(IP1_10_7, MMC0_CMD),
+ PINMUX_IPSR_GPSR(IP1_10_7, FRE),
+ PINMUX_IPSR_GPSR(IP1_10_7, ATACS10),
+ PINMUX_IPSR_GPSR(IP1_10_7, VI1_R4),
PINMUX_IPSR_MSEL(IP1_10_7, RX5_B, SEL_SCIF5_1),
PINMUX_IPSR_MSEL(IP1_10_7, HSCK1, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
PINMUX_IPSR_MSEL(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
- PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
- PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
- PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
- PINMUX_IPSR_DATA(IP1_14_11, FD0),
- PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
- PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
+ PINMUX_IPSR_GPSR(IP1_14_11, EX_CS4),
+ PINMUX_IPSR_GPSR(IP1_14_11, SD1_DAT0),
+ PINMUX_IPSR_GPSR(IP1_14_11, MMC0_D0),
+ PINMUX_IPSR_GPSR(IP1_14_11, FD0),
+ PINMUX_IPSR_GPSR(IP1_14_11, ATARD0),
+ PINMUX_IPSR_GPSR(IP1_14_11, VI1_R5),
PINMUX_IPSR_MSEL(IP1_14_11, SCK5_B, SEL_SCIF5_1),
- PINMUX_IPSR_DATA(IP1_14_11, HTX1),
- PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
- PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
+ PINMUX_IPSR_GPSR(IP1_14_11, HTX1),
+ PINMUX_IPSR_GPSR(IP1_14_11, TX2_E),
+ PINMUX_IPSR_GPSR(IP1_14_11, TX0_B),
PINMUX_IPSR_MSEL(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
- PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
- PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
- PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
- PINMUX_IPSR_DATA(IP1_18_15, FD1),
- PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
- PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
+ PINMUX_IPSR_GPSR(IP1_18_15, EX_CS5),
+ PINMUX_IPSR_GPSR(IP1_18_15, SD1_DAT1),
+ PINMUX_IPSR_GPSR(IP1_18_15, MMC0_D1),
+ PINMUX_IPSR_GPSR(IP1_18_15, FD1),
+ PINMUX_IPSR_GPSR(IP1_18_15, ATAWR0),
+ PINMUX_IPSR_GPSR(IP1_18_15, VI1_R6),
PINMUX_IPSR_MSEL(IP1_18_15, HRX1, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP1_18_15, RX2_E, SEL_SCIF2_4),
PINMUX_IPSR_MSEL(IP1_18_15, RX0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP1_18_15, SSI_WS9, SEL_SSI9_0),
- PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
- PINMUX_IPSR_DATA(IP1_20_19, PWM2),
+ PINMUX_IPSR_GPSR(IP1_20_19, MLB_CLK),
+ PINMUX_IPSR_GPSR(IP1_20_19, PWM2),
PINMUX_IPSR_MSEL(IP1_20_19, SCK4, SEL_SCIF4_0),
- PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
- PINMUX_IPSR_DATA(IP1_22_21, PWM3),
- PINMUX_IPSR_DATA(IP1_22_21, TX4),
- PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
- PINMUX_IPSR_DATA(IP1_24_23, PWM4),
+ PINMUX_IPSR_GPSR(IP1_22_21, MLB_SIG),
+ PINMUX_IPSR_GPSR(IP1_22_21, PWM3),
+ PINMUX_IPSR_GPSR(IP1_22_21, TX4),
+ PINMUX_IPSR_GPSR(IP1_24_23, MLB_DAT),
+ PINMUX_IPSR_GPSR(IP1_24_23, PWM4),
PINMUX_IPSR_MSEL(IP1_24_23, RX4, SEL_SCIF4_0),
- PINMUX_IPSR_DATA(IP1_28_25, HTX0),
- PINMUX_IPSR_DATA(IP1_28_25, TX1),
- PINMUX_IPSR_DATA(IP1_28_25, SDATA),
+ PINMUX_IPSR_GPSR(IP1_28_25, HTX0),
+ PINMUX_IPSR_GPSR(IP1_28_25, TX1),
+ PINMUX_IPSR_GPSR(IP1_28_25, SDATA),
PINMUX_IPSR_MSEL(IP1_28_25, CTS0_C, SEL_SCIF0_2),
- PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
- PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
- PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
- PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18),
- PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
- PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
+ PINMUX_IPSR_GPSR(IP1_28_25, SUB_TCK),
+ PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE2),
+ PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE10),
+ PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE18),
+ PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE26),
+ PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE34),
PINMUX_IPSR_MSEL(IP2_3_0, HRX0, SEL_HSCIF0_0),
PINMUX_IPSR_MSEL(IP2_3_0, RX1, SEL_SCIF1_0),
- PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
+ PINMUX_IPSR_GPSR(IP2_3_0, SCKZ),
PINMUX_IPSR_MSEL(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
- PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
- PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
- PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
- PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
- PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
- PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
+ PINMUX_IPSR_GPSR(IP2_3_0, SUB_TDI),
+ PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE3),
+ PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE11),
+ PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE19),
+ PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE27),
+ PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE35),
PINMUX_IPSR_MSEL(IP2_7_4, HSCK0, SEL_HSCIF0_0),
PINMUX_IPSR_MSEL(IP2_7_4, SCK1, SEL_SCIF1_0),
- PINMUX_IPSR_DATA(IP2_7_4, MTS),
- PINMUX_IPSR_DATA(IP2_7_4, PWM5),
+ PINMUX_IPSR_GPSR(IP2_7_4, MTS),
+ PINMUX_IPSR_GPSR(IP2_7_4, PWM5),
PINMUX_IPSR_MSEL(IP2_7_4, SCK0_C, SEL_SCIF0_2),
PINMUX_IPSR_MSEL(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
- PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
- PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
- PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
- PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
- PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
- PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
+ PINMUX_IPSR_GPSR(IP2_7_4, SUB_TDO),
+ PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE0),
+ PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE8),
+ PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE16),
+ PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE24),
+ PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE32),
PINMUX_IPSR_MSEL(IP2_11_8, HCTS0, SEL_HSCIF0_0),
PINMUX_IPSR_MSEL(IP2_11_8, CTS1, SEL_SCIF1_0),
- PINMUX_IPSR_DATA(IP2_11_8, STM),
- PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
+ PINMUX_IPSR_GPSR(IP2_11_8, STM),
+ PINMUX_IPSR_GPSR(IP2_11_8, PWM0_D),
PINMUX_IPSR_MSEL(IP2_11_8, RX0_C, SEL_SCIF0_2),
PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
- PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
+ PINMUX_IPSR_GPSR(IP2_11_8, SUB_TRST),
PINMUX_IPSR_MSEL(IP2_11_8, TCLK1_B, SEL_TMU1_1),
- PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
+ PINMUX_IPSR_GPSR(IP2_11_8, CC5_OSCOUT),
PINMUX_IPSR_MSEL(IP2_15_12, HRTS0, SEL_HSCIF0_0),
PINMUX_IPSR_MSEL(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
- PINMUX_IPSR_DATA(IP2_15_12, MDATA),
- PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
- PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
- PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1),
- PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9),
- PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17),
- PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25),
- PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
- PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
- PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
+ PINMUX_IPSR_GPSR(IP2_15_12, MDATA),
+ PINMUX_IPSR_GPSR(IP2_15_12, TX0_C),
+ PINMUX_IPSR_GPSR(IP2_15_12, SUB_TMS),
+ PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE1),
+ PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE9),
+ PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE17),
+ PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE25),
+ PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE33),
+ PINMUX_IPSR_GPSR(IP2_18_16, DU0_DR0),
+ PINMUX_IPSR_GPSR(IP2_18_16, LCDOUT0),
PINMUX_IPSR_MSEL(IP2_18_16, DREQ0, SEL_EXBUS0_0),
PINMUX_IPSR_MSEL(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
- PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
- PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
- PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
- PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
- PINMUX_IPSR_DATA(IP2_21_19, DACK0),
- PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
+ PINMUX_IPSR_GPSR(IP2_18_16, AUDATA0),
+ PINMUX_IPSR_GPSR(IP2_18_16, TX5_C),
+ PINMUX_IPSR_GPSR(IP2_21_19, DU0_DR1),
+ PINMUX_IPSR_GPSR(IP2_21_19, LCDOUT1),
+ PINMUX_IPSR_GPSR(IP2_21_19, DACK0),
+ PINMUX_IPSR_GPSR(IP2_21_19, DRACK0),
PINMUX_IPSR_MSEL(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
- PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
+ PINMUX_IPSR_GPSR(IP2_21_19, AUDATA1),
PINMUX_IPSR_MSEL(IP2_21_19, RX5_C, SEL_SCIF5_2),
- PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
- PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
- PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
- PINMUX_IPSR_DATA(IP2_23, LCDOUT3),
- PINMUX_IPSR_DATA(IP2_24, DU0_DR4),
- PINMUX_IPSR_DATA(IP2_24, LCDOUT4),
- PINMUX_IPSR_DATA(IP2_25, DU0_DR5),
- PINMUX_IPSR_DATA(IP2_25, LCDOUT5),
- PINMUX_IPSR_DATA(IP2_26, DU0_DR6),
- PINMUX_IPSR_DATA(IP2_26, LCDOUT6),
- PINMUX_IPSR_DATA(IP2_27, DU0_DR7),
- PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
- PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
- PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
+ PINMUX_IPSR_GPSR(IP2_22, DU0_DR2),
+ PINMUX_IPSR_GPSR(IP2_22, LCDOUT2),
+ PINMUX_IPSR_GPSR(IP2_23, DU0_DR3),
+ PINMUX_IPSR_GPSR(IP2_23, LCDOUT3),
+ PINMUX_IPSR_GPSR(IP2_24, DU0_DR4),
+ PINMUX_IPSR_GPSR(IP2_24, LCDOUT4),
+ PINMUX_IPSR_GPSR(IP2_25, DU0_DR5),
+ PINMUX_IPSR_GPSR(IP2_25, LCDOUT5),
+ PINMUX_IPSR_GPSR(IP2_26, DU0_DR6),
+ PINMUX_IPSR_GPSR(IP2_26, LCDOUT6),
+ PINMUX_IPSR_GPSR(IP2_27, DU0_DR7),
+ PINMUX_IPSR_GPSR(IP2_27, LCDOUT7),
+ PINMUX_IPSR_GPSR(IP2_30_28, DU0_DG0),
+ PINMUX_IPSR_GPSR(IP2_30_28, LCDOUT8),
PINMUX_IPSR_MSEL(IP2_30_28, DREQ1, SEL_EXBUS1_0),
PINMUX_IPSR_MSEL(IP2_30_28, SCL2, SEL_I2C2_0),
- PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
+ PINMUX_IPSR_GPSR(IP2_30_28, AUDATA2),
- PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
- PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
- PINMUX_IPSR_DATA(IP3_2_0, DACK1),
+ PINMUX_IPSR_GPSR(IP3_2_0, DU0_DG1),
+ PINMUX_IPSR_GPSR(IP3_2_0, LCDOUT9),
+ PINMUX_IPSR_GPSR(IP3_2_0, DACK1),
PINMUX_IPSR_MSEL(IP3_2_0, SDA2, SEL_I2C2_0),
- PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
- PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
- PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
- PINMUX_IPSR_DATA(IP3_4, DU0_DG3),
- PINMUX_IPSR_DATA(IP3_4, LCDOUT11),
- PINMUX_IPSR_DATA(IP3_5, DU0_DG4),
- PINMUX_IPSR_DATA(IP3_5, LCDOUT12),
- PINMUX_IPSR_DATA(IP3_6, DU0_DG5),
- PINMUX_IPSR_DATA(IP3_6, LCDOUT13),
- PINMUX_IPSR_DATA(IP3_7, DU0_DG6),
- PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
- PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
- PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
- PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
- PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
- PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
+ PINMUX_IPSR_GPSR(IP3_2_0, AUDATA3),
+ PINMUX_IPSR_GPSR(IP3_3, DU0_DG2),
+ PINMUX_IPSR_GPSR(IP3_3, LCDOUT10),
+ PINMUX_IPSR_GPSR(IP3_4, DU0_DG3),
+ PINMUX_IPSR_GPSR(IP3_4, LCDOUT11),
+ PINMUX_IPSR_GPSR(IP3_5, DU0_DG4),
+ PINMUX_IPSR_GPSR(IP3_5, LCDOUT12),
+ PINMUX_IPSR_GPSR(IP3_6, DU0_DG5),
+ PINMUX_IPSR_GPSR(IP3_6, LCDOUT13),
+ PINMUX_IPSR_GPSR(IP3_7, DU0_DG6),
+ PINMUX_IPSR_GPSR(IP3_7, LCDOUT14),
+ PINMUX_IPSR_GPSR(IP3_8, DU0_DG7),
+ PINMUX_IPSR_GPSR(IP3_8, LCDOUT15),
+ PINMUX_IPSR_GPSR(IP3_11_9, DU0_DB0),
+ PINMUX_IPSR_GPSR(IP3_11_9, LCDOUT16),
+ PINMUX_IPSR_GPSR(IP3_11_9, EX_WAIT1),
PINMUX_IPSR_MSEL(IP3_11_9, SCL1, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP3_11_9, TCLK1, SEL_TMU1_0),
- PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
- PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
- PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
- PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
+ PINMUX_IPSR_GPSR(IP3_11_9, AUDATA4),
+ PINMUX_IPSR_GPSR(IP3_14_12, DU0_DB1),
+ PINMUX_IPSR_GPSR(IP3_14_12, LCDOUT17),
+ PINMUX_IPSR_GPSR(IP3_14_12, EX_WAIT2),
PINMUX_IPSR_MSEL(IP3_14_12, SDA1, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
- PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
+ PINMUX_IPSR_GPSR(IP3_14_12, AUDATA5),
PINMUX_IPSR_MSEL(IP3_14_12, SCK5_C, SEL_SCIF5_2),
- PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
- PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
- PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
- PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
- PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
- PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
- PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
- PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
- PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
- PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
- PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
- PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
- PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
- PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
- PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
+ PINMUX_IPSR_GPSR(IP3_15, DU0_DB2),
+ PINMUX_IPSR_GPSR(IP3_15, LCDOUT18),
+ PINMUX_IPSR_GPSR(IP3_16, DU0_DB3),
+ PINMUX_IPSR_GPSR(IP3_16, LCDOUT19),
+ PINMUX_IPSR_GPSR(IP3_17, DU0_DB4),
+ PINMUX_IPSR_GPSR(IP3_17, LCDOUT20),
+ PINMUX_IPSR_GPSR(IP3_18, DU0_DB5),
+ PINMUX_IPSR_GPSR(IP3_18, LCDOUT21),
+ PINMUX_IPSR_GPSR(IP3_19, DU0_DB6),
+ PINMUX_IPSR_GPSR(IP3_19, LCDOUT22),
+ PINMUX_IPSR_GPSR(IP3_20, DU0_DB7),
+ PINMUX_IPSR_GPSR(IP3_20, LCDOUT23),
+ PINMUX_IPSR_GPSR(IP3_22_21, DU0_DOTCLKIN),
+ PINMUX_IPSR_GPSR(IP3_22_21, QSTVA_QVS),
+ PINMUX_IPSR_GPSR(IP3_22_21, TX3_D_IRDA_TX_D),
PINMUX_IPSR_MSEL(IP3_22_21, SCL3_B, SEL_I2C3_1),
- PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
- PINMUX_IPSR_DATA(IP3_23, QCLK),
- PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
- PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
+ PINMUX_IPSR_GPSR(IP3_23, DU0_DOTCLKOUT0),
+ PINMUX_IPSR_GPSR(IP3_23, QCLK),
+ PINMUX_IPSR_GPSR(IP3_26_24, DU0_DOTCLKOUT1),
+ PINMUX_IPSR_GPSR(IP3_26_24, QSTVB_QVE),
PINMUX_IPSR_MSEL(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
PINMUX_IPSR_MSEL(IP3_26_24, SDA3_B, SEL_I2C3_1),
PINMUX_IPSR_MSEL(IP3_26_24, SDA2_C, SEL_I2C2_2),
- PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
- PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
- PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
- PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
- PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
- PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
- PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
- PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
- PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
- PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
+ PINMUX_IPSR_GPSR(IP3_26_24, DACK0_B),
+ PINMUX_IPSR_GPSR(IP3_26_24, DRACK0_B),
+ PINMUX_IPSR_GPSR(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
+ PINMUX_IPSR_GPSR(IP3_27, QSTH_QHS),
+ PINMUX_IPSR_GPSR(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
+ PINMUX_IPSR_GPSR(IP3_28, QSTB_QHE),
+ PINMUX_IPSR_GPSR(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP3_31_29, QCPV_QDE),
+ PINMUX_IPSR_GPSR(IP3_31_29, CAN1_TX),
+ PINMUX_IPSR_GPSR(IP3_31_29, TX2_C),
PINMUX_IPSR_MSEL(IP3_31_29, SCL2_C, SEL_I2C2_2),
- PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
+ PINMUX_IPSR_GPSR(IP3_31_29, REMOCON),
- PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
- PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
+ PINMUX_IPSR_GPSR(IP4_1_0, DU0_DISP),
+ PINMUX_IPSR_GPSR(IP4_1_0, QPOLA),
PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
PINMUX_IPSR_MSEL(IP4_1_0, SCK2_C, SEL_SCIF2_2),
- PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
- PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
- PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
+ PINMUX_IPSR_GPSR(IP4_4_2, DU0_CDE),
+ PINMUX_IPSR_GPSR(IP4_4_2, QPOLB),
+ PINMUX_IPSR_GPSR(IP4_4_2, CAN1_RX),
PINMUX_IPSR_MSEL(IP4_4_2, RX2_C, SEL_SCIF2_2),
PINMUX_IPSR_MSEL(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
PINMUX_IPSR_MSEL(IP4_4_2, SCK0_B, SEL_SCIF0_1),
- PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
- PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
- PINMUX_IPSR_DATA(IP4_7_5, PWM6),
- PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
- PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
- PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
+ PINMUX_IPSR_GPSR(IP4_7_5, DU1_DR0),
+ PINMUX_IPSR_GPSR(IP4_7_5, VI2_DATA0_VI2_B0),
+ PINMUX_IPSR_GPSR(IP4_7_5, PWM6),
+ PINMUX_IPSR_GPSR(IP4_7_5, SD3_CLK),
+ PINMUX_IPSR_GPSR(IP4_7_5, TX3_E_IRDA_TX_E),
+ PINMUX_IPSR_GPSR(IP4_7_5, AUDCK),
PINMUX_IPSR_MSEL(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
- PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
- PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
- PINMUX_IPSR_DATA(IP4_10_8, PWM0),
- PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
+ PINMUX_IPSR_GPSR(IP4_10_8, DU1_DR1),
+ PINMUX_IPSR_GPSR(IP4_10_8, VI2_DATA1_VI2_B1),
+ PINMUX_IPSR_GPSR(IP4_10_8, PWM0),
+ PINMUX_IPSR_GPSR(IP4_10_8, SD3_CMD),
PINMUX_IPSR_MSEL(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
- PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
+ PINMUX_IPSR_GPSR(IP4_10_8, AUDSYNC),
PINMUX_IPSR_MSEL(IP4_10_8, CTS0_D, SEL_SCIF0_3),
- PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
- PINMUX_IPSR_DATA(IP4_11, VI2_G0),
- PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
- PINMUX_IPSR_DATA(IP4_12, VI2_G1),
- PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
- PINMUX_IPSR_DATA(IP4_13, VI2_G2),
- PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
- PINMUX_IPSR_DATA(IP4_14, VI2_G3),
- PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
- PINMUX_IPSR_DATA(IP4_15, VI2_G4),
- PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
- PINMUX_IPSR_DATA(IP4_16, VI2_G5),
- PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
- PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
+ PINMUX_IPSR_GPSR(IP4_11, DU1_DR2),
+ PINMUX_IPSR_GPSR(IP4_11, VI2_G0),
+ PINMUX_IPSR_GPSR(IP4_12, DU1_DR3),
+ PINMUX_IPSR_GPSR(IP4_12, VI2_G1),
+ PINMUX_IPSR_GPSR(IP4_13, DU1_DR4),
+ PINMUX_IPSR_GPSR(IP4_13, VI2_G2),
+ PINMUX_IPSR_GPSR(IP4_14, DU1_DR5),
+ PINMUX_IPSR_GPSR(IP4_14, VI2_G3),
+ PINMUX_IPSR_GPSR(IP4_15, DU1_DR6),
+ PINMUX_IPSR_GPSR(IP4_15, VI2_G4),
+ PINMUX_IPSR_GPSR(IP4_16, DU1_DR7),
+ PINMUX_IPSR_GPSR(IP4_16, VI2_G5),
+ PINMUX_IPSR_GPSR(IP4_19_17, DU1_DG0),
+ PINMUX_IPSR_GPSR(IP4_19_17, VI2_DATA2_VI2_B2),
PINMUX_IPSR_MSEL(IP4_19_17, SCL1_B, SEL_I2C1_1),
- PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
+ PINMUX_IPSR_GPSR(IP4_19_17, SD3_DAT2),
PINMUX_IPSR_MSEL(IP4_19_17, SCK3_E, SEL_SCIF3_4),
- PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
- PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
- PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
- PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
+ PINMUX_IPSR_GPSR(IP4_19_17, AUDATA6),
+ PINMUX_IPSR_GPSR(IP4_19_17, TX0_D),
+ PINMUX_IPSR_GPSR(IP4_22_20, DU1_DG1),
+ PINMUX_IPSR_GPSR(IP4_22_20, VI2_DATA3_VI2_B3),
PINMUX_IPSR_MSEL(IP4_22_20, SDA1_B, SEL_I2C1_1),
- PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
+ PINMUX_IPSR_GPSR(IP4_22_20, SD3_DAT3),
PINMUX_IPSR_MSEL(IP4_22_20, SCK5, SEL_SCIF5_0),
- PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
+ PINMUX_IPSR_GPSR(IP4_22_20, AUDATA7),
PINMUX_IPSR_MSEL(IP4_22_20, RX0_D, SEL_SCIF0_3),
- PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
- PINMUX_IPSR_DATA(IP4_23, VI2_G6),
- PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
- PINMUX_IPSR_DATA(IP4_24, VI2_G7),
- PINMUX_IPSR_DATA(IP4_25, DU1_DG4),
- PINMUX_IPSR_DATA(IP4_25, VI2_R0),
- PINMUX_IPSR_DATA(IP4_26, DU1_DG5),
- PINMUX_IPSR_DATA(IP4_26, VI2_R1),
- PINMUX_IPSR_DATA(IP4_27, DU1_DG6),
- PINMUX_IPSR_DATA(IP4_27, VI2_R2),
- PINMUX_IPSR_DATA(IP4_28, DU1_DG7),
- PINMUX_IPSR_DATA(IP4_28, VI2_R3),
- PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
- PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
+ PINMUX_IPSR_GPSR(IP4_23, DU1_DG2),
+ PINMUX_IPSR_GPSR(IP4_23, VI2_G6),
+ PINMUX_IPSR_GPSR(IP4_24, DU1_DG3),
+ PINMUX_IPSR_GPSR(IP4_24, VI2_G7),
+ PINMUX_IPSR_GPSR(IP4_25, DU1_DG4),
+ PINMUX_IPSR_GPSR(IP4_25, VI2_R0),
+ PINMUX_IPSR_GPSR(IP4_26, DU1_DG5),
+ PINMUX_IPSR_GPSR(IP4_26, VI2_R1),
+ PINMUX_IPSR_GPSR(IP4_27, DU1_DG6),
+ PINMUX_IPSR_GPSR(IP4_27, VI2_R2),
+ PINMUX_IPSR_GPSR(IP4_28, DU1_DG7),
+ PINMUX_IPSR_GPSR(IP4_28, VI2_R3),
+ PINMUX_IPSR_GPSR(IP4_31_29, DU1_DB0),
+ PINMUX_IPSR_GPSR(IP4_31_29, VI2_DATA4_VI2_B4),
PINMUX_IPSR_MSEL(IP4_31_29, SCL2_B, SEL_I2C2_1),
- PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
- PINMUX_IPSR_DATA(IP4_31_29, TX5),
+ PINMUX_IPSR_GPSR(IP4_31_29, SD3_DAT0),
+ PINMUX_IPSR_GPSR(IP4_31_29, TX5),
PINMUX_IPSR_MSEL(IP4_31_29, SCK0_D, SEL_SCIF0_3),
- PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
- PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
+ PINMUX_IPSR_GPSR(IP5_2_0, DU1_DB1),
+ PINMUX_IPSR_GPSR(IP5_2_0, VI2_DATA5_VI2_B5),
PINMUX_IPSR_MSEL(IP5_2_0, SDA2_B, SEL_I2C2_1),
- PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
+ PINMUX_IPSR_GPSR(IP5_2_0, SD3_DAT1),
PINMUX_IPSR_MSEL(IP5_2_0, RX5, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
- PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
- PINMUX_IPSR_DATA(IP5_3, VI2_R4),
- PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
- PINMUX_IPSR_DATA(IP5_4, VI2_R5),
- PINMUX_IPSR_DATA(IP5_5, DU1_DB4),
- PINMUX_IPSR_DATA(IP5_5, VI2_R6),
- PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
- PINMUX_IPSR_DATA(IP5_6, VI2_R7),
- PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
+ PINMUX_IPSR_GPSR(IP5_3, DU1_DB2),
+ PINMUX_IPSR_GPSR(IP5_3, VI2_R4),
+ PINMUX_IPSR_GPSR(IP5_4, DU1_DB3),
+ PINMUX_IPSR_GPSR(IP5_4, VI2_R5),
+ PINMUX_IPSR_GPSR(IP5_5, DU1_DB4),
+ PINMUX_IPSR_GPSR(IP5_5, VI2_R6),
+ PINMUX_IPSR_GPSR(IP5_6, DU1_DB5),
+ PINMUX_IPSR_GPSR(IP5_6, VI2_R7),
+ PINMUX_IPSR_GPSR(IP5_7, DU1_DB6),
PINMUX_IPSR_MSEL(IP5_7, SCL2_D, SEL_I2C2_3),
- PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
+ PINMUX_IPSR_GPSR(IP5_8, DU1_DB7),
PINMUX_IPSR_MSEL(IP5_8, SDA2_D, SEL_I2C2_3),
- PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
- PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
+ PINMUX_IPSR_GPSR(IP5_10_9, DU1_DOTCLKIN),
+ PINMUX_IPSR_GPSR(IP5_10_9, VI2_CLKENB),
PINMUX_IPSR_MSEL(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
PINMUX_IPSR_MSEL(IP5_10_9, SCL1_D, SEL_I2C1_3),
- PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
- PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
+ PINMUX_IPSR_GPSR(IP5_12_11, DU1_DOTCLKOUT),
+ PINMUX_IPSR_GPSR(IP5_12_11, VI2_FIELD),
PINMUX_IPSR_MSEL(IP5_12_11, SDA1_D, SEL_I2C1_3),
- PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
- PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
- PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
- PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
- PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC),
- PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC),
- PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
- PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK),
- PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B),
- PINMUX_IPSR_DATA(IP5_20_17, SD3_CD),
- PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1),
- PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB),
- PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB),
- PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
- PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
- PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
+ PINMUX_IPSR_GPSR(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
+ PINMUX_IPSR_GPSR(IP5_14_13, VI2_HSYNC),
+ PINMUX_IPSR_GPSR(IP5_14_13, VI3_HSYNC),
+ PINMUX_IPSR_GPSR(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
+ PINMUX_IPSR_GPSR(IP5_16_15, VI2_VSYNC),
+ PINMUX_IPSR_GPSR(IP5_16_15, VI3_VSYNC),
+ PINMUX_IPSR_GPSR(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP5_20_17, VI2_CLK),
+ PINMUX_IPSR_GPSR(IP5_20_17, TX3_B_IRDA_TX_B),
+ PINMUX_IPSR_GPSR(IP5_20_17, SD3_CD),
+ PINMUX_IPSR_GPSR(IP5_20_17, HSPI_TX1),
+ PINMUX_IPSR_GPSR(IP5_20_17, VI1_CLKENB),
+ PINMUX_IPSR_GPSR(IP5_20_17, VI3_CLKENB),
+ PINMUX_IPSR_GPSR(IP5_20_17, AUDIO_CLKC),
+ PINMUX_IPSR_GPSR(IP5_20_17, TX2_D),
+ PINMUX_IPSR_GPSR(IP5_20_17, SPEEDIN),
PINMUX_IPSR_MSEL(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
- PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
- PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
+ PINMUX_IPSR_GPSR(IP5_23_21, DU1_DISP),
+ PINMUX_IPSR_GPSR(IP5_23_21, VI2_DATA6_VI2_B6),
PINMUX_IPSR_MSEL(IP5_23_21, TCLK0, SEL_TMU0_0),
- PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
+ PINMUX_IPSR_GPSR(IP5_23_21, QSTVA_B_QVS_B),
PINMUX_IPSR_MSEL(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
PINMUX_IPSR_MSEL(IP5_23_21, SCK2_D, SEL_SCIF2_3),
- PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
+ PINMUX_IPSR_GPSR(IP5_23_21, AUDIO_CLKOUT_B),
PINMUX_IPSR_MSEL(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
- PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
- PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
+ PINMUX_IPSR_GPSR(IP5_27_24, DU1_CDE),
+ PINMUX_IPSR_GPSR(IP5_27_24, VI2_DATA7_VI2_B7),
PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
- PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
+ PINMUX_IPSR_GPSR(IP5_27_24, SD3_WP),
PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
- PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
- PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
- PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
+ PINMUX_IPSR_GPSR(IP5_27_24, VI1_FIELD),
+ PINMUX_IPSR_GPSR(IP5_27_24, VI3_FIELD),
+ PINMUX_IPSR_GPSR(IP5_27_24, AUDIO_CLKOUT),
PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3),
PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
- PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
- PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
- PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
- PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2),
- PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0),
- PINMUX_IPSR_DATA(IP5_30_29, MOUT0),
-
- PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129),
- PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1),
- PINMUX_IPSR_DATA(IP6_1_0, MOUT1),
- PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129),
- PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2),
- PINMUX_IPSR_DATA(IP6_3_2, MOUT2),
- PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0),
- PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3),
- PINMUX_IPSR_DATA(IP6_5_4, MOUT5),
- PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1),
- PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4),
- PINMUX_IPSR_DATA(IP6_7_6, MOUT6),
- PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2),
- PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5),
- PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
- PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
- PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
+ PINMUX_IPSR_GPSR(IP5_28, AUDIO_CLKA),
+ PINMUX_IPSR_GPSR(IP5_28, CAN_TXCLK),
+ PINMUX_IPSR_GPSR(IP5_30_29, AUDIO_CLKB),
+ PINMUX_IPSR_GPSR(IP5_30_29, USB_OVC2),
+ PINMUX_IPSR_GPSR(IP5_30_29, CAN_DEBUGOUT0),
+ PINMUX_IPSR_GPSR(IP5_30_29, MOUT0),
+
+ PINMUX_IPSR_GPSR(IP6_1_0, SSI_SCK0129),
+ PINMUX_IPSR_GPSR(IP6_1_0, CAN_DEBUGOUT1),
+ PINMUX_IPSR_GPSR(IP6_1_0, MOUT1),
+ PINMUX_IPSR_GPSR(IP6_3_2, SSI_WS0129),
+ PINMUX_IPSR_GPSR(IP6_3_2, CAN_DEBUGOUT2),
+ PINMUX_IPSR_GPSR(IP6_3_2, MOUT2),
+ PINMUX_IPSR_GPSR(IP6_5_4, SSI_SDATA0),
+ PINMUX_IPSR_GPSR(IP6_5_4, CAN_DEBUGOUT3),
+ PINMUX_IPSR_GPSR(IP6_5_4, MOUT5),
+ PINMUX_IPSR_GPSR(IP6_7_6, SSI_SDATA1),
+ PINMUX_IPSR_GPSR(IP6_7_6, CAN_DEBUGOUT4),
+ PINMUX_IPSR_GPSR(IP6_7_6, MOUT6),
+ PINMUX_IPSR_GPSR(IP6_8, SSI_SDATA2),
+ PINMUX_IPSR_GPSR(IP6_8, CAN_DEBUGOUT5),
+ PINMUX_IPSR_GPSR(IP6_11_9, SSI_SCK34),
+ PINMUX_IPSR_GPSR(IP6_11_9, CAN_DEBUGOUT6),
+ PINMUX_IPSR_GPSR(IP6_11_9, CAN0_TX_B),
PINMUX_IPSR_MSEL(IP6_11_9, IERX, SEL_IE_0),
PINMUX_IPSR_MSEL(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
- PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
- PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
+ PINMUX_IPSR_GPSR(IP6_14_12, SSI_WS34),
+ PINMUX_IPSR_GPSR(IP6_14_12, CAN_DEBUGOUT7),
PINMUX_IPSR_MSEL(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
- PINMUX_IPSR_DATA(IP6_14_12, IETX),
+ PINMUX_IPSR_GPSR(IP6_14_12, IETX),
PINMUX_IPSR_MSEL(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
- PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
- PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
- PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
+ PINMUX_IPSR_GPSR(IP6_17_15, SSI_SDATA3),
+ PINMUX_IPSR_GPSR(IP6_17_15, PWM0_C),
+ PINMUX_IPSR_GPSR(IP6_17_15, CAN_DEBUGOUT8),
PINMUX_IPSR_MSEL(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
PINMUX_IPSR_MSEL(IP6_17_15, IECLK, SEL_IE_0),
PINMUX_IPSR_MSEL(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
PINMUX_IPSR_MSEL(IP6_17_15, TCLK0_B, SEL_TMU0_1),
- PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
- PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
+ PINMUX_IPSR_GPSR(IP6_19_18, SSI_SDATA4),
+ PINMUX_IPSR_GPSR(IP6_19_18, CAN_DEBUGOUT9),
PINMUX_IPSR_MSEL(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
- PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
- PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
- PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
+ PINMUX_IPSR_GPSR(IP6_22_20, SSI_SCK5),
+ PINMUX_IPSR_GPSR(IP6_22_20, ADICLK),
+ PINMUX_IPSR_GPSR(IP6_22_20, CAN_DEBUGOUT10),
PINMUX_IPSR_MSEL(IP6_22_20, SCK3, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP6_22_20, TCLK0_D, SEL_TMU0_3),
- PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
+ PINMUX_IPSR_GPSR(IP6_24_23, SSI_WS5),
PINMUX_IPSR_MSEL(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
- PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
- PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
- PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
+ PINMUX_IPSR_GPSR(IP6_24_23, CAN_DEBUGOUT11),
+ PINMUX_IPSR_GPSR(IP6_24_23, TX3_IRDA_TX),
+ PINMUX_IPSR_GPSR(IP6_26_25, SSI_SDATA5),
PINMUX_IPSR_MSEL(IP6_26_25, ADIDATA, SEL_ADI_0),
- PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
+ PINMUX_IPSR_GPSR(IP6_26_25, CAN_DEBUGOUT12),
PINMUX_IPSR_MSEL(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
- PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
- PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
- PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
+ PINMUX_IPSR_GPSR(IP6_30_29, SSI_SCK6),
+ PINMUX_IPSR_GPSR(IP6_30_29, ADICHS0),
+ PINMUX_IPSR_GPSR(IP6_30_29, CAN0_TX),
PINMUX_IPSR_MSEL(IP6_30_29, IERX_B, SEL_IE_1),
- PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
- PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
+ PINMUX_IPSR_GPSR(IP7_1_0, SSI_WS6),
+ PINMUX_IPSR_GPSR(IP7_1_0, ADICHS1),
PINMUX_IPSR_MSEL(IP7_1_0, CAN0_RX, SEL_CAN0_0),
- PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
- PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
- PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
+ PINMUX_IPSR_GPSR(IP7_1_0, IETX_B),
+ PINMUX_IPSR_GPSR(IP7_3_2, SSI_SDATA6),
+ PINMUX_IPSR_GPSR(IP7_3_2, ADICHS2),
PINMUX_IPSR_MSEL(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
PINMUX_IPSR_MSEL(IP7_3_2, IECLK_B, SEL_IE_1),
PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
- PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
+ PINMUX_IPSR_GPSR(IP7_6_4, CAN_DEBUGOUT13),
PINMUX_IPSR_MSEL(IP7_6_4, IRQ0_B, SEL_INT0_1),
PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS78, SEL_SSI7_0),
- PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
+ PINMUX_IPSR_GPSR(IP7_9_7, CAN_DEBUGOUT14),
PINMUX_IPSR_MSEL(IP7_9_7, IRQ1_B, SEL_INT1_1),
PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
PINMUX_IPSR_MSEL(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
- PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
+ PINMUX_IPSR_GPSR(IP7_12_10, CAN_DEBUGOUT15),
PINMUX_IPSR_MSEL(IP7_12_10, IRQ2_B, SEL_INT2_1),
PINMUX_IPSR_MSEL(IP7_12_10, TCLK1_C, SEL_TMU1_2),
- PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
+ PINMUX_IPSR_GPSR(IP7_12_10, HSPI_TX1_C),
PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
- PINMUX_IPSR_DATA(IP7_14_13, VSP),
+ PINMUX_IPSR_GPSR(IP7_14_13, VSP),
PINMUX_IPSR_MSEL(IP7_14_13, IRQ3_B, SEL_INT3_1),
PINMUX_IPSR_MSEL(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
- PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
- PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
+ PINMUX_IPSR_GPSR(IP7_16_15, SD0_CLK),
+ PINMUX_IPSR_GPSR(IP7_16_15, ATACS01),
PINMUX_IPSR_MSEL(IP7_16_15, SCK1_B, SEL_SCIF1_1),
- PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
- PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
- PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
- PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
- PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
- PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
+ PINMUX_IPSR_GPSR(IP7_18_17, SD0_CMD),
+ PINMUX_IPSR_GPSR(IP7_18_17, ATACS11),
+ PINMUX_IPSR_GPSR(IP7_18_17, TX1_B),
+ PINMUX_IPSR_GPSR(IP7_18_17, CC5_TDO),
+ PINMUX_IPSR_GPSR(IP7_20_19, SD0_DAT0),
+ PINMUX_IPSR_GPSR(IP7_20_19, ATADIR1),
PINMUX_IPSR_MSEL(IP7_20_19, RX1_B, SEL_SCIF1_1),
- PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
- PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
- PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
+ PINMUX_IPSR_GPSR(IP7_20_19, CC5_TRST),
+ PINMUX_IPSR_GPSR(IP7_22_21, SD0_DAT1),
+ PINMUX_IPSR_GPSR(IP7_22_21, ATAG1),
PINMUX_IPSR_MSEL(IP7_22_21, SCK2_B, SEL_SCIF2_1),
- PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
- PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
- PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
- PINMUX_IPSR_DATA(IP7_24_23, TX2_B),
- PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
- PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
- PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
+ PINMUX_IPSR_GPSR(IP7_22_21, CC5_TMS),
+ PINMUX_IPSR_GPSR(IP7_24_23, SD0_DAT2),
+ PINMUX_IPSR_GPSR(IP7_24_23, ATARD1),
+ PINMUX_IPSR_GPSR(IP7_24_23, TX2_B),
+ PINMUX_IPSR_GPSR(IP7_24_23, CC5_TCK),
+ PINMUX_IPSR_GPSR(IP7_26_25, SD0_DAT3),
+ PINMUX_IPSR_GPSR(IP7_26_25, ATAWR1),
PINMUX_IPSR_MSEL(IP7_26_25, RX2_B, SEL_SCIF2_1),
- PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
- PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
+ PINMUX_IPSR_GPSR(IP7_26_25, CC5_TDI),
+ PINMUX_IPSR_GPSR(IP7_28_27, SD0_CD),
PINMUX_IPSR_MSEL(IP7_28_27, DREQ2, SEL_EXBUS2_0),
PINMUX_IPSR_MSEL(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
- PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
- PINMUX_IPSR_DATA(IP7_30_29, DACK2),
+ PINMUX_IPSR_GPSR(IP7_30_29, SD0_WP),
+ PINMUX_IPSR_GPSR(IP7_30_29, DACK2),
PINMUX_IPSR_MSEL(IP7_30_29, CTS1_B, SEL_SCIF1_1),
- PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
+ PINMUX_IPSR_GPSR(IP8_3_0, HSPI_CLK0),
PINMUX_IPSR_MSEL(IP8_3_0, CTS0, SEL_SCIF0_0),
- PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
- PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
- PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
- PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12),
- PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20),
- PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
- PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
- PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
+ PINMUX_IPSR_GPSR(IP8_3_0, USB_OVC0),
+ PINMUX_IPSR_GPSR(IP8_3_0, AD_CLK),
+ PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE4),
+ PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE12),
+ PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE20),
+ PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE28),
+ PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE36),
+ PINMUX_IPSR_GPSR(IP8_7_4, HSPI_CS0),
PINMUX_IPSR_MSEL(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
- PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
- PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
- PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
- PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13),
- PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21),
- PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29),
- PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37),
- PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0),
- PINMUX_IPSR_DATA(IP8_11_8, TX0),
- PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
- PINMUX_IPSR_DATA(IP8_11_8, AD_DO),
- PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6),
- PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14),
- PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22),
- PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
- PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
- PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
+ PINMUX_IPSR_GPSR(IP8_7_4, USB_OVC1),
+ PINMUX_IPSR_GPSR(IP8_7_4, AD_DI),
+ PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE5),
+ PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE13),
+ PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE21),
+ PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE29),
+ PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE37),
+ PINMUX_IPSR_GPSR(IP8_11_8, HSPI_TX0),
+ PINMUX_IPSR_GPSR(IP8_11_8, TX0),
+ PINMUX_IPSR_GPSR(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
+ PINMUX_IPSR_GPSR(IP8_11_8, AD_DO),
+ PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE6),
+ PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE14),
+ PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE22),
+ PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE30),
+ PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE38),
+ PINMUX_IPSR_GPSR(IP8_15_12, HSPI_RX0),
PINMUX_IPSR_MSEL(IP8_15_12, RX0, SEL_SCIF0_0),
- PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
- PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
- PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
- PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15),
- PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23),
- PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31),
- PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39),
- PINMUX_IPSR_DATA(IP8_17_16, FMCLK),
- PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK),
- PINMUX_IPSR_DATA(IP8_17_16, PCMOE),
- PINMUX_IPSR_DATA(IP8_18, BPFCLK),
- PINMUX_IPSR_DATA(IP8_18, PCMWE),
- PINMUX_IPSR_DATA(IP8_19, FMIN),
- PINMUX_IPSR_DATA(IP8_19, RDS_DATA),
- PINMUX_IPSR_DATA(IP8_20, VI0_CLK),
- PINMUX_IPSR_DATA(IP8_20, MMC1_CLK),
- PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB),
- PINMUX_IPSR_DATA(IP8_22_21, TX1_C),
- PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
- PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
- PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
+ PINMUX_IPSR_GPSR(IP8_15_12, CAN_STEP0),
+ PINMUX_IPSR_GPSR(IP8_15_12, AD_NCS),
+ PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE7),
+ PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE15),
+ PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE23),
+ PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE31),
+ PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE39),
+ PINMUX_IPSR_GPSR(IP8_17_16, FMCLK),
+ PINMUX_IPSR_GPSR(IP8_17_16, RDS_CLK),
+ PINMUX_IPSR_GPSR(IP8_17_16, PCMOE),
+ PINMUX_IPSR_GPSR(IP8_18, BPFCLK),
+ PINMUX_IPSR_GPSR(IP8_18, PCMWE),
+ PINMUX_IPSR_GPSR(IP8_19, FMIN),
+ PINMUX_IPSR_GPSR(IP8_19, RDS_DATA),
+ PINMUX_IPSR_GPSR(IP8_20, VI0_CLK),
+ PINMUX_IPSR_GPSR(IP8_20, MMC1_CLK),
+ PINMUX_IPSR_GPSR(IP8_22_21, VI0_CLKENB),
+ PINMUX_IPSR_GPSR(IP8_22_21, TX1_C),
+ PINMUX_IPSR_GPSR(IP8_22_21, HTX1_B),
+ PINMUX_IPSR_GPSR(IP8_22_21, MT1_SYNC),
+ PINMUX_IPSR_GPSR(IP8_24_23, VI0_FIELD),
PINMUX_IPSR_MSEL(IP8_24_23, RX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
- PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
+ PINMUX_IPSR_GPSR(IP8_27_25, VI0_HSYNC),
PINMUX_IPSR_MSEL(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP8_27_25, CTS1_C, SEL_SCIF1_2),
- PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
- PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
+ PINMUX_IPSR_GPSR(IP8_27_25, TX4_D),
+ PINMUX_IPSR_GPSR(IP8_27_25, MMC1_CMD),
PINMUX_IPSR_MSEL(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
- PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
+ PINMUX_IPSR_GPSR(IP8_30_28, VI0_VSYNC),
PINMUX_IPSR_MSEL(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP8_30_28, RX4_D, SEL_SCIF4_3),
PINMUX_IPSR_MSEL(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
- PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
+ PINMUX_IPSR_GPSR(IP9_1_0, MT1_VCXO),
PINMUX_IPSR_MSEL(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
- PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
- PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
- PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
- PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3),
- PINMUX_IPSR_DATA(IP9_5, MMC1_D1),
- PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4),
- PINMUX_IPSR_DATA(IP9_6, MMC1_D2),
- PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5),
- PINMUX_IPSR_DATA(IP9_7, MMC1_D3),
- PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6),
- PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4),
- PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0),
- PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7),
- PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
- PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
- PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
+ PINMUX_IPSR_GPSR(IP9_3_2, MT1_PWM),
+ PINMUX_IPSR_GPSR(IP9_4, VI0_DATA2_VI0_B2),
+ PINMUX_IPSR_GPSR(IP9_4, MMC1_D0),
+ PINMUX_IPSR_GPSR(IP9_5, VI0_DATA3_VI0_B3),
+ PINMUX_IPSR_GPSR(IP9_5, MMC1_D1),
+ PINMUX_IPSR_GPSR(IP9_6, VI0_DATA4_VI0_B4),
+ PINMUX_IPSR_GPSR(IP9_6, MMC1_D2),
+ PINMUX_IPSR_GPSR(IP9_7, VI0_DATA5_VI0_B5),
+ PINMUX_IPSR_GPSR(IP9_7, MMC1_D3),
+ PINMUX_IPSR_GPSR(IP9_9_8, VI0_DATA6_VI0_B6),
+ PINMUX_IPSR_GPSR(IP9_9_8, MMC1_D4),
+ PINMUX_IPSR_GPSR(IP9_9_8, ARM_TRACEDATA_0),
+ PINMUX_IPSR_GPSR(IP9_11_10, VI0_DATA7_VI0_B7),
+ PINMUX_IPSR_GPSR(IP9_11_10, MMC1_D5),
+ PINMUX_IPSR_GPSR(IP9_11_10, ARM_TRACEDATA_1),
+ PINMUX_IPSR_GPSR(IP9_13_12, VI0_G0),
PINMUX_IPSR_MSEL(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
PINMUX_IPSR_MSEL(IP9_13_12, IRQ0, SEL_INT0_0),
- PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
- PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
+ PINMUX_IPSR_GPSR(IP9_13_12, ARM_TRACEDATA_2),
+ PINMUX_IPSR_GPSR(IP9_15_14, VI0_G1),
PINMUX_IPSR_MSEL(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
PINMUX_IPSR_MSEL(IP9_15_14, IRQ1, SEL_INT1_0),
- PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
- PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
- PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
- PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6),
- PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4),
- PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0),
- PINMUX_IPSR_DATA(IP9_21_19, VI0_G3),
- PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV),
- PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7),
- PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5),
- PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
- PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
- PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
+ PINMUX_IPSR_GPSR(IP9_15_14, ARM_TRACEDATA_3),
+ PINMUX_IPSR_GPSR(IP9_18_16, VI0_G2),
+ PINMUX_IPSR_GPSR(IP9_18_16, ETH_TXD1),
+ PINMUX_IPSR_GPSR(IP9_18_16, MMC1_D6),
+ PINMUX_IPSR_GPSR(IP9_18_16, ARM_TRACEDATA_4),
+ PINMUX_IPSR_GPSR(IP9_18_16, TS_SPSYNC0),
+ PINMUX_IPSR_GPSR(IP9_21_19, VI0_G3),
+ PINMUX_IPSR_GPSR(IP9_21_19, ETH_CRS_DV),
+ PINMUX_IPSR_GPSR(IP9_21_19, MMC1_D7),
+ PINMUX_IPSR_GPSR(IP9_21_19, ARM_TRACEDATA_5),
+ PINMUX_IPSR_GPSR(IP9_21_19, TS_SDAT0),
+ PINMUX_IPSR_GPSR(IP9_23_22, VI0_G4),
+ PINMUX_IPSR_GPSR(IP9_23_22, ETH_TX_EN),
PINMUX_IPSR_MSEL(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
- PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
- PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
- PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
+ PINMUX_IPSR_GPSR(IP9_23_22, ARM_TRACEDATA_6),
+ PINMUX_IPSR_GPSR(IP9_25_24, VI0_G5),
+ PINMUX_IPSR_GPSR(IP9_25_24, ETH_RX_ER),
PINMUX_IPSR_MSEL(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
- PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
- PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
- PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
+ PINMUX_IPSR_GPSR(IP9_25_24, ARM_TRACEDATA_7),
+ PINMUX_IPSR_GPSR(IP9_27_26, VI0_G6),
+ PINMUX_IPSR_GPSR(IP9_27_26, ETH_RXD0),
PINMUX_IPSR_MSEL(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
- PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
- PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
- PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
+ PINMUX_IPSR_GPSR(IP9_27_26, ARM_TRACEDATA_8),
+ PINMUX_IPSR_GPSR(IP9_29_28, VI0_G7),
+ PINMUX_IPSR_GPSR(IP9_29_28, ETH_RXD1),
PINMUX_IPSR_MSEL(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
- PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
+ PINMUX_IPSR_GPSR(IP9_29_28, ARM_TRACEDATA_9),
- PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
+ PINMUX_IPSR_GPSR(IP10_2_0, VI0_R0),
PINMUX_IPSR_MSEL(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
PINMUX_IPSR_MSEL(IP10_2_0, SCK1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
- PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
+ PINMUX_IPSR_GPSR(IP10_2_0, ARM_TRACEDATA_10),
PINMUX_IPSR_MSEL(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
- PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
+ PINMUX_IPSR_GPSR(IP10_5_3, VI0_R1),
PINMUX_IPSR_MSEL(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
- PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
- PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
- PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
- PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C),
- PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
- PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
- PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
+ PINMUX_IPSR_GPSR(IP10_5_3, DACK1_B),
+ PINMUX_IPSR_GPSR(IP10_5_3, ARM_TRACEDATA_11),
+ PINMUX_IPSR_GPSR(IP10_5_3, DACK0_C),
+ PINMUX_IPSR_GPSR(IP10_5_3, DRACK0_C),
+ PINMUX_IPSR_GPSR(IP10_8_6, VI0_R2),
+ PINMUX_IPSR_GPSR(IP10_8_6, ETH_LINK),
+ PINMUX_IPSR_GPSR(IP10_8_6, SD2_CLK_B),
PINMUX_IPSR_MSEL(IP10_8_6, IRQ2, SEL_INT2_0),
- PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
- PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
- PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
+ PINMUX_IPSR_GPSR(IP10_8_6, ARM_TRACEDATA_12),
+ PINMUX_IPSR_GPSR(IP10_11_9, VI0_R3),
+ PINMUX_IPSR_GPSR(IP10_11_9, ETH_MAGIC),
PINMUX_IPSR_MSEL(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
PINMUX_IPSR_MSEL(IP10_11_9, IRQ3, SEL_INT3_0),
- PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
- PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
- PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
+ PINMUX_IPSR_GPSR(IP10_11_9, ARM_TRACEDATA_13),
+ PINMUX_IPSR_GPSR(IP10_14_12, VI0_R4),
+ PINMUX_IPSR_GPSR(IP10_14_12, ETH_REFCLK),
PINMUX_IPSR_MSEL(IP10_14_12, SD2_CD_B, SEL_SD2_1),
PINMUX_IPSR_MSEL(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
- PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
- PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
- PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
- PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
- PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
+ PINMUX_IPSR_GPSR(IP10_14_12, ARM_TRACEDATA_14),
+ PINMUX_IPSR_GPSR(IP10_14_12, MT1_CLK),
+ PINMUX_IPSR_GPSR(IP10_14_12, TS_SCK0),
+ PINMUX_IPSR_GPSR(IP10_17_15, VI0_R5),
+ PINMUX_IPSR_GPSR(IP10_17_15, ETH_TXD0),
PINMUX_IPSR_MSEL(IP10_17_15, SD2_WP_B, SEL_SD2_1),
PINMUX_IPSR_MSEL(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
- PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
- PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
- PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
- PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
- PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
+ PINMUX_IPSR_GPSR(IP10_17_15, ARM_TRACEDATA_15),
+ PINMUX_IPSR_GPSR(IP10_17_15, MT1_D),
+ PINMUX_IPSR_GPSR(IP10_17_15, TS_SDEN0),
+ PINMUX_IPSR_GPSR(IP10_20_18, VI0_R6),
+ PINMUX_IPSR_GPSR(IP10_20_18, ETH_MDC),
PINMUX_IPSR_MSEL(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
- PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
- PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
- PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
+ PINMUX_IPSR_GPSR(IP10_20_18, HSPI_TX1_B),
+ PINMUX_IPSR_GPSR(IP10_20_18, TRACECLK),
+ PINMUX_IPSR_GPSR(IP10_20_18, MT1_BEN),
PINMUX_IPSR_MSEL(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
- PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
- PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
- PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
+ PINMUX_IPSR_GPSR(IP10_23_21, VI0_R7),
+ PINMUX_IPSR_GPSR(IP10_23_21, ETH_MDIO),
+ PINMUX_IPSR_GPSR(IP10_23_21, DACK2_C),
PINMUX_IPSR_MSEL(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
PINMUX_IPSR_MSEL(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
- PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
- PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
- PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
+ PINMUX_IPSR_GPSR(IP10_23_21, TRACECTL),
+ PINMUX_IPSR_GPSR(IP10_23_21, MT1_PEN),
+ PINMUX_IPSR_GPSR(IP10_25_24, VI1_CLK),
PINMUX_IPSR_MSEL(IP10_25_24, SIM_D, SEL_SIM_0),
PINMUX_IPSR_MSEL(IP10_25_24, SDA3, SEL_I2C3_0),
- PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
- PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
- PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
+ PINMUX_IPSR_GPSR(IP10_28_26, VI1_HSYNC),
+ PINMUX_IPSR_GPSR(IP10_28_26, VI3_CLK),
+ PINMUX_IPSR_GPSR(IP10_28_26, SSI_SCK4),
PINMUX_IPSR_MSEL(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
PINMUX_IPSR_MSEL(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
- PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
- PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
- PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
- PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
+ PINMUX_IPSR_GPSR(IP10_31_29, VI1_VSYNC),
+ PINMUX_IPSR_GPSR(IP10_31_29, AUDIO_CLKOUT_C),
+ PINMUX_IPSR_GPSR(IP10_31_29, SSI_WS4),
+ PINMUX_IPSR_GPSR(IP10_31_29, SIM_CLK),
PINMUX_IPSR_MSEL(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
- PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
+ PINMUX_IPSR_GPSR(IP10_31_29, SPV_TRST),
PINMUX_IPSR_MSEL(IP10_31_29, SCL3, SEL_I2C3_0),
- PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
+ PINMUX_IPSR_GPSR(IP11_2_0, VI1_DATA0_VI1_B0),
PINMUX_IPSR_MSEL(IP11_2_0, SD2_DAT0, SEL_SD2_0),
- PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
- PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
- PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
- PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
+ PINMUX_IPSR_GPSR(IP11_2_0, SIM_RST),
+ PINMUX_IPSR_GPSR(IP11_2_0, SPV_TCK),
+ PINMUX_IPSR_GPSR(IP11_2_0, ADICLK_B),
+ PINMUX_IPSR_GPSR(IP11_5_3, VI1_DATA1_VI1_B1),
PINMUX_IPSR_MSEL(IP11_5_3, SD2_DAT1, SEL_SD2_0),
- PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
- PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
+ PINMUX_IPSR_GPSR(IP11_5_3, MT0_CLK),
+ PINMUX_IPSR_GPSR(IP11_5_3, SPV_TMS),
PINMUX_IPSR_MSEL(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
- PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
+ PINMUX_IPSR_GPSR(IP11_8_6, VI1_DATA2_VI1_B2),
PINMUX_IPSR_MSEL(IP11_8_6, SD2_DAT2, SEL_SD2_0),
- PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
- PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
+ PINMUX_IPSR_GPSR(IP11_8_6, MT0_D),
+ PINMUX_IPSR_GPSR(IP11_8_6, SPVTDI),
PINMUX_IPSR_MSEL(IP11_8_6, ADIDATA_B, SEL_ADI_1),
- PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
+ PINMUX_IPSR_GPSR(IP11_11_9, VI1_DATA3_VI1_B3),
PINMUX_IPSR_MSEL(IP11_11_9, SD2_DAT3, SEL_SD2_0),
- PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
- PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
- PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
- PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4),
- PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
- PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
- PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
+ PINMUX_IPSR_GPSR(IP11_11_9, MT0_BEN),
+ PINMUX_IPSR_GPSR(IP11_11_9, SPV_TDO),
+ PINMUX_IPSR_GPSR(IP11_11_9, ADICHS0_B),
+ PINMUX_IPSR_GPSR(IP11_14_12, VI1_DATA4_VI1_B4),
+ PINMUX_IPSR_GPSR(IP11_14_12, SD2_CLK),
+ PINMUX_IPSR_GPSR(IP11_14_12, MT0_PEN),
+ PINMUX_IPSR_GPSR(IP11_14_12, SPA_TRST),
PINMUX_IPSR_MSEL(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
- PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
- PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
+ PINMUX_IPSR_GPSR(IP11_14_12, ADICHS1_B),
+ PINMUX_IPSR_GPSR(IP11_17_15, VI1_DATA5_VI1_B5),
PINMUX_IPSR_MSEL(IP11_17_15, SD2_CMD, SEL_SD2_0),
- PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
- PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
+ PINMUX_IPSR_GPSR(IP11_17_15, MT0_SYNC),
+ PINMUX_IPSR_GPSR(IP11_17_15, SPA_TCK),
PINMUX_IPSR_MSEL(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
- PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
- PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
+ PINMUX_IPSR_GPSR(IP11_17_15, ADICHS2_B),
+ PINMUX_IPSR_GPSR(IP11_20_18, VI1_DATA6_VI1_B6),
PINMUX_IPSR_MSEL(IP11_20_18, SD2_CD, SEL_SD2_0),
- PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
- PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
- PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
- PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
+ PINMUX_IPSR_GPSR(IP11_20_18, MT0_VCXO),
+ PINMUX_IPSR_GPSR(IP11_20_18, SPA_TMS),
+ PINMUX_IPSR_GPSR(IP11_20_18, HSPI_TX1_D),
+ PINMUX_IPSR_GPSR(IP11_23_21, VI1_DATA7_VI1_B7),
PINMUX_IPSR_MSEL(IP11_23_21, SD2_WP, SEL_SD2_0),
- PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
- PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
+ PINMUX_IPSR_GPSR(IP11_23_21, MT0_PWM),
+ PINMUX_IPSR_GPSR(IP11_23_21, SPA_TDI),
PINMUX_IPSR_MSEL(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
- PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
- PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
- PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
+ PINMUX_IPSR_GPSR(IP11_26_24, VI1_G0),
+ PINMUX_IPSR_GPSR(IP11_26_24, VI3_DATA0),
+ PINMUX_IPSR_GPSR(IP11_26_24, TS_SCK1),
PINMUX_IPSR_MSEL(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
- PINMUX_IPSR_DATA(IP11_26_24, TX2),
- PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
+ PINMUX_IPSR_GPSR(IP11_26_24, TX2),
+ PINMUX_IPSR_GPSR(IP11_26_24, SPA_TDO),
PINMUX_IPSR_MSEL(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
- PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
- PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
- PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
- PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
- PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
+ PINMUX_IPSR_GPSR(IP11_29_27, VI1_G1),
+ PINMUX_IPSR_GPSR(IP11_29_27, VI3_DATA1),
+ PINMUX_IPSR_GPSR(IP11_29_27, SSI_SCK1),
+ PINMUX_IPSR_GPSR(IP11_29_27, TS_SDEN1),
+ PINMUX_IPSR_GPSR(IP11_29_27, DACK2_B),
PINMUX_IPSR_MSEL(IP11_29_27, RX2, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
- PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
- PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
- PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
- PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
+ PINMUX_IPSR_GPSR(IP12_2_0, VI1_G2),
+ PINMUX_IPSR_GPSR(IP12_2_0, VI3_DATA2),
+ PINMUX_IPSR_GPSR(IP12_2_0, SSI_WS1),
+ PINMUX_IPSR_GPSR(IP12_2_0, TS_SPSYNC1),
PINMUX_IPSR_MSEL(IP12_2_0, SCK2, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
- PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
- PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
- PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
- PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
+ PINMUX_IPSR_GPSR(IP12_5_3, VI1_G3),
+ PINMUX_IPSR_GPSR(IP12_5_3, VI3_DATA3),
+ PINMUX_IPSR_GPSR(IP12_5_3, SSI_SCK2),
+ PINMUX_IPSR_GPSR(IP12_5_3, TS_SDAT1),
PINMUX_IPSR_MSEL(IP12_5_3, SCL1_C, SEL_I2C1_2),
- PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
- PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
- PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
- PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
+ PINMUX_IPSR_GPSR(IP12_5_3, HTX0_B),
+ PINMUX_IPSR_GPSR(IP12_8_6, VI1_G4),
+ PINMUX_IPSR_GPSR(IP12_8_6, VI3_DATA4),
+ PINMUX_IPSR_GPSR(IP12_8_6, SSI_WS2),
PINMUX_IPSR_MSEL(IP12_8_6, SDA1_C, SEL_I2C1_2),
- PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
+ PINMUX_IPSR_GPSR(IP12_8_6, SIM_RST_B),
PINMUX_IPSR_MSEL(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
- PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
- PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
+ PINMUX_IPSR_GPSR(IP12_11_9, VI1_G5),
+ PINMUX_IPSR_GPSR(IP12_11_9, VI3_DATA5),
PINMUX_IPSR_MSEL(IP12_11_9, GPS_CLK, SEL_GPS_0),
- PINMUX_IPSR_DATA(IP12_11_9, FSE),
- PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
+ PINMUX_IPSR_GPSR(IP12_11_9, FSE),
+ PINMUX_IPSR_GPSR(IP12_11_9, TX4_B),
PINMUX_IPSR_MSEL(IP12_11_9, SIM_D_B, SEL_SIM_1),
- PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
- PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
+ PINMUX_IPSR_GPSR(IP12_14_12, VI1_G6),
+ PINMUX_IPSR_GPSR(IP12_14_12, VI3_DATA6),
PINMUX_IPSR_MSEL(IP12_14_12, GPS_SIGN, SEL_GPS_0),
- PINMUX_IPSR_DATA(IP12_14_12, FRB),
+ PINMUX_IPSR_GPSR(IP12_14_12, FRB),
PINMUX_IPSR_MSEL(IP12_14_12, RX4_B, SEL_SCIF4_1),
- PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
- PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
- PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
+ PINMUX_IPSR_GPSR(IP12_14_12, SIM_CLK_B),
+ PINMUX_IPSR_GPSR(IP12_17_15, VI1_G7),
+ PINMUX_IPSR_GPSR(IP12_17_15, VI3_DATA7),
PINMUX_IPSR_MSEL(IP12_17_15, GPS_MAG, SEL_GPS_0),
- PINMUX_IPSR_DATA(IP12_17_15, FCE),
+ PINMUX_IPSR_GPSR(IP12_17_15, FCE),
PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1),
};
PINMUX_SINGLE(DU_DOTCLKIN0),
PINMUX_SINGLE(DU_DOTCLKIN2),
- PINMUX_IPSR_DATA(IP0_2_0, D0),
+ PINMUX_IPSR_GPSR(IP0_2_0, D0),
PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
- PINMUX_IPSR_DATA(IP0_5_3, D1),
+ PINMUX_IPSR_GPSR(IP0_5_3, D1),
PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
- PINMUX_IPSR_DATA(IP0_8_6, D2),
+ PINMUX_IPSR_GPSR(IP0_8_6, D2),
PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
- PINMUX_IPSR_DATA(IP0_11_9, D3),
+ PINMUX_IPSR_GPSR(IP0_11_9, D3),
PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
- PINMUX_IPSR_DATA(IP0_15_12, D4),
+ PINMUX_IPSR_GPSR(IP0_15_12, D4),
PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
- PINMUX_IPSR_DATA(IP0_19_16, D5),
+ PINMUX_IPSR_GPSR(IP0_19_16, D5),
PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
- PINMUX_IPSR_DATA(IP0_22_20, D6),
+ PINMUX_IPSR_GPSR(IP0_22_20, D6),
PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
- PINMUX_IPSR_DATA(IP0_26_23, D7),
+ PINMUX_IPSR_GPSR(IP0_26_23, D7),
PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
- PINMUX_IPSR_DATA(IP0_30_27, D8),
+ PINMUX_IPSR_GPSR(IP0_30_27, D8),
PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
- PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
+ PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
- PINMUX_IPSR_DATA(IP1_3_0, D9),
+ PINMUX_IPSR_GPSR(IP1_3_0, D9),
PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
- PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
+ PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
- PINMUX_IPSR_DATA(IP1_7_4, D10),
+ PINMUX_IPSR_GPSR(IP1_7_4, D10),
PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
- PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
+ PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
- PINMUX_IPSR_DATA(IP1_11_8, D11),
+ PINMUX_IPSR_GPSR(IP1_11_8, D11),
PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
- PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
+ PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
- PINMUX_IPSR_DATA(IP1_14_12, D12),
+ PINMUX_IPSR_GPSR(IP1_14_12, D12),
PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
- PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
+ PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
- PINMUX_IPSR_DATA(IP1_17_15, D13),
- PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5),
+ PINMUX_IPSR_GPSR(IP1_17_15, D13),
+ PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
- PINMUX_IPSR_DATA(IP1_21_18, D14),
+ PINMUX_IPSR_GPSR(IP1_21_18, D14),
PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
- PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
+ PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
- PINMUX_IPSR_DATA(IP1_25_22, D15),
+ PINMUX_IPSR_GPSR(IP1_25_22, D15),
PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
- PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
+ PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
- PINMUX_IPSR_DATA(IP1_27_26, A0),
- PINMUX_IPSR_DATA(IP1_27_26, PWM3),
- PINMUX_IPSR_DATA(IP1_29_28, A1),
- PINMUX_IPSR_DATA(IP1_29_28, PWM4),
+ PINMUX_IPSR_GPSR(IP1_27_26, A0),
+ PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
+ PINMUX_IPSR_GPSR(IP1_29_28, A1),
+ PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
- PINMUX_IPSR_DATA(IP2_2_0, A2),
- PINMUX_IPSR_DATA(IP2_2_0, PWM5),
+ PINMUX_IPSR_GPSR(IP2_2_0, A2),
+ PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
- PINMUX_IPSR_DATA(IP2_5_3, A3),
- PINMUX_IPSR_DATA(IP2_5_3, PWM6),
+ PINMUX_IPSR_GPSR(IP2_5_3, A3),
+ PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
- PINMUX_IPSR_DATA(IP2_8_6, A4),
+ PINMUX_IPSR_GPSR(IP2_8_6, A4),
PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
- PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
- PINMUX_IPSR_DATA(IP2_11_9, A5),
+ PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
+ PINMUX_IPSR_GPSR(IP2_11_9, A5),
PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
- PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
- PINMUX_IPSR_DATA(IP2_14_12, A6),
+ PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
+ PINMUX_IPSR_GPSR(IP2_14_12, A6),
PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
- PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
- PINMUX_IPSR_DATA(IP2_17_15, A7),
+ PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
+ PINMUX_IPSR_GPSR(IP2_17_15, A7),
PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
- PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
- PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
- PINMUX_IPSR_DATA(IP2_21_18, A8),
+ PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
+ PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
+ PINMUX_IPSR_GPSR(IP2_21_18, A8),
PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP2_25_22, A9),
+ PINMUX_IPSR_GPSR(IP2_25_22, A9),
PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP2_28_26, A10),
+ PINMUX_IPSR_GPSR(IP2_28_26, A10),
PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
- PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
+ PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP3_3_0, A11),
+ PINMUX_IPSR_GPSR(IP3_3_0, A11),
PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
- PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
+ PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
+ PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP3_7_4, A12),
+ PINMUX_IPSR_GPSR(IP3_7_4, A12),
PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
- PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
+ PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
+ PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP3_11_8, A13),
+ PINMUX_IPSR_GPSR(IP3_11_8, A13),
PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
- PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
- PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
+ PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
+ PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
+ PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP3_14_12, A14),
+ PINMUX_IPSR_GPSR(IP3_14_12, A14),
PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
- PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
- PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
- PINMUX_IPSR_DATA(IP3_17_15, A15),
+ PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
+ PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
+ PINMUX_IPSR_GPSR(IP3_17_15, A15),
PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
- PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
- PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
- PINMUX_IPSR_DATA(IP3_19_18, A16),
- PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
- PINMUX_IPSR_DATA(IP3_22_20, A17),
+ PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
+ PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
+ PINMUX_IPSR_GPSR(IP3_19_18, A16),
+ PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
+ PINMUX_IPSR_GPSR(IP3_22_20, A17),
PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
- PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
- PINMUX_IPSR_DATA(IP3_25_23, A18),
+ PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
+ PINMUX_IPSR_GPSR(IP3_25_23, A18),
PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
- PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
- PINMUX_IPSR_DATA(IP3_28_26, A19),
+ PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
+ PINMUX_IPSR_GPSR(IP3_28_26, A19),
PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
- PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
+ PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
- PINMUX_IPSR_DATA(IP3_31_29, A20),
- PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
+ PINMUX_IPSR_GPSR(IP3_31_29, A20),
+ PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
+ PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
- PINMUX_IPSR_DATA(IP4_2_0, A21),
- PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
+ PINMUX_IPSR_GPSR(IP4_2_0, A21),
+ PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
- PINMUX_IPSR_DATA(IP4_5_3, A22),
- PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
+ PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
+ PINMUX_IPSR_GPSR(IP4_5_3, A22),
+ PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
- PINMUX_IPSR_DATA(IP4_8_6, A23),
- PINMUX_IPSR_DATA(IP4_8_6, IO2),
+ PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
+ PINMUX_IPSR_GPSR(IP4_8_6, A23),
+ PINMUX_IPSR_GPSR(IP4_8_6, IO2),
PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
- PINMUX_IPSR_DATA(IP4_11_9, A24),
- PINMUX_IPSR_DATA(IP4_11_9, IO3),
+ PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
+ PINMUX_IPSR_GPSR(IP4_11_9, A24),
+ PINMUX_IPSR_GPSR(IP4_11_9, IO3),
PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP4_14_12, A25),
- PINMUX_IPSR_DATA(IP4_14_12, SSL),
+ PINMUX_IPSR_GPSR(IP4_14_12, A25),
+ PINMUX_IPSR_GPSR(IP4_14_12, SSL),
PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
+ PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
+ PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
- PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
+ PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
+ PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
+ PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
+ PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
- PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
+ PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
+ PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
- PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
- PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
+ PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
+ PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
+ PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
- PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
+ PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
+ PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
- PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
- PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
- PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
+ PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
+ PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
+ PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
- PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N),
+ PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
+ PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
- PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
+ PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
- PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
+ PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
- PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
+ PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
- PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
+ PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
- PINMUX_IPSR_DATA(IP5_12_10, BS_N),
+ PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
- PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
+ PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP5_14_13, RD_N),
+ PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
- PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
+ PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
+ PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
- PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
- PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
+ PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
+ PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
+ PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
+ PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
- PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
- PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
+ PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
+ PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
+ PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
+ PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
- PINMUX_IPSR_DATA(IP6_2_0, DACK0),
- PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
- PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
+ PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
+ PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
+ PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
- PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
+ PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
- PINMUX_IPSR_DATA(IP6_8_6, DACK1),
- PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
- PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
+ PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
+ PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
+ PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
- PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
+ PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP6_13_11, DACK2),
- PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
- PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
+ PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
+ PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
+ PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
+ PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
- PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
+ PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
- PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
+ PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
- PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
+ PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
- PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
+ PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
- PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
+ PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
- PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
+ PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
- PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
+ PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
- PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
+ PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
- PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
+ PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
- PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
+ PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
- PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
+ PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
- PINMUX_IPSR_DATA(IP7_18_16, PWM0),
+ PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
- PINMUX_IPSR_DATA(IP7_21_19, PWM1),
+ PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
- PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
- PINMUX_IPSR_DATA(IP7_24_22, PWM2),
- PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
+ PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
+ PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
+ PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
- PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
+ PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1),
- PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
- PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
+ PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
+ PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
+ PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
- PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
+ PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
+ PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
- PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
+ PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
+ PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
- PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
+ PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
+ PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
- PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
+ PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
+ PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
- PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
+ PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
+ PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
- PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
+ PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
+ PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
- PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
+ PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
+ PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
+ PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
+ PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
+ PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
- PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
+ PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
- PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
+ PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
- PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
+ PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
- PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
+ PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
- PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
+ PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT),
+ PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
- PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
+ PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
+ PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
+ PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
+ PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
+ PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
+ PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
+ PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
- PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
+ PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
+ PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
- PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
+ PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
- PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
+ PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
+ PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
- PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
+ PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
- PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
- PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
- PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
+ PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
+ PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
+ PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
+ PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
- PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
- PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
+ PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
+ PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
- PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
- PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
+ PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
+ PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
- PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
- PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
+ PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
+ PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
- PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
- PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
+ PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
+ PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
- PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
- PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
+ PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
+ PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
- PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
+ PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
- PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
+ PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
+ PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
- PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
+ PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
- PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
- PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
+ PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
+ PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
- PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
+ PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
+ PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
- PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
+ PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
+ PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
- PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
+ PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
+ PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
- PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
+ PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
+ PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
- PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
+ PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
+ PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
- PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
+ PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
+ PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
- PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
+ PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
- PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
+ PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
+ PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
- PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
+ PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
- PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
- PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
- PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
- PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
- PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
- PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
- PINMUX_IPSR_DATA(IP11_8_7, STM_N),
- PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
- PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
- PINMUX_IPSR_DATA(IP11_10_9, MDATA),
- PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
- PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
- PINMUX_IPSR_DATA(IP11_12_11, SDATA),
- PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
- PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
- PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
- PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
- PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
+ PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
+ PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
+ PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
+ PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
+ PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
+ PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
+ PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
+ PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
+ PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
+ PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
+ PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
+ PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
+ PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
+ PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
+ PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
+ PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
+ PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
+ PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
+ PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
- PINMUX_IPSR_DATA(IP11_17_15, VSP),
+ PINMUX_IPSR_GPSR(IP11_17_15, VSP),
PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
- PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
- PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
+ PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
+ PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
- PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
+ PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
- PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
+ PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
- PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
+ PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
- PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
+ PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
- PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
+ PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
- PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
+ PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
- PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
- PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
+ PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
+ PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
- PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
- PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
+ PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
+ PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
- PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
- PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
+ PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
+ PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
- PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1),
- PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
- PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
- PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
+ PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
+ PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
+ PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
+ PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
- PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
- PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
+ PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
+ PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
- PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
- PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
- PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
+ PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
+ PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
+ PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
- PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
- PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
+ PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
+ PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
- PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
- PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
+ PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
+ PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
- PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
- PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
+ PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
+ PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
- PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
+ PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
- PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
- PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
+ PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
+ PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
+ PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
- PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
- PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
+ PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
+ PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
+ PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
- PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
- PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
+ PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
+ PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
+ PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
- PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
- PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
- PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
+ PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
+ PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
+ PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
- PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
- PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
- PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
+ PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
+ PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
+ PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
- PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
- PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
- PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
+ PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
+ PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
+ PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
- PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
- PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
- PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
+ PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
+ PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
+ PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
- PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
- PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
- PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
- PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
+ PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
+ PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
+ PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
+ PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
- PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
- PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
- PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
- PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
+ PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
+ PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
+ PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
+ PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
- PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
+ PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
- PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
+ PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
- PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
+ PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
- PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
- PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
+ PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
+ PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
- PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
+ PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
- PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
+ PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
- PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
+ PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
- PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
- PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
+ PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
+ PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
- PINMUX_IPSR_DATA(IP14_5_3, SCK0),
- PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
- PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
- PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
+ PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
+ PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
+ PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
+ PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
- PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
- PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
+ PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
+ PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
- PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
- PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
+ PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
+ PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
- PINMUX_IPSR_DATA(IP14_15_12, CTS0_N),
+ PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
- PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
- PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11),
- PINMUX_IPSR_DATA(IP14_15_12, PWM0_B),
+ PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
+ PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
+ PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
- PINMUX_IPSR_DATA(IP14_18_16, RTS0_N),
- PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
- PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
- PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
- PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
+ PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
+ PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
+ PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
+ PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
+ PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
- PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
- PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
+ PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
- PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
- PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
+ PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
+ PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
- PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
+ PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
- PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
- PINMUX_IPSR_DATA(IP14_27_25, QCLK),
+ PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
+ PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
- PINMUX_IPSR_DATA(IP14_30_28, RTS1_N),
+ PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
- PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
- PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
+ PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
+ PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
- PINMUX_IPSR_DATA(IP15_2_0, SCK2),
+ PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
- PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
- PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
+ PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
+ PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
- PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
- PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
+ PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
+ PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
- PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
- PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
+ PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
+ PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
- PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
+ PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
- PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
- PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
+ PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
+ PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
- PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
- PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
+ PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
+ PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
- PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
- PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
+ PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
+ PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
- PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
- PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
- PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
+ PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
+ PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
+ PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
- PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
- PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
- PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
+ PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
+ PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
+ PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
- PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
- PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
- PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
- PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
+ PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
+ PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
+ PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
+ PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
- PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
- PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
- PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
- PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
+ PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
+ PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
+ PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
+ PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
- PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
- PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
- PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
+ PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
+ PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
+ PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
- PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
- PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
- PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
+ PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
+ PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
+ PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
- PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
- PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
- PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
- PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
+ PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
+ PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
+ PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
+ PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
- PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
- PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
- PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
- PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
+ PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
+ PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
+ PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
+ PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
- PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
- PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
- PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
+ PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
+ PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
+ PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
PINMUX_SINGLE(SD1_CLK),
/* IPSR0 */
- PINMUX_IPSR_DATA(IP0_0, D0),
- PINMUX_IPSR_DATA(IP0_1, D1),
- PINMUX_IPSR_DATA(IP0_2, D2),
- PINMUX_IPSR_DATA(IP0_3, D3),
- PINMUX_IPSR_DATA(IP0_4, D4),
- PINMUX_IPSR_DATA(IP0_5, D5),
- PINMUX_IPSR_DATA(IP0_6, D6),
- PINMUX_IPSR_DATA(IP0_7, D7),
- PINMUX_IPSR_DATA(IP0_8, D8),
- PINMUX_IPSR_DATA(IP0_9, D9),
- PINMUX_IPSR_DATA(IP0_10, D10),
- PINMUX_IPSR_DATA(IP0_11, D11),
- PINMUX_IPSR_DATA(IP0_12, D12),
- PINMUX_IPSR_DATA(IP0_13, D13),
- PINMUX_IPSR_DATA(IP0_14, D14),
- PINMUX_IPSR_DATA(IP0_15, D15),
- PINMUX_IPSR_DATA(IP0_18_16, A0),
+ PINMUX_IPSR_GPSR(IP0_0, D0),
+ PINMUX_IPSR_GPSR(IP0_1, D1),
+ PINMUX_IPSR_GPSR(IP0_2, D2),
+ PINMUX_IPSR_GPSR(IP0_3, D3),
+ PINMUX_IPSR_GPSR(IP0_4, D4),
+ PINMUX_IPSR_GPSR(IP0_5, D5),
+ PINMUX_IPSR_GPSR(IP0_6, D6),
+ PINMUX_IPSR_GPSR(IP0_7, D7),
+ PINMUX_IPSR_GPSR(IP0_8, D8),
+ PINMUX_IPSR_GPSR(IP0_9, D9),
+ PINMUX_IPSR_GPSR(IP0_10, D10),
+ PINMUX_IPSR_GPSR(IP0_11, D11),
+ PINMUX_IPSR_GPSR(IP0_12, D12),
+ PINMUX_IPSR_GPSR(IP0_13, D13),
+ PINMUX_IPSR_GPSR(IP0_14, D14),
+ PINMUX_IPSR_GPSR(IP0_15, D15),
+ PINMUX_IPSR_GPSR(IP0_18_16, A0),
PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
PINMUX_IPSR_MSEL(IP0_18_16, SCL0_C, SEL_IIC0_2),
- PINMUX_IPSR_DATA(IP0_18_16, PWM2_B),
- PINMUX_IPSR_DATA(IP0_20_19, A1),
+ PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
+ PINMUX_IPSR_GPSR(IP0_20_19, A1),
PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP0_22_21, A2),
+ PINMUX_IPSR_GPSR(IP0_22_21, A2),
PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP0_24_23, A3),
+ PINMUX_IPSR_GPSR(IP0_24_23, A3),
PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP0_26_25, A4),
+ PINMUX_IPSR_GPSR(IP0_26_25, A4),
PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP0_28_27, A5),
+ PINMUX_IPSR_GPSR(IP0_28_27, A5),
PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP0_30_29, A6),
+ PINMUX_IPSR_GPSR(IP0_30_29, A6),
PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
/* IPSR1 */
- PINMUX_IPSR_DATA(IP1_1_0, A7),
+ PINMUX_IPSR_GPSR(IP1_1_0, A7),
PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
- PINMUX_IPSR_DATA(IP1_3_2, A8),
+ PINMUX_IPSR_GPSR(IP1_3_2, A8),
PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
PINMUX_IPSR_MSEL(IP1_3_2, SCL0, SEL_IIC0_0),
- PINMUX_IPSR_DATA(IP1_5_4, A9),
+ PINMUX_IPSR_GPSR(IP1_5_4, A9),
PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
PINMUX_IPSR_MSEL(IP1_5_4, SDA0, SEL_IIC0_0),
- PINMUX_IPSR_DATA(IP1_7_6, A10),
+ PINMUX_IPSR_GPSR(IP1_7_6, A10),
PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
- PINMUX_IPSR_DATA(IP1_10_8, A11),
+ PINMUX_IPSR_GPSR(IP1_10_8, A11),
PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
PINMUX_IPSR_MSEL(IP1_10_8, SCL3_D, SEL_IIC3_3),
PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
- PINMUX_IPSR_DATA(IP1_13_11, A12),
+ PINMUX_IPSR_GPSR(IP1_13_11, A12),
PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
PINMUX_IPSR_MSEL(IP1_13_11, SDA3_D, SEL_IIC3_3),
PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
- PINMUX_IPSR_DATA(IP1_16_14, A13),
+ PINMUX_IPSR_GPSR(IP1_16_14, A13),
PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
- PINMUX_IPSR_DATA(IP1_19_17, A14),
+ PINMUX_IPSR_GPSR(IP1_19_17, A14),
PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
- PINMUX_IPSR_DATA(IP1_22_20, A15),
+ PINMUX_IPSR_GPSR(IP1_22_20, A15),
PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
- PINMUX_IPSR_DATA(IP1_25_23, A16),
+ PINMUX_IPSR_GPSR(IP1_25_23, A16),
PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
- PINMUX_IPSR_DATA(IP1_28_26, A17),
+ PINMUX_IPSR_GPSR(IP1_28_26, A17),
PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
PINMUX_IPSR_MSEL(IP1_28_26, SDA0_C, SEL_IIC0_2),
- PINMUX_IPSR_DATA(IP1_31_29, A18),
+ PINMUX_IPSR_GPSR(IP1_31_29, A18),
PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
/* IPSR2 */
- PINMUX_IPSR_DATA(IP2_2_0, A19),
- PINMUX_IPSR_DATA(IP2_2_0, DACK1),
+ PINMUX_IPSR_GPSR(IP2_2_0, A19),
+ PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
- PINMUX_IPSR_DATA(IP2_2_0, A20),
+ PINMUX_IPSR_GPSR(IP2_2_0, A20),
PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
- PINMUX_IPSR_DATA(IP2_6_5, A21),
+ PINMUX_IPSR_GPSR(IP2_6_5, A21),
PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
- PINMUX_IPSR_DATA(IP2_9_7, A22),
+ PINMUX_IPSR_GPSR(IP2_9_7, A22),
PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
- PINMUX_IPSR_DATA(IP2_12_10, A23),
+ PINMUX_IPSR_GPSR(IP2_12_10, A23),
PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
- PINMUX_IPSR_DATA(IP2_15_13, A24),
+ PINMUX_IPSR_GPSR(IP2_15_13, A24),
PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
- PINMUX_IPSR_DATA(IP2_18_16, A25),
+ PINMUX_IPSR_GPSR(IP2_18_16, A25),
PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
- PINMUX_IPSR_DATA(IP2_20_19, CS0_N),
+ PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
PINMUX_IPSR_MSEL(IP2_20_19, SCL1, SEL_IIC1_0),
- PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26),
+ PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
PINMUX_IPSR_MSEL(IP2_22_21, SDA1, SEL_IIC1_0),
- PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N),
+ PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
- PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N),
+ PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
- PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N),
+ PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
- PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1),
+ PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
/* IPSR3 */
- PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N),
+ PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
- PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2),
- PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N),
- PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N),
+ PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
+ PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
+ PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
- PINMUX_IPSR_DATA(IP3_5_3, PWM1),
- PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1),
- PINMUX_IPSR_DATA(IP3_8_6, BS_N),
- PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N),
+ PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
+ PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
+ PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
+ PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
- PINMUX_IPSR_DATA(IP3_8_6, PWM2),
- PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2),
- PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N),
+ PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
+ PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
+ PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
- PINMUX_IPSR_DATA(IP3_13_12, WE0_N),
+ PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
- PINMUX_IPSR_DATA(IP3_15_14, WE1_N),
+ PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
- PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0),
+ PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
- PINMUX_IPSR_DATA(IP3_19_18, DREQ0),
- PINMUX_IPSR_DATA(IP3_19_18, PWM3),
- PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3),
- PINMUX_IPSR_DATA(IP3_21_20, DACK0),
- PINMUX_IPSR_DATA(IP3_21_20, DRACK0),
+ PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
+ PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
+ PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
+ PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
+ PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
PINMUX_IPSR_MSEL(IP4_9_8, SDA1_B, SEL_IIC1_1),
PINMUX_IPSR_MSEL(IP4_9_8, SDA8_B, SEL_IIC8_1),
PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
- PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2),
+ PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0),
PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
- PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2),
+ PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0),
PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
- PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2),
+ PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
- PINMUX_IPSR_DATA(IP4_19, SSI_SCK34),
- PINMUX_IPSR_DATA(IP4_20, SSI_WS34),
- PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3),
- PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4),
+ PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
+ PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
+ PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
+ PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
- PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4),
+ PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
- PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4),
+ PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
- PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5),
+ PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
- PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B),
+ PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
/* IPSR5 */
- PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5),
+ PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
- PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B),
- PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5),
+ PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
+ PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
- PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B),
- PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6),
+ PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
+ PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
- PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B),
- PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6),
+ PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
+ PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
- PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B),
- PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6),
+ PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
+ PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
- PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B),
+ PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
- PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
+ PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
- PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
+ PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
- PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
+ PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
- PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
- PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
+ PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
+ PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
- PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
- PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
+ PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
+ PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
- PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
- PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
+ PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
+ PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
PINMUX_IPSR_MSEL(IP6_15_14, SCL4_C, SEL_IIC4_2),
PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
- PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
- PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
+ PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
+ PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
PINMUX_IPSR_MSEL(IP6_18_16, SDA4_C, SEL_IIC4_2),
PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
- PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
- PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
+ PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
+ PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
PINMUX_IPSR_MSEL(IP6_20_19, SCL1_E, SEL_IIC1_4),
PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
- PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
+ PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
PINMUX_IPSR_MSEL(IP6_23_21, SDA1_E, SEL_IIC1_4),
PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
- PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
+ PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
- PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
+ PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
/* IPSR7 */
- PINMUX_IPSR_DATA(IP7_2_0, IRQ9),
+ PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
- PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0),
- PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0),
+ PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
+ PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
- PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1),
- PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1),
+ PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
+ PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
- PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2),
- PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2),
+ PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
+ PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
- PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3),
- PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3),
+ PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
+ PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
- PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4),
- PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4),
+ PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
+ PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
- PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5),
- PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5),
+ PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
+ PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
- PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6),
- PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6),
+ PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
+ PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
- PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7),
- PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7),
+ PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
+ PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
- PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0),
- PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8),
+ PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
+ PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
- PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1),
- PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9),
+ PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
+ PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
- PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2),
- PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10),
+ PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
+ PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B),
+ PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
/* IPSR8 */
- PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3),
- PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11),
+ PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
+ PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
- PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4),
- PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12),
+ PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
+ PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
- PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5),
- PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13),
+ PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
+ PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
- PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6),
- PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14),
+ PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
+ PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
- PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7),
- PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15),
+ PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
+ PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
- PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0),
- PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16),
+ PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
+ PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
- PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1),
- PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17),
+ PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
+ PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
- PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2),
- PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18),
+ PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
+ PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B),
+ PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
- PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3),
- PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19),
+ PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
+ PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4),
- PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20),
+ PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
+ PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
- PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5),
- PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21),
+ PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
+ PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
/* IPSR9 */
- PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6),
- PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22),
+ PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
+ PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
PINMUX_IPSR_MSEL(IP9_2_0, SCL3_C, SEL_IIC3_2),
PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
- PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7),
- PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23),
+ PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
+ PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
PINMUX_IPSR_MSEL(IP9_5_3, SDA3_C, SEL_IIC3_2),
PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
- PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS),
- PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0),
- PINMUX_IPSR_DATA(IP9_7, QCLK),
- PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1),
- PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE),
+ PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
+ PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
+ PINMUX_IPSR_GPSR(IP9_7, QCLK),
+ PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
+ PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP9_10_8, SCL2_B, SEL_IIC2_1),
- PINMUX_IPSR_DATA(IP9_10_8, PWM4),
- PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
- PINMUX_IPSR_DATA(IP9_11, QSTH_QHS),
- PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
- PINMUX_IPSR_DATA(IP9_12, QSTB_QHE),
- PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
- PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE),
+ PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
+ PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
+ PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
+ PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
+ PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
+ PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP9_15_13, SDA2_B, SEL_IIC2_1),
- PINMUX_IPSR_DATA(IP9_16, DU1_DISP),
- PINMUX_IPSR_DATA(IP9_16, QPOLA),
- PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE),
- PINMUX_IPSR_DATA(IP9_18_17, QPOLB),
- PINMUX_IPSR_DATA(IP9_18_17, PWM4_B),
- PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB),
+ PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
+ PINMUX_IPSR_GPSR(IP9_16, QPOLA),
+ PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
+ PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
+ PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
+ PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
- PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD),
+ PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
- PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
- PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
- PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3),
+ PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
- PINMUX_IPSR_DATA(IP9_31_29, VI0_G0),
+ PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
PINMUX_IPSR_MSEL(IP9_31_29, SCL8, SEL_IIC8_0),
PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
PINMUX_IPSR_MSEL(IP9_31_29, SCL4, SEL_IIC4_0),
PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
- PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N),
+ PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
/* IPSR10 */
- PINMUX_IPSR_DATA(IP10_2_0, VI0_G1),
+ PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
PINMUX_IPSR_MSEL(IP10_2_0, SDA8, SEL_IIC8_0),
PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
PINMUX_IPSR_MSEL(IP10_2_0, SDA4, SEL_IIC4_0),
PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
- PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N),
- PINMUX_IPSR_DATA(IP10_5_3, VI0_G2),
- PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
+ PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
+ PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
PINMUX_IPSR_MSEL(IP10_5_3, SCL3_B, SEL_IIC3_1),
PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
- PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N),
- PINMUX_IPSR_DATA(IP10_8_6, VI0_G3),
- PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
+ PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
+ PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
PINMUX_IPSR_MSEL(IP10_8_6, SDA3_B, SEL_IIC3_1),
PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
- PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N),
- PINMUX_IPSR_DATA(IP10_11_9, VI0_G4),
- PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB),
+ PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
+ PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
+ PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
- PINMUX_IPSR_DATA(IP10_14_12, VI0_G5),
- PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD),
+ PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
+ PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
- PINMUX_IPSR_DATA(IP10_16_15, VI0_G6),
- PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK),
+ PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
+ PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
- PINMUX_IPSR_DATA(IP10_18_17, VI0_G7),
- PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0),
+ PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
+ PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
- PINMUX_IPSR_DATA(IP10_21_19, VI0_R0),
- PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1),
+ PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
+ PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
- PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N),
- PINMUX_IPSR_DATA(IP10_24_22, VI0_R1),
- PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2),
+ PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
+ PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
+ PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
- PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N),
- PINMUX_IPSR_DATA(IP10_26_25, VI0_R2),
- PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3),
+ PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
+ PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
+ PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
- PINMUX_IPSR_DATA(IP10_28_27, VI0_R3),
- PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4),
+ PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
+ PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
- PINMUX_IPSR_DATA(IP10_31_29, VI0_R4),
- PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5),
+ PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
+ PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
PINMUX_IPSR_MSEL(IP10_31_29, SCL1_D, SEL_IIC1_3),
/* IPSR11 */
- PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
- PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
+ PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
+ PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
PINMUX_IPSR_MSEL(IP11_2_0, SDA1_D, SEL_IIC1_3),
- PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
- PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
+ PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
+ PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP11_5_3, SCL4_B, SEL_IIC4_1),
- PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
+ PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
+ PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
+ PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
+ PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
+ PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
+ PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
+ PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
+ PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
+ PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
+ PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
+ PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
+ PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
+ PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
- PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
- PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
+ PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
+ PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
+ PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
PINMUX_IPSR_MSEL(IP11_29_28, SCL2_C, SEL_IIC2_2),
- PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
- PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
+ PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
+ PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
PINMUX_IPSR_MSEL(IP11_31_30, SDA2_C, SEL_IIC2_2),
/* IPSR12 */
- PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
- PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
+ PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
+ PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
PINMUX_IPSR_MSEL(IP12_1_0, SCL3, SEL_IIC3_0),
PINMUX_IPSR_MSEL(IP12_1_0, SCL7, SEL_IIC7_0),
- PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
- PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
+ PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
+ PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
PINMUX_IPSR_MSEL(IP12_3_2, SDA3, SEL_IIC3_0),
PINMUX_IPSR_MSEL(IP12_3_2, SDA7, SEL_IIC7_0),
- PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
- PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
+ PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
+ PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
PINMUX_IPSR_MSEL(IP12_6_4, SCL2_D, SEL_IIC2_3),
PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
- PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
+ PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
+ PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
PINMUX_IPSR_MSEL(IP12_9_7, SDA2_D, SEL_IIC2_3),
PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
- PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
+ PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
+ PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
- PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
+ PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
+ PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
- PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
+ PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
+ PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
- PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
- PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
+ PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
+ PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
- PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
+ PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
+ PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
- PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
+ PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
+ PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
+ PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
+ PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
/* IPSR13 */
PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
+ PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
+ PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
+ PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
- PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
+ PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
+ PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
- PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
+ PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
+ PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
+ PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
+ PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
+ PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
+ PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
+ PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
- PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
+ PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
- PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
+ PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
- PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
+ PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
- PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
+ PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
+ PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
+ PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
- PINMUX_IPSR_DATA(IP13_30_28, PWM0),
- PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
+ PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
+ PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
+ PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
PINMUX_IPSR_MSEL(IP13_30_28, SCL1_C, SEL_IIC1_2),
/* IPSR14 */
- PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
- PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
+ PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
+ PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
PINMUX_IPSR_MSEL(IP14_1_0, SDA1_C, SEL_IIC1_2),
- PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
- PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
- PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
- PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
- PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
- PINMUX_IPSR_DATA(IP14_4, MMC_D0),
- PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
- PINMUX_IPSR_DATA(IP14_5, MMC_D1),
- PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
- PINMUX_IPSR_DATA(IP14_6, MMC_D2),
- PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
- PINMUX_IPSR_DATA(IP14_7, MMC_D3),
- PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
- PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
+ PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
+ PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
+ PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
+ PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
+ PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
+ PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
+ PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
+ PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
+ PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
+ PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
+ PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
+ PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
+ PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
+ PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
PINMUX_IPSR_MSEL(IP14_10_8, SCL8_C, SEL_IIC8_2),
PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
- PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
- PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
+ PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
+ PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
PINMUX_IPSR_MSEL(IP14_13_11, SDA8_C, SEL_IIC8_2),
PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
- PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
+ PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
- PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
+ PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
- PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
+ PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
- PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
+ PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
PINMUX_IPSR_MSEL(IP14_28_26, SCL7_C, SEL_IIC7_2),
- PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
+ PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
PINMUX_IPSR_MSEL(IP14_31_29, SDA7_C, SEL_IIC7_2),
- PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
+ PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
/* IPSR15 */
PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
- PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
+ PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
- PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
+ PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
- PINMUX_IPSR_DATA(IP15_11_9, PWM5),
- PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
+ PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
+ PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
- PINMUX_IPSR_DATA(IP15_14_12, PWM6),
- PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
+ PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
+ PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
- PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
+ PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
/* IPSR16 */
PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
- PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
+ PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
- PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
+ PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
- PINMUX_IPSR_DATA(IP16_7_6, MLB_CLK),
+ PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
- PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
- PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
+ PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
+ PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
- PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
- PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
+ PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
+ PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
};
/*
* r8a7794 processor support - PFC hardware block.
*
- * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2014-2015 Renesas Electronics Corporation
* Copyright (C) 2015 Renesas Solutions Corp.
- * Copyright (C) 2015 Cogent Embedded, Inc., <source@cogentembedded.com>
+ * Copyright (C) 2015-2016 Cogent Embedded, Inc., <source@cogentembedded.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
PINMUX_SINGLE(SD1_DATA3),
/* IPSR0 */
- PINMUX_IPSR_DATA(IP0_0, SD1_CD),
+ PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
- PINMUX_IPSR_DATA(IP0_9_8, SD1_WP),
- PINMUX_IPSR_DATA(IP0_9_8, IRQ7),
+ PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
+ PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
- PINMUX_IPSR_DATA(IP0_10, MMC_CLK),
- PINMUX_IPSR_DATA(IP0_10, SD2_CLK),
- PINMUX_IPSR_DATA(IP0_11, MMC_CMD),
- PINMUX_IPSR_DATA(IP0_11, SD2_CMD),
- PINMUX_IPSR_DATA(IP0_12, MMC_D0),
- PINMUX_IPSR_DATA(IP0_12, SD2_DATA0),
- PINMUX_IPSR_DATA(IP0_13, MMC_D1),
- PINMUX_IPSR_DATA(IP0_13, SD2_DATA1),
- PINMUX_IPSR_DATA(IP0_14, MMC_D2),
- PINMUX_IPSR_DATA(IP0_14, SD2_DATA2),
- PINMUX_IPSR_DATA(IP0_15, MMC_D3),
- PINMUX_IPSR_DATA(IP0_15, SD2_DATA3),
- PINMUX_IPSR_DATA(IP0_16, MMC_D4),
- PINMUX_IPSR_DATA(IP0_16, SD2_CD),
- PINMUX_IPSR_DATA(IP0_17, MMC_D5),
- PINMUX_IPSR_DATA(IP0_17, SD2_WP),
- PINMUX_IPSR_DATA(IP0_19_18, MMC_D6),
+ PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
+ PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
+ PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
+ PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
+ PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
+ PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
+ PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
+ PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
+ PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
+ PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
+ PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
+ PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
+ PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
+ PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
+ PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
+ PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
+ PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
- PINMUX_IPSR_DATA(IP0_21_20, MMC_D7),
+ PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
- PINMUX_IPSR_DATA(IP0_23_22, D0),
+ PINMUX_IPSR_GPSR(IP0_23_22, D0),
PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
- PINMUX_IPSR_DATA(IP0_23_22, IRQ4),
- PINMUX_IPSR_DATA(IP0_24, D1),
+ PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
+ PINMUX_IPSR_GPSR(IP0_24, D1),
PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
- PINMUX_IPSR_DATA(IP0_25, D2),
+ PINMUX_IPSR_GPSR(IP0_25, D2),
PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
- PINMUX_IPSR_DATA(IP0_27_26, D3),
+ PINMUX_IPSR_GPSR(IP0_27_26, D3),
PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
- PINMUX_IPSR_DATA(IP0_29_28, D4),
+ PINMUX_IPSR_GPSR(IP0_29_28, D4),
PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
- PINMUX_IPSR_DATA(IP0_31_30, D5),
+ PINMUX_IPSR_GPSR(IP0_31_30, D5),
PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
/* IPSR1 */
- PINMUX_IPSR_DATA(IP1_1_0, D6),
+ PINMUX_IPSR_GPSR(IP1_1_0, D6),
PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
- PINMUX_IPSR_DATA(IP1_3_2, D7),
- PINMUX_IPSR_DATA(IP1_3_2, IRQ3),
+ PINMUX_IPSR_GPSR(IP1_3_2, D7),
+ PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
- PINMUX_IPSR_DATA(IP1_3_2, PWM6_B),
- PINMUX_IPSR_DATA(IP1_5_4, D8),
- PINMUX_IPSR_DATA(IP1_5_4, HSCIF2_HRX),
+ PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
+ PINMUX_IPSR_GPSR(IP1_5_4, D8),
+ PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
- PINMUX_IPSR_DATA(IP1_7_6, D9),
- PINMUX_IPSR_DATA(IP1_7_6, HSCIF2_HTX),
+ PINMUX_IPSR_GPSR(IP1_7_6, D9),
+ PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
- PINMUX_IPSR_DATA(IP1_10_8, D10),
- PINMUX_IPSR_DATA(IP1_10_8, HSCIF2_HSCK),
+ PINMUX_IPSR_GPSR(IP1_10_8, D10),
+ PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
- PINMUX_IPSR_DATA(IP1_10_8, IRQ6),
- PINMUX_IPSR_DATA(IP1_10_8, PWM5_C),
- PINMUX_IPSR_DATA(IP1_12_11, D11),
- PINMUX_IPSR_DATA(IP1_12_11, HSCIF2_HCTS_N),
+ PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
+ PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
+ PINMUX_IPSR_GPSR(IP1_12_11, D11),
+ PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
- PINMUX_IPSR_DATA(IP1_14_13, D12),
- PINMUX_IPSR_DATA(IP1_14_13, HSCIF2_HRTS_N),
+ PINMUX_IPSR_GPSR(IP1_14_13, D12),
+ PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
- PINMUX_IPSR_DATA(IP1_17_15, D13),
+ PINMUX_IPSR_GPSR(IP1_17_15, D13),
PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
- PINMUX_IPSR_DATA(IP1_17_15, TANS1),
- PINMUX_IPSR_DATA(IP1_17_15, PWM2_C),
+ PINMUX_IPSR_GPSR(IP1_17_15, TANS1),
+ PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
- PINMUX_IPSR_DATA(IP1_19_18, D14),
+ PINMUX_IPSR_GPSR(IP1_19_18, D14),
PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
PINMUX_IPSR_MSEL(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1),
- PINMUX_IPSR_DATA(IP1_21_20, D15),
+ PINMUX_IPSR_GPSR(IP1_21_20, D15),
PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
PINMUX_IPSR_MSEL(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1),
- PINMUX_IPSR_DATA(IP1_23_22, A0),
- PINMUX_IPSR_DATA(IP1_23_22, SCIFB1_SCK),
- PINMUX_IPSR_DATA(IP1_23_22, PWM3_B),
- PINMUX_IPSR_DATA(IP1_24, A1),
- PINMUX_IPSR_DATA(IP1_24, SCIFB1_TXD),
- PINMUX_IPSR_DATA(IP1_26, A3),
- PINMUX_IPSR_DATA(IP1_26, SCIFB0_SCK),
- PINMUX_IPSR_DATA(IP1_27, A4),
- PINMUX_IPSR_DATA(IP1_27, SCIFB0_TXD),
- PINMUX_IPSR_DATA(IP1_29_28, A5),
- PINMUX_IPSR_DATA(IP1_29_28, SCIFB0_RXD),
- PINMUX_IPSR_DATA(IP1_29_28, PWM4_B),
- PINMUX_IPSR_DATA(IP1_29_28, TPUTO3_C),
- PINMUX_IPSR_DATA(IP1_31_30, A6),
- PINMUX_IPSR_DATA(IP1_31_30, SCIFB0_CTS_N),
+ PINMUX_IPSR_GPSR(IP1_23_22, A0),
+ PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
+ PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
+ PINMUX_IPSR_GPSR(IP1_24, A1),
+ PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
+ PINMUX_IPSR_GPSR(IP1_26, A3),
+ PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
+ PINMUX_IPSR_GPSR(IP1_27, A4),
+ PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
+ PINMUX_IPSR_GPSR(IP1_29_28, A5),
+ PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
+ PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
+ PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
+ PINMUX_IPSR_GPSR(IP1_31_30, A6),
+ PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
- PINMUX_IPSR_DATA(IP1_31_30, TPUTO2_C),
+ PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
/* IPSR2 */
- PINMUX_IPSR_DATA(IP2_1_0, A7),
- PINMUX_IPSR_DATA(IP2_1_0, SCIFB0_RTS_N),
+ PINMUX_IPSR_GPSR(IP2_1_0, A7),
+ PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
- PINMUX_IPSR_DATA(IP2_3_2, A8),
+ PINMUX_IPSR_GPSR(IP2_3_2, A8),
PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
- PINMUX_IPSR_DATA(IP2_5_4, A9),
+ PINMUX_IPSR_GPSR(IP2_5_4, A9),
PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
- PINMUX_IPSR_DATA(IP2_7_6, A10),
+ PINMUX_IPSR_GPSR(IP2_7_6, A10),
PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
PINMUX_IPSR_MSEL(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1),
- PINMUX_IPSR_DATA(IP2_9_8, A11),
+ PINMUX_IPSR_GPSR(IP2_9_8, A11),
PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
PINMUX_IPSR_MSEL(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1),
- PINMUX_IPSR_DATA(IP2_11_10, A12),
+ PINMUX_IPSR_GPSR(IP2_11_10, A12),
PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
- PINMUX_IPSR_DATA(IP2_13_12, A13),
+ PINMUX_IPSR_GPSR(IP2_13_12, A13),
PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
- PINMUX_IPSR_DATA(IP2_15_14, A14),
+ PINMUX_IPSR_GPSR(IP2_15_14, A14),
PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
- PINMUX_IPSR_DATA(IP2_17_16, A15),
+ PINMUX_IPSR_GPSR(IP2_17_16, A15),
PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
- PINMUX_IPSR_DATA(IP2_20_18, A16),
+ PINMUX_IPSR_GPSR(IP2_20_18, A16),
PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0),
PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
- PINMUX_IPSR_DATA(IP2_20_18, TPUTO2_B),
- PINMUX_IPSR_DATA(IP2_23_21, A17),
+ PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
+ PINMUX_IPSR_GPSR(IP2_23_21, A17),
PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
- PINMUX_IPSR_DATA(IP2_26_24, A18),
+ PINMUX_IPSR_GPSR(IP2_26_24, A18),
PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1),
- PINMUX_IPSR_DATA(IP2_29_27, A19),
+ PINMUX_IPSR_GPSR(IP2_29_27, A19),
PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
- PINMUX_IPSR_DATA(IP2_29_27, PWM4),
- PINMUX_IPSR_DATA(IP2_29_27, TPUTO2),
- PINMUX_IPSR_DATA(IP2_29_27, MOUT0),
- PINMUX_IPSR_DATA(IP2_31_30, A20),
- PINMUX_IPSR_DATA(IP2_31_30, SPCLK),
- PINMUX_IPSR_DATA(IP2_29_27, MOUT1),
+ PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
+ PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
+ PINMUX_IPSR_GPSR(IP2_29_27, MOUT0),
+ PINMUX_IPSR_GPSR(IP2_31_30, A20),
+ PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
+ PINMUX_IPSR_GPSR(IP2_29_27, MOUT1),
/* IPSR3 */
- PINMUX_IPSR_DATA(IP3_1_0, A21),
- PINMUX_IPSR_DATA(IP3_1_0, MOSI_IO0),
- PINMUX_IPSR_DATA(IP3_1_0, MOUT2),
- PINMUX_IPSR_DATA(IP3_3_2, A22),
- PINMUX_IPSR_DATA(IP3_3_2, MISO_IO1),
- PINMUX_IPSR_DATA(IP3_3_2, MOUT5),
- PINMUX_IPSR_DATA(IP3_3_2, ATADIR1_N),
- PINMUX_IPSR_DATA(IP3_5_4, A23),
- PINMUX_IPSR_DATA(IP3_5_4, IO2),
- PINMUX_IPSR_DATA(IP3_5_4, MOUT6),
- PINMUX_IPSR_DATA(IP3_5_4, ATAWR1_N),
- PINMUX_IPSR_DATA(IP3_7_6, A24),
- PINMUX_IPSR_DATA(IP3_7_6, IO3),
- PINMUX_IPSR_DATA(IP3_7_6, EX_WAIT2),
- PINMUX_IPSR_DATA(IP3_9_8, A25),
- PINMUX_IPSR_DATA(IP3_9_8, SSL),
- PINMUX_IPSR_DATA(IP3_9_8, ATARD1_N),
- PINMUX_IPSR_DATA(IP3_10, CS0_N),
- PINMUX_IPSR_DATA(IP3_10, VI1_DATA8),
- PINMUX_IPSR_DATA(IP3_11, CS1_N_A26),
- PINMUX_IPSR_DATA(IP3_11, VI1_DATA9),
- PINMUX_IPSR_DATA(IP3_12, EX_CS0_N),
- PINMUX_IPSR_DATA(IP3_12, VI1_DATA10),
- PINMUX_IPSR_DATA(IP3_14_13, EX_CS1_N),
- PINMUX_IPSR_DATA(IP3_14_13, TPUTO3_B),
- PINMUX_IPSR_DATA(IP3_14_13, SCIFB2_RXD),
- PINMUX_IPSR_DATA(IP3_14_13, VI1_DATA11),
- PINMUX_IPSR_DATA(IP3_17_15, EX_CS2_N),
- PINMUX_IPSR_DATA(IP3_17_15, PWM0),
+ PINMUX_IPSR_GPSR(IP3_1_0, A21),
+ PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
+ PINMUX_IPSR_GPSR(IP3_1_0, MOUT2),
+ PINMUX_IPSR_GPSR(IP3_3_2, A22),
+ PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
+ PINMUX_IPSR_GPSR(IP3_3_2, MOUT5),
+ PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
+ PINMUX_IPSR_GPSR(IP3_5_4, A23),
+ PINMUX_IPSR_GPSR(IP3_5_4, IO2),
+ PINMUX_IPSR_GPSR(IP3_5_4, MOUT6),
+ PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
+ PINMUX_IPSR_GPSR(IP3_7_6, A24),
+ PINMUX_IPSR_GPSR(IP3_7_6, IO3),
+ PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
+ PINMUX_IPSR_GPSR(IP3_9_8, A25),
+ PINMUX_IPSR_GPSR(IP3_9_8, SSL),
+ PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
+ PINMUX_IPSR_GPSR(IP3_10, CS0_N),
+ PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
+ PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
+ PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
+ PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
+ PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
+ PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
+ PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
+ PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
+ PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
+ PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
+ PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0),
- PINMUX_IPSR_DATA(IP3_17_15, TPUTO3),
- PINMUX_IPSR_DATA(IP3_17_15, SCIFB2_TXD),
+ PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
+ PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1),
- PINMUX_IPSR_DATA(IP3_20_18, EX_CS3_N),
+ PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0),
PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
- PINMUX_IPSR_DATA(IP3_20_18, SCIFB2_SCK),
+ PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1),
- PINMUX_IPSR_DATA(IP3_23_21, EX_CS4_N),
+ PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0),
PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
- PINMUX_IPSR_DATA(IP3_23_21, SCIFB2_CTS_N),
+ PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1),
- PINMUX_IPSR_DATA(IP3_26_24, EX_CS5_N),
+ PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0),
PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
- PINMUX_IPSR_DATA(IP3_26_24, SCIFB2_RTS_N),
+ PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1),
- PINMUX_IPSR_DATA(IP3_29_27, BS_N),
- PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
- PINMUX_IPSR_DATA(IP3_29_27, PWM1_C),
- PINMUX_IPSR_DATA(IP3_29_27, TPUTO0_C),
- PINMUX_IPSR_DATA(IP3_29_27, ATACS01_N),
+ PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
+ PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
+ PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
+ PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
+ PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1),
- PINMUX_IPSR_DATA(IP3_30, RD_N),
- PINMUX_IPSR_DATA(IP3_30, ATACS11_N),
- PINMUX_IPSR_DATA(IP3_31, RD_WR_N),
- PINMUX_IPSR_DATA(IP3_31, ATAG1_N),
+ PINMUX_IPSR_GPSR(IP3_30, RD_N),
+ PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
+ PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
+ PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
/* IPSR4 */
- PINMUX_IPSR_DATA(IP4_1_0, EX_WAIT0),
+ PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
- PINMUX_IPSR_DATA(IP4_1_0, PWMFSW0),
- PINMUX_IPSR_DATA(IP4_4_2, DU0_DR0),
- PINMUX_IPSR_DATA(IP4_4_2, LCDOUT16),
+ PINMUX_IPSR_GPSR(IP4_1_0, PWMFSW0),
+ PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
+ PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
- PINMUX_IPSR_DATA(IP4_4_2, CC50_STATE0),
- PINMUX_IPSR_DATA(IP4_7_5, DU0_DR1),
- PINMUX_IPSR_DATA(IP4_7_5, LCDOUT17),
+ PINMUX_IPSR_GPSR(IP4_4_2, CC50_STATE0),
+ PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
+ PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
- PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE1),
- PINMUX_IPSR_DATA(IP4_9_8, DU0_DR2),
- PINMUX_IPSR_DATA(IP4_9_8, LCDOUT18),
- PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE2),
- PINMUX_IPSR_DATA(IP4_11_10, DU0_DR3),
- PINMUX_IPSR_DATA(IP4_11_10, LCDOUT19),
- PINMUX_IPSR_DATA(IP4_11_10, CC50_STATE3),
- PINMUX_IPSR_DATA(IP4_13_12, DU0_DR4),
- PINMUX_IPSR_DATA(IP4_13_12, LCDOUT20),
- PINMUX_IPSR_DATA(IP4_13_12, CC50_STATE4),
- PINMUX_IPSR_DATA(IP4_15_14, DU0_DR5),
- PINMUX_IPSR_DATA(IP4_15_14, LCDOUT21),
- PINMUX_IPSR_DATA(IP4_15_14, CC50_STATE5),
- PINMUX_IPSR_DATA(IP4_17_16, DU0_DR6),
- PINMUX_IPSR_DATA(IP4_17_16, LCDOUT22),
- PINMUX_IPSR_DATA(IP4_17_16, CC50_STATE6),
- PINMUX_IPSR_DATA(IP4_19_18, DU0_DR7),
- PINMUX_IPSR_DATA(IP4_19_18, LCDOUT23),
- PINMUX_IPSR_DATA(IP4_19_18, CC50_STATE7),
- PINMUX_IPSR_DATA(IP4_22_20, DU0_DG0),
- PINMUX_IPSR_DATA(IP4_22_20, LCDOUT8),
+ PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE1),
+ PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
+ PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
+ PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE2),
+ PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
+ PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
+ PINMUX_IPSR_GPSR(IP4_11_10, CC50_STATE3),
+ PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
+ PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
+ PINMUX_IPSR_GPSR(IP4_13_12, CC50_STATE4),
+ PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
+ PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
+ PINMUX_IPSR_GPSR(IP4_15_14, CC50_STATE5),
+ PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
+ PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
+ PINMUX_IPSR_GPSR(IP4_17_16, CC50_STATE6),
+ PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
+ PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
+ PINMUX_IPSR_GPSR(IP4_19_18, CC50_STATE7),
+ PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
+ PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
- PINMUX_IPSR_DATA(IP4_22_20, CC50_STATE8),
- PINMUX_IPSR_DATA(IP4_25_23, DU0_DG1),
- PINMUX_IPSR_DATA(IP4_25_23, LCDOUT9),
+ PINMUX_IPSR_GPSR(IP4_22_20, CC50_STATE8),
+ PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
+ PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
- PINMUX_IPSR_DATA(IP4_25_23, CC50_STATE9),
- PINMUX_IPSR_DATA(IP4_27_26, DU0_DG2),
- PINMUX_IPSR_DATA(IP4_27_26, LCDOUT10),
- PINMUX_IPSR_DATA(IP4_27_26, CC50_STATE10),
- PINMUX_IPSR_DATA(IP4_29_28, DU0_DG3),
- PINMUX_IPSR_DATA(IP4_29_28, LCDOUT11),
- PINMUX_IPSR_DATA(IP4_29_28, CC50_STATE11),
- PINMUX_IPSR_DATA(IP4_31_30, DU0_DG4),
- PINMUX_IPSR_DATA(IP4_31_30, LCDOUT12),
- PINMUX_IPSR_DATA(IP4_31_30, CC50_STATE12),
+ PINMUX_IPSR_GPSR(IP4_25_23, CC50_STATE9),
+ PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
+ PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
+ PINMUX_IPSR_GPSR(IP4_27_26, CC50_STATE10),
+ PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
+ PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
+ PINMUX_IPSR_GPSR(IP4_29_28, CC50_STATE11),
+ PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
+ PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
+ PINMUX_IPSR_GPSR(IP4_31_30, CC50_STATE12),
/* IPSR5 */
- PINMUX_IPSR_DATA(IP5_1_0, DU0_DG5),
- PINMUX_IPSR_DATA(IP5_1_0, LCDOUT13),
- PINMUX_IPSR_DATA(IP5_1_0, CC50_STATE13),
- PINMUX_IPSR_DATA(IP5_3_2, DU0_DG6),
- PINMUX_IPSR_DATA(IP5_3_2, LCDOUT14),
- PINMUX_IPSR_DATA(IP5_3_2, CC50_STATE14),
- PINMUX_IPSR_DATA(IP5_5_4, DU0_DG7),
- PINMUX_IPSR_DATA(IP5_5_4, LCDOUT15),
- PINMUX_IPSR_DATA(IP5_5_4, CC50_STATE15),
- PINMUX_IPSR_DATA(IP5_8_6, DU0_DB0),
- PINMUX_IPSR_DATA(IP5_8_6, LCDOUT0),
+ PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
+ PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
+ PINMUX_IPSR_GPSR(IP5_1_0, CC50_STATE13),
+ PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
+ PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
+ PINMUX_IPSR_GPSR(IP5_3_2, CC50_STATE14),
+ PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
+ PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
+ PINMUX_IPSR_GPSR(IP5_5_4, CC50_STATE15),
+ PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
+ PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
- PINMUX_IPSR_DATA(IP5_8_6, CC50_STATE16),
- PINMUX_IPSR_DATA(IP5_11_9, DU0_DB1),
- PINMUX_IPSR_DATA(IP5_11_9, LCDOUT1),
+ PINMUX_IPSR_GPSR(IP5_8_6, CC50_STATE16),
+ PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
+ PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
- PINMUX_IPSR_DATA(IP5_11_9, CC50_STATE17),
- PINMUX_IPSR_DATA(IP5_13_12, DU0_DB2),
- PINMUX_IPSR_DATA(IP5_13_12, LCDOUT2),
- PINMUX_IPSR_DATA(IP5_13_12, CC50_STATE18),
- PINMUX_IPSR_DATA(IP5_15_14, DU0_DB3),
- PINMUX_IPSR_DATA(IP5_15_14, LCDOUT3),
- PINMUX_IPSR_DATA(IP5_15_14, CC50_STATE19),
- PINMUX_IPSR_DATA(IP5_17_16, DU0_DB4),
- PINMUX_IPSR_DATA(IP5_17_16, LCDOUT4),
- PINMUX_IPSR_DATA(IP5_17_16, CC50_STATE20),
- PINMUX_IPSR_DATA(IP5_19_18, DU0_DB5),
- PINMUX_IPSR_DATA(IP5_19_18, LCDOUT5),
- PINMUX_IPSR_DATA(IP5_19_18, CC50_STATE21),
- PINMUX_IPSR_DATA(IP5_21_20, DU0_DB6),
- PINMUX_IPSR_DATA(IP5_21_20, LCDOUT6),
- PINMUX_IPSR_DATA(IP5_21_20, CC50_STATE22),
- PINMUX_IPSR_DATA(IP5_23_22, DU0_DB7),
- PINMUX_IPSR_DATA(IP5_23_22, LCDOUT7),
- PINMUX_IPSR_DATA(IP5_23_22, CC50_STATE23),
- PINMUX_IPSR_DATA(IP5_25_24, DU0_DOTCLKIN),
- PINMUX_IPSR_DATA(IP5_25_24, QSTVA_QVS),
- PINMUX_IPSR_DATA(IP5_25_24, CC50_STATE24),
- PINMUX_IPSR_DATA(IP5_27_26, DU0_DOTCLKOUT0),
- PINMUX_IPSR_DATA(IP5_27_26, QCLK),
- PINMUX_IPSR_DATA(IP5_27_26, CC50_STATE25),
- PINMUX_IPSR_DATA(IP5_29_28, DU0_DOTCLKOUT1),
- PINMUX_IPSR_DATA(IP5_29_28, QSTVB_QVE),
- PINMUX_IPSR_DATA(IP5_29_28, CC50_STATE26),
- PINMUX_IPSR_DATA(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
- PINMUX_IPSR_DATA(IP5_31_30, QSTH_QHS),
- PINMUX_IPSR_DATA(IP5_31_30, CC50_STATE27),
+ PINMUX_IPSR_GPSR(IP5_11_9, CC50_STATE17),
+ PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
+ PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
+ PINMUX_IPSR_GPSR(IP5_13_12, CC50_STATE18),
+ PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
+ PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
+ PINMUX_IPSR_GPSR(IP5_15_14, CC50_STATE19),
+ PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
+ PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
+ PINMUX_IPSR_GPSR(IP5_17_16, CC50_STATE20),
+ PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
+ PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
+ PINMUX_IPSR_GPSR(IP5_19_18, CC50_STATE21),
+ PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
+ PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
+ PINMUX_IPSR_GPSR(IP5_21_20, CC50_STATE22),
+ PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
+ PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
+ PINMUX_IPSR_GPSR(IP5_23_22, CC50_STATE23),
+ PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
+ PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
+ PINMUX_IPSR_GPSR(IP5_25_24, CC50_STATE24),
+ PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
+ PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
+ PINMUX_IPSR_GPSR(IP5_27_26, CC50_STATE25),
+ PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
+ PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
+ PINMUX_IPSR_GPSR(IP5_29_28, CC50_STATE26),
+ PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
+ PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
+ PINMUX_IPSR_GPSR(IP5_31_30, CC50_STATE27),
/* IPSR6 */
- PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
- PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE),
- PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28),
- PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
- PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE),
- PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29),
- PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP),
- PINMUX_IPSR_DATA(IP6_5_4, QPOLA),
- PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30),
- PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE),
- PINMUX_IPSR_DATA(IP6_7_6, QPOLB),
- PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31),
- PINMUX_IPSR_DATA(IP6_8, VI0_CLK),
- PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK),
- PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0),
- PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV),
- PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1),
- PINMUX_IPSR_DATA(IP6_10, AVB_RXD0),
- PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2),
- PINMUX_IPSR_DATA(IP6_11, AVB_RXD1),
- PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3),
- PINMUX_IPSR_DATA(IP6_12, AVB_RXD2),
- PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4),
- PINMUX_IPSR_DATA(IP6_13, AVB_RXD3),
- PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5),
- PINMUX_IPSR_DATA(IP6_14, AVB_RXD4),
- PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6),
- PINMUX_IPSR_DATA(IP6_15, AVB_RXD5),
- PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7),
- PINMUX_IPSR_DATA(IP6_16, AVB_RXD6),
- PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB),
+ PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
+ PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
+ PINMUX_IPSR_GPSR(IP6_1_0, CC50_STATE28),
+ PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
+ PINMUX_IPSR_GPSR(IP6_3_2, CC50_STATE29),
+ PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
+ PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
+ PINMUX_IPSR_GPSR(IP6_5_4, CC50_STATE30),
+ PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
+ PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
+ PINMUX_IPSR_GPSR(IP6_7_6, CC50_STATE31),
+ PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
+ PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
+ PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
+ PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
+ PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
+ PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
+ PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
+ PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
+ PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
+ PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
+ PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
+ PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
+ PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
+ PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
+ PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
+ PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
+ PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
+ PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
+ PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7),
- PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD),
+ PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
+ PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER),
- PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
+ PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP6_25_23, AVB_COL),
- PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
+ PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
- PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN),
+ PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP6_31_29, VI0_G0),
+ PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
- PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK),
+ PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0),
/* IPSR7 */
PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_2_0, VI0_G1),
+ PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
- PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0),
+ PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0),
PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_5_3, VI0_G2),
+ PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
- PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1),
+ PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0),
PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_8_6, VI0_G3),
+ PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
- PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2),
+ PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0),
PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_11_9, VI0_G4),
+ PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
- PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3),
+ PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_14_12, VI0_G5),
+ PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
- PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4),
+ PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_17_15, VI0_G6),
+ PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
- PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5),
+ PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_20_18, VI0_G7),
+ PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
PINMUX_IPSR_MSEL(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
- PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6),
+ PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_23_21, VI0_R0),
+ PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
PINMUX_IPSR_MSEL(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
- PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7),
+ PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_26_24, VI0_R1),
+ PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
- PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER),
+ PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_29_27, VI0_R2),
+ PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
- PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK),
+ PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
- PINMUX_IPSR_DATA(IP7_31, DREQ0_N),
- PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD),
+ PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
+ PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
/* IPSR8 */
PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP8_2_0, VI0_R3),
+ PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
- PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC),
+ PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
- PINMUX_IPSR_DATA(IP8_5_3, VI0_R4),
+ PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
- PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO),
+ PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
- PINMUX_IPSR_DATA(IP8_8_6, VI0_R5),
+ PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
- PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK),
+ PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
- PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N),
- PINMUX_IPSR_DATA(IP8_11_9, VI0_R6),
+ PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
+ PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
- PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC),
+ PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
- PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N),
- PINMUX_IPSR_DATA(IP8_14_12, VI0_R7),
+ PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
+ PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
- PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT),
+ PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
- PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS),
+ PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
- PINMUX_IPSR_DATA(IP8_19_17, PWM5),
+ PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
- PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK),
+ PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
- PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B),
+ PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
- PINMUX_IPSR_DATA(IP8_22_20, TPUTO0),
+ PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
- PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE),
+ PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
- PINMUX_IPSR_DATA(IP8_25_23, PWM5_B),
- PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0),
+ PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
+ PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
- PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B),
+ PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
- PINMUX_IPSR_DATA(IP8_28_26, IRQ5),
- PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1),
+ PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
+ PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
- PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD),
+ PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
- PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2),
+ PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0),
/* IPSR9 */
- PINMUX_IPSR_DATA(IP9_2_0, MSIOF0_TXD),
+ PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
- PINMUX_IPSR_DATA(IP9_2_0, DU1_DR3),
+ PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1),
PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0),
- PINMUX_IPSR_DATA(IP9_5_3, MSIOF0_SCK),
- PINMUX_IPSR_DATA(IP9_5_3, IRQ0),
+ PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
+ PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
- PINMUX_IPSR_DATA(IP9_5_3, DU1_DR4),
+ PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0),
- PINMUX_IPSR_DATA(IP9_5_3, TPUTO1_C),
- PINMUX_IPSR_DATA(IP9_8_6, MSIOF0_SYNC),
- PINMUX_IPSR_DATA(IP9_8_6, PWM1),
+ PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
+ PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
+ PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
- PINMUX_IPSR_DATA(IP9_8_6, DU1_DR5),
+ PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0),
PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
- PINMUX_IPSR_DATA(IP9_11_9, MSIOF0_SS1),
+ PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
- PINMUX_IPSR_DATA(IP9_11_9, DU1_DR6),
+ PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0),
PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1),
- PINMUX_IPSR_DATA(IP9_14_12, MSIOF0_SS2),
+ PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
- PINMUX_IPSR_DATA(IP9_14_12, DU1_DR7),
+ PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0),
PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1),
PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
- PINMUX_IPSR_DATA(IP9_16_15, PWM6),
- PINMUX_IPSR_DATA(IP9_16_15, DU1_DG0),
+ PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
+ PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
- PINMUX_IPSR_DATA(IP9_18_17, TPUTO1),
- PINMUX_IPSR_DATA(IP9_18_17, DU1_DG1),
- PINMUX_IPSR_DATA(IP9_21_19, HSCIF1_HSCK),
- PINMUX_IPSR_DATA(IP9_21_19, PWM2),
+ PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
+ PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
+ PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
+ PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
- PINMUX_IPSR_DATA(IP9_21_19, DU1_DG2),
+ PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1),
PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
- PINMUX_IPSR_DATA(IP9_24_22, DU1_DG3),
+ PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
- PINMUX_IPSR_DATA(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
- PINMUX_IPSR_DATA(IP9_24_22, CC50_STATE32),
+ PINMUX_IPSR_GPSR(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
+ PINMUX_IPSR_GPSR(IP9_24_22, CC50_STATE32),
PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
- PINMUX_IPSR_DATA(IP9_27_25, DU1_DG4),
+ PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
- PINMUX_IPSR_DATA(IP9_27_25, CAN_STEP0),
- PINMUX_IPSR_DATA(IP9_27_25, CC50_STATE33),
+ PINMUX_IPSR_GPSR(IP9_27_25, CAN_STEP0),
+ PINMUX_IPSR_GPSR(IP9_27_25, CC50_STATE33),
PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
- PINMUX_IPSR_DATA(IP9_30_28, PWM3),
+ PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
- PINMUX_IPSR_DATA(IP9_30_28, DU1_DG5),
+ PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
- PINMUX_IPSR_DATA(IP9_30_28, CAN_TXCLK),
- PINMUX_IPSR_DATA(IP9_30_28, CC50_STATE34),
+ PINMUX_IPSR_GPSR(IP9_30_28, CAN_TXCLK),
+ PINMUX_IPSR_GPSR(IP9_30_28, CC50_STATE34),
/* IPSR10 */
PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0),
- PINMUX_IPSR_DATA(IP10_2_0, DU1_DG6),
+ PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
- PINMUX_IPSR_DATA(IP10_2_0, CAN_DEBUGOUT0),
- PINMUX_IPSR_DATA(IP10_2_0, CC50_STATE35),
+ PINMUX_IPSR_GPSR(IP10_2_0, CAN_DEBUGOUT0),
+ PINMUX_IPSR_GPSR(IP10_2_0, CC50_STATE35),
PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0),
- PINMUX_IPSR_DATA(IP10_5_3, DU1_DG7),
+ PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
- PINMUX_IPSR_DATA(IP10_5_3, CAN_DEBUGOUT1),
- PINMUX_IPSR_DATA(IP10_5_3, CC50_STATE36),
+ PINMUX_IPSR_GPSR(IP10_5_3, CAN_DEBUGOUT1),
+ PINMUX_IPSR_GPSR(IP10_5_3, CC50_STATE36),
PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0),
- PINMUX_IPSR_DATA(IP10_8_6, DU1_DB0),
+ PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
- PINMUX_IPSR_DATA(IP10_8_6, USB0_EXTLP),
- PINMUX_IPSR_DATA(IP10_8_6, CAN_DEBUGOUT2),
- PINMUX_IPSR_DATA(IP10_8_6, CC50_STATE37),
+ PINMUX_IPSR_GPSR(IP10_8_6, USB0_EXTLP),
+ PINMUX_IPSR_GPSR(IP10_8_6, CAN_DEBUGOUT2),
+ PINMUX_IPSR_GPSR(IP10_8_6, CC50_STATE37),
PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0),
- PINMUX_IPSR_DATA(IP10_11_9, DU1_DB1),
+ PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
- PINMUX_IPSR_DATA(IP10_11_9, USB0_OVC1),
- PINMUX_IPSR_DATA(IP10_11_9, CAN_DEBUGOUT3),
- PINMUX_IPSR_DATA(IP10_11_9, CC50_STATE38),
+ PINMUX_IPSR_GPSR(IP10_11_9, USB0_OVC1),
+ PINMUX_IPSR_GPSR(IP10_11_9, CAN_DEBUGOUT3),
+ PINMUX_IPSR_GPSR(IP10_11_9, CC50_STATE38),
PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
- PINMUX_IPSR_DATA(IP10_14_12, IRQ1),
- PINMUX_IPSR_DATA(IP10_14_12, DU1_DB2),
+ PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
+ PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
- PINMUX_IPSR_DATA(IP10_14_12, USB0_IDIN),
- PINMUX_IPSR_DATA(IP10_14_12, CAN_DEBUGOUT4),
- PINMUX_IPSR_DATA(IP10_14_12, CC50_STATE39),
+ PINMUX_IPSR_GPSR(IP10_14_12, USB0_IDIN),
+ PINMUX_IPSR_GPSR(IP10_14_12, CAN_DEBUGOUT4),
+ PINMUX_IPSR_GPSR(IP10_14_12, CC50_STATE39),
PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
- PINMUX_IPSR_DATA(IP10_17_15, IRQ2),
+ PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
- PINMUX_IPSR_DATA(IP10_17_15, DU1_DB3),
+ PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
- PINMUX_IPSR_DATA(IP10_17_15, TANS2),
- PINMUX_IPSR_DATA(IP10_17_15, CAN_DEBUGOUT5),
- PINMUX_IPSR_DATA(IP10_17_15, CC50_OSCOUT),
+ PINMUX_IPSR_GPSR(IP10_17_15, TANS2),
+ PINMUX_IPSR_GPSR(IP10_17_15, CAN_DEBUGOUT5),
+ PINMUX_IPSR_GPSR(IP10_17_15, CC50_OSCOUT),
PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
- PINMUX_IPSR_DATA(IP10_20_18, DU1_DB4),
+ PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
- PINMUX_IPSR_DATA(IP10_20_18, CAN_DEBUGOUT6),
+ PINMUX_IPSR_GPSR(IP10_20_18, CAN_DEBUGOUT6),
PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2),
PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
- PINMUX_IPSR_DATA(IP10_23_21, DU1_DB5),
+ PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
- PINMUX_IPSR_DATA(IP10_23_21, CAN_DEBUGOUT7),
+ PINMUX_IPSR_GPSR(IP10_23_21, CAN_DEBUGOUT7),
PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2),
PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
- PINMUX_IPSR_DATA(IP10_26_24, DU1_DB6),
+ PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
- PINMUX_IPSR_DATA(IP10_26_24, CAN_DEBUGOUT8),
+ PINMUX_IPSR_GPSR(IP10_26_24, CAN_DEBUGOUT8),
PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
- PINMUX_IPSR_DATA(IP10_29_27, DU1_DB7),
+ PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
- PINMUX_IPSR_DATA(IP10_29_27, CAN_DEBUGOUT9),
+ PINMUX_IPSR_GPSR(IP10_29_27, CAN_DEBUGOUT9),
PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
- PINMUX_IPSR_DATA(IP10_31_30, DU1_DOTCLKIN),
- PINMUX_IPSR_DATA(IP10_31_30, CAN_DEBUGOUT10),
+ PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
+ PINMUX_IPSR_GPSR(IP10_31_30, CAN_DEBUGOUT10),
/* IPSR11 */
PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
- PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0),
- PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11),
+ PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
+ PINMUX_IPSR_GPSR(IP11_2_0, CAN_DEBUGOUT11),
PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
- PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1),
- PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12),
+ PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
+ PINMUX_IPSR_GPSR(IP11_5_3, CAN_DEBUGOUT12),
PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
- PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
- PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13),
+ PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
+ PINMUX_IPSR_GPSR(IP11_7_6, CAN_DEBUGOUT13),
PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
- PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
- PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14),
+ PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
+ PINMUX_IPSR_GPSR(IP11_10_8, CAN_DEBUGOUT14),
PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
- PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
- PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15),
+ PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP11_13_11, CAN_DEBUGOUT15),
PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
- PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP),
+ PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
PINMUX_IPSR_MSEL(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
- PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE),
+ PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
- PINMUX_IPSR_DATA(IP11_20_18, IRQ8),
+ PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
- PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N),
- PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129),
+ PINMUX_IPSR_GPSR(IP11_20_18, PCMOE_N),
+ PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1),
- PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N),
- PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129),
+ PINMUX_IPSR_GPSR(IP11_23_21, PCMWE_N),
+ PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1),
- PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0),
+ PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
- PINMUX_IPSR_DATA(IP11_29_27, PWM0_B),
+ PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1),
/* IPSR12 */
- PINMUX_IPSR_DATA(IP12_2_0, SSI_SCK34),
+ PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1),
PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
- PINMUX_IPSR_DATA(IP12_5_3, SSI_WS34),
+ PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
- PINMUX_IPSR_DATA(IP12_8_6, SSI_SDATA3),
+ PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
- PINMUX_IPSR_DATA(IP12_8_6, DREQ2_N),
+ PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
- PINMUX_IPSR_DATA(IP12_10_9, MLB_CLK),
+ PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP12_10_9, IRD_TX),
+ PINMUX_IPSR_GPSR(IP12_10_9, IRD_TX),
PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
- PINMUX_IPSR_DATA(IP12_12_11, MLB_SIG),
+ PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP12_12_11, IRD_RX),
+ PINMUX_IPSR_GPSR(IP12_12_11, IRD_RX),
PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
- PINMUX_IPSR_DATA(IP12_14_13, MLB_DAT),
+ PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP12_14_13, IRD_SCK),
+ PINMUX_IPSR_GPSR(IP12_14_13, IRD_SCK),
PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
- PINMUX_IPSR_DATA(IP12_17_15, PWM1_B),
- PINMUX_IPSR_DATA(IP12_17_15, IRQ9),
+ PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
+ PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
- PINMUX_IPSR_DATA(IP12_17_15, DACK2),
+ PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2),
- PINMUX_IPSR_DATA(IP12_20_18, VI1_CLK),
+ PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2),
- PINMUX_IPSR_DATA(IP12_23_21, VI1_DATA0),
+ PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
- PINMUX_IPSR_DATA(IP12_26_24, VI1_DATA1),
+ PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),
- PINMUX_IPSR_DATA(IP12_26_24, ATAG0_N),
+ PINMUX_IPSR_GPSR(IP12_26_24, ATAG0_N),
PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
- PINMUX_IPSR_DATA(IP12_29_27, VI1_DATA2),
+ PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),
- PINMUX_IPSR_DATA(IP12_29_27, ATAWR0_N),
+ PINMUX_IPSR_GPSR(IP12_29_27, ATAWR0_N),
PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
/* IPSR13 */
PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
- PINMUX_IPSR_DATA(IP13_2_0, VI1_DATA3),
+ PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0),
- PINMUX_IPSR_DATA(IP13_2_0, ATACS00_N),
+ PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
- PINMUX_IPSR_DATA(IP13_5_3, VI1_DATA4),
+ PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0),
- PINMUX_IPSR_DATA(IP13_5_3, ATACS10_N),
+ PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
- PINMUX_IPSR_DATA(IP13_8_6, PWM2_B),
- PINMUX_IPSR_DATA(IP13_8_6, VI1_DATA5),
+ PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
+ PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0),
- PINMUX_IPSR_DATA(IP13_8_6, EX_WAIT1),
+ PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
- PINMUX_IPSR_DATA(IP13_11_9, VI1_DATA6),
- PINMUX_IPSR_DATA(IP13_11_9, ATARD0_N),
+ PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
+ PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
- PINMUX_IPSR_DATA(IP13_14_12, VI1_DATA7),
- PINMUX_IPSR_DATA(IP13_14_12, ATADIR0_N),
+ PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
+ PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
- PINMUX_IPSR_DATA(IP13_17_15, VI1_CLKENB),
+ PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1),
PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
- PINMUX_IPSR_DATA(IP13_20_18, VI1_FIELD),
+ PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1),
PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
- PINMUX_IPSR_DATA(IP13_23_21, VI1_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1),
PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
- PINMUX_IPSR_DATA(IP13_26_24, VI1_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1),
PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
PINMUX_GPIO_GP_ALL(),
};
+/* - Audio Clock ------------------------------------------------------------ */
+static const unsigned int audio_clka_pins[] = {
+ /* CLKA */
+ RCAR_GP_PIN(5, 20),
+};
+static const unsigned int audio_clka_mux[] = {
+ AUDIO_CLKA_MARK,
+};
+static const unsigned int audio_clka_b_pins[] = {
+ /* CLKA */
+ RCAR_GP_PIN(3, 25),
+};
+static const unsigned int audio_clka_b_mux[] = {
+ AUDIO_CLKA_B_MARK,
+};
+static const unsigned int audio_clka_c_pins[] = {
+ /* CLKA */
+ RCAR_GP_PIN(4, 20),
+};
+static const unsigned int audio_clka_c_mux[] = {
+ AUDIO_CLKA_C_MARK,
+};
+static const unsigned int audio_clka_d_pins[] = {
+ /* CLKA */
+ RCAR_GP_PIN(5, 0),
+};
+static const unsigned int audio_clka_d_mux[] = {
+ AUDIO_CLKA_D_MARK,
+};
+static const unsigned int audio_clkb_pins[] = {
+ /* CLKB */
+ RCAR_GP_PIN(5, 21),
+};
+static const unsigned int audio_clkb_mux[] = {
+ AUDIO_CLKB_MARK,
+};
+static const unsigned int audio_clkb_b_pins[] = {
+ /* CLKB */
+ RCAR_GP_PIN(3, 26),
+};
+static const unsigned int audio_clkb_b_mux[] = {
+ AUDIO_CLKB_B_MARK,
+};
+static const unsigned int audio_clkb_c_pins[] = {
+ /* CLKB */
+ RCAR_GP_PIN(4, 21),
+};
+static const unsigned int audio_clkb_c_mux[] = {
+ AUDIO_CLKB_C_MARK,
+};
+static const unsigned int audio_clkc_pins[] = {
+ /* CLKC */
+ RCAR_GP_PIN(5, 22),
+};
+static const unsigned int audio_clkc_mux[] = {
+ AUDIO_CLKC_MARK,
+};
+static const unsigned int audio_clkc_b_pins[] = {
+ /* CLKC */
+ RCAR_GP_PIN(3, 29),
+};
+static const unsigned int audio_clkc_b_mux[] = {
+ AUDIO_CLKC_B_MARK,
+};
+static const unsigned int audio_clkc_c_pins[] = {
+ /* CLKC */
+ RCAR_GP_PIN(4, 22),
+};
+static const unsigned int audio_clkc_c_mux[] = {
+ AUDIO_CLKC_C_MARK,
+};
+static const unsigned int audio_clkout_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(5, 23),
+};
+static const unsigned int audio_clkout_mux[] = {
+ AUDIO_CLKOUT_MARK,
+};
+static const unsigned int audio_clkout_b_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(3, 12),
+};
+static const unsigned int audio_clkout_b_mux[] = {
+ AUDIO_CLKOUT_B_MARK,
+};
+static const unsigned int audio_clkout_c_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(4, 23),
+};
+static const unsigned int audio_clkout_c_mux[] = {
+ AUDIO_CLKOUT_C_MARK,
+};
+/* - AVB -------------------------------------------------------------------- */
+static const unsigned int avb_link_pins[] = {
+ RCAR_GP_PIN(3, 26),
+};
+static const unsigned int avb_link_mux[] = {
+ AVB_LINK_MARK,
+};
+static const unsigned int avb_magic_pins[] = {
+ RCAR_GP_PIN(3, 27),
+};
+static const unsigned int avb_magic_mux[] = {
+ AVB_MAGIC_MARK,
+};
+static const unsigned int avb_phy_int_pins[] = {
+ RCAR_GP_PIN(3, 28),
+};
+static const unsigned int avb_phy_int_mux[] = {
+ AVB_PHY_INT_MARK,
+};
+static const unsigned int avb_mdio_pins[] = {
+ RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int avb_mdio_mux[] = {
+ AVB_MDC_MARK, AVB_MDIO_MARK,
+};
+static const unsigned int avb_mii_pins[] = {
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+ RCAR_GP_PIN(3, 17),
+
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
+ RCAR_GP_PIN(3, 5),
+
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+ RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int avb_mii_mux[] = {
+ AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+ AVB_TXD3_MARK,
+
+ AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+ AVB_RXD3_MARK,
+
+ AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+ AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
+ AVB_TX_CLK_MARK, AVB_COL_MARK,
+};
+static const unsigned int avb_gmii_pins[] = {
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
+ RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+ RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
+ RCAR_GP_PIN(3, 11),
+};
+static const unsigned int avb_gmii_mux[] = {
+ AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
+ AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
+ AVB_TXD6_MARK, AVB_TXD7_MARK,
+
+ AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
+ AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
+ AVB_RXD6_MARK, AVB_RXD7_MARK,
+
+ AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
+ AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
+ AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
+ AVB_COL_MARK,
+};
+static const unsigned int avb_avtp_capture_pins[] = {
+ RCAR_GP_PIN(5, 11),
+};
+static const unsigned int avb_avtp_capture_mux[] = {
+ AVB_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb_avtp_match_pins[] = {
+ RCAR_GP_PIN(5, 12),
+};
+static const unsigned int avb_avtp_match_mux[] = {
+ AVB_AVTP_MATCH_MARK,
+};
+static const unsigned int avb_avtp_capture_b_pins[] = {
+ RCAR_GP_PIN(1, 1),
+};
+static const unsigned int avb_avtp_capture_b_mux[] = {
+ AVB_AVTP_CAPTURE_B_MARK,
+};
+static const unsigned int avb_avtp_match_b_pins[] = {
+ RCAR_GP_PIN(1, 2),
+};
+static const unsigned int avb_avtp_match_b_mux[] = {
+ AVB_AVTP_MATCH_B_MARK,
+};
/* - ETH -------------------------------------------------------------------- */
static const unsigned int eth_link_pins[] = {
/* LINK */
static const unsigned int sdhi2_wp_mux[] = {
SD2_WP_MARK,
};
+/* - SSI -------------------------------------------------------------------- */
+static const unsigned int ssi0_data_pins[] = {
+ /* SDATA0 */
+ RCAR_GP_PIN(5, 3),
+};
+static const unsigned int ssi0_data_mux[] = {
+ SSI_SDATA0_MARK,
+};
+static const unsigned int ssi0129_ctrl_pins[] = {
+ /* SCK0129, WS0129 */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int ssi0129_ctrl_mux[] = {
+ SSI_SCK0129_MARK, SSI_WS0129_MARK,
+};
+static const unsigned int ssi1_data_pins[] = {
+ /* SDATA1 */
+ RCAR_GP_PIN(5, 13),
+};
+static const unsigned int ssi1_data_mux[] = {
+ SSI_SDATA1_MARK,
+};
+static const unsigned int ssi1_ctrl_pins[] = {
+ /* SCK1, WS1 */
+ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
+};
+static const unsigned int ssi1_ctrl_mux[] = {
+ SSI_SCK1_MARK, SSI_WS1_MARK,
+};
+static const unsigned int ssi1_data_b_pins[] = {
+ /* SDATA1 */
+ RCAR_GP_PIN(4, 13),
+};
+static const unsigned int ssi1_data_b_mux[] = {
+ SSI_SDATA1_B_MARK,
+};
+static const unsigned int ssi1_ctrl_b_pins[] = {
+ /* SCK1, WS1 */
+ RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+};
+static const unsigned int ssi1_ctrl_b_mux[] = {
+ SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
+};
+static const unsigned int ssi2_data_pins[] = {
+ /* SDATA2 */
+ RCAR_GP_PIN(5, 16),
+};
+static const unsigned int ssi2_data_mux[] = {
+ SSI_SDATA2_MARK,
+};
+static const unsigned int ssi2_ctrl_pins[] = {
+ /* SCK2, WS2 */
+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+};
+static const unsigned int ssi2_ctrl_mux[] = {
+ SSI_SCK2_MARK, SSI_WS2_MARK,
+};
+static const unsigned int ssi2_data_b_pins[] = {
+ /* SDATA2 */
+ RCAR_GP_PIN(4, 16),
+};
+static const unsigned int ssi2_data_b_mux[] = {
+ SSI_SDATA2_B_MARK,
+};
+static const unsigned int ssi2_ctrl_b_pins[] = {
+ /* SCK2, WS2 */
+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
+};
+static const unsigned int ssi2_ctrl_b_mux[] = {
+ SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
+};
+static const unsigned int ssi3_data_pins[] = {
+ /* SDATA3 */
+ RCAR_GP_PIN(5, 6),
+};
+static const unsigned int ssi3_data_mux[] = {
+ SSI_SDATA3_MARK
+};
+static const unsigned int ssi34_ctrl_pins[] = {
+ /* SCK34, WS34 */
+ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
+};
+static const unsigned int ssi34_ctrl_mux[] = {
+ SSI_SCK34_MARK, SSI_WS34_MARK,
+};
+static const unsigned int ssi4_data_pins[] = {
+ /* SDATA4 */
+ RCAR_GP_PIN(5, 9),
+};
+static const unsigned int ssi4_data_mux[] = {
+ SSI_SDATA4_MARK,
+};
+static const unsigned int ssi4_ctrl_pins[] = {
+ /* SCK4, WS4 */
+ RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
+};
+static const unsigned int ssi4_ctrl_mux[] = {
+ SSI_SCK4_MARK, SSI_WS4_MARK,
+};
+static const unsigned int ssi4_data_b_pins[] = {
+ /* SDATA4 */
+ RCAR_GP_PIN(4, 22),
+};
+static const unsigned int ssi4_data_b_mux[] = {
+ SSI_SDATA4_B_MARK,
+};
+static const unsigned int ssi4_ctrl_b_pins[] = {
+ /* SCK4, WS4 */
+ RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int ssi4_ctrl_b_mux[] = {
+ SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
+};
+static const unsigned int ssi5_data_pins[] = {
+ /* SDATA5 */
+ RCAR_GP_PIN(4, 26),
+};
+static const unsigned int ssi5_data_mux[] = {
+ SSI_SDATA5_MARK,
+};
+static const unsigned int ssi5_ctrl_pins[] = {
+ /* SCK5, WS5 */
+ RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
+};
+static const unsigned int ssi5_ctrl_mux[] = {
+ SSI_SCK5_MARK, SSI_WS5_MARK,
+};
+static const unsigned int ssi5_data_b_pins[] = {
+ /* SDATA5 */
+ RCAR_GP_PIN(3, 21),
+};
+static const unsigned int ssi5_data_b_mux[] = {
+ SSI_SDATA5_B_MARK,
+};
+static const unsigned int ssi5_ctrl_b_pins[] = {
+ /* SCK5, WS5 */
+ RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
+};
+static const unsigned int ssi5_ctrl_b_mux[] = {
+ SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
+};
+static const unsigned int ssi6_data_pins[] = {
+ /* SDATA6 */
+ RCAR_GP_PIN(4, 29),
+};
+static const unsigned int ssi6_data_mux[] = {
+ SSI_SDATA6_MARK,
+};
+static const unsigned int ssi6_ctrl_pins[] = {
+ /* SCK6, WS6 */
+ RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
+};
+static const unsigned int ssi6_ctrl_mux[] = {
+ SSI_SCK6_MARK, SSI_WS6_MARK,
+};
+static const unsigned int ssi6_data_b_pins[] = {
+ /* SDATA6 */
+ RCAR_GP_PIN(3, 24),
+};
+static const unsigned int ssi6_data_b_mux[] = {
+ SSI_SDATA6_B_MARK,
+};
+static const unsigned int ssi6_ctrl_b_pins[] = {
+ /* SCK6, WS6 */
+ RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+};
+static const unsigned int ssi6_ctrl_b_mux[] = {
+ SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
+};
+static const unsigned int ssi7_data_pins[] = {
+ /* SDATA7 */
+ RCAR_GP_PIN(5, 0),
+};
+static const unsigned int ssi7_data_mux[] = {
+ SSI_SDATA7_MARK,
+};
+static const unsigned int ssi78_ctrl_pins[] = {
+ /* SCK78, WS78 */
+ RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
+};
+static const unsigned int ssi78_ctrl_mux[] = {
+ SSI_SCK78_MARK, SSI_WS78_MARK,
+};
+static const unsigned int ssi7_data_b_pins[] = {
+ /* SDATA7 */
+ RCAR_GP_PIN(3, 27),
+};
+static const unsigned int ssi7_data_b_mux[] = {
+ SSI_SDATA7_B_MARK,
+};
+static const unsigned int ssi78_ctrl_b_pins[] = {
+ /* SCK78, WS78 */
+ RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
+};
+static const unsigned int ssi78_ctrl_b_mux[] = {
+ SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
+};
+static const unsigned int ssi8_data_pins[] = {
+ /* SDATA8 */
+ RCAR_GP_PIN(5, 10),
+};
+static const unsigned int ssi8_data_mux[] = {
+ SSI_SDATA8_MARK,
+};
+static const unsigned int ssi8_data_b_pins[] = {
+ /* SDATA8 */
+ RCAR_GP_PIN(3, 28),
+};
+static const unsigned int ssi8_data_b_mux[] = {
+ SSI_SDATA8_B_MARK,
+};
+static const unsigned int ssi9_data_pins[] = {
+ /* SDATA9 */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int ssi9_data_mux[] = {
+ SSI_SDATA9_MARK,
+};
+static const unsigned int ssi9_ctrl_pins[] = {
+ /* SCK9, WS9 */
+ RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
+};
+static const unsigned int ssi9_ctrl_mux[] = {
+ SSI_SCK9_MARK, SSI_WS9_MARK,
+};
+static const unsigned int ssi9_data_b_pins[] = {
+ /* SDATA9 */
+ RCAR_GP_PIN(4, 19),
+};
+static const unsigned int ssi9_data_b_mux[] = {
+ SSI_SDATA9_B_MARK,
+};
+static const unsigned int ssi9_ctrl_b_pins[] = {
+ /* SCK9, WS9 */
+ RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
+};
+static const unsigned int ssi9_ctrl_b_mux[] = {
+ SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
+};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
RCAR_GP_PIN(5, 24), /* PWEN */
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(audio_clka),
+ SH_PFC_PIN_GROUP(audio_clka_b),
+ SH_PFC_PIN_GROUP(audio_clka_c),
+ SH_PFC_PIN_GROUP(audio_clka_d),
+ SH_PFC_PIN_GROUP(audio_clkb),
+ SH_PFC_PIN_GROUP(audio_clkb_b),
+ SH_PFC_PIN_GROUP(audio_clkb_c),
+ SH_PFC_PIN_GROUP(audio_clkc),
+ SH_PFC_PIN_GROUP(audio_clkc_b),
+ SH_PFC_PIN_GROUP(audio_clkc_c),
+ SH_PFC_PIN_GROUP(audio_clkout),
+ SH_PFC_PIN_GROUP(audio_clkout_b),
+ SH_PFC_PIN_GROUP(audio_clkout_c),
+ SH_PFC_PIN_GROUP(avb_link),
+ SH_PFC_PIN_GROUP(avb_magic),
+ SH_PFC_PIN_GROUP(avb_phy_int),
+ SH_PFC_PIN_GROUP(avb_mdio),
+ SH_PFC_PIN_GROUP(avb_mii),
+ SH_PFC_PIN_GROUP(avb_gmii),
+ SH_PFC_PIN_GROUP(avb_avtp_capture),
+ SH_PFC_PIN_GROUP(avb_avtp_match),
+ SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+ SH_PFC_PIN_GROUP(avb_avtp_match_b),
SH_PFC_PIN_GROUP(eth_link),
SH_PFC_PIN_GROUP(eth_magic),
SH_PFC_PIN_GROUP(eth_mdio),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd),
SH_PFC_PIN_GROUP(sdhi2_wp),
+ SH_PFC_PIN_GROUP(ssi0_data),
+ SH_PFC_PIN_GROUP(ssi0129_ctrl),
+ SH_PFC_PIN_GROUP(ssi1_data),
+ SH_PFC_PIN_GROUP(ssi1_ctrl),
+ SH_PFC_PIN_GROUP(ssi1_data_b),
+ SH_PFC_PIN_GROUP(ssi1_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi2_data),
+ SH_PFC_PIN_GROUP(ssi2_ctrl),
+ SH_PFC_PIN_GROUP(ssi2_data_b),
+ SH_PFC_PIN_GROUP(ssi2_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi3_data),
+ SH_PFC_PIN_GROUP(ssi34_ctrl),
+ SH_PFC_PIN_GROUP(ssi4_data),
+ SH_PFC_PIN_GROUP(ssi4_ctrl),
+ SH_PFC_PIN_GROUP(ssi4_data_b),
+ SH_PFC_PIN_GROUP(ssi4_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi5_data),
+ SH_PFC_PIN_GROUP(ssi5_ctrl),
+ SH_PFC_PIN_GROUP(ssi5_data_b),
+ SH_PFC_PIN_GROUP(ssi5_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi6_data),
+ SH_PFC_PIN_GROUP(ssi6_ctrl),
+ SH_PFC_PIN_GROUP(ssi6_data_b),
+ SH_PFC_PIN_GROUP(ssi6_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi7_data),
+ SH_PFC_PIN_GROUP(ssi78_ctrl),
+ SH_PFC_PIN_GROUP(ssi7_data_b),
+ SH_PFC_PIN_GROUP(ssi78_ctrl_b),
+ SH_PFC_PIN_GROUP(ssi8_data),
+ SH_PFC_PIN_GROUP(ssi8_data_b),
+ SH_PFC_PIN_GROUP(ssi9_data),
+ SH_PFC_PIN_GROUP(ssi9_ctrl),
+ SH_PFC_PIN_GROUP(ssi9_data_b),
+ SH_PFC_PIN_GROUP(ssi9_ctrl_b),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
VIN_DATA_PIN_GROUP(vin0_data, 24),
SH_PFC_PIN_GROUP(vin1_clk),
};
+static const char * const audio_clk_groups[] = {
+ "audio_clka",
+ "audio_clka_b",
+ "audio_clka_c",
+ "audio_clka_d",
+ "audio_clkb",
+ "audio_clkb_b",
+ "audio_clkb_c",
+ "audio_clkc",
+ "audio_clkc_b",
+ "audio_clkc_c",
+ "audio_clkout",
+ "audio_clkout_b",
+ "audio_clkout_c",
+};
+
+static const char * const avb_groups[] = {
+ "avb_link",
+ "avb_magic",
+ "avb_phy_int",
+ "avb_mdio",
+ "avb_mii",
+ "avb_gmii",
+ "avb_avtp_capture",
+ "avb_avtp_match",
+ "avb_avtp_capture_b",
+ "avb_avtp_match_b",
+};
+
static const char * const eth_groups[] = {
"eth_link",
"eth_magic",
"sdhi2_wp",
};
+static const char * const ssi_groups[] = {
+ "ssi0_data",
+ "ssi0129_ctrl",
+ "ssi1_data",
+ "ssi1_ctrl",
+ "ssi1_data_b",
+ "ssi1_ctrl_b",
+ "ssi2_data",
+ "ssi2_ctrl",
+ "ssi2_data_b",
+ "ssi2_ctrl_b",
+ "ssi3_data",
+ "ssi34_ctrl",
+ "ssi4_data",
+ "ssi4_ctrl",
+ "ssi4_data_b",
+ "ssi4_ctrl_b",
+ "ssi5_data",
+ "ssi5_ctrl",
+ "ssi5_data_b",
+ "ssi5_ctrl_b",
+ "ssi6_data",
+ "ssi6_ctrl",
+ "ssi6_data_b",
+ "ssi6_ctrl_b",
+ "ssi7_data",
+ "ssi78_ctrl",
+ "ssi7_data_b",
+ "ssi78_ctrl_b",
+ "ssi8_data",
+ "ssi8_data_b",
+ "ssi9_data",
+ "ssi9_ctrl",
+ "ssi9_data_b",
+ "ssi9_ctrl_b",
+};
+
static const char * const usb0_groups[] = {
"usb0",
};
};
static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(audio_clk),
+ SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(eth),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(vin0),
FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
/* IP6_3_2 [2] */
FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
+ 0,
/* IP6_1_0 [2] */
FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
},
#define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
#define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
#define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
-#define GPSR6_1 F_(SSI_WS0129, IP13_27_24)
-#define GPSR6_0 F_(SSI_SCK0129, IP13_23_20)
+#define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
+#define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
/* GPSR7 */
#define GPSR7_3 FM(HDMI1_CEC)
#define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_23_20 FM(SSI_SCK0129) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_27_24 FM(SSI_WS0129) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
-#define MOD_SEL2_2_1 FM(SEL_VSP_0) FM(SEL_VSP_1) FM(SEL_VSP_2) FM(SEL_VSP_3)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
#define PINMUX_MOD_SELS\
MOD_SEL0_5_4 MOD_SEL1_5 \
MOD_SEL1_4 \
MOD_SEL0_3 MOD_SEL1_3 \
-MOD_SEL0_2_1 MOD_SEL1_2 MOD_SEL2_2_1 \
+MOD_SEL0_2_1 MOD_SEL1_2 \
MOD_SEL1_1 \
MOD_SEL1_0 MOD_SEL2_0
PINMUX_SINGLE(SSI_WS5),
/* IPSR0 */
- PINMUX_IPSR_DATA(IP0_3_0, AVB_MDC),
+ PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
- PINMUX_IPSR_DATA(IP0_7_4, AVB_MAGIC),
+ PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
- PINMUX_IPSR_DATA(IP0_11_8, AVB_PHY_INT),
+ PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
- PINMUX_IPSR_DATA(IP0_15_12, AVB_LINK),
+ PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
- PINMUX_IPSR_DATA(IP0_27_24, IRQ0),
- PINMUX_IPSR_DATA(IP0_27_24, QPOLB),
- PINMUX_IPSR_DATA(IP0_27_24, DU_CDE),
+ PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
+ PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
+ PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
- PINMUX_IPSR_DATA(IP0_31_28, IRQ1),
- PINMUX_IPSR_DATA(IP0_31_28, QPOLA),
- PINMUX_IPSR_DATA(IP0_31_28, DU_DISP),
+ PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
+ PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
+ PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
/* IPSR1 */
- PINMUX_IPSR_DATA(IP1_3_0, IRQ2),
- PINMUX_IPSR_DATA(IP1_3_0, QCPV_QDE),
- PINMUX_IPSR_DATA(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
+ PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
+ PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
- PINMUX_IPSR_DATA(IP1_7_4, IRQ3),
- PINMUX_IPSR_DATA(IP1_7_4, QSTVB_QVE),
- PINMUX_IPSR_DATA(IP1_7_4, A25),
- PINMUX_IPSR_DATA(IP1_7_4, DU_DOTCLKOUT1),
+ PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
+ PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
+ PINMUX_IPSR_GPSR(IP1_7_4, A25),
+ PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
- PINMUX_IPSR_DATA(IP1_11_8, IRQ4),
- PINMUX_IPSR_DATA(IP1_11_8, QSTH_QHS),
- PINMUX_IPSR_DATA(IP1_11_8, A24),
- PINMUX_IPSR_DATA(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
+ PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
+ PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
+ PINMUX_IPSR_GPSR(IP1_11_8, A24),
+ PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
- PINMUX_IPSR_DATA(IP1_15_12, IRQ5),
- PINMUX_IPSR_DATA(IP1_15_12, QSTB_QHE),
- PINMUX_IPSR_DATA(IP1_15_12, A23),
- PINMUX_IPSR_DATA(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
+ PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
+ PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
+ PINMUX_IPSR_GPSR(IP1_15_12, A23),
+ PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
- PINMUX_IPSR_DATA(IP1_19_16, PWM0),
- PINMUX_IPSR_DATA(IP1_19_16, AVB_AVTP_PPS),
- PINMUX_IPSR_DATA(IP1_19_16, A22),
+ PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
+ PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
+ PINMUX_IPSR_GPSR(IP1_19_16, A22),
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
- PINMUX_IPSR_DATA(IP1_23_20, A21),
+ PINMUX_IPSR_GPSR(IP1_23_20, A21),
PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
- PINMUX_IPSR_DATA(IP1_27_24, A20),
+ PINMUX_IPSR_GPSR(IP1_27_24, A20),
PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
- PINMUX_IPSR_DATA(IP1_31_28, A0),
- PINMUX_IPSR_DATA(IP1_31_28, LCDOUT16),
+ PINMUX_IPSR_GPSR(IP1_31_28, A0),
+ PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
- PINMUX_IPSR_DATA(IP1_31_28, VI4_DATA8),
- PINMUX_IPSR_DATA(IP1_31_28, DU_DB0),
+ PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
+ PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
/* IPSR2 */
- PINMUX_IPSR_DATA(IP2_3_0, A1),
- PINMUX_IPSR_DATA(IP2_3_0, LCDOUT17),
+ PINMUX_IPSR_GPSR(IP2_3_0, A1),
+ PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
- PINMUX_IPSR_DATA(IP2_3_0, VI4_DATA9),
- PINMUX_IPSR_DATA(IP2_3_0, DU_DB1),
+ PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
+ PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
- PINMUX_IPSR_DATA(IP2_7_4, A2),
- PINMUX_IPSR_DATA(IP2_7_4, LCDOUT18),
+ PINMUX_IPSR_GPSR(IP2_7_4, A2),
+ PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
- PINMUX_IPSR_DATA(IP2_7_4, VI4_DATA10),
- PINMUX_IPSR_DATA(IP2_7_4, DU_DB2),
+ PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
+ PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
- PINMUX_IPSR_DATA(IP2_11_8, A3),
- PINMUX_IPSR_DATA(IP2_11_8, LCDOUT19),
+ PINMUX_IPSR_GPSR(IP2_11_8, A3),
+ PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
- PINMUX_IPSR_DATA(IP2_11_8, VI4_DATA11),
- PINMUX_IPSR_DATA(IP2_11_8, DU_DB3),
+ PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
+ PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
- PINMUX_IPSR_DATA(IP2_15_12, A4),
- PINMUX_IPSR_DATA(IP2_15_12, LCDOUT20),
+ PINMUX_IPSR_GPSR(IP2_15_12, A4),
+ PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
- PINMUX_IPSR_DATA(IP2_15_12, VI4_DATA12),
- PINMUX_IPSR_DATA(IP2_15_12, VI5_DATA12),
- PINMUX_IPSR_DATA(IP2_15_12, DU_DB4),
+ PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
+ PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
+ PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
- PINMUX_IPSR_DATA(IP2_19_16, A5),
- PINMUX_IPSR_DATA(IP2_19_16, LCDOUT21),
+ PINMUX_IPSR_GPSR(IP2_19_16, A5),
+ PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
- PINMUX_IPSR_DATA(IP2_19_16, VI4_DATA13),
- PINMUX_IPSR_DATA(IP2_19_16, VI5_DATA13),
- PINMUX_IPSR_DATA(IP2_19_16, DU_DB5),
+ PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
+ PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
+ PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
- PINMUX_IPSR_DATA(IP2_23_20, A6),
- PINMUX_IPSR_DATA(IP2_23_20, LCDOUT22),
+ PINMUX_IPSR_GPSR(IP2_23_20, A6),
+ PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
- PINMUX_IPSR_DATA(IP2_23_20, VI4_DATA14),
- PINMUX_IPSR_DATA(IP2_23_20, VI5_DATA14),
- PINMUX_IPSR_DATA(IP2_23_20, DU_DB6),
+ PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
+ PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
+ PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
- PINMUX_IPSR_DATA(IP2_27_24, A7),
- PINMUX_IPSR_DATA(IP2_27_24, LCDOUT23),
+ PINMUX_IPSR_GPSR(IP2_27_24, A7),
+ PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
- PINMUX_IPSR_DATA(IP2_27_24, VI4_DATA15),
- PINMUX_IPSR_DATA(IP2_27_24, VI5_DATA15),
- PINMUX_IPSR_DATA(IP2_27_24, DU_DB7),
+ PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
+ PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
+ PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
- PINMUX_IPSR_DATA(IP2_31_28, A8),
+ PINMUX_IPSR_GPSR(IP2_31_28, A8),
PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
/* IPSR3 */
- PINMUX_IPSR_DATA(IP3_3_0, A9),
+ PINMUX_IPSR_GPSR(IP3_3_0, A9),
PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
- PINMUX_IPSR_DATA(IP3_3_0, VI5_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
- PINMUX_IPSR_DATA(IP3_7_4, A10),
+ PINMUX_IPSR_GPSR(IP3_7_4, A10),
PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
- PINMUX_IPSR_DATA(IP3_7_4, VI5_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
- PINMUX_IPSR_DATA(IP3_11_8, A11),
+ PINMUX_IPSR_GPSR(IP3_11_8, A11),
PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
- PINMUX_IPSR_DATA(IP3_11_8, HSCK4),
- PINMUX_IPSR_DATA(IP3_11_8, VI5_FIELD),
+ PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
+ PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
- PINMUX_IPSR_DATA(IP3_15_12, A12),
- PINMUX_IPSR_DATA(IP3_15_12, LCDOUT12),
+ PINMUX_IPSR_GPSR(IP3_15_12, A12),
+ PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
- PINMUX_IPSR_DATA(IP3_15_12, VI5_DATA8),
- PINMUX_IPSR_DATA(IP3_15_12, DU_DG4),
+ PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
+ PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
- PINMUX_IPSR_DATA(IP3_19_16, A13),
- PINMUX_IPSR_DATA(IP3_19_16, LCDOUT13),
+ PINMUX_IPSR_GPSR(IP3_19_16, A13),
+ PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
- PINMUX_IPSR_DATA(IP3_19_16, VI5_DATA9),
- PINMUX_IPSR_DATA(IP3_19_16, DU_DG5),
+ PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
+ PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
- PINMUX_IPSR_DATA(IP3_23_20, A14),
- PINMUX_IPSR_DATA(IP3_23_20, LCDOUT14),
+ PINMUX_IPSR_GPSR(IP3_23_20, A14),
+ PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
- PINMUX_IPSR_DATA(IP3_23_20, HCTS4_N),
- PINMUX_IPSR_DATA(IP3_23_20, VI5_DATA10),
- PINMUX_IPSR_DATA(IP3_23_20, DU_DG6),
+ PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
+ PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
+ PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
- PINMUX_IPSR_DATA(IP3_27_24, A15),
- PINMUX_IPSR_DATA(IP3_27_24, LCDOUT15),
+ PINMUX_IPSR_GPSR(IP3_27_24, A15),
+ PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
- PINMUX_IPSR_DATA(IP3_27_24, HRTS4_N),
- PINMUX_IPSR_DATA(IP3_27_24, VI5_DATA11),
- PINMUX_IPSR_DATA(IP3_27_24, DU_DG7),
+ PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
+ PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
+ PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
- PINMUX_IPSR_DATA(IP3_31_28, A16),
- PINMUX_IPSR_DATA(IP3_31_28, LCDOUT8),
- PINMUX_IPSR_DATA(IP3_31_28, VI4_FIELD),
- PINMUX_IPSR_DATA(IP3_31_28, DU_DG0),
+ PINMUX_IPSR_GPSR(IP3_31_28, A16),
+ PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
+ PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
+ PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
/* IPSR4 */
- PINMUX_IPSR_DATA(IP4_3_0, A17),
- PINMUX_IPSR_DATA(IP4_3_0, LCDOUT9),
- PINMUX_IPSR_DATA(IP4_3_0, VI4_VSYNC_N),
- PINMUX_IPSR_DATA(IP4_3_0, DU_DG1),
-
- PINMUX_IPSR_DATA(IP4_7_4, A18),
- PINMUX_IPSR_DATA(IP4_7_4, LCDOUT10),
- PINMUX_IPSR_DATA(IP4_7_4, VI4_HSYNC_N),
- PINMUX_IPSR_DATA(IP4_7_4, DU_DG2),
-
- PINMUX_IPSR_DATA(IP4_11_8, A19),
- PINMUX_IPSR_DATA(IP4_11_8, LCDOUT11),
- PINMUX_IPSR_DATA(IP4_11_8, VI4_CLKENB),
- PINMUX_IPSR_DATA(IP4_11_8, DU_DG3),
-
- PINMUX_IPSR_DATA(IP4_15_12, CS0_N),
- PINMUX_IPSR_DATA(IP4_15_12, VI5_CLKENB),
-
- PINMUX_IPSR_DATA(IP4_19_16, CS1_N_A26),
- PINMUX_IPSR_DATA(IP4_19_16, VI5_CLK),
+ PINMUX_IPSR_GPSR(IP4_3_0, A17),
+ PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
+ PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
+
+ PINMUX_IPSR_GPSR(IP4_7_4, A18),
+ PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
+ PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
+
+ PINMUX_IPSR_GPSR(IP4_11_8, A19),
+ PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
+ PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
+ PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
+
+ PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
+ PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
+
+ PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
+ PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
- PINMUX_IPSR_DATA(IP4_23_20, BS_N),
- PINMUX_IPSR_DATA(IP4_23_20, QSTVA_QVS),
+ PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
+ PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
- PINMUX_IPSR_DATA(IP4_23_20, SCK3),
- PINMUX_IPSR_DATA(IP4_23_20, HSCK3),
- PINMUX_IPSR_DATA(IP4_23_20, CAN1_TX),
- PINMUX_IPSR_DATA(IP4_23_20, CANFD1_TX),
+ PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
+ PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
+ PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
+ PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
- PINMUX_IPSR_DATA(IP4_27_24, RD_N),
+ PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
- PINMUX_IPSR_DATA(IP4_31_28, RD_WR_N),
+ PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
/* IPSR5 */
- PINMUX_IPSR_DATA(IP5_3_0, WE0_N),
+ PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
- PINMUX_IPSR_DATA(IP5_3_0, CTS3_N),
- PINMUX_IPSR_DATA(IP5_3_0, HCTS3_N),
+ PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
+ PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
- PINMUX_IPSR_DATA(IP5_3_0, CAN_CLK),
+ PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
- PINMUX_IPSR_DATA(IP5_7_4, WE1_N),
+ PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
- PINMUX_IPSR_DATA(IP5_7_4, RTS3_N_TANS),
- PINMUX_IPSR_DATA(IP5_7_4, HRTS3_N),
+ PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
+ PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
- PINMUX_IPSR_DATA(IP5_7_4, CAN1_RX),
- PINMUX_IPSR_DATA(IP5_7_4, CANFD1_RX),
+ PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
+ PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
- PINMUX_IPSR_DATA(IP5_11_8, QCLK),
- PINMUX_IPSR_DATA(IP5_11_8, VI4_CLK),
- PINMUX_IPSR_DATA(IP5_11_8, DU_DOTCLKOUT0),
+ PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
+ PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
+ PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
- PINMUX_IPSR_DATA(IP5_15_12, D0),
+ PINMUX_IPSR_GPSR(IP5_15_12, D0),
PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
- PINMUX_IPSR_DATA(IP5_15_12, VI4_DATA16),
- PINMUX_IPSR_DATA(IP5_15_12, VI5_DATA0),
+ PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
+ PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
- PINMUX_IPSR_DATA(IP5_19_16, D1),
+ PINMUX_IPSR_GPSR(IP5_19_16, D1),
PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
- PINMUX_IPSR_DATA(IP5_19_16, VI4_DATA17),
- PINMUX_IPSR_DATA(IP5_19_16, VI5_DATA1),
+ PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
+ PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
- PINMUX_IPSR_DATA(IP5_23_20, D2),
+ PINMUX_IPSR_GPSR(IP5_23_20, D2),
PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
- PINMUX_IPSR_DATA(IP5_23_20, VI4_DATA18),
- PINMUX_IPSR_DATA(IP5_23_20, VI5_DATA2),
+ PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
+ PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
- PINMUX_IPSR_DATA(IP5_27_24, D3),
+ PINMUX_IPSR_GPSR(IP5_27_24, D3),
PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
- PINMUX_IPSR_DATA(IP5_27_24, VI4_DATA19),
- PINMUX_IPSR_DATA(IP5_27_24, VI5_DATA3),
+ PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
+ PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
- PINMUX_IPSR_DATA(IP5_31_28, D4),
+ PINMUX_IPSR_GPSR(IP5_31_28, D4),
PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
- PINMUX_IPSR_DATA(IP5_31_28, VI4_DATA20),
- PINMUX_IPSR_DATA(IP5_31_28, VI5_DATA4),
+ PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
+ PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
/* IPSR6 */
- PINMUX_IPSR_DATA(IP6_3_0, D5),
+ PINMUX_IPSR_GPSR(IP6_3_0, D5),
PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
- PINMUX_IPSR_DATA(IP6_3_0, VI4_DATA21),
- PINMUX_IPSR_DATA(IP6_3_0, VI5_DATA5),
+ PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
+ PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
- PINMUX_IPSR_DATA(IP6_7_4, D6),
+ PINMUX_IPSR_GPSR(IP6_7_4, D6),
PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
- PINMUX_IPSR_DATA(IP6_7_4, VI4_DATA22),
- PINMUX_IPSR_DATA(IP6_7_4, VI5_DATA6),
+ PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
+ PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
- PINMUX_IPSR_DATA(IP6_11_8, D7),
+ PINMUX_IPSR_GPSR(IP6_11_8, D7),
PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
- PINMUX_IPSR_DATA(IP6_11_8, VI4_DATA23),
- PINMUX_IPSR_DATA(IP6_11_8, VI5_DATA7),
+ PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
+ PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
- PINMUX_IPSR_DATA(IP6_15_12, D8),
- PINMUX_IPSR_DATA(IP6_15_12, LCDOUT0),
+ PINMUX_IPSR_GPSR(IP6_15_12, D8),
+ PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
- PINMUX_IPSR_DATA(IP6_15_12, DU_DR0),
+ PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
- PINMUX_IPSR_DATA(IP6_19_16, D9),
- PINMUX_IPSR_DATA(IP6_19_16, LCDOUT1),
+ PINMUX_IPSR_GPSR(IP6_19_16, D9),
+ PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
- PINMUX_IPSR_DATA(IP6_19_16, DU_DR1),
+ PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
- PINMUX_IPSR_DATA(IP6_23_20, D10),
- PINMUX_IPSR_DATA(IP6_23_20, LCDOUT2),
+ PINMUX_IPSR_GPSR(IP6_23_20, D10),
+ PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
- PINMUX_IPSR_DATA(IP6_23_20, DU_DR2),
+ PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
- PINMUX_IPSR_DATA(IP6_27_24, D11),
- PINMUX_IPSR_DATA(IP6_27_24, LCDOUT3),
+ PINMUX_IPSR_GPSR(IP6_27_24, D11),
+ PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
- PINMUX_IPSR_DATA(IP6_27_24, DU_DR3),
+ PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
- PINMUX_IPSR_DATA(IP6_31_28, D12),
- PINMUX_IPSR_DATA(IP6_31_28, LCDOUT4),
+ PINMUX_IPSR_GPSR(IP6_31_28, D12),
+ PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
- PINMUX_IPSR_DATA(IP6_31_28, DU_DR4),
+ PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
/* IPSR7 */
- PINMUX_IPSR_DATA(IP7_3_0, D13),
- PINMUX_IPSR_DATA(IP7_3_0, LCDOUT5),
+ PINMUX_IPSR_GPSR(IP7_3_0, D13),
+ PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
- PINMUX_IPSR_DATA(IP7_3_0, DU_DR5),
+ PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
- PINMUX_IPSR_DATA(IP7_7_4, D14),
- PINMUX_IPSR_DATA(IP7_7_4, LCDOUT6),
+ PINMUX_IPSR_GPSR(IP7_7_4, D14),
+ PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
- PINMUX_IPSR_DATA(IP7_7_4, DU_DR6),
+ PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
- PINMUX_IPSR_DATA(IP7_11_8, D15),
- PINMUX_IPSR_DATA(IP7_11_8, LCDOUT7),
+ PINMUX_IPSR_GPSR(IP7_11_8, D15),
+ PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
- PINMUX_IPSR_DATA(IP7_11_8, DU_DR7),
+ PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
- PINMUX_IPSR_DATA(IP7_15_12, FSCLKST),
+ PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
- PINMUX_IPSR_DATA(IP7_19_16, SD0_CLK),
+ PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
- PINMUX_IPSR_DATA(IP7_23_20, SD0_CMD),
+ PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
- PINMUX_IPSR_DATA(IP7_27_24, SD0_DAT0),
+ PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
- PINMUX_IPSR_DATA(IP7_31_28, SD0_DAT1),
+ PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
/* IPSR8 */
- PINMUX_IPSR_DATA(IP8_3_0, SD0_DAT2),
+ PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
- PINMUX_IPSR_DATA(IP8_7_4, SD0_DAT3),
+ PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
- PINMUX_IPSR_DATA(IP8_11_8, SD1_CLK),
+ PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
- PINMUX_IPSR_DATA(IP8_15_12, SD1_CMD),
+ PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
- PINMUX_IPSR_DATA(IP8_19_16, SD1_DAT0),
- PINMUX_IPSR_DATA(IP8_19_16, SD2_DAT4),
+ PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
+ PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
- PINMUX_IPSR_DATA(IP8_23_20, SD1_DAT1),
- PINMUX_IPSR_DATA(IP8_23_20, SD2_DAT5),
+ PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
+ PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
- PINMUX_IPSR_DATA(IP8_27_24, SD1_DAT2),
- PINMUX_IPSR_DATA(IP8_27_24, SD2_DAT6),
+ PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
+ PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
- PINMUX_IPSR_DATA(IP8_31_28, SD1_DAT3),
- PINMUX_IPSR_DATA(IP8_31_28, SD2_DAT7),
+ PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
+ PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
/* IPSR9 */
- PINMUX_IPSR_DATA(IP9_3_0, SD2_CLK),
+ PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
- PINMUX_IPSR_DATA(IP9_7_4, SD2_DAT0),
+ PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
- PINMUX_IPSR_DATA(IP9_11_8, SD2_DAT1),
+ PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
- PINMUX_IPSR_DATA(IP9_15_12, SD2_DAT2),
+ PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
- PINMUX_IPSR_DATA(IP9_19_16, SD2_DAT3),
+ PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
- PINMUX_IPSR_DATA(IP9_23_20, SD2_DS),
+ PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
- PINMUX_IPSR_DATA(IP9_27_24, SD3_DAT4),
+ PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
- PINMUX_IPSR_DATA(IP9_31_28, SD3_DAT5),
+ PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
/* IPSR10 */
- PINMUX_IPSR_DATA(IP10_3_0, SD3_DAT6),
- PINMUX_IPSR_DATA(IP10_3_0, SD3_CD),
+ PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
+ PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
- PINMUX_IPSR_DATA(IP10_7_4, SD3_DAT7),
- PINMUX_IPSR_DATA(IP10_7_4, SD3_WP),
+ PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
+ PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
- PINMUX_IPSR_DATA(IP10_11_8, SD0_CD),
+ PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
- PINMUX_IPSR_DATA(IP10_15_12, SD0_WP),
+ PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
- PINMUX_IPSR_DATA(IP10_19_16, SD1_CD),
+ PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD),
PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
- PINMUX_IPSR_DATA(IP10_23_20, SD1_WP),
+ PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP),
PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1),
- PINMUX_IPSR_DATA(IP10_27_24, SCK0),
+ PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
- PINMUX_IPSR_DATA(IP10_27_24, ADICHS2),
+ PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
- PINMUX_IPSR_DATA(IP10_31_28, RX0),
+ PINMUX_IPSR_GPSR(IP10_31_28, RX0),
PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
/* IPSR11 */
- PINMUX_IPSR_DATA(IP11_3_0, TX0),
+ PINMUX_IPSR_GPSR(IP11_3_0, TX0),
PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
- PINMUX_IPSR_DATA(IP11_7_4, CTS0_N),
+ PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
- PINMUX_IPSR_DATA(IP11_7_4, ADICS_SAMP),
+ PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
- PINMUX_IPSR_DATA(IP11_11_8, RTS0_N_TANS),
+ PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS),
PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
- PINMUX_IPSR_DATA(IP11_11_8, ADICHS1),
+ PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
- PINMUX_IPSR_DATA(IP11_23_20, CTS1_N),
+ PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
- PINMUX_IPSR_DATA(IP11_23_20, ADIDATA),
+ PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
- PINMUX_IPSR_DATA(IP11_27_24, RTS1_N_TANS),
+ PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
- PINMUX_IPSR_DATA(IP11_27_24, ADICHS0),
+ PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
- PINMUX_IPSR_DATA(IP11_31_28, SCK2),
+ PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
- PINMUX_IPSR_DATA(IP11_31_28, ADICLK),
+ PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
/* IPSR12 */
PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
- PINMUX_IPSR_DATA(IP12_11_8, HSCK0),
+ PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
- PINMUX_IPSR_DATA(IP12_15_12, HRX0),
+ PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
- PINMUX_IPSR_DATA(IP12_19_16, HTX0),
+ PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
- PINMUX_IPSR_DATA(IP12_23_20, HCTS0_N),
+ PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
- PINMUX_IPSR_DATA(IP12_27_24, HRTS0_N),
+ PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
- PINMUX_IPSR_DATA(IP12_31_28, MSIOF0_SYNC),
+ PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
/* IPSR13 */
- PINMUX_IPSR_DATA(IP13_3_0, MSIOF0_SS1),
- PINMUX_IPSR_DATA(IP13_3_0, RX5),
+ PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
+ PINMUX_IPSR_GPSR(IP13_3_0, RX5),
PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
- PINMUX_IPSR_DATA(IP13_7_4, MSIOF0_SS2),
- PINMUX_IPSR_DATA(IP13_7_4, TX5),
+ PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
+ PINMUX_IPSR_GPSR(IP13_7_4, TX5),
PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
- PINMUX_IPSR_DATA(IP13_11_8, MLB_CLK),
+ PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
- PINMUX_IPSR_DATA(IP13_15_12, MLB_SIG),
+ PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
- PINMUX_IPSR_DATA(IP13_19_16, MLB_DAT),
+ PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
- PINMUX_IPSR_DATA(IP13_23_20, SSI_SCK0129),
+ PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
- PINMUX_IPSR_DATA(IP13_27_24, SSI_WS0129),
+ PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
- PINMUX_IPSR_DATA(IP13_31_28, SSI_SDATA0),
+ PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
/* IPSR14 */
PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
- PINMUX_IPSR_DATA(IP14_11_8, SSI_SCK34),
+ PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK34),
PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
- PINMUX_IPSR_DATA(IP14_15_12, SSI_WS34),
+ PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS34),
PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
- PINMUX_IPSR_DATA(IP14_19_16, SSI_SDATA3),
+ PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
- PINMUX_IPSR_DATA(IP14_23_20, SSI_SCK4),
+ PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
- PINMUX_IPSR_DATA(IP14_27_24, SSI_WS4),
+ PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
- PINMUX_IPSR_DATA(IP14_31_28, SSI_SDATA4),
+ PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
/* IPSR15 */
- PINMUX_IPSR_DATA(IP15_3_0, SSI_SCK6),
- PINMUX_IPSR_DATA(IP15_3_0, USB2_PWEN),
+ PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
+ PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
- PINMUX_IPSR_DATA(IP15_7_4, SSI_WS6),
- PINMUX_IPSR_DATA(IP15_7_4, USB2_OVC),
+ PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
+ PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
- PINMUX_IPSR_DATA(IP15_11_8, SSI_SDATA6),
+ PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
- PINMUX_IPSR_DATA(IP15_15_12, SSI_SCK78),
+ PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
- PINMUX_IPSR_DATA(IP15_19_16, SSI_WS78),
+ PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
- PINMUX_IPSR_DATA(IP15_23_20, SSI_SDATA7),
+ PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
- PINMUX_IPSR_DATA(IP15_27_24, SSI_SDATA8),
+ PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
- PINMUX_IPSR_DATA(IP15_31_28, SCK1),
+ PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
- PINMUX_IPSR_DATA(IP15_31_28, SCK5),
+ PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
/* IPSR16 */
PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
- PINMUX_IPSR_DATA(IP16_3_0, CC5_OSCOUT),
+ PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT),
PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
- PINMUX_IPSR_DATA(IP16_11_8, USB0_PWEN),
+ PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
- PINMUX_IPSR_DATA(IP16_15_12, USB0_OVC),
+ PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
- PINMUX_IPSR_DATA(IP16_19_16, USB1_PWEN),
+ PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
- PINMUX_IPSR_DATA(IP16_23_20, USB1_OVC),
+ PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
- PINMUX_IPSR_DATA(IP16_27_24, USB30_PWEN),
+ PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
- PINMUX_IPSR_DATA(IP16_27_24, TPU0TO0),
+ PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
- PINMUX_IPSR_DATA(IP16_31_28, USB30_OVC),
+ PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
- PINMUX_IPSR_DATA(IP16_31_28, TPU0TO1),
+ PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
/* IPSR17 */
- PINMUX_IPSR_DATA(IP17_3_0, USB31_PWEN),
+ PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
- PINMUX_IPSR_DATA(IP17_3_0, TPU0TO2),
+ PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
- PINMUX_IPSR_DATA(IP17_7_4, USB31_OVC),
+ PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
- PINMUX_IPSR_DATA(IP17_7_4, TPU0TO3),
+ PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
/* I2C */
PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
AVB_AVTP_CAPTURE_B_MARK,
};
+/* - CAN ------------------------------------------------------------------ */
+static const unsigned int can0_data_a_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
+};
+static const unsigned int can0_data_a_mux[] = {
+ CAN0_TX_A_MARK, CAN0_RX_A_MARK,
+};
+static const unsigned int can0_data_b_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int can0_data_b_mux[] = {
+ CAN0_TX_B_MARK, CAN0_RX_B_MARK,
+};
+static const unsigned int can1_data_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
+};
+static const unsigned int can1_data_mux[] = {
+ CAN1_TX_MARK, CAN1_RX_MARK,
+};
+
+/* - CAN Clock -------------------------------------------------------------- */
+static const unsigned int can_clk_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int can_clk_mux[] = {
+ CAN_CLK_MARK,
+};
+
+/* - CAN FD --------------------------------------------------------------- */
+static const unsigned int canfd0_data_a_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
+};
+static const unsigned int canfd0_data_a_mux[] = {
+ CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
+};
+static const unsigned int canfd0_data_b_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int canfd0_data_b_mux[] = {
+ CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
+};
+static const unsigned int canfd1_data_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
+};
+static const unsigned int canfd1_data_mux[] = {
+ CANFD1_TX_MARK, CANFD1_RX_MARK,
+};
+
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
SDA6_C_MARK, SCL6_C_MARK,
};
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+ /* IRQ0 */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+ /* IRQ1 */
+ RCAR_GP_PIN(2, 1),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+ /* IRQ2 */
+ RCAR_GP_PIN(2, 2),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+ /* IRQ3 */
+ RCAR_GP_PIN(2, 3),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+ IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+ /* IRQ4 */
+ RCAR_GP_PIN(2, 4),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+ IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+ /* IRQ5 */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+ IRQ5_MARK,
+};
+
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
MSIOF3_RXD_D_MARK,
};
+/* - PWM0 --------------------------------------------------------------------*/
+static const unsigned int pwm0_pins[] = {
+ /* PWM */
+ RCAR_GP_PIN(2, 6),
+};
+static const unsigned int pwm0_mux[] = {
+ PWM0_MARK,
+};
+/* - PWM1 --------------------------------------------------------------------*/
+static const unsigned int pwm1_a_pins[] = {
+ /* PWM */
+ RCAR_GP_PIN(2, 7),
+};
+static const unsigned int pwm1_a_mux[] = {
+ PWM1_A_MARK,
+};
+static const unsigned int pwm1_b_pins[] = {
+ /* PWM */
+ RCAR_GP_PIN(1, 8),
+};
+static const unsigned int pwm1_b_mux[] = {
+ PWM1_B_MARK,
+};
+/* - PWM2 --------------------------------------------------------------------*/
+static const unsigned int pwm2_a_pins[] = {
+ /* PWM */
+ RCAR_GP_PIN(2, 8),
+};
+static const unsigned int pwm2_a_mux[] = {
+ PWM2_A_MARK,
+};
+static const unsigned int pwm2_b_pins[] = {
+ /* PWM */
+ RCAR_GP_PIN(1, 11),
+};
+static const unsigned int pwm2_b_mux[] = {
+ PWM2_B_MARK,
+};
+/* - PWM3 --------------------------------------------------------------------*/
+static const unsigned int pwm3_a_pins[] = {
+ /* PWM */
+ RCAR_GP_PIN(1, 0),
+};
+static const unsigned int pwm3_a_mux[] = {
+ PWM3_A_MARK,
+};
+static const unsigned int pwm3_b_pins[] = {
+ /* PWM */
+ RCAR_GP_PIN(2, 2),
+};
+static const unsigned int pwm3_b_mux[] = {
+ PWM3_B_MARK,
+};
+/* - PWM4 --------------------------------------------------------------------*/
+static const unsigned int pwm4_a_pins[] = {
+ /* PWM */
+ RCAR_GP_PIN(1, 1),
+};
+static const unsigned int pwm4_a_mux[] = {
+ PWM4_A_MARK,
+};
+static const unsigned int pwm4_b_pins[] = {
+ /* PWM */
+ RCAR_GP_PIN(2, 3),
+};
+static const unsigned int pwm4_b_mux[] = {
+ PWM4_B_MARK,
+};
+/* - PWM5 --------------------------------------------------------------------*/
+static const unsigned int pwm5_a_pins[] = {
+ /* PWM */
+ RCAR_GP_PIN(1, 2),
+};
+static const unsigned int pwm5_a_mux[] = {
+ PWM5_A_MARK,
+};
+static const unsigned int pwm5_b_pins[] = {
+ /* PWM */
+ RCAR_GP_PIN(2, 4),
+};
+static const unsigned int pwm5_b_mux[] = {
+ PWM5_B_MARK,
+};
+/* - PWM6 --------------------------------------------------------------------*/
+static const unsigned int pwm6_a_pins[] = {
+ /* PWM */
+ RCAR_GP_PIN(1, 3),
+};
+static const unsigned int pwm6_a_mux[] = {
+ PWM6_A_MARK,
+};
+static const unsigned int pwm6_b_pins[] = {
+ /* PWM */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int pwm6_b_mux[] = {
+ PWM6_B_MARK,
+};
+
/* - SATA --------------------------------------------------------------------*/
static const unsigned int sata0_devslp_a_pins[] = {
/* DEVSLP */
RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
};
static const unsigned int ssi01239_ctrl_mux[] = {
- SSI_SCK0129_MARK, SSI_WS0129_MARK,
+ SSI_SCK01239_MARK, SSI_WS01239_MARK,
};
static const unsigned int ssi1_data_a_pins[] = {
/* SDATA */
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
};
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_pins[] = {
+ /* PWEN, OVC */
+ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+};
+static const unsigned int usb0_mux[] = {
+ USB0_PWEN_MARK, USB0_OVC_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_pins[] = {
+ /* PWEN, OVC */
+ RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
+};
+static const unsigned int usb1_mux[] = {
+ USB1_PWEN_MARK, USB1_OVC_MARK,
+};
+/* - USB2 ------------------------------------------------------------------- */
+static const unsigned int usb2_pins[] = {
+ /* PWEN, OVC */
+ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
+};
+static const unsigned int usb2_mux[] = {
+ USB2_PWEN_MARK, USB2_OVC_MARK,
+};
+
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
SH_PFC_PIN_GROUP(audio_clk_a_b),
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
SH_PFC_PIN_GROUP(avb_avtp_match_b),
SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+ SH_PFC_PIN_GROUP(can0_data_a),
+ SH_PFC_PIN_GROUP(can0_data_b),
+ SH_PFC_PIN_GROUP(can1_data),
+ SH_PFC_PIN_GROUP(can_clk),
+ SH_PFC_PIN_GROUP(canfd0_data_a),
+ SH_PFC_PIN_GROUP(canfd0_data_b),
+ SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
SH_PFC_PIN_GROUP(i2c6_a),
SH_PFC_PIN_GROUP(i2c6_b),
SH_PFC_PIN_GROUP(i2c6_c),
+ SH_PFC_PIN_GROUP(intc_ex_irq0),
+ SH_PFC_PIN_GROUP(intc_ex_irq1),
+ SH_PFC_PIN_GROUP(intc_ex_irq2),
+ SH_PFC_PIN_GROUP(intc_ex_irq3),
+ SH_PFC_PIN_GROUP(intc_ex_irq4),
+ SH_PFC_PIN_GROUP(intc_ex_irq5),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
SH_PFC_PIN_GROUP(msiof3_ss1_d),
SH_PFC_PIN_GROUP(msiof3_txd_d),
SH_PFC_PIN_GROUP(msiof3_rxd_d),
+ SH_PFC_PIN_GROUP(pwm0),
+ SH_PFC_PIN_GROUP(pwm1_a),
+ SH_PFC_PIN_GROUP(pwm1_b),
+ SH_PFC_PIN_GROUP(pwm2_a),
+ SH_PFC_PIN_GROUP(pwm2_b),
+ SH_PFC_PIN_GROUP(pwm3_a),
+ SH_PFC_PIN_GROUP(pwm3_b),
+ SH_PFC_PIN_GROUP(pwm4_a),
+ SH_PFC_PIN_GROUP(pwm4_b),
+ SH_PFC_PIN_GROUP(pwm5_a),
+ SH_PFC_PIN_GROUP(pwm5_b),
+ SH_PFC_PIN_GROUP(pwm6_a),
+ SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(sata0_devslp_a),
SH_PFC_PIN_GROUP(sata0_devslp_b),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+ SH_PFC_PIN_GROUP(usb0),
+ SH_PFC_PIN_GROUP(usb1),
+ SH_PFC_PIN_GROUP(usb2),
};
static const char * const audio_clk_groups[] = {
"avb_avtp_capture_b",
};
+static const char * const can0_groups[] = {
+ "can0_data_a",
+ "can0_data_b",
+};
+
+static const char * const can1_groups[] = {
+ "can1_data",
+};
+
+static const char * const can_clk_groups[] = {
+ "can_clk",
+};
+
+static const char * const canfd0_groups[] = {
+ "canfd0_data_a",
+ "canfd0_data_b",
+};
+
+static const char * const canfd1_groups[] = {
+ "canfd1_data",
+};
+
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
"i2c6_c",
};
+static const char * const intc_ex_groups[] = {
+ "intc_ex_irq0",
+ "intc_ex_irq1",
+ "intc_ex_irq2",
+ "intc_ex_irq3",
+ "intc_ex_irq4",
+ "intc_ex_irq5",
+};
+
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
"msiof3_rxd_d",
};
+static const char * const pwm0_groups[] = {
+ "pwm0",
+};
+
+static const char * const pwm1_groups[] = {
+ "pwm1_a",
+ "pwm1_b",
+};
+
+static const char * const pwm2_groups[] = {
+ "pwm2_a",
+ "pwm2_b",
+};
+
+static const char * const pwm3_groups[] = {
+ "pwm3_a",
+ "pwm3_b",
+};
+
+static const char * const pwm4_groups[] = {
+ "pwm4_a",
+ "pwm4_b",
+};
+
+static const char * const pwm5_groups[] = {
+ "pwm5_a",
+ "pwm5_b",
+};
+
+static const char * const pwm6_groups[] = {
+ "pwm6_a",
+ "pwm6_b",
+};
+
static const char * const sata0_groups[] = {
"sata0_devslp_a",
"sata0_devslp_b",
"ssi9_ctrl_b",
};
+static const char * const usb0_groups[] = {
+ "usb0",
+};
+
+static const char * const usb1_groups[] = {
+ "usb1",
+};
+
+static const char * const usb2_groups[] = {
+ "usb2",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
+ SH_PFC_FUNCTION(can0),
+ SH_PFC_FUNCTION(can1),
+ SH_PFC_FUNCTION(can_clk),
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c6),
+ SH_PFC_FUNCTION(intc_ex),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
+ SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm4),
+ SH_PFC_FUNCTION(pwm5),
+ SH_PFC_FUNCTION(pwm6),
SH_PFC_FUNCTION(sata0),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
+ SH_PFC_FUNCTION(usb0),
+ SH_PFC_FUNCTION(usb1),
+ SH_PFC_FUNCTION(usb2),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3 */
0, 0,
- MOD_SEL2_2_1
+ /* RESERVED 2, 1 */
+ 0, 0, 0, 0,
MOD_SEL2_0 }
},
{ },
PINMUX_SINGLE(IRQ3_B),
/* IPSR0 */
- PINMUX_IPSR_DATA(IP0_1_0, A0),
- PINMUX_IPSR_DATA(IP0_1_0, ST0_CLKIN),
+ PINMUX_IPSR_GPSR(IP0_1_0, A0),
+ PINMUX_IPSR_GPSR(IP0_1_0, ST0_CLKIN),
PINMUX_IPSR_MSEL(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
- PINMUX_IPSR_DATA(IP0_3_2, A1),
- PINMUX_IPSR_DATA(IP0_3_2, ST0_REQ),
+ PINMUX_IPSR_GPSR(IP0_3_2, A1),
+ PINMUX_IPSR_GPSR(IP0_3_2, ST0_REQ),
PINMUX_IPSR_MSEL(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
- PINMUX_IPSR_DATA(IP0_5_4, A2),
- PINMUX_IPSR_DATA(IP0_5_4, ST0_SYC),
+ PINMUX_IPSR_GPSR(IP0_5_4, A2),
+ PINMUX_IPSR_GPSR(IP0_5_4, ST0_SYC),
PINMUX_IPSR_MSEL(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
- PINMUX_IPSR_DATA(IP0_7_6, A3),
- PINMUX_IPSR_DATA(IP0_7_6, ST0_VLD),
+ PINMUX_IPSR_GPSR(IP0_7_6, A3),
+ PINMUX_IPSR_GPSR(IP0_7_6, ST0_VLD),
PINMUX_IPSR_MSEL(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
- PINMUX_IPSR_DATA(IP0_9_8, A4),
- PINMUX_IPSR_DATA(IP0_9_8, ST0_D0),
+ PINMUX_IPSR_GPSR(IP0_9_8, A4),
+ PINMUX_IPSR_GPSR(IP0_9_8, ST0_D0),
PINMUX_IPSR_MSEL(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
- PINMUX_IPSR_DATA(IP0_11_10, A5),
- PINMUX_IPSR_DATA(IP0_11_10, ST0_D1),
+ PINMUX_IPSR_GPSR(IP0_11_10, A5),
+ PINMUX_IPSR_GPSR(IP0_11_10, ST0_D1),
PINMUX_IPSR_MSEL(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1),
- PINMUX_IPSR_DATA(IP0_13_12, A6),
- PINMUX_IPSR_DATA(IP0_13_12, ST0_D2),
+ PINMUX_IPSR_GPSR(IP0_13_12, A6),
+ PINMUX_IPSR_GPSR(IP0_13_12, ST0_D2),
PINMUX_IPSR_MSEL(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1),
- PINMUX_IPSR_DATA(IP0_15_14, A7),
- PINMUX_IPSR_DATA(IP0_15_14, ST0_D3),
+ PINMUX_IPSR_GPSR(IP0_15_14, A7),
+ PINMUX_IPSR_GPSR(IP0_15_14, ST0_D3),
PINMUX_IPSR_MSEL(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1),
- PINMUX_IPSR_DATA(IP0_17_16, A8),
- PINMUX_IPSR_DATA(IP0_17_16, ST0_D4),
+ PINMUX_IPSR_GPSR(IP0_17_16, A8),
+ PINMUX_IPSR_GPSR(IP0_17_16, ST0_D4),
PINMUX_IPSR_MSEL(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2),
- PINMUX_IPSR_DATA(IP0_19_18, A9),
- PINMUX_IPSR_DATA(IP0_19_18, ST0_D5),
+ PINMUX_IPSR_GPSR(IP0_19_18, A9),
+ PINMUX_IPSR_GPSR(IP0_19_18, ST0_D5),
PINMUX_IPSR_MSEL(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2),
- PINMUX_IPSR_DATA(IP0_21_20, A10),
- PINMUX_IPSR_DATA(IP0_21_20, ST0_D6),
+ PINMUX_IPSR_GPSR(IP0_21_20, A10),
+ PINMUX_IPSR_GPSR(IP0_21_20, ST0_D6),
PINMUX_IPSR_MSEL(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2),
- PINMUX_IPSR_DATA(IP0_23_22, A11),
- PINMUX_IPSR_DATA(IP0_23_22, ST0_D7),
+ PINMUX_IPSR_GPSR(IP0_23_22, A11),
+ PINMUX_IPSR_GPSR(IP0_23_22, ST0_D7),
PINMUX_IPSR_MSEL(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2),
- PINMUX_IPSR_DATA(IP0_25_24, A12),
+ PINMUX_IPSR_GPSR(IP0_25_24, A12),
PINMUX_IPSR_MSEL(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1),
- PINMUX_IPSR_DATA(IP0_27_26, A13),
+ PINMUX_IPSR_GPSR(IP0_27_26, A13),
PINMUX_IPSR_MSEL(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1),
- PINMUX_IPSR_DATA(IP0_29_28, A14),
+ PINMUX_IPSR_GPSR(IP0_29_28, A14),
PINMUX_IPSR_MSEL(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1),
- PINMUX_IPSR_DATA(IP0_31_30, A15),
- PINMUX_IPSR_DATA(IP0_31_30, ST0_VCO_CLKIN),
+ PINMUX_IPSR_GPSR(IP0_31_30, A15),
+ PINMUX_IPSR_GPSR(IP0_31_30, ST0_VCO_CLKIN),
PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
/* IPSR1 */
- PINMUX_IPSR_DATA(IP1_1_0, A16),
- PINMUX_IPSR_DATA(IP1_1_0, ST0_PWM),
+ PINMUX_IPSR_GPSR(IP1_1_0, A16),
+ PINMUX_IPSR_GPSR(IP1_1_0, ST0_PWM),
PINMUX_IPSR_MSEL(IP1_1_0, LCD_DON_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1),
- PINMUX_IPSR_DATA(IP1_3_2, A17),
- PINMUX_IPSR_DATA(IP1_3_2, ST1_VCO_CLKIN),
+ PINMUX_IPSR_GPSR(IP1_3_2, A17),
+ PINMUX_IPSR_GPSR(IP1_3_2, ST1_VCO_CLKIN),
PINMUX_IPSR_MSEL(IP1_3_2, LCD_CL1_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1),
- PINMUX_IPSR_DATA(IP1_5_4, A18),
- PINMUX_IPSR_DATA(IP1_5_4, ST1_PWM),
+ PINMUX_IPSR_GPSR(IP1_5_4, A18),
+ PINMUX_IPSR_GPSR(IP1_5_4, ST1_PWM),
PINMUX_IPSR_MSEL(IP1_5_4, LCD_CL2_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1),
- PINMUX_IPSR_DATA(IP1_7_6, A19),
- PINMUX_IPSR_DATA(IP1_7_6, ST1_CLKIN),
+ PINMUX_IPSR_GPSR(IP1_7_6, A19),
+ PINMUX_IPSR_GPSR(IP1_7_6, ST1_CLKIN),
PINMUX_IPSR_MSEL(IP1_7_6, LCD_CLK_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1),
- PINMUX_IPSR_DATA(IP1_9_8, A20),
- PINMUX_IPSR_DATA(IP1_9_8, ST1_REQ),
+ PINMUX_IPSR_GPSR(IP1_9_8, A20),
+ PINMUX_IPSR_GPSR(IP1_9_8, ST1_REQ),
PINMUX_IPSR_MSEL(IP1_9_8, LCD_FLM_A, SEL_LCDC_0),
- PINMUX_IPSR_DATA(IP1_11_10, A21),
- PINMUX_IPSR_DATA(IP1_11_10, ST1_SYC),
+ PINMUX_IPSR_GPSR(IP1_11_10, A21),
+ PINMUX_IPSR_GPSR(IP1_11_10, ST1_SYC),
PINMUX_IPSR_MSEL(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0),
- PINMUX_IPSR_DATA(IP1_13_12, A22),
- PINMUX_IPSR_DATA(IP1_13_12, ST1_VLD),
+ PINMUX_IPSR_GPSR(IP1_13_12, A22),
+ PINMUX_IPSR_GPSR(IP1_13_12, ST1_VLD),
PINMUX_IPSR_MSEL(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0),
- PINMUX_IPSR_DATA(IP1_15_14, A23),
- PINMUX_IPSR_DATA(IP1_15_14, ST1_D0),
+ PINMUX_IPSR_GPSR(IP1_15_14, A23),
+ PINMUX_IPSR_GPSR(IP1_15_14, ST1_D0),
PINMUX_IPSR_MSEL(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0),
- PINMUX_IPSR_DATA(IP1_17_16, A24),
+ PINMUX_IPSR_GPSR(IP1_17_16, A24),
PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
- PINMUX_IPSR_DATA(IP1_17_16, ST1_D1),
+ PINMUX_IPSR_GPSR(IP1_17_16, ST1_D1),
- PINMUX_IPSR_DATA(IP1_19_18, A25),
+ PINMUX_IPSR_GPSR(IP1_19_18, A25),
PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
- PINMUX_IPSR_DATA(IP1_17_16, ST1_D2),
+ PINMUX_IPSR_GPSR(IP1_17_16, ST1_D2),
- PINMUX_IPSR_DATA(IP1_22_20, D0),
+ PINMUX_IPSR_GPSR(IP1_22_20, D0),
PINMUX_IPSR_MSEL(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP1_22_20, MMC_D0_A, SEL_MMC_0),
- PINMUX_IPSR_DATA(IP1_22_20, ST1_D3),
+ PINMUX_IPSR_GPSR(IP1_22_20, ST1_D3),
PINMUX_IPSR_MSEL(IP1_22_20, FD0_A, SEL_FLCTL_0),
- PINMUX_IPSR_DATA(IP1_25_23, D1),
+ PINMUX_IPSR_GPSR(IP1_25_23, D1),
PINMUX_IPSR_MSEL(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP1_25_23, MMC_D1_A, SEL_MMC_0),
- PINMUX_IPSR_DATA(IP1_25_23, ST1_D4),
+ PINMUX_IPSR_GPSR(IP1_25_23, ST1_D4),
PINMUX_IPSR_MSEL(IP1_25_23, FD1_A, SEL_FLCTL_0),
- PINMUX_IPSR_DATA(IP1_28_26, D2),
+ PINMUX_IPSR_GPSR(IP1_28_26, D2),
PINMUX_IPSR_MSEL(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP1_28_26, MMC_D2_A, SEL_MMC_0),
- PINMUX_IPSR_DATA(IP1_28_26, ST1_D5),
+ PINMUX_IPSR_GPSR(IP1_28_26, ST1_D5),
PINMUX_IPSR_MSEL(IP1_28_26, FD2_A, SEL_FLCTL_0),
- PINMUX_IPSR_DATA(IP1_31_29, D3),
+ PINMUX_IPSR_GPSR(IP1_31_29, D3),
PINMUX_IPSR_MSEL(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP1_31_29, MMC_D3_A, SEL_MMC_0),
- PINMUX_IPSR_DATA(IP1_31_29, ST1_D6),
+ PINMUX_IPSR_GPSR(IP1_31_29, ST1_D6),
PINMUX_IPSR_MSEL(IP1_31_29, FD3_A, SEL_FLCTL_0),
/* IPSR2 */
- PINMUX_IPSR_DATA(IP2_2_0, D4),
+ PINMUX_IPSR_GPSR(IP2_2_0, D4),
PINMUX_IPSR_MSEL(IP2_2_0, SD0_CD_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP2_2_0, MMC_D4_A, SEL_MMC_0),
- PINMUX_IPSR_DATA(IP2_2_0, ST1_D7),
+ PINMUX_IPSR_GPSR(IP2_2_0, ST1_D7),
PINMUX_IPSR_MSEL(IP2_2_0, FD4_A, SEL_FLCTL_0),
- PINMUX_IPSR_DATA(IP2_4_3, D5),
+ PINMUX_IPSR_GPSR(IP2_4_3, D5),
PINMUX_IPSR_MSEL(IP2_4_3, SD0_WP_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP2_4_3, MMC_D5_A, SEL_MMC_0),
PINMUX_IPSR_MSEL(IP2_4_3, FD5_A, SEL_FLCTL_0),
- PINMUX_IPSR_DATA(IP2_7_5, D6),
+ PINMUX_IPSR_GPSR(IP2_7_5, D6),
PINMUX_IPSR_MSEL(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0),
PINMUX_IPSR_MSEL(IP2_7_5, MMC_D6_A, SEL_MMC_0),
PINMUX_IPSR_MSEL(IP2_7_5, QSPCLK_A, SEL_RQSPI_0),
PINMUX_IPSR_MSEL(IP2_7_5, FD6_A, SEL_FLCTL_0),
- PINMUX_IPSR_DATA(IP2_10_8, D7),
+ PINMUX_IPSR_GPSR(IP2_10_8, D7),
PINMUX_IPSR_MSEL(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0),
PINMUX_IPSR_MSEL(IP2_10_8, MMC_D7_A, SEL_MMC_0),
PINMUX_IPSR_MSEL(IP2_10_8, QSSL_A, SEL_RQSPI_0),
PINMUX_IPSR_MSEL(IP2_10_8, FD7_A, SEL_FLCTL_0),
- PINMUX_IPSR_DATA(IP2_13_11, D8),
+ PINMUX_IPSR_GPSR(IP2_13_11, D8),
PINMUX_IPSR_MSEL(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP2_13_11, MMC_CLK_A, SEL_MMC_0),
PINMUX_IPSR_MSEL(IP2_13_11, QIO2_A, SEL_RQSPI_0),
PINMUX_IPSR_MSEL(IP2_13_11, FCE_A, SEL_FLCTL_0),
PINMUX_IPSR_MSEL(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1),
- PINMUX_IPSR_DATA(IP2_16_14, D9),
+ PINMUX_IPSR_GPSR(IP2_16_14, D9),
PINMUX_IPSR_MSEL(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP2_16_14, MMC_CMD_A, SEL_MMC_0),
PINMUX_IPSR_MSEL(IP2_16_14, QIO3_A, SEL_RQSPI_0),
PINMUX_IPSR_MSEL(IP2_16_14, FCLE_A, SEL_FLCTL_0),
PINMUX_IPSR_MSEL(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1),
- PINMUX_IPSR_DATA(IP2_19_17, D10),
+ PINMUX_IPSR_GPSR(IP2_19_17, D10),
PINMUX_IPSR_MSEL(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0),
PINMUX_IPSR_MSEL(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0),
PINMUX_IPSR_MSEL(IP2_19_17, FALE_A, SEL_FLCTL_0),
PINMUX_IPSR_MSEL(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1),
- PINMUX_IPSR_DATA(IP2_22_20, D11),
+ PINMUX_IPSR_GPSR(IP2_22_20, D11),
PINMUX_IPSR_MSEL(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0),
PINMUX_IPSR_MSEL(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0),
PINMUX_IPSR_MSEL(IP2_22_20, FRE_A, SEL_FLCTL_0),
- PINMUX_IPSR_DATA(IP2_24_23, D12),
+ PINMUX_IPSR_GPSR(IP2_24_23, D12),
PINMUX_IPSR_MSEL(IP2_24_23, FWE_A, SEL_FLCTL_0),
PINMUX_IPSR_MSEL(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1),
- PINMUX_IPSR_DATA(IP2_27_25, D13),
+ PINMUX_IPSR_GPSR(IP2_27_25, D13),
PINMUX_IPSR_MSEL(IP2_27_25, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP2_27_25, FRB_A, SEL_FLCTL_0),
PINMUX_IPSR_MSEL(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1),
- PINMUX_IPSR_DATA(IP2_30_28, D14),
+ PINMUX_IPSR_GPSR(IP2_30_28, D14),
PINMUX_IPSR_MSEL(IP2_30_28, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP2_30_28, FSE_A, SEL_FLCTL_0),
PINMUX_IPSR_MSEL(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1),
/* IPSR3 */
- PINMUX_IPSR_DATA(IP3_1_0, D15),
+ PINMUX_IPSR_GPSR(IP3_1_0, D15),
PINMUX_IPSR_MSEL(IP3_1_0, SCK2_B, SEL_SCIF2_1),
- PINMUX_IPSR_DATA(IP3_2, CS1_A26),
+ PINMUX_IPSR_GPSR(IP3_2, CS1_A26),
PINMUX_IPSR_MSEL(IP3_2, QIO3_B, SEL_RQSPI_1),
- PINMUX_IPSR_DATA(IP3_5_3, EX_CS1),
+ PINMUX_IPSR_GPSR(IP3_5_3, EX_CS1),
PINMUX_IPSR_MSEL(IP3_5_3, RX3_B, SEL_SCIF2_1),
- PINMUX_IPSR_DATA(IP3_5_3, ATACS0),
+ PINMUX_IPSR_GPSR(IP3_5_3, ATACS0),
PINMUX_IPSR_MSEL(IP3_5_3, QIO2_B, SEL_RQSPI_1),
- PINMUX_IPSR_DATA(IP3_5_3, ET0_ETXD0),
+ PINMUX_IPSR_GPSR(IP3_5_3, ET0_ETXD0),
- PINMUX_IPSR_DATA(IP3_8_6, EX_CS2),
+ PINMUX_IPSR_GPSR(IP3_8_6, EX_CS2),
PINMUX_IPSR_MSEL(IP3_8_6, TX3_B, SEL_SCIF3_1),
- PINMUX_IPSR_DATA(IP3_8_6, ATACS1),
+ PINMUX_IPSR_GPSR(IP3_8_6, ATACS1),
PINMUX_IPSR_MSEL(IP3_8_6, QSPCLK_B, SEL_RQSPI_1),
PINMUX_IPSR_MSEL(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),
- PINMUX_IPSR_DATA(IP3_11_9, EX_CS3),
+ PINMUX_IPSR_GPSR(IP3_11_9, EX_CS3),
PINMUX_IPSR_MSEL(IP3_11_9, SD1_CD_A, SEL_SDHI1_0),
- PINMUX_IPSR_DATA(IP3_11_9, ATARD),
+ PINMUX_IPSR_GPSR(IP3_11_9, ATARD),
PINMUX_IPSR_MSEL(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1),
PINMUX_IPSR_MSEL(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0),
- PINMUX_IPSR_DATA(IP3_14_12, EX_CS4),
+ PINMUX_IPSR_GPSR(IP3_14_12, EX_CS4),
PINMUX_IPSR_MSEL(IP3_14_12, SD1_WP_A, SEL_SDHI1_0),
- PINMUX_IPSR_DATA(IP3_14_12, ATAWR),
+ PINMUX_IPSR_GPSR(IP3_14_12, ATAWR),
PINMUX_IPSR_MSEL(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1),
PINMUX_IPSR_MSEL(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0),
- PINMUX_IPSR_DATA(IP3_17_15, EX_CS5),
+ PINMUX_IPSR_GPSR(IP3_17_15, EX_CS5),
PINMUX_IPSR_MSEL(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0),
- PINMUX_IPSR_DATA(IP3_17_15, ATADIR),
+ PINMUX_IPSR_GPSR(IP3_17_15, ATADIR),
PINMUX_IPSR_MSEL(IP3_17_15, QSSL_B, SEL_RQSPI_1),
PINMUX_IPSR_MSEL(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0),
- PINMUX_IPSR_DATA(IP3_19_18, RD_WR),
- PINMUX_IPSR_DATA(IP3_19_18, TCLK0),
+ PINMUX_IPSR_GPSR(IP3_19_18, RD_WR),
+ PINMUX_IPSR_GPSR(IP3_19_18, TCLK0),
PINMUX_IPSR_MSEL(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1),
- PINMUX_IPSR_DATA(IP3_19_18, ET0_ETXD4),
+ PINMUX_IPSR_GPSR(IP3_19_18, ET0_ETXD4),
- PINMUX_IPSR_DATA(IP3_20, EX_WAIT0),
+ PINMUX_IPSR_GPSR(IP3_20, EX_WAIT0),
PINMUX_IPSR_MSEL(IP3_20, TCLK1_B, SEL_TMU_1),
- PINMUX_IPSR_DATA(IP3_23_21, EX_WAIT1),
+ PINMUX_IPSR_GPSR(IP3_23_21, EX_WAIT1),
PINMUX_IPSR_MSEL(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0),
- PINMUX_IPSR_DATA(IP3_23_21, DREQ2),
+ PINMUX_IPSR_GPSR(IP3_23_21, DREQ2),
PINMUX_IPSR_MSEL(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2),
PINMUX_IPSR_MSEL(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2),
PINMUX_IPSR_MSEL(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0),
- PINMUX_IPSR_DATA(IP3_26_24, EX_WAIT2),
+ PINMUX_IPSR_GPSR(IP3_26_24, EX_WAIT2),
PINMUX_IPSR_MSEL(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0),
- PINMUX_IPSR_DATA(IP3_26_24, DACK2),
+ PINMUX_IPSR_GPSR(IP3_26_24, DACK2),
PINMUX_IPSR_MSEL(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2),
PINMUX_IPSR_MSEL(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2),
PINMUX_IPSR_MSEL(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0),
- PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
+ PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
PINMUX_IPSR_MSEL(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0),
- PINMUX_IPSR_DATA(IP3_29_27, ATAG),
+ PINMUX_IPSR_GPSR(IP3_29_27, ATAG),
PINMUX_IPSR_MSEL(IP3_29_27, TCLK1_A, SEL_TMU_0),
- PINMUX_IPSR_DATA(IP3_29_27, ET0_ETXD7),
+ PINMUX_IPSR_GPSR(IP3_29_27, ET0_ETXD7),
/* IPSR4 */
PINMUX_IPSR_MSEL(IP4_2_0, HCTS0_A, SEL_HSCIF_0),
PINMUX_IPSR_MSEL(IP4_2_0, CTS1_A, SEL_SCIF1_0),
- PINMUX_IPSR_DATA(IP4_2_0, VI0_FIELD),
+ PINMUX_IPSR_GPSR(IP4_2_0, VI0_FIELD),
PINMUX_IPSR_MSEL(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0),
- PINMUX_IPSR_DATA(IP4_2_0, ET0_ERXD7),
+ PINMUX_IPSR_GPSR(IP4_2_0, ET0_ERXD7),
PINMUX_IPSR_MSEL(IP4_5_3, HRTS0_A, SEL_HSCIF_0),
PINMUX_IPSR_MSEL(IP4_5_3, RTS1_A, SEL_SCIF1_0),
- PINMUX_IPSR_DATA(IP4_5_3, VI0_HSYNC),
+ PINMUX_IPSR_GPSR(IP4_5_3, VI0_HSYNC),
PINMUX_IPSR_MSEL(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0),
- PINMUX_IPSR_DATA(IP4_5_3, ET0_RX_DV),
+ PINMUX_IPSR_GPSR(IP4_5_3, ET0_RX_DV),
PINMUX_IPSR_MSEL(IP4_8_6, HSCK0_A, SEL_HSCIF_0),
PINMUX_IPSR_MSEL(IP4_8_6, SCK1_A, SEL_SCIF1_0),
- PINMUX_IPSR_DATA(IP4_8_6, VI0_VSYNC),
+ PINMUX_IPSR_GPSR(IP4_8_6, VI0_VSYNC),
PINMUX_IPSR_MSEL(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0),
- PINMUX_IPSR_DATA(IP4_8_6, ET0_RX_ER),
+ PINMUX_IPSR_GPSR(IP4_8_6, ET0_RX_ER),
PINMUX_IPSR_MSEL(IP4_11_9, HRX0_A, SEL_HSCIF_0),
PINMUX_IPSR_MSEL(IP4_11_9, RX1_A, SEL_SCIF1_0),
- PINMUX_IPSR_DATA(IP4_11_9, VI0_DATA0_VI0_B0),
+ PINMUX_IPSR_GPSR(IP4_11_9, VI0_DATA0_VI0_B0),
PINMUX_IPSR_MSEL(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0),
- PINMUX_IPSR_DATA(IP4_11_9, ET0_CRS),
+ PINMUX_IPSR_GPSR(IP4_11_9, ET0_CRS),
PINMUX_IPSR_MSEL(IP4_14_12, HTX0_A, SEL_HSCIF_0),
PINMUX_IPSR_MSEL(IP4_14_12, TX1_A, SEL_SCIF1_0),
- PINMUX_IPSR_DATA(IP4_14_12, VI0_DATA1_VI0_B1),
+ PINMUX_IPSR_GPSR(IP4_14_12, VI0_DATA1_VI0_B1),
PINMUX_IPSR_MSEL(IP4_14_12, RMII0_MDC_A, SEL_RMII_0),
- PINMUX_IPSR_DATA(IP4_14_12, ET0_COL),
+ PINMUX_IPSR_GPSR(IP4_14_12, ET0_COL),
PINMUX_IPSR_MSEL(IP4_17_15, CTS0_B, SEL_SCIF0_1),
- PINMUX_IPSR_DATA(IP4_17_15, VI0_DATA2_VI0_B2),
+ PINMUX_IPSR_GPSR(IP4_17_15, VI0_DATA2_VI0_B2),
PINMUX_IPSR_MSEL(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0),
- PINMUX_IPSR_DATA(IP4_17_15, ET0_MDC),
+ PINMUX_IPSR_GPSR(IP4_17_15, ET0_MDC),
PINMUX_IPSR_MSEL(IP4_19_18, RTS0_B, SEL_SCIF0_1),
- PINMUX_IPSR_DATA(IP4_19_18, VI0_DATA3_VI0_B3),
+ PINMUX_IPSR_GPSR(IP4_19_18, VI0_DATA3_VI0_B3),
PINMUX_IPSR_MSEL(IP4_19_18, ET0_MDIO_A, SEL_ET0_0),
PINMUX_IPSR_MSEL(IP4_21_20, SCK1_B, SEL_SCIF1_1),
- PINMUX_IPSR_DATA(IP4_21_20, VI0_DATA4_VI0_B4),
+ PINMUX_IPSR_GPSR(IP4_21_20, VI0_DATA4_VI0_B4),
PINMUX_IPSR_MSEL(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0),
PINMUX_IPSR_MSEL(IP4_23_22, RX1_B, SEL_SCIF1_1),
- PINMUX_IPSR_DATA(IP4_23_22, VI0_DATA5_VI0_B5),
+ PINMUX_IPSR_GPSR(IP4_23_22, VI0_DATA5_VI0_B5),
PINMUX_IPSR_MSEL(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0),
PINMUX_IPSR_MSEL(IP4_25_24, TX1_B, SEL_SCIF1_1),
- PINMUX_IPSR_DATA(IP4_25_24, VI0_DATA6_VI0_G0),
+ PINMUX_IPSR_GPSR(IP4_25_24, VI0_DATA6_VI0_G0),
PINMUX_IPSR_MSEL(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0),
PINMUX_IPSR_MSEL(IP4_27_26, CTS1_B, SEL_SCIF1_1),
- PINMUX_IPSR_DATA(IP4_27_26, VI0_DATA7_VI0_G1),
+ PINMUX_IPSR_GPSR(IP4_27_26, VI0_DATA7_VI0_G1),
PINMUX_IPSR_MSEL(IP4_29_28, RTS1_B, SEL_SCIF1_1),
- PINMUX_IPSR_DATA(IP4_29_28, VI0_G2),
+ PINMUX_IPSR_GPSR(IP4_29_28, VI0_G2),
PINMUX_IPSR_MSEL(IP4_31_30, SCK2_A, SEL_SCIF2_0),
- PINMUX_IPSR_DATA(IP4_31_30, VI0_G3),
+ PINMUX_IPSR_GPSR(IP4_31_30, VI0_G3),
/* IPSR5 */
PINMUX_IPSR_MSEL(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_2_0, RX2_A, SEL_SCIF2_0),
- PINMUX_IPSR_DATA(IP5_2_0, VI0_G4),
+ PINMUX_IPSR_GPSR(IP5_2_0, VI0_G4),
PINMUX_IPSR_MSEL(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1),
PINMUX_IPSR_MSEL(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_5_3, TX2_A, SEL_SCIF2_0),
- PINMUX_IPSR_DATA(IP5_5_3, VI0_G5),
+ PINMUX_IPSR_GPSR(IP5_5_3, VI0_G5),
PINMUX_IPSR_MSEL(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1),
PINMUX_IPSR_MSEL(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_8_6, RX3_A, SEL_SCIF3_0),
- PINMUX_IPSR_DATA(IP4_8_6, VI0_R0),
+ PINMUX_IPSR_GPSR(IP4_8_6, VI0_R0),
PINMUX_IPSR_MSEL(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1),
PINMUX_IPSR_MSEL(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_11_9, TX3_A, SEL_SCIF3_0),
- PINMUX_IPSR_DATA(IP5_11_9, VI0_R1),
+ PINMUX_IPSR_GPSR(IP5_11_9, VI0_R1),
PINMUX_IPSR_MSEL(IP5_11_9, ET0_MDIO_B, SEL_ET0_1),
PINMUX_IPSR_MSEL(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_14_12, RX4_A, SEL_SCIF4_0),
- PINMUX_IPSR_DATA(IP5_14_12, VI0_R2),
+ PINMUX_IPSR_GPSR(IP5_14_12, VI0_R2),
PINMUX_IPSR_MSEL(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1),
PINMUX_IPSR_MSEL(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_17_15, TX4_A, SEL_SCIF4_0),
- PINMUX_IPSR_DATA(IP5_17_15, VI0_R3),
+ PINMUX_IPSR_GPSR(IP5_17_15, VI0_R3),
PINMUX_IPSR_MSEL(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1),
PINMUX_IPSR_MSEL(IP5_20_18, SD2_CD_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_20_18, RX5_A, SEL_SCIF5_0),
- PINMUX_IPSR_DATA(IP5_20_18, VI0_R4),
+ PINMUX_IPSR_GPSR(IP5_20_18, VI0_R4),
PINMUX_IPSR_MSEL(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1),
PINMUX_IPSR_MSEL(IP5_22_21, SD2_WP_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_22_21, TX5_A, SEL_SCIF5_0),
- PINMUX_IPSR_DATA(IP5_22_21, VI0_R5),
+ PINMUX_IPSR_GPSR(IP5_22_21, VI0_R5),
- PINMUX_IPSR_DATA(IP5_24_23, REF125CK),
- PINMUX_IPSR_DATA(IP5_24_23, ADTRG),
+ PINMUX_IPSR_GPSR(IP5_24_23, REF125CK),
+ PINMUX_IPSR_GPSR(IP5_24_23, ADTRG),
PINMUX_IPSR_MSEL(IP5_24_23, RX5_C, SEL_SCIF5_2),
- PINMUX_IPSR_DATA(IP5_26_25, REF50CK),
+ PINMUX_IPSR_GPSR(IP5_26_25, REF50CK),
PINMUX_IPSR_MSEL(IP5_26_25, CTS1_E, SEL_SCIF1_3),
PINMUX_IPSR_MSEL(IP5_26_25, HCTS0_D, SEL_HSCIF_3),
/* IPSR6 */
- PINMUX_IPSR_DATA(IP6_2_0, DU0_DR0),
+ PINMUX_IPSR_GPSR(IP6_2_0, DU0_DR0),
PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1),
PINMUX_IPSR_MSEL(IP6_2_0, HRX0_D, SEL_HSCIF_3),
PINMUX_IPSR_MSEL(IP6_2_0, IETX_A, SEL_IEBUS_0),
PINMUX_IPSR_MSEL(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0),
- PINMUX_IPSR_DATA(IP6_2_0, HIFD00),
+ PINMUX_IPSR_GPSR(IP6_2_0, HIFD00),
- PINMUX_IPSR_DATA(IP6_5_3, DU0_DR1),
+ PINMUX_IPSR_GPSR(IP6_5_3, DU0_DR1),
PINMUX_IPSR_MSEL(IP6_5_3, SCK0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP6_5_3, HTX0_D, SEL_HSCIF_3),
PINMUX_IPSR_MSEL(IP6_5_3, IERX_A, SEL_IEBUS_0),
PINMUX_IPSR_MSEL(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0),
- PINMUX_IPSR_DATA(IP6_5_3, HIFD01),
+ PINMUX_IPSR_GPSR(IP6_5_3, HIFD01),
- PINMUX_IPSR_DATA(IP6_7_6, DU0_DR2),
+ PINMUX_IPSR_GPSR(IP6_7_6, DU0_DR2),
PINMUX_IPSR_MSEL(IP6_7_6, RX0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0),
- PINMUX_IPSR_DATA(IP6_7_6, HIFD02),
+ PINMUX_IPSR_GPSR(IP6_7_6, HIFD02),
- PINMUX_IPSR_DATA(IP6_9_8, DU0_DR3),
+ PINMUX_IPSR_GPSR(IP6_9_8, DU0_DR3),
PINMUX_IPSR_MSEL(IP6_9_8, TX0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0),
- PINMUX_IPSR_DATA(IP6_9_8, HIFD03),
+ PINMUX_IPSR_GPSR(IP6_9_8, HIFD03),
- PINMUX_IPSR_DATA(IP6_11_10, DU0_DR4),
+ PINMUX_IPSR_GPSR(IP6_11_10, DU0_DR4),
PINMUX_IPSR_MSEL(IP6_11_10, CTS0_C, SEL_SCIF0_2),
PINMUX_IPSR_MSEL(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0),
- PINMUX_IPSR_DATA(IP6_11_10, HIFD04),
+ PINMUX_IPSR_GPSR(IP6_11_10, HIFD04),
- PINMUX_IPSR_DATA(IP6_13_12, DU0_DR5),
+ PINMUX_IPSR_GPSR(IP6_13_12, DU0_DR5),
PINMUX_IPSR_MSEL(IP6_13_12, RTS0_C, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0),
- PINMUX_IPSR_DATA(IP6_13_12, HIFD05),
+ PINMUX_IPSR_GPSR(IP6_13_12, HIFD05),
- PINMUX_IPSR_DATA(IP6_15_14, DU0_DR6),
+ PINMUX_IPSR_GPSR(IP6_15_14, DU0_DR6),
PINMUX_IPSR_MSEL(IP6_15_14, SCK1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0),
- PINMUX_IPSR_DATA(IP6_15_14, HIFD06),
+ PINMUX_IPSR_GPSR(IP6_15_14, HIFD06),
- PINMUX_IPSR_DATA(IP6_17_16, DU0_DR7),
+ PINMUX_IPSR_GPSR(IP6_17_16, DU0_DR7),
PINMUX_IPSR_MSEL(IP6_17_16, RX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0),
- PINMUX_IPSR_DATA(IP6_17_16, HIFD07),
+ PINMUX_IPSR_GPSR(IP6_17_16, HIFD07),
- PINMUX_IPSR_DATA(IP6_20_18, DU0_DG0),
+ PINMUX_IPSR_GPSR(IP6_20_18, DU0_DG0),
PINMUX_IPSR_MSEL(IP6_20_18, TX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP6_20_18, HSCK0_D, SEL_HSCIF_3),
PINMUX_IPSR_MSEL(IP6_20_18, IECLK_A, SEL_IEBUS_0),
PINMUX_IPSR_MSEL(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0),
- PINMUX_IPSR_DATA(IP6_20_18, HIFD08),
+ PINMUX_IPSR_GPSR(IP6_20_18, HIFD08),
- PINMUX_IPSR_DATA(IP6_23_21, DU0_DG1),
+ PINMUX_IPSR_GPSR(IP6_23_21, DU0_DG1),
PINMUX_IPSR_MSEL(IP6_23_21, CTS1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP6_23_21, HRTS0_D, SEL_HSCIF_3),
PINMUX_IPSR_MSEL(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0),
- PINMUX_IPSR_DATA(IP6_23_21, HIFD09),
+ PINMUX_IPSR_GPSR(IP6_23_21, HIFD09),
/* IPSR7 */
- PINMUX_IPSR_DATA(IP7_2_0, DU0_DG2),
+ PINMUX_IPSR_GPSR(IP7_2_0, DU0_DG2),
PINMUX_IPSR_MSEL(IP7_2_0, RTS1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP7_2_0, RMII0_MDC_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0),
- PINMUX_IPSR_DATA(IP7_2_0, HIFD10),
+ PINMUX_IPSR_GPSR(IP7_2_0, HIFD10),
- PINMUX_IPSR_DATA(IP7_5_3, DU0_DG3),
+ PINMUX_IPSR_GPSR(IP7_5_3, DU0_DG3),
PINMUX_IPSR_MSEL(IP7_5_3, SCK2_C, SEL_SCIF2_2),
PINMUX_IPSR_MSEL(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0),
- PINMUX_IPSR_DATA(IP7_5_3, HIFD11),
+ PINMUX_IPSR_GPSR(IP7_5_3, HIFD11),
- PINMUX_IPSR_DATA(IP7_8_6, DU0_DG4),
+ PINMUX_IPSR_GPSR(IP7_8_6, DU0_DG4),
PINMUX_IPSR_MSEL(IP7_8_6, RX2_C, SEL_SCIF2_2),
PINMUX_IPSR_MSEL(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0),
- PINMUX_IPSR_DATA(IP7_8_6, HIFD12),
+ PINMUX_IPSR_GPSR(IP7_8_6, HIFD12),
- PINMUX_IPSR_DATA(IP7_11_9, DU0_DG5),
+ PINMUX_IPSR_GPSR(IP7_11_9, DU0_DG5),
PINMUX_IPSR_MSEL(IP7_11_9, TX2_C, SEL_SCIF2_2),
PINMUX_IPSR_MSEL(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0),
- PINMUX_IPSR_DATA(IP7_11_9, HIFD13),
+ PINMUX_IPSR_GPSR(IP7_11_9, HIFD13),
- PINMUX_IPSR_DATA(IP7_14_12, DU0_DG6),
+ PINMUX_IPSR_GPSR(IP7_14_12, DU0_DG6),
PINMUX_IPSR_MSEL(IP7_14_12, RX3_C, SEL_SCIF3_2),
PINMUX_IPSR_MSEL(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0),
- PINMUX_IPSR_DATA(IP7_14_12, HIFD14),
+ PINMUX_IPSR_GPSR(IP7_14_12, HIFD14),
- PINMUX_IPSR_DATA(IP7_17_15, DU0_DG7),
+ PINMUX_IPSR_GPSR(IP7_17_15, DU0_DG7),
PINMUX_IPSR_MSEL(IP7_17_15, TX3_C, SEL_SCIF3_2),
PINMUX_IPSR_MSEL(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0),
- PINMUX_IPSR_DATA(IP7_17_15, HIFD15),
+ PINMUX_IPSR_GPSR(IP7_17_15, HIFD15),
- PINMUX_IPSR_DATA(IP7_20_18, DU0_DB0),
+ PINMUX_IPSR_GPSR(IP7_20_18, DU0_DB0),
PINMUX_IPSR_MSEL(IP7_20_18, RX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0),
- PINMUX_IPSR_DATA(IP7_20_18, HIFCS),
+ PINMUX_IPSR_GPSR(IP7_20_18, HIFCS),
- PINMUX_IPSR_DATA(IP7_23_21, DU0_DB1),
+ PINMUX_IPSR_GPSR(IP7_23_21, DU0_DB1),
PINMUX_IPSR_MSEL(IP7_23_21, TX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0),
- PINMUX_IPSR_DATA(IP7_23_21, HIFWR),
+ PINMUX_IPSR_GPSR(IP7_23_21, HIFWR),
- PINMUX_IPSR_DATA(IP7_26_24, DU0_DB2),
+ PINMUX_IPSR_GPSR(IP7_26_24, DU0_DB2),
PINMUX_IPSR_MSEL(IP7_26_24, RX5_B, SEL_SCIF5_1),
PINMUX_IPSR_MSEL(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0),
- PINMUX_IPSR_DATA(IP7_28_27, DU0_DB3),
+ PINMUX_IPSR_GPSR(IP7_28_27, DU0_DB3),
PINMUX_IPSR_MSEL(IP7_28_27, TX5_B, SEL_SCIF5_1),
PINMUX_IPSR_MSEL(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0),
- PINMUX_IPSR_DATA(IP7_28_27, HIFRD),
+ PINMUX_IPSR_GPSR(IP7_28_27, HIFRD),
- PINMUX_IPSR_DATA(IP7_30_29, DU0_DB4),
- PINMUX_IPSR_DATA(IP7_30_29, HIFINT),
+ PINMUX_IPSR_GPSR(IP7_30_29, DU0_DB4),
+ PINMUX_IPSR_GPSR(IP7_30_29, HIFINT),
/* IPSR8 */
- PINMUX_IPSR_DATA(IP8_1_0, DU0_DB5),
- PINMUX_IPSR_DATA(IP8_1_0, HIFDREQ),
+ PINMUX_IPSR_GPSR(IP8_1_0, DU0_DB5),
+ PINMUX_IPSR_GPSR(IP8_1_0, HIFDREQ),
- PINMUX_IPSR_DATA(IP8_3_2, DU0_DB6),
- PINMUX_IPSR_DATA(IP8_3_2, HIFRDY),
+ PINMUX_IPSR_GPSR(IP8_3_2, DU0_DB6),
+ PINMUX_IPSR_GPSR(IP8_3_2, HIFRDY),
- PINMUX_IPSR_DATA(IP8_5_4, DU0_DB7),
+ PINMUX_IPSR_GPSR(IP8_5_4, DU0_DB7),
PINMUX_IPSR_MSEL(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1),
PINMUX_IPSR_MSEL(IP8_5_4, HIFEBL_B, SEL_HIF_1),
- PINMUX_IPSR_DATA(IP8_7_6, DU0_DOTCLKIN),
+ PINMUX_IPSR_GPSR(IP8_7_6, DU0_DOTCLKIN),
PINMUX_IPSR_MSEL(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2),
PINMUX_IPSR_MSEL(IP8_7_6, SSI_WS0_B, SEL_SSI0_1),
- PINMUX_IPSR_DATA(IP8_9_8, DU0_DOTCLKOUT),
+ PINMUX_IPSR_GPSR(IP8_9_8, DU0_DOTCLKOUT),
PINMUX_IPSR_MSEL(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2),
PINMUX_IPSR_MSEL(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1),
- PINMUX_IPSR_DATA(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
+ PINMUX_IPSR_GPSR(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
PINMUX_IPSR_MSEL(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2),
PINMUX_IPSR_MSEL(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1),
- PINMUX_IPSR_DATA(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
+ PINMUX_IPSR_GPSR(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
PINMUX_IPSR_MSEL(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2),
PINMUX_IPSR_MSEL(IP8_13_12, SSI_WS1_B, SEL_SSI1_1),
- PINMUX_IPSR_DATA(IP8_15_14, DU0_EXODDF_DU0_ODDF),
+ PINMUX_IPSR_GPSR(IP8_15_14, DU0_EXODDF_DU0_ODDF),
PINMUX_IPSR_MSEL(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP8_15_14, HSCK0_B, SEL_HSCIF_1),
PINMUX_IPSR_MSEL(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1),
- PINMUX_IPSR_DATA(IP8_17_16, DU0_DISP),
+ PINMUX_IPSR_GPSR(IP8_17_16, DU0_DISP),
PINMUX_IPSR_MSEL(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP8_17_16, HRX0_B, SEL_HSCIF_1),
PINMUX_IPSR_MSEL(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1),
- PINMUX_IPSR_DATA(IP8_19_18, DU0_CDE),
+ PINMUX_IPSR_GPSR(IP8_19_18, DU0_CDE),
PINMUX_IPSR_MSEL(IP8_19_18, HTX0_B, SEL_HSCIF_1),
PINMUX_IPSR_MSEL(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1),
PINMUX_IPSR_MSEL(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1),
PINMUX_IPSR_MSEL(IP8_22_20, IRQ0_A, SEL_INTC_0),
PINMUX_IPSR_MSEL(IP8_22_20, HSPI_TX_B, SEL_HSPI_1),
PINMUX_IPSR_MSEL(IP8_22_20, RX3_E, SEL_SCIF3_4),
- PINMUX_IPSR_DATA(IP8_22_20, ET0_ERXD0),
+ PINMUX_IPSR_GPSR(IP8_22_20, ET0_ERXD0),
PINMUX_IPSR_MSEL(IP8_25_23, IRQ1_A, SEL_INTC_0),
PINMUX_IPSR_MSEL(IP8_25_23, HSPI_RX_B, SEL_HSPI_1),
PINMUX_IPSR_MSEL(IP8_25_23, TX3_E, SEL_SCIF3_4),
- PINMUX_IPSR_DATA(IP8_25_23, ET0_ERXD1),
+ PINMUX_IPSR_GPSR(IP8_25_23, ET0_ERXD1),
PINMUX_IPSR_MSEL(IP8_27_26, IRQ2_A, SEL_INTC_0),
PINMUX_IPSR_MSEL(IP8_27_26, CTS0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1),
/* IPSE10 */
- PINMUX_IPSR_DATA(IP10_2_0, SSI_SCK23),
+ PINMUX_IPSR_GPSR(IP10_2_0, SSI_SCK23),
PINMUX_IPSR_MSEL(IP10_2_0, VI1_4_B, SEL_VIN1_1),
PINMUX_IPSR_MSEL(IP10_2_0, RX1_D, SEL_SCIF1_3),
PINMUX_IPSR_MSEL(IP10_2_0, FCLE_B, SEL_FLCTL_1),
PINMUX_IPSR_MSEL(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1),
- PINMUX_IPSR_DATA(IP10_5_3, SSI_WS23),
+ PINMUX_IPSR_GPSR(IP10_5_3, SSI_WS23),
PINMUX_IPSR_MSEL(IP10_5_3, VI1_5_B, SEL_VIN1_1),
PINMUX_IPSR_MSEL(IP10_5_3, TX1_D, SEL_SCIF1_3),
PINMUX_IPSR_MSEL(IP10_5_3, HSCK0_C, SEL_HSCIF_2),
PINMUX_IPSR_MSEL(IP10_5_3, FALE_B, SEL_FLCTL_1),
PINMUX_IPSR_MSEL(IP10_5_3, LCD_DON_B, SEL_LCDC_1),
- PINMUX_IPSR_DATA(IP10_8_6, SSI_SDATA2),
+ PINMUX_IPSR_GPSR(IP10_8_6, SSI_SDATA2),
PINMUX_IPSR_MSEL(IP10_8_6, VI1_6_B, SEL_VIN1_1),
PINMUX_IPSR_MSEL(IP10_8_6, HRX0_C, SEL_HSCIF_2),
PINMUX_IPSR_MSEL(IP10_8_6, FRE_B, SEL_FLCTL_1),
PINMUX_IPSR_MSEL(IP10_8_6, LCD_CL1_B, SEL_LCDC_1),
- PINMUX_IPSR_DATA(IP10_11_9, SSI_SDATA3),
+ PINMUX_IPSR_GPSR(IP10_11_9, SSI_SDATA3),
PINMUX_IPSR_MSEL(IP10_11_9, VI1_7_B, SEL_VIN1_1),
PINMUX_IPSR_MSEL(IP10_11_9, HTX0_C, SEL_HSCIF_2),
PINMUX_IPSR_MSEL(IP10_11_9, FWE_B, SEL_FLCTL_1),
PINMUX_IPSR_MSEL(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0),
PINMUX_IPSR_MSEL(IP10_15, LCD_CLK_B, SEL_LCDC_1),
- PINMUX_IPSR_DATA(IP10_18_16, AUDIO_CLKC),
+ PINMUX_IPSR_GPSR(IP10_18_16, AUDIO_CLKC),
PINMUX_IPSR_MSEL(IP10_18_16, SCK1_E, SEL_SCIF1_4),
PINMUX_IPSR_MSEL(IP10_18_16, HCTS0_C, SEL_HSCIF_2),
PINMUX_IPSR_MSEL(IP10_18_16, FRB_B, SEL_FLCTL_1),
PINMUX_IPSR_MSEL(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1),
- PINMUX_IPSR_DATA(IP10_21_19, AUDIO_CLKOUT),
+ PINMUX_IPSR_GPSR(IP10_21_19, AUDIO_CLKOUT),
PINMUX_IPSR_MSEL(IP10_21_19, TX1_E, SEL_SCIF1_4),
PINMUX_IPSR_MSEL(IP10_21_19, HRTS0_C, SEL_HSCIF_2),
PINMUX_IPSR_MSEL(IP10_21_19, FSE_B, SEL_FLCTL_1),
PINMUX_IPSR_MSEL(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0),
PINMUX_IPSR_MSEL(IP10_24_23, TX4_D, SEL_SCIF4_3),
- PINMUX_IPSR_DATA(IP10_24_23, MLB_CLK),
+ PINMUX_IPSR_GPSR(IP10_24_23, MLB_CLK),
PINMUX_IPSR_MSEL(IP10_25, CAN1_RX_A, SEL_RCAN1_0),
PINMUX_IPSR_MSEL(IP10_25, IRQ1_B, SEL_INTC_1),
PINMUX_IPSR_MSEL(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0),
PINMUX_IPSR_MSEL(IP10_27_26, IRQ0_B, SEL_INTC_1),
- PINMUX_IPSR_DATA(IP10_27_26, MLB_SIG),
+ PINMUX_IPSR_GPSR(IP10_27_26, MLB_SIG),
PINMUX_IPSR_MSEL(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0),
PINMUX_IPSR_MSEL(IP10_29_28, TX5_C, SEL_SCIF1_2),
- PINMUX_IPSR_DATA(IP10_29_28, MLB_DAT),
+ PINMUX_IPSR_GPSR(IP10_29_28, MLB_DAT),
/* IPSR11 */
- PINMUX_IPSR_DATA(IP11_0, SCL1),
+ PINMUX_IPSR_GPSR(IP11_0, SCL1),
PINMUX_IPSR_MSEL(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2),
- PINMUX_IPSR_DATA(IP11_1, SDA1),
+ PINMUX_IPSR_GPSR(IP11_1, SDA1),
PINMUX_IPSR_MSEL(IP11_0, RX1_E, SEL_SCIF1_4),
- PINMUX_IPSR_DATA(IP11_2, SDA0),
+ PINMUX_IPSR_GPSR(IP11_2, SDA0),
PINMUX_IPSR_MSEL(IP11_2, HIFEBL_A, SEL_HIF_0),
- PINMUX_IPSR_DATA(IP11_3, SDSELF),
+ PINMUX_IPSR_GPSR(IP11_3, SDSELF),
PINMUX_IPSR_MSEL(IP11_3, RTS1_E, SEL_SCIF1_3),
PINMUX_IPSR_MSEL(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0),
PINMUX_IPSR_MSEL(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0),
- PINMUX_IPSR_DATA(IP11_6_4, VI0_CLK),
+ PINMUX_IPSR_GPSR(IP11_6_4, VI0_CLK),
PINMUX_IPSR_MSEL(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0),
- PINMUX_IPSR_DATA(IP11_6_4, ET0_ERXD4),
+ PINMUX_IPSR_GPSR(IP11_6_4, ET0_ERXD4),
PINMUX_IPSR_MSEL(IP11_9_7, SCK0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_9_7, HSPI_CS_A, SEL_HSPI_0),
- PINMUX_IPSR_DATA(IP11_9_7, VI0_CLKENB),
+ PINMUX_IPSR_GPSR(IP11_9_7, VI0_CLKENB),
PINMUX_IPSR_MSEL(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0),
- PINMUX_IPSR_DATA(IP11_9_7, ET0_ERXD5),
+ PINMUX_IPSR_GPSR(IP11_9_7, ET0_ERXD5),
PINMUX_IPSR_MSEL(IP11_11_10, RX0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_11_10, HSPI_RX_A, SEL_HSPI_0),
PINMUX_IPSR_MSEL(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0),
- PINMUX_IPSR_DATA(IP11_11_10, ET0_ERXD6),
+ PINMUX_IPSR_GPSR(IP11_11_10, ET0_ERXD6),
PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_12, HSPI_TX_A, SEL_HSPI_0),
- PINMUX_IPSR_DATA(IP11_15_13, PENC1),
+ PINMUX_IPSR_GPSR(IP11_15_13, PENC1),
PINMUX_IPSR_MSEL(IP11_15_13, TX3_D, SEL_SCIF3_3),
PINMUX_IPSR_MSEL(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1),
PINMUX_IPSR_MSEL(IP11_15_13, TX5_D, SEL_SCIF5_3),
PINMUX_IPSR_MSEL(IP11_15_13, IETX_B, SEL_IEBUS_1),
- PINMUX_IPSR_DATA(IP11_18_16, USB_OVC1),
+ PINMUX_IPSR_GPSR(IP11_18_16, USB_OVC1),
PINMUX_IPSR_MSEL(IP11_18_16, RX3_D, SEL_SCIF3_3),
PINMUX_IPSR_MSEL(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1),
PINMUX_IPSR_MSEL(IP11_18_16, RX5_D, SEL_SCIF5_3),
PINMUX_IPSR_MSEL(IP11_18_16, IERX_B, SEL_IEBUS_1),
- PINMUX_IPSR_DATA(IP11_20_19, DREQ0),
+ PINMUX_IPSR_GPSR(IP11_20_19, DREQ0),
PINMUX_IPSR_MSEL(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0),
- PINMUX_IPSR_DATA(IP11_20_19, ET0_TX_EN),
+ PINMUX_IPSR_GPSR(IP11_20_19, ET0_TX_EN),
- PINMUX_IPSR_DATA(IP11_22_21, DACK0),
+ PINMUX_IPSR_GPSR(IP11_22_21, DACK0),
PINMUX_IPSR_MSEL(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0),
- PINMUX_IPSR_DATA(IP11_22_21, ET0_TX_ER),
+ PINMUX_IPSR_GPSR(IP11_22_21, ET0_TX_ER),
- PINMUX_IPSR_DATA(IP11_25_23, DREQ1),
+ PINMUX_IPSR_GPSR(IP11_25_23, DREQ1),
PINMUX_IPSR_MSEL(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1),
PINMUX_IPSR_MSEL(IP11_25_23, RX4_B, SEL_SCIF4_1),
PINMUX_IPSR_MSEL(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0),
PINMUX_IPSR_MSEL(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0),
- PINMUX_IPSR_DATA(IP11_27_26, DACK1),
+ PINMUX_IPSR_GPSR(IP11_27_26, DACK1),
PINMUX_IPSR_MSEL(IP11_27_26, HSPI_CS_B, SEL_HSPI_1),
PINMUX_IPSR_MSEL(IP11_27_26, TX4_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0),
- PINMUX_IPSR_DATA(IP11_28, PRESETOUT),
- PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
+ PINMUX_IPSR_GPSR(IP11_28, PRESETOUT),
+ PINMUX_IPSR_GPSR(IP11_28, ST_CLKOUT),
};
static const struct sh_pfc_pin pinmux_pins[] = {
const u8 *var_field_width;
};
+/*
+ * Describe a config register consisting of several fields of the same width
+ * - name: Register name (unused, for documentation purposes only)
+ * - r: Physical register address
+ * - r_width: Width of the register (in bits)
+ * - f_width: Width of the fixed-width register fields (in bits)
+ * This macro must be followed by initialization data: For each register field
+ * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
+ * one for each possible combination of the register field bit values.
+ */
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
.reg = r, .reg_width = r_width, .field_width = f_width, \
.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
+/*
+ * Describe a config register consisting of several fields of different widths
+ * - name: Register name (unused, for documentation purposes only)
+ * - r: Physical register address
+ * - r_width: Width of the register (in bits)
+ * - var_fw0, var_fwn...: List of widths of the register fields (in bits),
+ * From left to right (i.e. MSB to LSB)
+ * This macro must be followed by initialization data: For each register field
+ * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
+ * one for each possible combination of the register field bit values.
+ */
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
.reg = r, .reg_width = r_width, \
.var_field_width = (const u8 [r_width]) \
const u16 *enum_ids;
};
+/*
+ * Describe a data register
+ * - name: Register name (unused, for documentation purposes only)
+ * - r: Physical register address
+ * - r_width: Width of the register (in bits)
+ * This macro must be followed by initialization data: For each register bit
+ * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
+ */
#define PINMUX_DATA_REG(name, r, r_width) \
.reg = r, .reg_width = r_width, \
.enum_ids = (const u16 [r_width]) \
const short *gpios;
};
+/*
+ * Describe the mapping from GPIOs to a single IRQ
+ * - ids...: List of GPIOs that are mapped to the same IRQ
+ */
#define PINMUX_IRQ(ids...) \
{ .gpios = (const short []) { ids, -1 } }
* sh_pfc_soc_info pinmux_data array macros
*/
+/*
+ * Describe generic pinmux data
+ * - data_or_mark: *_DATA or *_MARK enum ID
+ * - ids...: List of enum IDs to associate with data_or_mark
+ */
#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
-#define PINMUX_IPSR_NOGP(ispr, fn) \
+/*
+ * Describe a pinmux configuration without GPIO function that needs
+ * configuration in a Peripheral Function Select Register (IPSR)
+ * - ipsr: IPSR field (unused, for documentation purposes only)
+ * - fn: Function name, referring to a field in the IPSR
+ */
+#define PINMUX_IPSR_NOGP(ipsr, fn) \
PINMUX_DATA(fn##_MARK, FN_##fn)
-#define PINMUX_IPSR_DATA(ipsr, fn) \
+
+/*
+ * Describe a pinmux configuration with GPIO function that needs configuration
+ * in both a Peripheral Function Select Register (IPSR) and in a
+ * GPIO/Peripheral Function Select Register (GPSR)
+ * - ipsr: IPSR field
+ * - fn: Function name, also referring to the IPSR field
+ */
+#define PINMUX_IPSR_GPSR(ipsr, fn) \
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
-#define PINMUX_IPSR_NOGM(ispr, fn, ms) \
- PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
-#define PINMUX_IPSR_NOFN(ipsr, fn, ms) \
- PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms)
-#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
- PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
+
+/*
+ * Describe a pinmux configuration without GPIO function that needs
+ * configuration in a Peripheral Function Select Register (IPSR), and where the
+ * pinmux function has a representation in a Module Select Register (MOD_SEL).
+ * - ipsr: IPSR field (unused, for documentation purposes only)
+ * - fn: Function name, also referring to the IPSR field
+ * - msel: Module selector
+ */
+#define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
+ PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
+
+/*
+ * Describe a pinmux configuration with GPIO function where the pinmux function
+ * has no representation in a Peripheral Function Select Register (IPSR), but
+ * instead solely depends on a group selection.
+ * - gpsr: GPSR field
+ * - fn: Function name, also referring to the GPSR field
+ * - gsel: Group selector
+ */
+#define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
+ PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
+
+/*
+ * Describe a pinmux configuration with GPIO function that needs configuration
+ * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
+ * Function Select Register (GPSR), and where the pinmux function has a
+ * representation in a Module Select Register (MOD_SEL).
+ * - ipsr: IPSR field
+ * - fn: Function name, also referring to the IPSR field
+ * - msel: Module selector
+ */
+#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
+ PINMUX_DATA(fn##_MARK, FN_##msel, FN_##ipsr, FN_##fn)
/*
* Describe a pinmux configuration for a single-function pin with GPIO
PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
/*
- * PORTnCR macro
+ * PORTnCR helper macro for SH-Mobile/R-Mobile
*/
#define PORTCR(nr, reg) \
{ \
--- /dev/null
+if ARCH_STM32 || COMPILE_TEST
+
+config PINCTRL_STM32
+ bool
+ depends on OF
+ select PINMUX
+ select GENERIC_PINCONF
+ select GPIOLIB
+
+config PINCTRL_STM32F429
+ bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429
+ depends on OF
+ default MACH_STM32F429
+ select PINCTRL_STM32
+
+endif
--- /dev/null
+# Core
+obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_STM32F429) += pinctrl-stm32f429.o
--- /dev/null
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ * License terms: GNU General Public License (GPL), version 2
+ *
+ * Heavily based on Mediatek's pinctrl driver
+ */
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-stm32.h"
+
+#define STM32_GPIO_MODER 0x00
+#define STM32_GPIO_TYPER 0x04
+#define STM32_GPIO_SPEEDR 0x08
+#define STM32_GPIO_PUPDR 0x0c
+#define STM32_GPIO_IDR 0x10
+#define STM32_GPIO_ODR 0x14
+#define STM32_GPIO_BSRR 0x18
+#define STM32_GPIO_LCKR 0x1c
+#define STM32_GPIO_AFRL 0x20
+#define STM32_GPIO_AFRH 0x24
+
+#define STM32_GPIO_PINS_PER_BANK 16
+
+#define gpio_range_to_bank(chip) \
+ container_of(chip, struct stm32_gpio_bank, range)
+
+static const char * const stm32_gpio_functions[] = {
+ "gpio", "af0", "af1",
+ "af2", "af3", "af4",
+ "af5", "af6", "af7",
+ "af8", "af9", "af10",
+ "af11", "af12", "af13",
+ "af14", "af15", "analog",
+};
+
+struct stm32_pinctrl_group {
+ const char *name;
+ unsigned long config;
+ unsigned pin;
+};
+
+struct stm32_gpio_bank {
+ void __iomem *base;
+ struct clk *clk;
+ spinlock_t lock;
+ struct gpio_chip gpio_chip;
+ struct pinctrl_gpio_range range;
+};
+
+struct stm32_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *pctl_dev;
+ struct pinctrl_desc pctl_desc;
+ struct stm32_pinctrl_group *groups;
+ unsigned ngroups;
+ const char **grp_names;
+ struct stm32_gpio_bank *banks;
+ unsigned nbanks;
+ const struct stm32_pinctrl_match_data *match_data;
+};
+
+static inline int stm32_gpio_pin(int gpio)
+{
+ return gpio % STM32_GPIO_PINS_PER_BANK;
+}
+
+static inline u32 stm32_gpio_get_mode(u32 function)
+{
+ switch (function) {
+ case STM32_PIN_GPIO:
+ return 0;
+ case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
+ return 2;
+ case STM32_PIN_ANALOG:
+ return 3;
+ }
+
+ return 0;
+}
+
+static inline u32 stm32_gpio_get_alt(u32 function)
+{
+ switch (function) {
+ case STM32_PIN_GPIO:
+ return 0;
+ case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
+ return function - 1;
+ case STM32_PIN_ANALOG:
+ return 0;
+ }
+
+ return 0;
+}
+
+/* GPIO functions */
+
+static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
+ unsigned offset, int value)
+{
+ if (!value)
+ offset += STM32_GPIO_PINS_PER_BANK;
+
+ clk_enable(bank->clk);
+
+ writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
+
+ clk_disable(bank->clk);
+}
+
+static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+ return pinctrl_request_gpio(chip->base + offset);
+}
+
+static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+ pinctrl_free_gpio(chip->base + offset);
+}
+
+static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+ int ret;
+
+ clk_enable(bank->clk);
+
+ ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
+
+ clk_disable(bank->clk);
+
+ return ret;
+}
+
+static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+
+ __stm32_gpio_set(bank, offset, value);
+}
+
+static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ return pinctrl_gpio_direction_input(chip->base + offset);
+}
+
+static int stm32_gpio_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+
+ __stm32_gpio_set(bank, offset, value);
+ pinctrl_gpio_direction_output(chip->base + offset);
+
+ return 0;
+}
+
+static struct gpio_chip stm32_gpio_template = {
+ .request = stm32_gpio_request,
+ .free = stm32_gpio_free,
+ .get = stm32_gpio_get,
+ .set = stm32_gpio_set,
+ .direction_input = stm32_gpio_direction_input,
+ .direction_output = stm32_gpio_direction_output,
+};
+
+/* Pinctrl functions */
+
+static struct stm32_pinctrl_group *
+stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
+{
+ int i;
+
+ for (i = 0; i < pctl->ngroups; i++) {
+ struct stm32_pinctrl_group *grp = pctl->groups + i;
+
+ if (grp->pin == pin)
+ return grp;
+ }
+
+ return NULL;
+}
+
+static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
+ u32 pin_num, u32 fnum)
+{
+ int i;
+
+ for (i = 0; i < pctl->match_data->npins; i++) {
+ const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
+ const struct stm32_desc_function *func = pin->functions;
+
+ if (pin->pin.number != pin_num)
+ continue;
+
+ while (func && func->name) {
+ if (func->num == fnum)
+ return true;
+ func++;
+ }
+
+ break;
+ }
+
+ return false;
+}
+
+static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
+ u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
+ struct pinctrl_map **map, unsigned *reserved_maps,
+ unsigned *num_maps)
+{
+ if (*num_maps == *reserved_maps)
+ return -ENOSPC;
+
+ (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
+ (*map)[*num_maps].data.mux.group = grp->name;
+
+ if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
+ dev_err(pctl->dev, "invalid function %d on pin %d .\n",
+ fnum, pin);
+ return -EINVAL;
+ }
+
+ (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
+ (*num_maps)++;
+
+ return 0;
+}
+
+static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *node,
+ struct pinctrl_map **map,
+ unsigned *reserved_maps,
+ unsigned *num_maps)
+{
+ struct stm32_pinctrl *pctl;
+ struct stm32_pinctrl_group *grp;
+ struct property *pins;
+ u32 pinfunc, pin, func;
+ unsigned long *configs;
+ unsigned int num_configs;
+ bool has_config = 0;
+ unsigned reserve = 0;
+ int num_pins, num_funcs, maps_per_pin, i, err;
+
+ pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ pins = of_find_property(node, "pinmux", NULL);
+ if (!pins) {
+ dev_err(pctl->dev, "missing pins property in node %s .\n",
+ node->name);
+ return -EINVAL;
+ }
+
+ err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
+ &num_configs);
+ if (err)
+ return err;
+
+ if (num_configs)
+ has_config = 1;
+
+ num_pins = pins->length / sizeof(u32);
+ num_funcs = num_pins;
+ maps_per_pin = 0;
+ if (num_funcs)
+ maps_per_pin++;
+ if (has_config && num_pins >= 1)
+ maps_per_pin++;
+
+ if (!num_pins || !maps_per_pin)
+ return -EINVAL;
+
+ reserve = num_pins * maps_per_pin;
+
+ err = pinctrl_utils_reserve_map(pctldev, map,
+ reserved_maps, num_maps, reserve);
+ if (err)
+ return err;
+
+ for (i = 0; i < num_pins; i++) {
+ err = of_property_read_u32_index(node, "pinmux",
+ i, &pinfunc);
+ if (err)
+ return err;
+
+ pin = STM32_GET_PIN_NO(pinfunc);
+ func = STM32_GET_PIN_FUNC(pinfunc);
+
+ if (pin >= pctl->match_data->npins) {
+ dev_err(pctl->dev, "invalid pin number.\n");
+ return -EINVAL;
+ }
+
+ if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
+ dev_err(pctl->dev, "invalid function.\n");
+ return -EINVAL;
+ }
+
+ grp = stm32_pctrl_find_group_by_pin(pctl, pin);
+ if (!grp) {
+ dev_err(pctl->dev, "unable to match pin %d to group\n",
+ pin);
+ return -EINVAL;
+ }
+
+ err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
+ reserved_maps, num_maps);
+ if (err)
+ return err;
+
+ if (has_config) {
+ err = pinctrl_utils_add_map_configs(pctldev, map,
+ reserved_maps, num_maps, grp->name,
+ configs, num_configs,
+ PIN_MAP_TYPE_CONFIGS_GROUP);
+ if (err)
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np_config,
+ struct pinctrl_map **map, unsigned *num_maps)
+{
+ struct device_node *np;
+ unsigned reserved_maps;
+ int ret;
+
+ *map = NULL;
+ *num_maps = 0;
+ reserved_maps = 0;
+
+ for_each_child_of_node(np_config, np) {
+ ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
+ &reserved_maps, num_maps);
+ if (ret < 0) {
+ pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->ngroups;
+}
+
+static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned group)
+{
+ struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->groups[group].name;
+}
+
+static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned group,
+ const unsigned **pins,
+ unsigned *num_pins)
+{
+ struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = (unsigned *)&pctl->groups[group].pin;
+ *num_pins = 1;
+
+ return 0;
+}
+
+static const struct pinctrl_ops stm32_pctrl_ops = {
+ .dt_node_to_map = stm32_pctrl_dt_node_to_map,
+ .dt_free_map = pinctrl_utils_dt_free_map,
+ .get_groups_count = stm32_pctrl_get_groups_count,
+ .get_group_name = stm32_pctrl_get_group_name,
+ .get_group_pins = stm32_pctrl_get_group_pins,
+};
+
+
+/* Pinmux functions */
+
+static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(stm32_gpio_functions);
+}
+
+static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ return stm32_gpio_functions[selector];
+}
+
+static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
+ unsigned function,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = pctl->grp_names;
+ *num_groups = pctl->ngroups;
+
+ return 0;
+}
+
+static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
+ int pin, u32 mode, u32 alt)
+{
+ u32 val;
+ int alt_shift = (pin % 8) * 4;
+ int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
+ unsigned long flags;
+
+ clk_enable(bank->clk);
+ spin_lock_irqsave(&bank->lock, flags);
+
+ val = readl_relaxed(bank->base + alt_offset);
+ val &= ~GENMASK(alt_shift + 3, alt_shift);
+ val |= (alt << alt_shift);
+ writel_relaxed(val, bank->base + alt_offset);
+
+ val = readl_relaxed(bank->base + STM32_GPIO_MODER);
+ val &= ~GENMASK(pin * 2 + 1, pin * 2);
+ val |= mode << (pin * 2);
+ writel_relaxed(val, bank->base + STM32_GPIO_MODER);
+
+ spin_unlock_irqrestore(&bank->lock, flags);
+ clk_disable(bank->clk);
+}
+
+static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
+ unsigned function,
+ unsigned group)
+{
+ bool ret;
+ struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct stm32_pinctrl_group *g = pctl->groups + group;
+ struct pinctrl_gpio_range *range;
+ struct stm32_gpio_bank *bank;
+ u32 mode, alt;
+ int pin;
+
+ ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
+ if (!ret) {
+ dev_err(pctl->dev, "invalid function %d on group %d .\n",
+ function, group);
+ return -EINVAL;
+ }
+
+ range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
+ bank = gpio_range_to_bank(range);
+ pin = stm32_gpio_pin(g->pin);
+
+ mode = stm32_gpio_get_mode(function);
+ alt = stm32_gpio_get_alt(function);
+
+ stm32_pmx_set_mode(bank, pin, mode, alt);
+
+ return 0;
+}
+
+static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range, unsigned gpio,
+ bool input)
+{
+ struct stm32_gpio_bank *bank = gpio_range_to_bank(range);
+ int pin = stm32_gpio_pin(gpio);
+
+ stm32_pmx_set_mode(bank, pin, !input, 0);
+
+ return 0;
+}
+
+static const struct pinmux_ops stm32_pmx_ops = {
+ .get_functions_count = stm32_pmx_get_funcs_cnt,
+ .get_function_name = stm32_pmx_get_func_name,
+ .get_function_groups = stm32_pmx_get_func_groups,
+ .set_mux = stm32_pmx_set_mux,
+ .gpio_set_direction = stm32_pmx_gpio_set_direction,
+};
+
+/* Pinconf functions */
+
+static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
+ unsigned offset, u32 drive)
+{
+ unsigned long flags;
+ u32 val;
+
+ clk_enable(bank->clk);
+ spin_lock_irqsave(&bank->lock, flags);
+
+ val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
+ val &= ~BIT(offset);
+ val |= drive << offset;
+ writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
+
+ spin_unlock_irqrestore(&bank->lock, flags);
+ clk_disable(bank->clk);
+}
+
+static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
+ unsigned offset, u32 speed)
+{
+ unsigned long flags;
+ u32 val;
+
+ clk_enable(bank->clk);
+ spin_lock_irqsave(&bank->lock, flags);
+
+ val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
+ val &= ~GENMASK(offset * 2 + 1, offset * 2);
+ val |= speed << (offset * 2);
+ writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
+
+ spin_unlock_irqrestore(&bank->lock, flags);
+ clk_disable(bank->clk);
+}
+
+static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
+ unsigned offset, u32 bias)
+{
+ unsigned long flags;
+ u32 val;
+
+ clk_enable(bank->clk);
+ spin_lock_irqsave(&bank->lock, flags);
+
+ val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
+ val &= ~GENMASK(offset * 2 + 1, offset * 2);
+ val |= bias << (offset * 2);
+ writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
+
+ spin_unlock_irqrestore(&bank->lock, flags);
+ clk_disable(bank->clk);
+}
+
+static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
+ unsigned int pin, enum pin_config_param param,
+ enum pin_config_param arg)
+{
+ struct pinctrl_gpio_range *range;
+ struct stm32_gpio_bank *bank;
+ int offset, ret = 0;
+
+ range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
+ bank = gpio_range_to_bank(range);
+ offset = stm32_gpio_pin(pin);
+
+ switch (param) {
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ stm32_pconf_set_driving(bank, offset, 0);
+ break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ stm32_pconf_set_driving(bank, offset, 1);
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ stm32_pconf_set_speed(bank, offset, arg);
+ break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ stm32_pconf_set_bias(bank, offset, 0);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ stm32_pconf_set_bias(bank, offset, 1);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ stm32_pconf_set_bias(bank, offset, 2);
+ break;
+ case PIN_CONFIG_OUTPUT:
+ __stm32_gpio_set(bank, offset, arg);
+ ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned group,
+ unsigned long *config)
+{
+ struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *config = pctl->groups[group].config;
+
+ return 0;
+}
+
+static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
+ unsigned long *configs, unsigned num_configs)
+{
+ struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct stm32_pinctrl_group *g = &pctl->groups[group];
+ int i, ret;
+
+ for (i = 0; i < num_configs; i++) {
+ ret = stm32_pconf_parse_conf(pctldev, g->pin,
+ pinconf_to_config_param(configs[i]),
+ pinconf_to_config_argument(configs[i]));
+ if (ret < 0)
+ return ret;
+
+ g->config = configs[i];
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops stm32_pconf_ops = {
+ .pin_config_group_get = stm32_pconf_group_get,
+ .pin_config_group_set = stm32_pconf_group_set,
+};
+
+static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
+ struct device_node *np)
+{
+ int bank_nr = pctl->nbanks;
+ struct stm32_gpio_bank *bank = &pctl->banks[bank_nr];
+ struct pinctrl_gpio_range *range = &bank->range;
+ struct device *dev = pctl->dev;
+ struct resource res;
+ struct reset_control *rstc;
+ int err, npins;
+
+ rstc = of_reset_control_get(np, NULL);
+ if (!IS_ERR(rstc))
+ reset_control_deassert(rstc);
+
+ if (of_address_to_resource(np, 0, &res))
+ return -ENODEV;
+
+ bank->base = devm_ioremap_resource(dev, &res);
+ if (IS_ERR(bank->base))
+ return PTR_ERR(bank->base);
+
+ bank->clk = of_clk_get_by_name(np, NULL);
+ if (IS_ERR(bank->clk)) {
+ dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
+ return PTR_ERR(bank->clk);
+ }
+
+ err = clk_prepare(bank->clk);
+ if (err) {
+ dev_err(dev, "failed to prepare clk (%d)\n", err);
+ return err;
+ }
+
+ npins = pctl->match_data->npins;
+ npins -= bank_nr * STM32_GPIO_PINS_PER_BANK;
+ if (npins < 0)
+ return -EINVAL;
+ else if (npins > STM32_GPIO_PINS_PER_BANK)
+ npins = STM32_GPIO_PINS_PER_BANK;
+
+ bank->gpio_chip = stm32_gpio_template;
+ bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
+ bank->gpio_chip.ngpio = npins;
+ bank->gpio_chip.of_node = np;
+ bank->gpio_chip.parent = dev;
+ spin_lock_init(&bank->lock);
+
+ of_property_read_string(np, "st,bank-name", &range->name);
+ bank->gpio_chip.label = range->name;
+
+ range->id = bank_nr;
+ range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK;
+ range->npins = bank->gpio_chip.ngpio;
+ range->gc = &bank->gpio_chip;
+ err = gpiochip_add_data(&bank->gpio_chip, bank);
+ if (err) {
+ dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
+ return err;
+ }
+
+ dev_info(dev, "%s bank added\n", range->name);
+ return 0;
+}
+
+static int stm32_pctrl_build_state(struct platform_device *pdev)
+{
+ struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
+ int i;
+
+ pctl->ngroups = pctl->match_data->npins;
+
+ /* Allocate groups */
+ pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
+ sizeof(*pctl->groups), GFP_KERNEL);
+ if (!pctl->groups)
+ return -ENOMEM;
+
+ /* We assume that one pin is one group, use pin name as group name. */
+ pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
+ sizeof(*pctl->grp_names), GFP_KERNEL);
+ if (!pctl->grp_names)
+ return -ENOMEM;
+
+ for (i = 0; i < pctl->match_data->npins; i++) {
+ const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
+ struct stm32_pinctrl_group *group = pctl->groups + i;
+
+ group->name = pin->pin.name;
+ group->pin = pin->pin.number;
+
+ pctl->grp_names[i] = pin->pin.name;
+ }
+
+ return 0;
+}
+
+int stm32_pctl_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *child;
+ const struct of_device_id *match;
+ struct device *dev = &pdev->dev;
+ struct stm32_pinctrl *pctl;
+ struct pinctrl_pin_desc *pins;
+ int i, ret, banks = 0;
+
+ if (!np)
+ return -EINVAL;
+
+ match = of_match_device(dev->driver->of_match_table, dev);
+ if (!match || !match->data)
+ return -EINVAL;
+
+ if (!of_find_property(np, "pins-are-numbered", NULL)) {
+ dev_err(dev, "only support pins-are-numbered format\n");
+ return -EINVAL;
+ }
+
+ pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
+ if (!pctl)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pctl);
+
+ pctl->dev = dev;
+ pctl->match_data = match->data;
+ ret = stm32_pctrl_build_state(pdev);
+ if (ret) {
+ dev_err(dev, "build state failed: %d\n", ret);
+ return -EINVAL;
+ }
+
+ for_each_child_of_node(np, child)
+ if (of_property_read_bool(child, "gpio-controller"))
+ banks++;
+
+ if (!banks) {
+ dev_err(dev, "at least one GPIO bank is required\n");
+ return -EINVAL;
+ }
+
+ pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
+ GFP_KERNEL);
+ if (!pctl->banks)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ if (of_property_read_bool(child, "gpio-controller")) {
+ ret = stm32_gpiolib_register_bank(pctl, child);
+ if (ret)
+ return ret;
+
+ pctl->nbanks++;
+ }
+ }
+
+ pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins),
+ GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+
+ for (i = 0; i < pctl->match_data->npins; i++)
+ pins[i] = pctl->match_data->pins[i].pin;
+
+ pctl->pctl_desc.name = dev_name(&pdev->dev);
+ pctl->pctl_desc.owner = THIS_MODULE;
+ pctl->pctl_desc.pins = pins;
+ pctl->pctl_desc.npins = pctl->match_data->npins;
+ pctl->pctl_desc.confops = &stm32_pconf_ops;
+ pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
+ pctl->pctl_desc.pmxops = &stm32_pmx_ops;
+ pctl->dev = &pdev->dev;
+
+ pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl);
+ if (!pctl->pctl_dev) {
+ dev_err(&pdev->dev, "Failed pinctrl registration\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < pctl->nbanks; i++)
+ pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[i].range);
+
+ dev_info(dev, "Pinctrl STM32 initialized\n");
+
+ return 0;
+}
+
--- /dev/null
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ * License terms: GNU General Public License (GPL), version 2
+ */
+#ifndef __PINCTRL_STM32_H
+#define __PINCTRL_STM32_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
+#define STM32_PIN_NO(x) ((x) << 8)
+#define STM32_GET_PIN_NO(x) ((x) >> 8)
+#define STM32_GET_PIN_FUNC(x) ((x) & 0xff)
+
+#define STM32_PIN_GPIO 0
+#define STM32_PIN_AF(x) ((x) + 1)
+#define STM32_PIN_ANALOG (STM32_PIN_AF(15) + 1)
+
+struct stm32_desc_function {
+ const char *name;
+ const unsigned char num;
+};
+
+struct stm32_desc_pin {
+ struct pinctrl_pin_desc pin;
+ const struct stm32_desc_function *functions;
+};
+
+#define STM32_PIN(_pin, ...) \
+ { \
+ .pin = _pin, \
+ .functions = (struct stm32_desc_function[]){ \
+ __VA_ARGS__, { } }, \
+ }
+
+#define STM32_FUNCTION(_num, _name) \
+ { \
+ .num = _num, \
+ .name = _name, \
+ }
+
+struct stm32_pinctrl_match_data {
+ const struct stm32_desc_pin *pins;
+ const unsigned int npins;
+};
+
+int stm32_pctl_probe(struct platform_device *pdev);
+
+#endif /* __PINCTRL_STM32_H */
+
--- /dev/null
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ * License terms: GNU General Public License (GPL), version 2
+ */
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-stm32.h"
+
+static const struct stm32_desc_pin stm32f429_pins[] = {
+ STM32_PIN(
+ PINCTRL_PIN(0, "PA0"),
+ STM32_FUNCTION(0, "GPIOA0"),
+ STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
+ STM32_FUNCTION(3, "TIM5_CH1"),
+ STM32_FUNCTION(4, "TIM8_ETR"),
+ STM32_FUNCTION(8, "USART2_CTS"),
+ STM32_FUNCTION(9, "UART4_TX"),
+ STM32_FUNCTION(12, "ETH_MII_CRS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(1, "PA1"),
+ STM32_FUNCTION(0, "GPIOA1"),
+ STM32_FUNCTION(2, "TIM2_CH2"),
+ STM32_FUNCTION(3, "TIM5_CH2"),
+ STM32_FUNCTION(8, "USART2_RTS"),
+ STM32_FUNCTION(9, "UART4_RX"),
+ STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(2, "PA2"),
+ STM32_FUNCTION(0, "GPIOA2"),
+ STM32_FUNCTION(2, "TIM2_CH3"),
+ STM32_FUNCTION(3, "TIM5_CH3"),
+ STM32_FUNCTION(4, "TIM9_CH1"),
+ STM32_FUNCTION(8, "USART2_TX"),
+ STM32_FUNCTION(12, "ETH_MDIO"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(3, "PA3"),
+ STM32_FUNCTION(0, "GPIOA3"),
+ STM32_FUNCTION(2, "TIM2_CH4"),
+ STM32_FUNCTION(3, "TIM5_CH4"),
+ STM32_FUNCTION(4, "TIM9_CH2"),
+ STM32_FUNCTION(8, "USART2_RX"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D0"),
+ STM32_FUNCTION(12, "ETH_MII_COL"),
+ STM32_FUNCTION(15, "LCD_B5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(4, "PA4"),
+ STM32_FUNCTION(0, "GPIOA4"),
+ STM32_FUNCTION(6, "SPI1_NSS"),
+ STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(8, "USART2_CK"),
+ STM32_FUNCTION(13, "OTG_HS_SOF"),
+ STM32_FUNCTION(14, "DCMI_HSYNC"),
+ STM32_FUNCTION(15, "LCD_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(5, "PA5"),
+ STM32_FUNCTION(0, "GPIOA5"),
+ STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
+ STM32_FUNCTION(4, "TIM8_CH1N"),
+ STM32_FUNCTION(6, "SPI1_SCK"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_CK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(6, "PA6"),
+ STM32_FUNCTION(0, "GPIOA6"),
+ STM32_FUNCTION(2, "TIM1_BKIN"),
+ STM32_FUNCTION(3, "TIM3_CH1"),
+ STM32_FUNCTION(4, "TIM8_BKIN"),
+ STM32_FUNCTION(6, "SPI1_MISO"),
+ STM32_FUNCTION(10, "TIM13_CH1"),
+ STM32_FUNCTION(14, "DCMI_PIXCLK"),
+ STM32_FUNCTION(15, "LCD_G2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(7, "PA7"),
+ STM32_FUNCTION(0, "GPIOA7"),
+ STM32_FUNCTION(2, "TIM1_CH1N"),
+ STM32_FUNCTION(3, "TIM3_CH2"),
+ STM32_FUNCTION(4, "TIM8_CH1N"),
+ STM32_FUNCTION(6, "SPI1_MOSI"),
+ STM32_FUNCTION(10, "TIM14_CH1"),
+ STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(8, "PA8"),
+ STM32_FUNCTION(0, "GPIOA8"),
+ STM32_FUNCTION(1, "MCO1"),
+ STM32_FUNCTION(2, "TIM1_CH1"),
+ STM32_FUNCTION(5, "I2C3_SCL"),
+ STM32_FUNCTION(8, "USART1_CK"),
+ STM32_FUNCTION(11, "OTG_FS_SOF"),
+ STM32_FUNCTION(15, "LCD_R6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(9, "PA9"),
+ STM32_FUNCTION(0, "GPIOA9"),
+ STM32_FUNCTION(2, "TIM1_CH2"),
+ STM32_FUNCTION(5, "I2C3_SMBA"),
+ STM32_FUNCTION(8, "USART1_TX"),
+ STM32_FUNCTION(14, "DCMI_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(10, "PA10"),
+ STM32_FUNCTION(0, "GPIOA10"),
+ STM32_FUNCTION(2, "TIM1_CH3"),
+ STM32_FUNCTION(8, "USART1_RX"),
+ STM32_FUNCTION(11, "OTG_FS_ID"),
+ STM32_FUNCTION(14, "DCMI_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(11, "PA11"),
+ STM32_FUNCTION(0, "GPIOA11"),
+ STM32_FUNCTION(2, "TIM1_CH4"),
+ STM32_FUNCTION(8, "USART1_CTS"),
+ STM32_FUNCTION(10, "CAN1_RX"),
+ STM32_FUNCTION(11, "OTG_FS_DM"),
+ STM32_FUNCTION(15, "LCD_R4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(12, "PA12"),
+ STM32_FUNCTION(0, "GPIOA12"),
+ STM32_FUNCTION(2, "TIM1_ETR"),
+ STM32_FUNCTION(8, "USART1_RTS"),
+ STM32_FUNCTION(10, "CAN1_TX"),
+ STM32_FUNCTION(11, "OTG_FS_DP"),
+ STM32_FUNCTION(15, "LCD_R5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(13, "PA13"),
+ STM32_FUNCTION(0, "GPIOA13"),
+ STM32_FUNCTION(1, "JTMS SWDIO"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(14, "PA14"),
+ STM32_FUNCTION(0, "GPIOA14"),
+ STM32_FUNCTION(1, "JTCK SWCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(15, "PA15"),
+ STM32_FUNCTION(0, "GPIOA15"),
+ STM32_FUNCTION(1, "JTDI"),
+ STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
+ STM32_FUNCTION(6, "SPI1_NSS"),
+ STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(16, "PB0"),
+ STM32_FUNCTION(0, "GPIOB0"),
+ STM32_FUNCTION(2, "TIM1_CH2N"),
+ STM32_FUNCTION(3, "TIM3_CH3"),
+ STM32_FUNCTION(4, "TIM8_CH2N"),
+ STM32_FUNCTION(10, "LCD_R3"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D1"),
+ STM32_FUNCTION(12, "ETH_MII_RXD2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(17, "PB1"),
+ STM32_FUNCTION(0, "GPIOB1"),
+ STM32_FUNCTION(2, "TIM1_CH3N"),
+ STM32_FUNCTION(3, "TIM3_CH4"),
+ STM32_FUNCTION(4, "TIM8_CH3N"),
+ STM32_FUNCTION(10, "LCD_R6"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D2"),
+ STM32_FUNCTION(12, "ETH_MII_RXD3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(18, "PB2"),
+ STM32_FUNCTION(0, "GPIOB2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(19, "PB3"),
+ STM32_FUNCTION(0, "GPIOB3"),
+ STM32_FUNCTION(1, "JTDO TRACESWO"),
+ STM32_FUNCTION(2, "TIM2_CH2"),
+ STM32_FUNCTION(6, "SPI1_SCK"),
+ STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(20, "PB4"),
+ STM32_FUNCTION(0, "GPIOB4"),
+ STM32_FUNCTION(1, "NJTRST"),
+ STM32_FUNCTION(3, "TIM3_CH1"),
+ STM32_FUNCTION(6, "SPI1_MISO"),
+ STM32_FUNCTION(7, "SPI3_MISO"),
+ STM32_FUNCTION(8, "I2S3EXT_SD"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(21, "PB5"),
+ STM32_FUNCTION(0, "GPIOB5"),
+ STM32_FUNCTION(3, "TIM3_CH2"),
+ STM32_FUNCTION(5, "I2C1_SMBA"),
+ STM32_FUNCTION(6, "SPI1_MOSI"),
+ STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
+ STM32_FUNCTION(10, "CAN2_RX"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D7"),
+ STM32_FUNCTION(12, "ETH_PPS_OUT"),
+ STM32_FUNCTION(13, "FMC_SDCKE1"),
+ STM32_FUNCTION(14, "DCMI_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(22, "PB6"),
+ STM32_FUNCTION(0, "GPIOB6"),
+ STM32_FUNCTION(3, "TIM4_CH1"),
+ STM32_FUNCTION(5, "I2C1_SCL"),
+ STM32_FUNCTION(8, "USART1_TX"),
+ STM32_FUNCTION(10, "CAN2_TX"),
+ STM32_FUNCTION(13, "FMC_SDNE1"),
+ STM32_FUNCTION(14, "DCMI_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(23, "PB7"),
+ STM32_FUNCTION(0, "GPIOB7"),
+ STM32_FUNCTION(3, "TIM4_CH2"),
+ STM32_FUNCTION(5, "I2C1_SDA"),
+ STM32_FUNCTION(8, "USART1_RX"),
+ STM32_FUNCTION(13, "FMC_NL"),
+ STM32_FUNCTION(14, "DCMI_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(24, "PB8"),
+ STM32_FUNCTION(0, "GPIOB8"),
+ STM32_FUNCTION(3, "TIM4_CH3"),
+ STM32_FUNCTION(4, "TIM10_CH1"),
+ STM32_FUNCTION(5, "I2C1_SCL"),
+ STM32_FUNCTION(10, "CAN1_RX"),
+ STM32_FUNCTION(12, "ETH_MII_TXD3"),
+ STM32_FUNCTION(13, "SDIO_D4"),
+ STM32_FUNCTION(14, "DCMI_D6"),
+ STM32_FUNCTION(15, "LCD_B6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(25, "PB9"),
+ STM32_FUNCTION(0, "GPIOB9"),
+ STM32_FUNCTION(3, "TIM4_CH4"),
+ STM32_FUNCTION(4, "TIM11_CH1"),
+ STM32_FUNCTION(5, "I2C1_SDA"),
+ STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(10, "CAN1_TX"),
+ STM32_FUNCTION(13, "SDIO_D5"),
+ STM32_FUNCTION(14, "DCMI_D7"),
+ STM32_FUNCTION(15, "LCD_B7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(26, "PB10"),
+ STM32_FUNCTION(0, "GPIOB10"),
+ STM32_FUNCTION(2, "TIM2_CH3"),
+ STM32_FUNCTION(5, "I2C2_SCL"),
+ STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(8, "USART3_TX"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D3"),
+ STM32_FUNCTION(12, "ETH_MII_RX_ER"),
+ STM32_FUNCTION(15, "LCD_G4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(27, "PB11"),
+ STM32_FUNCTION(0, "GPIOB11"),
+ STM32_FUNCTION(2, "TIM2_CH4"),
+ STM32_FUNCTION(5, "I2C2_SDA"),
+ STM32_FUNCTION(8, "USART3_RX"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D4"),
+ STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
+ STM32_FUNCTION(15, "LCD_G5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(28, "PB12"),
+ STM32_FUNCTION(0, "GPIOB12"),
+ STM32_FUNCTION(2, "TIM1_BKIN"),
+ STM32_FUNCTION(5, "I2C2_SMBA"),
+ STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(8, "USART3_CK"),
+ STM32_FUNCTION(10, "CAN2_RX"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D5"),
+ STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
+ STM32_FUNCTION(13, "OTG_HS_ID"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(29, "PB13"),
+ STM32_FUNCTION(0, "GPIOB13"),
+ STM32_FUNCTION(2, "TIM1_CH1N"),
+ STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(8, "USART3_CTS"),
+ STM32_FUNCTION(10, "CAN2_TX"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D6"),
+ STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(30, "PB14"),
+ STM32_FUNCTION(0, "GPIOB14"),
+ STM32_FUNCTION(2, "TIM1_CH2N"),
+ STM32_FUNCTION(4, "TIM8_CH2N"),
+ STM32_FUNCTION(6, "SPI2_MISO"),
+ STM32_FUNCTION(7, "I2S2EXT_SD"),
+ STM32_FUNCTION(8, "USART3_RTS"),
+ STM32_FUNCTION(10, "TIM12_CH1"),
+ STM32_FUNCTION(13, "OTG_HS_DM"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(31, "PB15"),
+ STM32_FUNCTION(0, "GPIOB15"),
+ STM32_FUNCTION(1, "RTC_REFIN"),
+ STM32_FUNCTION(2, "TIM1_CH3N"),
+ STM32_FUNCTION(4, "TIM8_CH3N"),
+ STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
+ STM32_FUNCTION(10, "TIM12_CH2"),
+ STM32_FUNCTION(13, "OTG_HS_DP"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(32, "PC0"),
+ STM32_FUNCTION(0, "GPIOC0"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_STP"),
+ STM32_FUNCTION(13, "FMC_SDNWE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(33, "PC1"),
+ STM32_FUNCTION(0, "GPIOC1"),
+ STM32_FUNCTION(12, "ETH_MDC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(34, "PC2"),
+ STM32_FUNCTION(0, "GPIOC2"),
+ STM32_FUNCTION(6, "SPI2_MISO"),
+ STM32_FUNCTION(7, "I2S2EXT_SD"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
+ STM32_FUNCTION(12, "ETH_MII_TXD2"),
+ STM32_FUNCTION(13, "FMC_SDNE0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(35, "PC3"),
+ STM32_FUNCTION(0, "GPIOC3"),
+ STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
+ STM32_FUNCTION(12, "ETH_MII_TX_CLK"),
+ STM32_FUNCTION(13, "FMC_SDCKE0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(36, "PC4"),
+ STM32_FUNCTION(0, "GPIOC4"),
+ STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(37, "PC5"),
+ STM32_FUNCTION(0, "GPIOC5"),
+ STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(38, "PC6"),
+ STM32_FUNCTION(0, "GPIOC6"),
+ STM32_FUNCTION(3, "TIM3_CH1"),
+ STM32_FUNCTION(4, "TIM8_CH1"),
+ STM32_FUNCTION(6, "I2S2_MCK"),
+ STM32_FUNCTION(9, "USART6_TX"),
+ STM32_FUNCTION(13, "SDIO_D6"),
+ STM32_FUNCTION(14, "DCMI_D0"),
+ STM32_FUNCTION(15, "LCD_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(39, "PC7"),
+ STM32_FUNCTION(0, "GPIOC7"),
+ STM32_FUNCTION(3, "TIM3_CH2"),
+ STM32_FUNCTION(4, "TIM8_CH2"),
+ STM32_FUNCTION(7, "I2S3_MCK"),
+ STM32_FUNCTION(9, "USART6_RX"),
+ STM32_FUNCTION(13, "SDIO_D7"),
+ STM32_FUNCTION(14, "DCMI_D1"),
+ STM32_FUNCTION(15, "LCD_G6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(40, "PC8"),
+ STM32_FUNCTION(0, "GPIOC8"),
+ STM32_FUNCTION(3, "TIM3_CH3"),
+ STM32_FUNCTION(4, "TIM8_CH3"),
+ STM32_FUNCTION(9, "USART6_CK"),
+ STM32_FUNCTION(13, "SDIO_D0"),
+ STM32_FUNCTION(14, "DCMI_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(41, "PC9"),
+ STM32_FUNCTION(0, "GPIOC9"),
+ STM32_FUNCTION(1, "MCO2"),
+ STM32_FUNCTION(3, "TIM3_CH4"),
+ STM32_FUNCTION(4, "TIM8_CH4"),
+ STM32_FUNCTION(5, "I2C3_SDA"),
+ STM32_FUNCTION(6, "I2S_CKIN"),
+ STM32_FUNCTION(13, "SDIO_D1"),
+ STM32_FUNCTION(14, "DCMI_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(42, "PC10"),
+ STM32_FUNCTION(0, "GPIOC10"),
+ STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(8, "USART3_TX"),
+ STM32_FUNCTION(9, "UART4_TX"),
+ STM32_FUNCTION(13, "SDIO_D2"),
+ STM32_FUNCTION(14, "DCMI_D8"),
+ STM32_FUNCTION(15, "LCD_R2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(43, "PC11"),
+ STM32_FUNCTION(0, "GPIOC11"),
+ STM32_FUNCTION(6, "I2S3EXT_SD"),
+ STM32_FUNCTION(7, "SPI3_MISO"),
+ STM32_FUNCTION(8, "USART3_RX"),
+ STM32_FUNCTION(9, "UART4_RX"),
+ STM32_FUNCTION(13, "SDIO_D3"),
+ STM32_FUNCTION(14, "DCMI_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(44, "PC12"),
+ STM32_FUNCTION(0, "GPIOC12"),
+ STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
+ STM32_FUNCTION(8, "USART3_CK"),
+ STM32_FUNCTION(9, "UART5_TX"),
+ STM32_FUNCTION(13, "SDIO_CK"),
+ STM32_FUNCTION(14, "DCMI_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(45, "PC13"),
+ STM32_FUNCTION(0, "GPIOC13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(46, "PC14"),
+ STM32_FUNCTION(0, "GPIOC14"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(47, "PC15"),
+ STM32_FUNCTION(0, "GPIOC15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(48, "PD0"),
+ STM32_FUNCTION(0, "GPIOD0"),
+ STM32_FUNCTION(10, "CAN1_RX"),
+ STM32_FUNCTION(13, "FMC_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(49, "PD1"),
+ STM32_FUNCTION(0, "GPIOD1"),
+ STM32_FUNCTION(10, "CAN1_TX"),
+ STM32_FUNCTION(13, "FMC_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(50, "PD2"),
+ STM32_FUNCTION(0, "GPIOD2"),
+ STM32_FUNCTION(3, "TIM3_ETR"),
+ STM32_FUNCTION(9, "UART5_RX"),
+ STM32_FUNCTION(13, "SDIO_CMD"),
+ STM32_FUNCTION(14, "DCMI_D11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(51, "PD3"),
+ STM32_FUNCTION(0, "GPIOD3"),
+ STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(8, "USART2_CTS"),
+ STM32_FUNCTION(13, "FMC_CLK"),
+ STM32_FUNCTION(14, "DCMI_D5"),
+ STM32_FUNCTION(15, "LCD_G7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(52, "PD4"),
+ STM32_FUNCTION(0, "GPIOD4"),
+ STM32_FUNCTION(8, "USART2_RTS"),
+ STM32_FUNCTION(13, "FMC_NOE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(53, "PD5"),
+ STM32_FUNCTION(0, "GPIOD5"),
+ STM32_FUNCTION(8, "USART2_TX"),
+ STM32_FUNCTION(13, "FMC_NWE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(54, "PD6"),
+ STM32_FUNCTION(0, "GPIOD6"),
+ STM32_FUNCTION(6, "SPI3_MOSI I2S3_SD"),
+ STM32_FUNCTION(7, "SAI1_SD_A"),
+ STM32_FUNCTION(8, "USART2_RX"),
+ STM32_FUNCTION(13, "FMC_NWAIT"),
+ STM32_FUNCTION(14, "DCMI_D10"),
+ STM32_FUNCTION(15, "LCD_B2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(55, "PD7"),
+ STM32_FUNCTION(0, "GPIOD7"),
+ STM32_FUNCTION(8, "USART2_CK"),
+ STM32_FUNCTION(13, "FMC_NE1 FMC_NCE2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(56, "PD8"),
+ STM32_FUNCTION(0, "GPIOD8"),
+ STM32_FUNCTION(8, "USART3_TX"),
+ STM32_FUNCTION(13, "FMC_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(57, "PD9"),
+ STM32_FUNCTION(0, "GPIOD9"),
+ STM32_FUNCTION(8, "USART3_RX"),
+ STM32_FUNCTION(13, "FMC_D14"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(58, "PD10"),
+ STM32_FUNCTION(0, "GPIOD10"),
+ STM32_FUNCTION(8, "USART3_CK"),
+ STM32_FUNCTION(13, "FMC_D15"),
+ STM32_FUNCTION(15, "LCD_B3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(59, "PD11"),
+ STM32_FUNCTION(0, "GPIOD11"),
+ STM32_FUNCTION(8, "USART3_CTS"),
+ STM32_FUNCTION(13, "FMC_A16"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(60, "PD12"),
+ STM32_FUNCTION(0, "GPIOD12"),
+ STM32_FUNCTION(3, "TIM4_CH1"),
+ STM32_FUNCTION(8, "USART3_RTS"),
+ STM32_FUNCTION(13, "FMC_A17"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(61, "PD13"),
+ STM32_FUNCTION(0, "GPIOD13"),
+ STM32_FUNCTION(3, "TIM4_CH2"),
+ STM32_FUNCTION(13, "FMC_A18"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(62, "PD14"),
+ STM32_FUNCTION(0, "GPIOD14"),
+ STM32_FUNCTION(3, "TIM4_CH3"),
+ STM32_FUNCTION(13, "FMC_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(63, "PD15"),
+ STM32_FUNCTION(0, "GPIOD15"),
+ STM32_FUNCTION(3, "TIM4_CH4"),
+ STM32_FUNCTION(13, "FMC_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(64, "PE0"),
+ STM32_FUNCTION(0, "GPIOE0"),
+ STM32_FUNCTION(3, "TIM4_ETR"),
+ STM32_FUNCTION(9, "UART8_RX"),
+ STM32_FUNCTION(13, "FMC_NBL0"),
+ STM32_FUNCTION(14, "DCMI_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(65, "PE1"),
+ STM32_FUNCTION(0, "GPIOE1"),
+ STM32_FUNCTION(9, "UART8_TX"),
+ STM32_FUNCTION(13, "FMC_NBL1"),
+ STM32_FUNCTION(14, "DCMI_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(66, "PE2"),
+ STM32_FUNCTION(0, "GPIOE2"),
+ STM32_FUNCTION(1, "TRACECLK"),
+ STM32_FUNCTION(6, "SPI4_SCK"),
+ STM32_FUNCTION(7, "SAI1_MCLK_A"),
+ STM32_FUNCTION(12, "ETH_MII_TXD3"),
+ STM32_FUNCTION(13, "FMC_A23"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(67, "PE3"),
+ STM32_FUNCTION(0, "GPIOE3"),
+ STM32_FUNCTION(1, "TRACED0"),
+ STM32_FUNCTION(7, "SAI1_SD_B"),
+ STM32_FUNCTION(13, "FMC_A19"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(68, "PE4"),
+ STM32_FUNCTION(0, "GPIOE4"),
+ STM32_FUNCTION(1, "TRACED1"),
+ STM32_FUNCTION(6, "SPI4_NSS"),
+ STM32_FUNCTION(7, "SAI1_FS_A"),
+ STM32_FUNCTION(13, "FMC_A20"),
+ STM32_FUNCTION(14, "DCMI_D4"),
+ STM32_FUNCTION(15, "LCD_B0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(69, "PE5"),
+ STM32_FUNCTION(0, "GPIOE5"),
+ STM32_FUNCTION(1, "TRACED2"),
+ STM32_FUNCTION(4, "TIM9_CH1"),
+ STM32_FUNCTION(6, "SPI4_MISO"),
+ STM32_FUNCTION(7, "SAI1_SCK_A"),
+ STM32_FUNCTION(13, "FMC_A21"),
+ STM32_FUNCTION(14, "DCMI_D6"),
+ STM32_FUNCTION(15, "LCD_G0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(70, "PE6"),
+ STM32_FUNCTION(0, "GPIOE6"),
+ STM32_FUNCTION(1, "TRACED3"),
+ STM32_FUNCTION(4, "TIM9_CH2"),
+ STM32_FUNCTION(6, "SPI4_MOSI"),
+ STM32_FUNCTION(7, "SAI1_SD_A"),
+ STM32_FUNCTION(13, "FMC_A22"),
+ STM32_FUNCTION(14, "DCMI_D7"),
+ STM32_FUNCTION(15, "LCD_G1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(71, "PE7"),
+ STM32_FUNCTION(0, "GPIOE7"),
+ STM32_FUNCTION(2, "TIM1_ETR"),
+ STM32_FUNCTION(9, "UART7_RX"),
+ STM32_FUNCTION(13, "FMC_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(72, "PE8"),
+ STM32_FUNCTION(0, "GPIOE8"),
+ STM32_FUNCTION(2, "TIM1_CH1N"),
+ STM32_FUNCTION(9, "UART7_TX"),
+ STM32_FUNCTION(13, "FMC_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(73, "PE9"),
+ STM32_FUNCTION(0, "GPIOE9"),
+ STM32_FUNCTION(2, "TIM1_CH1"),
+ STM32_FUNCTION(13, "FMC_D6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(74, "PE10"),
+ STM32_FUNCTION(0, "GPIOE10"),
+ STM32_FUNCTION(2, "TIM1_CH2N"),
+ STM32_FUNCTION(13, "FMC_D7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(75, "PE11"),
+ STM32_FUNCTION(0, "GPIOE11"),
+ STM32_FUNCTION(2, "TIM1_CH2"),
+ STM32_FUNCTION(6, "SPI4_NSS"),
+ STM32_FUNCTION(13, "FMC_D8"),
+ STM32_FUNCTION(15, "LCD_G3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(76, "PE12"),
+ STM32_FUNCTION(0, "GPIOE12"),
+ STM32_FUNCTION(2, "TIM1_CH3N"),
+ STM32_FUNCTION(6, "SPI4_SCK"),
+ STM32_FUNCTION(13, "FMC_D9"),
+ STM32_FUNCTION(15, "LCD_B4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(77, "PE13"),
+ STM32_FUNCTION(0, "GPIOE13"),
+ STM32_FUNCTION(2, "TIM1_CH3"),
+ STM32_FUNCTION(6, "SPI4_MISO"),
+ STM32_FUNCTION(13, "FMC_D10"),
+ STM32_FUNCTION(15, "LCD_DE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(78, "PE14"),
+ STM32_FUNCTION(0, "GPIOE14"),
+ STM32_FUNCTION(2, "TIM1_CH4"),
+ STM32_FUNCTION(6, "SPI4_MOSI"),
+ STM32_FUNCTION(13, "FMC_D11"),
+ STM32_FUNCTION(15, "LCD_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(79, "PE15"),
+ STM32_FUNCTION(0, "GPIOE15"),
+ STM32_FUNCTION(2, "TIM1_BKIN"),
+ STM32_FUNCTION(13, "FMC_D12"),
+ STM32_FUNCTION(15, "LCD_R7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(80, "PF0"),
+ STM32_FUNCTION(0, "GPIOF0"),
+ STM32_FUNCTION(5, "I2C2_SDA"),
+ STM32_FUNCTION(13, "FMC_A0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(81, "PF1"),
+ STM32_FUNCTION(0, "GPIOF1"),
+ STM32_FUNCTION(5, "I2C2_SCL"),
+ STM32_FUNCTION(13, "FMC_A1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(82, "PF2"),
+ STM32_FUNCTION(0, "GPIOF2"),
+ STM32_FUNCTION(5, "I2C2_SMBA"),
+ STM32_FUNCTION(13, "FMC_A2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(83, "PF3"),
+ STM32_FUNCTION(0, "GPIOF3"),
+ STM32_FUNCTION(13, "FMC_A3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(84, "PF4"),
+ STM32_FUNCTION(0, "GPIOF4"),
+ STM32_FUNCTION(13, "FMC_A4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(85, "PF5"),
+ STM32_FUNCTION(0, "GPIOF5"),
+ STM32_FUNCTION(13, "FMC_A5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(86, "PF6"),
+ STM32_FUNCTION(0, "GPIOF6"),
+ STM32_FUNCTION(4, "TIM10_CH1"),
+ STM32_FUNCTION(6, "SPI5_NSS"),
+ STM32_FUNCTION(7, "SAI1_SD_B"),
+ STM32_FUNCTION(9, "UART7_RX"),
+ STM32_FUNCTION(13, "FMC_NIORD"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(87, "PF7"),
+ STM32_FUNCTION(0, "GPIOF7"),
+ STM32_FUNCTION(4, "TIM11_CH1"),
+ STM32_FUNCTION(6, "SPI5_SCK"),
+ STM32_FUNCTION(7, "SAI1_MCLK_B"),
+ STM32_FUNCTION(9, "UART7_TX"),
+ STM32_FUNCTION(13, "FMC_NREG"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(88, "PF8"),
+ STM32_FUNCTION(0, "GPIOF8"),
+ STM32_FUNCTION(6, "SPI5_MISO"),
+ STM32_FUNCTION(7, "SAI1_SCK_B"),
+ STM32_FUNCTION(10, "TIM13_CH1"),
+ STM32_FUNCTION(13, "FMC_NIOWR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(89, "PF9"),
+ STM32_FUNCTION(0, "GPIOF9"),
+ STM32_FUNCTION(6, "SPI5_MOSI"),
+ STM32_FUNCTION(7, "SAI1_FS_B"),
+ STM32_FUNCTION(10, "TIM14_CH1"),
+ STM32_FUNCTION(13, "FMC_CD"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(90, "PF10"),
+ STM32_FUNCTION(0, "GPIOF10"),
+ STM32_FUNCTION(13, "FMC_INTR"),
+ STM32_FUNCTION(14, "DCMI_D11"),
+ STM32_FUNCTION(15, "LCD_DE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(91, "PF11"),
+ STM32_FUNCTION(0, "GPIOF11"),
+ STM32_FUNCTION(6, "SPI5_MOSI"),
+ STM32_FUNCTION(13, "FMC_SDNRAS"),
+ STM32_FUNCTION(14, "DCMI_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(92, "PF12"),
+ STM32_FUNCTION(0, "GPIOF12"),
+ STM32_FUNCTION(13, "FMC_A6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(93, "PF13"),
+ STM32_FUNCTION(0, "GPIOF13"),
+ STM32_FUNCTION(13, "FMC_A7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(94, "PF14"),
+ STM32_FUNCTION(0, "GPIOF14"),
+ STM32_FUNCTION(13, "FMC_A8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(95, "PF15"),
+ STM32_FUNCTION(0, "GPIOF15"),
+ STM32_FUNCTION(13, "FMC_A9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(96, "PG0"),
+ STM32_FUNCTION(0, "GPIOG0"),
+ STM32_FUNCTION(13, "FMC_A10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(97, "PG1"),
+ STM32_FUNCTION(0, "GPIOG1"),
+ STM32_FUNCTION(13, "FMC_A11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(98, "PG2"),
+ STM32_FUNCTION(0, "GPIOG2"),
+ STM32_FUNCTION(13, "FMC_A12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(99, "PG3"),
+ STM32_FUNCTION(0, "GPIOG3"),
+ STM32_FUNCTION(13, "FMC_A13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(100, "PG4"),
+ STM32_FUNCTION(0, "GPIOG4"),
+ STM32_FUNCTION(13, "FMC_A14 FMC_BA0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(101, "PG5"),
+ STM32_FUNCTION(0, "GPIOG5"),
+ STM32_FUNCTION(13, "FMC_A15 FMC_BA1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(102, "PG6"),
+ STM32_FUNCTION(0, "GPIOG6"),
+ STM32_FUNCTION(13, "FMC_INT2"),
+ STM32_FUNCTION(14, "DCMI_D12"),
+ STM32_FUNCTION(15, "LCD_R7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(103, "PG7"),
+ STM32_FUNCTION(0, "GPIOG7"),
+ STM32_FUNCTION(9, "USART6_CK"),
+ STM32_FUNCTION(13, "FMC_INT3"),
+ STM32_FUNCTION(14, "DCMI_D13"),
+ STM32_FUNCTION(15, "LCD_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(104, "PG8"),
+ STM32_FUNCTION(0, "GPIOG8"),
+ STM32_FUNCTION(6, "SPI6_NSS"),
+ STM32_FUNCTION(9, "USART6_RTS"),
+ STM32_FUNCTION(12, "ETH_PPS_OUT"),
+ STM32_FUNCTION(13, "FMC_SDCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(105, "PG9"),
+ STM32_FUNCTION(0, "GPIOG9"),
+ STM32_FUNCTION(9, "USART6_RX"),
+ STM32_FUNCTION(13, "FMC_NE2 FMC_NCE3"),
+ STM32_FUNCTION(14, "DCMI_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(106, "PG10"),
+ STM32_FUNCTION(0, "GPIOG10"),
+ STM32_FUNCTION(10, "LCD_G3"),
+ STM32_FUNCTION(13, "FMC_NCE4_1 FMC_NE3"),
+ STM32_FUNCTION(14, "DCMI_D2"),
+ STM32_FUNCTION(15, "LCD_B2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(107, "PG11"),
+ STM32_FUNCTION(0, "GPIOG11"),
+ STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
+ STM32_FUNCTION(13, "FMC_NCE4_2"),
+ STM32_FUNCTION(14, "DCMI_D3"),
+ STM32_FUNCTION(15, "LCD_B3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(108, "PG12"),
+ STM32_FUNCTION(0, "GPIOG12"),
+ STM32_FUNCTION(6, "SPI6_MISO"),
+ STM32_FUNCTION(9, "USART6_RTS"),
+ STM32_FUNCTION(10, "LCD_B4"),
+ STM32_FUNCTION(13, "FMC_NE4"),
+ STM32_FUNCTION(15, "LCD_B1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(109, "PG13"),
+ STM32_FUNCTION(0, "GPIOG13"),
+ STM32_FUNCTION(6, "SPI6_SCK"),
+ STM32_FUNCTION(9, "USART6_CTS"),
+ STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
+ STM32_FUNCTION(13, "FMC_A24"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(110, "PG14"),
+ STM32_FUNCTION(0, "GPIOG14"),
+ STM32_FUNCTION(6, "SPI6_MOSI"),
+ STM32_FUNCTION(9, "USART6_TX"),
+ STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
+ STM32_FUNCTION(13, "FMC_A25"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(111, "PG15"),
+ STM32_FUNCTION(0, "GPIOG15"),
+ STM32_FUNCTION(9, "USART6_CTS"),
+ STM32_FUNCTION(13, "FMC_SDNCAS"),
+ STM32_FUNCTION(14, "DCMI_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(112, "PH0"),
+ STM32_FUNCTION(0, "GPIOH0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(113, "PH1"),
+ STM32_FUNCTION(0, "GPIOH1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(114, "PH2"),
+ STM32_FUNCTION(0, "GPIOH2"),
+ STM32_FUNCTION(12, "ETH_MII_CRS"),
+ STM32_FUNCTION(13, "FMC_SDCKE0"),
+ STM32_FUNCTION(15, "LCD_R0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(115, "PH3"),
+ STM32_FUNCTION(0, "GPIOH3"),
+ STM32_FUNCTION(12, "ETH_MII_COL"),
+ STM32_FUNCTION(13, "FMC_SDNE0"),
+ STM32_FUNCTION(15, "LCD_R1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(116, "PH4"),
+ STM32_FUNCTION(0, "GPIOH4"),
+ STM32_FUNCTION(5, "I2C2_SCL"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(117, "PH5"),
+ STM32_FUNCTION(0, "GPIOH5"),
+ STM32_FUNCTION(5, "I2C2_SDA"),
+ STM32_FUNCTION(6, "SPI5_NSS"),
+ STM32_FUNCTION(13, "FMC_SDNWE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(118, "PH6"),
+ STM32_FUNCTION(0, "GPIOH6"),
+ STM32_FUNCTION(5, "I2C2_SMBA"),
+ STM32_FUNCTION(6, "SPI5_SCK"),
+ STM32_FUNCTION(10, "TIM12_CH1"),
+ STM32_FUNCTION(12, "ETH_MII_RXD2"),
+ STM32_FUNCTION(13, "FMC_SDNE1"),
+ STM32_FUNCTION(14, "DCMI_D8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(119, "PH7"),
+ STM32_FUNCTION(0, "GPIOH7"),
+ STM32_FUNCTION(5, "I2C3_SCL"),
+ STM32_FUNCTION(6, "SPI5_MISO"),
+ STM32_FUNCTION(12, "ETH_MII_RXD3"),
+ STM32_FUNCTION(13, "FMC_SDCKE1"),
+ STM32_FUNCTION(14, "DCMI_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(120, "PH8"),
+ STM32_FUNCTION(0, "GPIOH8"),
+ STM32_FUNCTION(5, "I2C3_SDA"),
+ STM32_FUNCTION(13, "FMC_D16"),
+ STM32_FUNCTION(14, "DCMI_HSYNC"),
+ STM32_FUNCTION(15, "LCD_R2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(121, "PH9"),
+ STM32_FUNCTION(0, "GPIOH9"),
+ STM32_FUNCTION(5, "I2C3_SMBA"),
+ STM32_FUNCTION(10, "TIM12_CH2"),
+ STM32_FUNCTION(13, "FMC_D17"),
+ STM32_FUNCTION(14, "DCMI_D0"),
+ STM32_FUNCTION(15, "LCD_R3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(122, "PH10"),
+ STM32_FUNCTION(0, "GPIOH10"),
+ STM32_FUNCTION(3, "TIM5_CH1"),
+ STM32_FUNCTION(13, "FMC_D18"),
+ STM32_FUNCTION(14, "DCMI_D1"),
+ STM32_FUNCTION(15, "LCD_R4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(123, "PH11"),
+ STM32_FUNCTION(0, "GPIOH11"),
+ STM32_FUNCTION(3, "TIM5_CH2"),
+ STM32_FUNCTION(13, "FMC_D19"),
+ STM32_FUNCTION(14, "DCMI_D2"),
+ STM32_FUNCTION(15, "LCD_R5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(124, "PH12"),
+ STM32_FUNCTION(0, "GPIOH12"),
+ STM32_FUNCTION(3, "TIM5_CH3"),
+ STM32_FUNCTION(13, "FMC_D20"),
+ STM32_FUNCTION(14, "DCMI_D3"),
+ STM32_FUNCTION(15, "LCD_R6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(125, "PH13"),
+ STM32_FUNCTION(0, "GPIOH13"),
+ STM32_FUNCTION(4, "TIM8_CH1N"),
+ STM32_FUNCTION(10, "CAN1_TX"),
+ STM32_FUNCTION(13, "FMC_D21"),
+ STM32_FUNCTION(15, "LCD_G2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(126, "PH14"),
+ STM32_FUNCTION(0, "GPIOH14"),
+ STM32_FUNCTION(4, "TIM8_CH2N"),
+ STM32_FUNCTION(13, "FMC_D22"),
+ STM32_FUNCTION(14, "DCMI_D4"),
+ STM32_FUNCTION(15, "LCD_G3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(127, "PH15"),
+ STM32_FUNCTION(0, "GPIOH15"),
+ STM32_FUNCTION(4, "TIM8_CH3N"),
+ STM32_FUNCTION(13, "FMC_D23"),
+ STM32_FUNCTION(14, "DCMI_D11"),
+ STM32_FUNCTION(15, "LCD_G4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(128, "PI0"),
+ STM32_FUNCTION(0, "GPIOI0"),
+ STM32_FUNCTION(3, "TIM5_CH4"),
+ STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(13, "FMC_D24"),
+ STM32_FUNCTION(14, "DCMI_D13"),
+ STM32_FUNCTION(15, "LCD_G5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(129, "PI1"),
+ STM32_FUNCTION(0, "GPIOI1"),
+ STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(13, "FMC_D25"),
+ STM32_FUNCTION(14, "DCMI_D8"),
+ STM32_FUNCTION(15, "LCD_G6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(130, "PI2"),
+ STM32_FUNCTION(0, "GPIOI2"),
+ STM32_FUNCTION(4, "TIM8_CH4"),
+ STM32_FUNCTION(6, "SPI2_MISO"),
+ STM32_FUNCTION(7, "I2S2EXT_SD"),
+ STM32_FUNCTION(13, "FMC_D26"),
+ STM32_FUNCTION(14, "DCMI_D9"),
+ STM32_FUNCTION(15, "LCD_G7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(131, "PI3"),
+ STM32_FUNCTION(0, "GPIOI3"),
+ STM32_FUNCTION(4, "TIM8_ETR"),
+ STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
+ STM32_FUNCTION(13, "FMC_D27"),
+ STM32_FUNCTION(14, "DCMI_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(132, "PI4"),
+ STM32_FUNCTION(0, "GPIOI4"),
+ STM32_FUNCTION(4, "TIM8_BKIN"),
+ STM32_FUNCTION(13, "FMC_NBL2"),
+ STM32_FUNCTION(14, "DCMI_D5"),
+ STM32_FUNCTION(15, "LCD_B4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(133, "PI5"),
+ STM32_FUNCTION(0, "GPIOI5"),
+ STM32_FUNCTION(4, "TIM8_CH1"),
+ STM32_FUNCTION(13, "FMC_NBL3"),
+ STM32_FUNCTION(14, "DCMI_VSYNC"),
+ STM32_FUNCTION(15, "LCD_B5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(134, "PI6"),
+ STM32_FUNCTION(0, "GPIOI6"),
+ STM32_FUNCTION(4, "TIM8_CH2"),
+ STM32_FUNCTION(13, "FMC_D28"),
+ STM32_FUNCTION(14, "DCMI_D6"),
+ STM32_FUNCTION(15, "LCD_B6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(135, "PI7"),
+ STM32_FUNCTION(0, "GPIOI7"),
+ STM32_FUNCTION(4, "TIM8_CH3"),
+ STM32_FUNCTION(13, "FMC_D29"),
+ STM32_FUNCTION(14, "DCMI_D7"),
+ STM32_FUNCTION(15, "LCD_B7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(136, "PI8"),
+ STM32_FUNCTION(0, "GPIOI8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(137, "PI9"),
+ STM32_FUNCTION(0, "GPIOI9"),
+ STM32_FUNCTION(10, "CAN1_RX"),
+ STM32_FUNCTION(13, "FMC_D30"),
+ STM32_FUNCTION(15, "LCD_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(138, "PI10"),
+ STM32_FUNCTION(0, "GPIOI10"),
+ STM32_FUNCTION(12, "ETH_MII_RX_ER"),
+ STM32_FUNCTION(13, "FMC_D31"),
+ STM32_FUNCTION(15, "LCD_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(139, "PI11"),
+ STM32_FUNCTION(0, "GPIOI11"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(140, "PI12"),
+ STM32_FUNCTION(0, "GPIOI12"),
+ STM32_FUNCTION(15, "LCD_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(141, "PI13"),
+ STM32_FUNCTION(0, "GPIOI13"),
+ STM32_FUNCTION(15, "LCD_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(142, "PI14"),
+ STM32_FUNCTION(0, "GPIOI14"),
+ STM32_FUNCTION(15, "LCD_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(143, "PI15"),
+ STM32_FUNCTION(0, "GPIOI15"),
+ STM32_FUNCTION(15, "LCD_R0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(144, "PJ0"),
+ STM32_FUNCTION(0, "GPIOJ0"),
+ STM32_FUNCTION(15, "LCD_R1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(145, "PJ1"),
+ STM32_FUNCTION(0, "GPIOJ1"),
+ STM32_FUNCTION(15, "LCD_R2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(146, "PJ2"),
+ STM32_FUNCTION(0, "GPIOJ2"),
+ STM32_FUNCTION(15, "LCD_R3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(147, "PJ3"),
+ STM32_FUNCTION(0, "GPIOJ3"),
+ STM32_FUNCTION(15, "LCD_R4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(148, "PJ4"),
+ STM32_FUNCTION(0, "GPIOJ4"),
+ STM32_FUNCTION(15, "LCD_R5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(149, "PJ5"),
+ STM32_FUNCTION(0, "GPIOJ5"),
+ STM32_FUNCTION(15, "LCD_R6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(150, "PJ6"),
+ STM32_FUNCTION(0, "GPIOJ6"),
+ STM32_FUNCTION(15, "LCD_R7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(151, "PJ7"),
+ STM32_FUNCTION(0, "GPIOJ7"),
+ STM32_FUNCTION(15, "LCD_G0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(152, "PJ8"),
+ STM32_FUNCTION(0, "GPIOJ8"),
+ STM32_FUNCTION(15, "LCD_G1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(153, "PJ9"),
+ STM32_FUNCTION(0, "GPIOJ9"),
+ STM32_FUNCTION(15, "LCD_G2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(154, "PJ10"),
+ STM32_FUNCTION(0, "GPIOJ10"),
+ STM32_FUNCTION(15, "LCD_G3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(155, "PJ11"),
+ STM32_FUNCTION(0, "GPIOJ11"),
+ STM32_FUNCTION(15, "LCD_G4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(156, "PJ12"),
+ STM32_FUNCTION(0, "GPIOJ12"),
+ STM32_FUNCTION(15, "LCD_B0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(157, "PJ13"),
+ STM32_FUNCTION(0, "GPIOJ13"),
+ STM32_FUNCTION(15, "LCD_B1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(158, "PJ14"),
+ STM32_FUNCTION(0, "GPIOJ14"),
+ STM32_FUNCTION(15, "LCD_B2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(159, "PJ15"),
+ STM32_FUNCTION(0, "GPIOJ15"),
+ STM32_FUNCTION(15, "LCD_B3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(160, "PK0"),
+ STM32_FUNCTION(0, "GPIOK0"),
+ STM32_FUNCTION(15, "LCD_G5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(161, "PK1"),
+ STM32_FUNCTION(0, "GPIOK1"),
+ STM32_FUNCTION(15, "LCD_G6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(162, "PK2"),
+ STM32_FUNCTION(0, "GPIOK2"),
+ STM32_FUNCTION(15, "LCD_G7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(163, "PK3"),
+ STM32_FUNCTION(0, "GPIOK3"),
+ STM32_FUNCTION(15, "LCD_B4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(164, "PK4"),
+ STM32_FUNCTION(0, "GPIOK4"),
+ STM32_FUNCTION(15, "LCD_B5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(165, "PK5"),
+ STM32_FUNCTION(0, "GPIOK5"),
+ STM32_FUNCTION(15, "LCD_B6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(166, "PK6"),
+ STM32_FUNCTION(0, "GPIOK6"),
+ STM32_FUNCTION(15, "LCD_B7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(167, "PK7"),
+ STM32_FUNCTION(0, "GPIOK7"),
+ STM32_FUNCTION(15, "LCD_DE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+};
+
+static struct stm32_pinctrl_match_data stm32f429_match_data = {
+ .pins = stm32f429_pins,
+ .npins = ARRAY_SIZE(stm32f429_pins),
+};
+
+static const struct of_device_id stm32f429_pctrl_match[] = {
+ {
+ .compatible = "st,stm32f429-pinctrl",
+ .data = &stm32f429_match_data,
+ },
+ { }
+};
+
+static struct platform_driver stm32f429_pinctrl_driver = {
+ .probe = stm32_pctl_probe,
+ .driver = {
+ .name = "stm32f429-pinctrl",
+ .of_match_table = stm32f429_pctrl_match,
+ },
+};
+
+static int __init stm32f429_pinctrl_init(void)
+{
+ return platform_driver_register(&stm32f429_pinctrl_driver);
+}
+device_initcall(stm32f429_pinctrl_init);
if ARCH_SUNXI
-config PINCTRL_SUNXI_COMMON
+config PINCTRL_SUNXI
bool
select PINMUX
select GENERIC_PINCONF
config PINCTRL_SUN4I_A10
def_bool MACH_SUN4I
- select PINCTRL_SUNXI_COMMON
+ select PINCTRL_SUNXI
config PINCTRL_SUN5I_A10S
def_bool MACH_SUN5I
- select PINCTRL_SUNXI_COMMON
+ select PINCTRL_SUNXI
config PINCTRL_SUN5I_A13
def_bool MACH_SUN5I
- select PINCTRL_SUNXI_COMMON
+ select PINCTRL_SUNXI
config PINCTRL_SUN6I_A31
def_bool MACH_SUN6I
- select PINCTRL_SUNXI_COMMON
+ select PINCTRL_SUNXI
config PINCTRL_SUN6I_A31S
def_bool MACH_SUN6I
- select PINCTRL_SUNXI_COMMON
+ select PINCTRL_SUNXI
config PINCTRL_SUN6I_A31_R
def_bool MACH_SUN6I
depends on RESET_CONTROLLER
- select PINCTRL_SUNXI_COMMON
+ select PINCTRL_SUNXI
config PINCTRL_SUN7I_A20
def_bool MACH_SUN7I
- select PINCTRL_SUNXI_COMMON
+ select PINCTRL_SUNXI
config PINCTRL_SUN8I_A23
def_bool MACH_SUN8I
- select PINCTRL_SUNXI_COMMON
+ select PINCTRL_SUNXI
config PINCTRL_SUN8I_A33
def_bool MACH_SUN8I
- select PINCTRL_SUNXI_COMMON
+ select PINCTRL_SUNXI
config PINCTRL_SUN8I_A83T
def_bool MACH_SUN8I
- select PINCTRL_SUNXI_COMMON
+ select PINCTRL_SUNXI
config PINCTRL_SUN8I_A23_R
def_bool MACH_SUN8I
depends on RESET_CONTROLLER
- select PINCTRL_SUNXI_COMMON
+ select PINCTRL_SUNXI
config PINCTRL_SUN8I_H3
+ def_bool MACH_SUN8I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_H3_R
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
config PINCTRL_SUN9I_A80
def_bool MACH_SUN9I
- select PINCTRL_SUNXI_COMMON
+ select PINCTRL_SUNXI
config PINCTRL_SUN9I_A80_R
def_bool MACH_SUN9I
depends on RESET_CONTROLLER
- select PINCTRL_SUNXI_COMMON
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A64
+ bool
+ select PINCTRL_SUNXI
endif
# Core
-obj-$(CONFIG_PINCTRL_SUNXI_COMMON) += pinctrl-sunxi.o
+obj-y += pinctrl-sunxi.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
+obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o
obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
+obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
--- /dev/null
+/*
+ * Allwinner A64 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2016 - ARM Ltd.
+ * Author: Andre Przywara <andre.przywara@arm.com>
+ *
+ * Based on pinctrl-sun7i-a20.c, which is:
+ * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin a64_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* TX */
+ SUNXI_FUNCTION(0x4, "jtag"), /* MS0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RX */
+ SUNXI_FUNCTION(0x4, "jtag"), /* CK0 */
+ SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
+ SUNXI_FUNCTION(0x4, "jtag"), /* DO0 */
+ SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "jtag"), /* DI0 */
+ SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif2"), /* SYNC */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* SYNC */
+ SUNXI_FUNCTION(0x5, "sim"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif2"), /* BCLK */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */
+ SUNXI_FUNCTION(0x5, "sim"), /* DATA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif2"), /* DOUT */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */
+ SUNXI_FUNCTION(0x5, "sim"), /* RST */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif2"), /* DIN */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */
+ SUNXI_FUNCTION(0x5, "sim"), /* DET */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "uart0"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* EINT9 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
+ SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* DS */
+ SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
+ SUNXI_FUNCTION(0x4, "spi0")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
+ SUNXI_FUNCTION(0x4, "spi0")), /* CS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NRE# */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NRB1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "uart3"), /* TX */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CS */
+ SUNXI_FUNCTION(0x5, "ccir")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart3"), /* RX */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x5, "ccir")), /* DE */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
+ SUNXI_FUNCTION(0x3, "uart4"), /* TX */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x5, "ccir")), /* HSYNC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
+ SUNXI_FUNCTION(0x3, "uart4"), /* RX */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x5, "ccir")), /* VSYNC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
+ SUNXI_FUNCTION(0x3, "uart4"), /* RTS */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
+ SUNXI_FUNCTION(0x3, "uart4"), /* CTS */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
+ SUNXI_FUNCTION(0x4, "emac"), /* ERXD3 */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
+ SUNXI_FUNCTION(0x4, "emac"), /* ERXD2 */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ERXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ERXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ERXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ERXCTL */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ENULL */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */
+ SUNXI_FUNCTION(0x4, "emac"), /* ETXD3 */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */
+ SUNXI_FUNCTION(0x4, "emac"), /* ETXD2 */
+ SUNXI_FUNCTION(0x5, "ccir")), /* D7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ETXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */
+ SUNXI_FUNCTION(0x4, "emac")), /* ETXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */
+ SUNXI_FUNCTION(0x4, "emac")), /* ETXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ETXCTL */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */
+ SUNXI_FUNCTION(0x4, "emac")), /* ECLKIN */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
+ SUNXI_FUNCTION(0x4, "emac")), /* EMDC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "emac")), /* EMDIO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* PCK */
+ SUNXI_FUNCTION(0x4, "ts0")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* CK */
+ SUNXI_FUNCTION(0x4, "ts0")), /* ERR */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* HSYNC */
+ SUNXI_FUNCTION(0x4, "ts0")), /* SYNC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* VSYNC */
+ SUNXI_FUNCTION(0x4, "ts0")), /* DVLD */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* D0 */
+ SUNXI_FUNCTION(0x4, "ts0")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* D1 */
+ SUNXI_FUNCTION(0x4, "ts0")), /* D1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* D2 */
+ SUNXI_FUNCTION(0x4, "ts0")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* D3 */
+ SUNXI_FUNCTION(0x4, "ts0")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* D4 */
+ SUNXI_FUNCTION(0x4, "ts0")), /* D4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* D5 */
+ SUNXI_FUNCTION(0x4, "ts0")), /* D5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* D6 */
+ SUNXI_FUNCTION(0x4, "ts0")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* D7 */
+ SUNXI_FUNCTION(0x4, "ts0")), /* D7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pll"), /* LOCK_DBG */
+ SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "jtag")), /* MSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart0")), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
+ SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
+ SUNXI_FUNCTION(0x4, "uart0")), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif3"), /* SYNC */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* SYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif3"), /* BCLK */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif3"), /* DOUT */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "aif3"), /* DIN */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* EINT13 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart3"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart3"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mic"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mic"), /* DATA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* EINT11 */
+};
+
+static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
+ .pins = a64_pins,
+ .npins = ARRAY_SIZE(a64_pins),
+ .irq_banks = 3,
+};
+
+static int a64_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &a64_pinctrl_data);
+}
+
+static const struct of_device_id a64_pinctrl_match[] = {
+ { .compatible = "allwinner,sun50i-a64-pinctrl", },
+ {}
+};
+
+static struct platform_driver a64_pinctrl_driver = {
+ .probe = a64_pinctrl_probe,
+ .driver = {
+ .name = "sun50i-a64-pinctrl",
+ .of_match_table = a64_pinctrl_match,
+ },
+};
+builtin_platform_driver(a64_pinctrl_driver);
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
- SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
- SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
- SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
- SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
- SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
- SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
+ SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
+ SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
- SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
+ SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
- SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
+ SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
- SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
+ SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
- SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
+ SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
- SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
+ SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
- SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
+ SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
+ SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
+ SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
--- /dev/null
+/*
+ * Allwinner H3 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2016 Krzysztof Adamski <k@japko.eu>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_h3_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_pwm"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_cir_rx"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
+};
+
+static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = {
+ .pins = sun8i_h3_r_pins,
+ .npins = ARRAY_SIZE(sun8i_h3_r_pins),
+ .irq_banks = 1,
+ .pin_base = PL_BASE,
+ .irq_read_needs_mux = true
+};
+
+static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &sun8i_h3_r_pinctrl_data);
+}
+
+static const struct of_device_id sun8i_h3_r_pinctrl_match[] = {
+ { .compatible = "allwinner,sun8i-h3-r-pinctrl", },
+ {}
+};
+
+static struct platform_driver sun8i_h3_r_pinctrl_driver = {
+ .probe = sun8i_h3_r_pinctrl_probe,
+ .driver = {
+ .name = "sun8i-h3-r-pinctrl",
+ .of_match_table = sun8i_h3_r_pinctrl_match,
+ },
+};
+builtin_platform_driver(sun8i_h3_r_pinctrl_driver);
* warranty of any kind, whether express or implied.
*/
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
{ .compatible = "allwinner,sun9i-a80-r-pinctrl", },
{}
};
-MODULE_DEVICE_TABLE(of, sun9i_a80_r_pinctrl_match);
static struct platform_driver sun9i_a80_r_pinctrl_driver = {
.probe = sun9i_a80_r_pinctrl_probe,
.of_match_table = sun9i_a80_r_pinctrl_match,
},
};
-module_platform_driver(sun9i_a80_r_pinctrl_driver);
-
-MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
-MODULE_DESCRIPTION("Allwinner A80 R_PIO pinctrl driver");
-MODULE_LICENSE("GPL");
+builtin_platform_driver(sun9i_a80_r_pinctrl_driver);
#include <linux/gpio/driver.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
-#include <linux/module.h>
+#include <linux/export.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
u8 index = sunxi_data_offset(offset);
u32 set_mux = pctl->desc->irq_read_needs_mux &&
test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags);
+ u32 pin = offset + chip->base;
u32 val;
if (set_mux)
- sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT);
+ sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
if (set_mux)
- sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ);
+ sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
return !!val;
}
--- /dev/null
+config PINCTRL_TEGRA
+ bool
+ select PINMUX
+ select PINCONF
+
+config PINCTRL_TEGRA20
+ bool
+ select PINCTRL_TEGRA
+
+config PINCTRL_TEGRA30
+ bool
+ select PINCTRL_TEGRA
+
+config PINCTRL_TEGRA114
+ bool
+ select PINCTRL_TEGRA
+
+config PINCTRL_TEGRA124
+ bool
+ select PINCTRL_TEGRA
+
+config PINCTRL_TEGRA210
+ bool
+ select PINCTRL_TEGRA
+
+config PINCTRL_TEGRA_XUSB
+ def_bool y if ARCH_TEGRA
+ select GENERIC_PHY
+ select PINCONF
+ select PINMUX
--- /dev/null
+obj-y += pinctrl-tegra.o
+obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
+obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
+obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
+obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o
+obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o
+obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o
--- /dev/null
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
+#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
+#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
+#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
+
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
+
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
+
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
+
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
+
+struct tegra_xusb_padctl_function {
+ const char *name;
+ const char * const *groups;
+ unsigned int num_groups;
+};
+
+struct tegra_xusb_padctl_soc {
+ const struct pinctrl_pin_desc *pins;
+ unsigned int num_pins;
+
+ const struct tegra_xusb_padctl_function *functions;
+ unsigned int num_functions;
+
+ const struct tegra_xusb_padctl_lane *lanes;
+ unsigned int num_lanes;
+};
+
+struct tegra_xusb_padctl_lane {
+ const char *name;
+
+ unsigned int offset;
+ unsigned int shift;
+ unsigned int mask;
+ unsigned int iddq;
+
+ const unsigned int *funcs;
+ unsigned int num_funcs;
+};
+
+struct tegra_xusb_padctl {
+ struct device *dev;
+ void __iomem *regs;
+ struct mutex lock;
+ struct reset_control *rst;
+
+ const struct tegra_xusb_padctl_soc *soc;
+ struct pinctrl_dev *pinctrl;
+ struct pinctrl_desc desc;
+
+ struct phy_provider *provider;
+ struct phy *phys[2];
+
+ unsigned int enable;
+};
+
+static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
+ unsigned long offset)
+{
+ writel(value, padctl->regs + offset);
+}
+
+static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
+ unsigned long offset)
+{
+ return readl(padctl->regs + offset);
+}
+
+static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl)
+{
+ struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
+
+ return padctl->soc->num_pins;
+}
+
+static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
+ unsigned int group)
+{
+ struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
+
+ return padctl->soc->pins[group].name;
+}
+
+static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl,
+ unsigned group,
+ const unsigned **pins,
+ unsigned *num_pins)
+{
+ /*
+ * For the tegra-xusb pad controller groups are synonomous
+ * with lanes/pins and there is always one lane/pin per group.
+ */
+ *pins = &pinctrl->desc->pins[group].number;
+ *num_pins = 1;
+
+ return 0;
+}
+
+enum tegra_xusb_padctl_param {
+ TEGRA_XUSB_PADCTL_IDDQ,
+};
+
+static const struct tegra_xusb_padctl_property {
+ const char *name;
+ enum tegra_xusb_padctl_param param;
+} properties[] = {
+ { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ },
+};
+
+#define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value))
+#define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16)
+#define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
+
+static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
+ struct device_node *np,
+ struct pinctrl_map **maps,
+ unsigned int *reserved_maps,
+ unsigned int *num_maps)
+{
+ unsigned int i, reserve = 0, num_configs = 0;
+ unsigned long config, *configs = NULL;
+ const char *function, *group;
+ struct property *prop;
+ int err = 0;
+ u32 value;
+
+ err = of_property_read_string(np, "nvidia,function", &function);
+ if (err < 0) {
+ if (err != -EINVAL)
+ return err;
+
+ function = NULL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(properties); i++) {
+ err = of_property_read_u32(np, properties[i].name, &value);
+ if (err < 0) {
+ if (err == -EINVAL)
+ continue;
+
+ goto out;
+ }
+
+ config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value);
+
+ err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
+ &num_configs, config);
+ if (err < 0)
+ goto out;
+ }
+
+ if (function)
+ reserve++;
+
+ if (num_configs)
+ reserve++;
+
+ err = of_property_count_strings(np, "nvidia,lanes");
+ if (err < 0)
+ goto out;
+
+ reserve *= err;
+
+ err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
+ num_maps, reserve);
+ if (err < 0)
+ goto out;
+
+ of_property_for_each_string(np, "nvidia,lanes", prop, group) {
+ if (function) {
+ err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
+ reserved_maps, num_maps, group,
+ function);
+ if (err < 0)
+ goto out;
+ }
+
+ if (num_configs) {
+ err = pinctrl_utils_add_map_configs(padctl->pinctrl,
+ maps, reserved_maps, num_maps, group,
+ configs, num_configs,
+ PIN_MAP_TYPE_CONFIGS_GROUP);
+ if (err < 0)
+ goto out;
+ }
+ }
+
+ err = 0;
+
+out:
+ kfree(configs);
+ return err;
+}
+
+static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
+ struct device_node *parent,
+ struct pinctrl_map **maps,
+ unsigned int *num_maps)
+{
+ struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
+ unsigned int reserved_maps = 0;
+ struct device_node *np;
+ int err;
+
+ *num_maps = 0;
+ *maps = NULL;
+
+ for_each_child_of_node(parent, np) {
+ err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
+ &reserved_maps,
+ num_maps);
+ if (err < 0) {
+ of_node_put(np);
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
+ .get_groups_count = tegra_xusb_padctl_get_groups_count,
+ .get_group_name = tegra_xusb_padctl_get_group_name,
+ .get_group_pins = tegra_xusb_padctl_get_group_pins,
+ .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
+ .dt_free_map = pinctrl_utils_dt_free_map,
+};
+
+static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl)
+{
+ struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
+
+ return padctl->soc->num_functions;
+}
+
+static const char *
+tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl,
+ unsigned int function)
+{
+ struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
+
+ return padctl->soc->functions[function].name;
+}
+
+static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
+ unsigned int function,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
+
+ *num_groups = padctl->soc->functions[function].num_groups;
+ *groups = padctl->soc->functions[function].groups;
+
+ return 0;
+}
+
+static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
+ unsigned int function,
+ unsigned int group)
+{
+ struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
+ const struct tegra_xusb_padctl_lane *lane;
+ unsigned int i;
+ u32 value;
+
+ lane = &padctl->soc->lanes[group];
+
+ for (i = 0; i < lane->num_funcs; i++)
+ if (lane->funcs[i] == function)
+ break;
+
+ if (i >= lane->num_funcs)
+ return -EINVAL;
+
+ value = padctl_readl(padctl, lane->offset);
+ value &= ~(lane->mask << lane->shift);
+ value |= i << lane->shift;
+ padctl_writel(padctl, value, lane->offset);
+
+ return 0;
+}
+
+static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
+ .get_functions_count = tegra_xusb_padctl_get_functions_count,
+ .get_function_name = tegra_xusb_padctl_get_function_name,
+ .get_function_groups = tegra_xusb_padctl_get_function_groups,
+ .set_mux = tegra_xusb_padctl_pinmux_set,
+};
+
+static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
+ unsigned int group,
+ unsigned long *config)
+{
+ struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
+ const struct tegra_xusb_padctl_lane *lane;
+ enum tegra_xusb_padctl_param param;
+ u32 value;
+
+ param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config);
+ lane = &padctl->soc->lanes[group];
+
+ switch (param) {
+ case TEGRA_XUSB_PADCTL_IDDQ:
+ /* lanes with iddq == 0 don't support this parameter */
+ if (lane->iddq == 0)
+ return -EINVAL;
+
+ value = padctl_readl(padctl, lane->offset);
+
+ if (value & BIT(lane->iddq))
+ value = 0;
+ else
+ value = 1;
+
+ *config = TEGRA_XUSB_PADCTL_PACK(param, value);
+ break;
+
+ default:
+ dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
+ param);
+ return -ENOTSUPP;
+ }
+
+ return 0;
+}
+
+static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
+ unsigned int group,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
+ const struct tegra_xusb_padctl_lane *lane;
+ enum tegra_xusb_padctl_param param;
+ unsigned long value;
+ unsigned int i;
+ u32 regval;
+
+ lane = &padctl->soc->lanes[group];
+
+ for (i = 0; i < num_configs; i++) {
+ param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]);
+ value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]);
+
+ switch (param) {
+ case TEGRA_XUSB_PADCTL_IDDQ:
+ /* lanes with iddq == 0 don't support this parameter */
+ if (lane->iddq == 0)
+ return -EINVAL;
+
+ regval = padctl_readl(padctl, lane->offset);
+
+ if (value)
+ regval &= ~BIT(lane->iddq);
+ else
+ regval |= BIT(lane->iddq);
+
+ padctl_writel(padctl, regval, lane->offset);
+ break;
+
+ default:
+ dev_err(padctl->dev,
+ "invalid configuration parameter: %04x\n",
+ param);
+ return -ENOTSUPP;
+ }
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static const char *strip_prefix(const char *s)
+{
+ const char *comma = strchr(s, ',');
+ if (!comma)
+ return s;
+
+ return comma + 1;
+}
+
+static void
+tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl,
+ struct seq_file *s,
+ unsigned int group)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(properties); i++) {
+ unsigned long config, value;
+ int err;
+
+ config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0);
+
+ err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group,
+ &config);
+ if (err < 0)
+ continue;
+
+ value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
+
+ seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name),
+ value);
+ }
+}
+
+static void
+tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl,
+ struct seq_file *s,
+ unsigned long config)
+{
+ enum tegra_xusb_padctl_param param;
+ const char *name = "unknown";
+ unsigned long value;
+ unsigned int i;
+
+ param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config);
+ value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
+
+ for (i = 0; i < ARRAY_SIZE(properties); i++) {
+ if (properties[i].param == param) {
+ name = properties[i].name;
+ break;
+ }
+ }
+
+ seq_printf(s, "%s=%lu", strip_prefix(name), value);
+}
+#endif
+
+static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = {
+ .pin_config_group_get = tegra_xusb_padctl_pinconf_group_get,
+ .pin_config_group_set = tegra_xusb_padctl_pinconf_group_set,
+#ifdef CONFIG_DEBUG_FS
+ .pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show,
+ .pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show,
+#endif
+};
+
+static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
+{
+ u32 value;
+
+ mutex_lock(&padctl->lock);
+
+ if (padctl->enable++ > 0)
+ goto out;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ usleep_range(100, 200);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ usleep_range(100, 200);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+out:
+ mutex_unlock(&padctl->lock);
+ return 0;
+}
+
+static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
+{
+ u32 value;
+
+ mutex_lock(&padctl->lock);
+
+ if (WARN_ON(padctl->enable == 0))
+ goto out;
+
+ if (--padctl->enable > 0)
+ goto out;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ usleep_range(100, 200);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+ usleep_range(100, 200);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
+ value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
+ padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
+
+out:
+ mutex_unlock(&padctl->lock);
+ return 0;
+}
+
+static int tegra_xusb_phy_init(struct phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
+
+ return tegra_xusb_padctl_enable(padctl);
+}
+
+static int tegra_xusb_phy_exit(struct phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
+
+ return tegra_xusb_padctl_disable(padctl);
+}
+
+static int pcie_phy_power_on(struct phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
+ unsigned long timeout;
+ int err = -ETIMEDOUT;
+ u32 value;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+ value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
+ value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
+ XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
+ XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+ value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+
+ timeout = jiffies + msecs_to_jiffies(50);
+
+ while (time_before(jiffies, timeout)) {
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+ if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
+ err = 0;
+ break;
+ }
+
+ usleep_range(100, 200);
+ }
+
+ return err;
+}
+
+static int pcie_phy_power_off(struct phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
+ u32 value;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+ value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
+
+ return 0;
+}
+
+static const struct phy_ops pcie_phy_ops = {
+ .init = tegra_xusb_phy_init,
+ .exit = tegra_xusb_phy_exit,
+ .power_on = pcie_phy_power_on,
+ .power_off = pcie_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int sata_phy_power_on(struct phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
+ unsigned long timeout;
+ int err = -ETIMEDOUT;
+ u32 value;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
+ value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
+ value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
+ value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+ timeout = jiffies + msecs_to_jiffies(50);
+
+ while (time_before(jiffies, timeout)) {
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
+ err = 0;
+ break;
+ }
+
+ usleep_range(100, 200);
+ }
+
+ return err;
+}
+
+static int sata_phy_power_off(struct phy *phy)
+{
+ struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
+ u32 value;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+ value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
+ value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
+ value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
+ value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
+ padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
+
+ return 0;
+}
+
+static const struct phy_ops sata_phy_ops = {
+ .init = tegra_xusb_phy_init,
+ .exit = tegra_xusb_phy_exit,
+ .power_on = sata_phy_power_on,
+ .power_off = sata_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static struct phy *tegra_xusb_padctl_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
+ unsigned int index = args->args[0];
+
+ if (args->args_count <= 0)
+ return ERR_PTR(-EINVAL);
+
+ if (index >= ARRAY_SIZE(padctl->phys))
+ return ERR_PTR(-EINVAL);
+
+ return padctl->phys[index];
+}
+
+#define PIN_OTG_0 0
+#define PIN_OTG_1 1
+#define PIN_OTG_2 2
+#define PIN_ULPI_0 3
+#define PIN_HSIC_0 4
+#define PIN_HSIC_1 5
+#define PIN_PCIE_0 6
+#define PIN_PCIE_1 7
+#define PIN_PCIE_2 8
+#define PIN_PCIE_3 9
+#define PIN_PCIE_4 10
+#define PIN_SATA_0 11
+
+static const struct pinctrl_pin_desc tegra124_pins[] = {
+ PINCTRL_PIN(PIN_OTG_0, "otg-0"),
+ PINCTRL_PIN(PIN_OTG_1, "otg-1"),
+ PINCTRL_PIN(PIN_OTG_2, "otg-2"),
+ PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
+ PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
+ PINCTRL_PIN(PIN_HSIC_1, "hsic-1"),
+ PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
+ PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
+ PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
+ PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
+ PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
+ PINCTRL_PIN(PIN_SATA_0, "sata-0"),
+};
+
+static const char * const tegra124_snps_groups[] = {
+ "otg-0",
+ "otg-1",
+ "otg-2",
+ "ulpi-0",
+ "hsic-0",
+ "hsic-1",
+};
+
+static const char * const tegra124_xusb_groups[] = {
+ "otg-0",
+ "otg-1",
+ "otg-2",
+ "ulpi-0",
+ "hsic-0",
+ "hsic-1",
+};
+
+static const char * const tegra124_uart_groups[] = {
+ "otg-0",
+ "otg-1",
+ "otg-2",
+};
+
+static const char * const tegra124_pcie_groups[] = {
+ "pcie-0",
+ "pcie-1",
+ "pcie-2",
+ "pcie-3",
+ "pcie-4",
+};
+
+static const char * const tegra124_usb3_groups[] = {
+ "pcie-0",
+ "pcie-1",
+ "sata-0",
+};
+
+static const char * const tegra124_sata_groups[] = {
+ "sata-0",
+};
+
+static const char * const tegra124_rsvd_groups[] = {
+ "otg-0",
+ "otg-1",
+ "otg-2",
+ "pcie-0",
+ "pcie-1",
+ "pcie-2",
+ "pcie-3",
+ "pcie-4",
+ "sata-0",
+};
+
+#define TEGRA124_FUNCTION(_name) \
+ { \
+ .name = #_name, \
+ .num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \
+ .groups = tegra124_##_name##_groups, \
+ }
+
+static struct tegra_xusb_padctl_function tegra124_functions[] = {
+ TEGRA124_FUNCTION(snps),
+ TEGRA124_FUNCTION(xusb),
+ TEGRA124_FUNCTION(uart),
+ TEGRA124_FUNCTION(pcie),
+ TEGRA124_FUNCTION(usb3),
+ TEGRA124_FUNCTION(sata),
+ TEGRA124_FUNCTION(rsvd),
+};
+
+enum tegra124_function {
+ TEGRA124_FUNC_SNPS,
+ TEGRA124_FUNC_XUSB,
+ TEGRA124_FUNC_UART,
+ TEGRA124_FUNC_PCIE,
+ TEGRA124_FUNC_USB3,
+ TEGRA124_FUNC_SATA,
+ TEGRA124_FUNC_RSVD,
+};
+
+static const unsigned int tegra124_otg_functions[] = {
+ TEGRA124_FUNC_SNPS,
+ TEGRA124_FUNC_XUSB,
+ TEGRA124_FUNC_UART,
+ TEGRA124_FUNC_RSVD,
+};
+
+static const unsigned int tegra124_usb_functions[] = {
+ TEGRA124_FUNC_SNPS,
+ TEGRA124_FUNC_XUSB,
+};
+
+static const unsigned int tegra124_pci_functions[] = {
+ TEGRA124_FUNC_PCIE,
+ TEGRA124_FUNC_USB3,
+ TEGRA124_FUNC_SATA,
+ TEGRA124_FUNC_RSVD,
+};
+
+#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
+ { \
+ .name = _name, \
+ .offset = _offset, \
+ .shift = _shift, \
+ .mask = _mask, \
+ .iddq = _iddq, \
+ .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
+ .funcs = tegra124_##_funcs##_functions, \
+ }
+
+static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
+ TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
+ TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
+ TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
+ TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
+ TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
+ TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
+ TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
+ TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
+ TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
+ TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
+ TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
+ TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
+};
+
+static const struct tegra_xusb_padctl_soc tegra124_soc = {
+ .num_pins = ARRAY_SIZE(tegra124_pins),
+ .pins = tegra124_pins,
+ .num_functions = ARRAY_SIZE(tegra124_functions),
+ .functions = tegra124_functions,
+ .num_lanes = ARRAY_SIZE(tegra124_lanes),
+ .lanes = tegra124_lanes,
+};
+
+static const struct of_device_id tegra_xusb_padctl_of_match[] = {
+ { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
+ { }
+};
+MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match);
+
+static int tegra_xusb_padctl_probe(struct platform_device *pdev)
+{
+ struct tegra_xusb_padctl *padctl;
+ const struct of_device_id *match;
+ struct resource *res;
+ struct phy *phy;
+ int err;
+
+ padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
+ if (!padctl)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, padctl);
+ mutex_init(&padctl->lock);
+ padctl->dev = &pdev->dev;
+
+ match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node);
+ padctl->soc = match->data;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ padctl->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(padctl->regs))
+ return PTR_ERR(padctl->regs);
+
+ padctl->rst = devm_reset_control_get(&pdev->dev, NULL);
+ if (IS_ERR(padctl->rst))
+ return PTR_ERR(padctl->rst);
+
+ err = reset_control_deassert(padctl->rst);
+ if (err < 0)
+ return err;
+
+ memset(&padctl->desc, 0, sizeof(padctl->desc));
+ padctl->desc.name = dev_name(padctl->dev);
+ padctl->desc.pins = tegra124_pins;
+ padctl->desc.npins = ARRAY_SIZE(tegra124_pins);
+ padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
+ padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
+ padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
+ padctl->desc.owner = THIS_MODULE;
+
+ padctl->pinctrl = pinctrl_register(&padctl->desc, &pdev->dev, padctl);
+ if (IS_ERR(padctl->pinctrl)) {
+ dev_err(&pdev->dev, "failed to register pincontrol\n");
+ err = PTR_ERR(padctl->pinctrl);
+ goto reset;
+ }
+
+ phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops);
+ if (IS_ERR(phy)) {
+ err = PTR_ERR(phy);
+ goto unregister;
+ }
+
+ padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
+ phy_set_drvdata(phy, padctl);
+
+ phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops);
+ if (IS_ERR(phy)) {
+ err = PTR_ERR(phy);
+ goto unregister;
+ }
+
+ padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
+ phy_set_drvdata(phy, padctl);
+
+ padctl->provider = devm_of_phy_provider_register(&pdev->dev,
+ tegra_xusb_padctl_xlate);
+ if (IS_ERR(padctl->provider)) {
+ err = PTR_ERR(padctl->provider);
+ dev_err(&pdev->dev, "failed to register PHYs: %d\n", err);
+ goto unregister;
+ }
+
+ return 0;
+
+unregister:
+ pinctrl_unregister(padctl->pinctrl);
+reset:
+ reset_control_assert(padctl->rst);
+ return err;
+}
+
+static int tegra_xusb_padctl_remove(struct platform_device *pdev)
+{
+ struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
+ int err;
+
+ pinctrl_unregister(padctl->pinctrl);
+
+ err = reset_control_assert(padctl->rst);
+ if (err < 0)
+ dev_err(&pdev->dev, "failed to assert reset: %d\n", err);
+
+ return err;
+}
+
+static struct platform_driver tegra_xusb_padctl_driver = {
+ .driver = {
+ .name = "tegra-xusb-padctl",
+ .of_match_table = tegra_xusb_padctl_of_match,
+ },
+ .probe = tegra_xusb_padctl_probe,
+ .remove = tegra_xusb_padctl_remove,
+};
+module_platform_driver(tegra_xusb_padctl_driver);
+
+MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
+MODULE_DESCRIPTION("Tegra 124 XUSB Pad Control driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * Driver for the NVIDIA Tegra pinmux
+ *
+ * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Derived from code:
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2010 NVIDIA Corporation
+ * Copyright (C) 2009-2011 ST-Ericsson AB
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-tegra.h"
+
+struct tegra_pmx {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+
+ const struct tegra_pinctrl_soc_data *soc;
+ const char **group_pins;
+
+ int nbanks;
+ void __iomem **regs;
+};
+
+static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
+{
+ return readl(pmx->regs[bank] + reg);
+}
+
+static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
+{
+ writel(val, pmx->regs[bank] + reg);
+}
+
+static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+ return pmx->soc->ngroups;
+}
+
+static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned group)
+{
+ struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+ return pmx->soc->groups[group].name;
+}
+
+static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned group,
+ const unsigned **pins,
+ unsigned *num_pins)
+{
+ struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = pmx->soc->groups[group].pins;
+ *num_pins = pmx->soc->groups[group].npins;
+
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s,
+ unsigned offset)
+{
+ seq_printf(s, " %s", dev_name(pctldev->dev));
+}
+#endif
+
+static const struct cfg_param {
+ const char *property;
+ enum tegra_pinconf_param param;
+} cfg_params[] = {
+ {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
+ {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
+ {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
+ {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
+ {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
+ {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
+ {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
+ {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
+ {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
+ {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
+ {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
+ {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
+ {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
+ {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
+ {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
+ {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
+};
+
+static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map,
+ unsigned *reserved_maps,
+ unsigned *num_maps)
+{
+ struct device *dev = pctldev->dev;
+ int ret, i;
+ const char *function;
+ u32 val;
+ unsigned long config;
+ unsigned long *configs = NULL;
+ unsigned num_configs = 0;
+ unsigned reserve;
+ struct property *prop;
+ const char *group;
+
+ ret = of_property_read_string(np, "nvidia,function", &function);
+ if (ret < 0) {
+ /* EINVAL=missing, which is fine since it's optional */
+ if (ret != -EINVAL)
+ dev_err(dev,
+ "could not parse property nvidia,function\n");
+ function = NULL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
+ ret = of_property_read_u32(np, cfg_params[i].property, &val);
+ if (!ret) {
+ config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
+ ret = pinctrl_utils_add_config(pctldev, &configs,
+ &num_configs, config);
+ if (ret < 0)
+ goto exit;
+ /* EINVAL=missing, which is fine since it's optional */
+ } else if (ret != -EINVAL) {
+ dev_err(dev, "could not parse property %s\n",
+ cfg_params[i].property);
+ }
+ }
+
+ reserve = 0;
+ if (function != NULL)
+ reserve++;
+ if (num_configs)
+ reserve++;
+ ret = of_property_count_strings(np, "nvidia,pins");
+ if (ret < 0) {
+ dev_err(dev, "could not parse property nvidia,pins\n");
+ goto exit;
+ }
+ reserve *= ret;
+
+ ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
+ num_maps, reserve);
+ if (ret < 0)
+ goto exit;
+
+ of_property_for_each_string(np, "nvidia,pins", prop, group) {
+ if (function) {
+ ret = pinctrl_utils_add_map_mux(pctldev, map,
+ reserved_maps, num_maps, group,
+ function);
+ if (ret < 0)
+ goto exit;
+ }
+
+ if (num_configs) {
+ ret = pinctrl_utils_add_map_configs(pctldev, map,
+ reserved_maps, num_maps, group,
+ configs, num_configs,
+ PIN_MAP_TYPE_CONFIGS_GROUP);
+ if (ret < 0)
+ goto exit;
+ }
+ }
+
+ ret = 0;
+
+exit:
+ kfree(configs);
+ return ret;
+}
+
+static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np_config,
+ struct pinctrl_map **map,
+ unsigned *num_maps)
+{
+ unsigned reserved_maps;
+ struct device_node *np;
+ int ret;
+
+ reserved_maps = 0;
+ *map = NULL;
+ *num_maps = 0;
+
+ for_each_child_of_node(np_config, np) {
+ ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
+ &reserved_maps, num_maps);
+ if (ret < 0) {
+ pinctrl_utils_dt_free_map(pctldev, *map,
+ *num_maps);
+ of_node_put(np);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static const struct pinctrl_ops tegra_pinctrl_ops = {
+ .get_groups_count = tegra_pinctrl_get_groups_count,
+ .get_group_name = tegra_pinctrl_get_group_name,
+ .get_group_pins = tegra_pinctrl_get_group_pins,
+#ifdef CONFIG_DEBUG_FS
+ .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
+#endif
+ .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
+ .dt_free_map = pinctrl_utils_dt_free_map,
+};
+
+static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+ return pmx->soc->nfunctions;
+}
+
+static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned function)
+{
+ struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+ return pmx->soc->functions[function].name;
+}
+
+static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
+ unsigned function,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = pmx->soc->functions[function].groups;
+ *num_groups = pmx->soc->functions[function].ngroups;
+
+ return 0;
+}
+
+static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
+ unsigned function,
+ unsigned group)
+{
+ struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+ const struct tegra_pingroup *g;
+ int i;
+ u32 val;
+
+ g = &pmx->soc->groups[group];
+
+ if (WARN_ON(g->mux_reg < 0))
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
+ if (g->funcs[i] == function)
+ break;
+ }
+ if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
+ return -EINVAL;
+
+ val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
+ val &= ~(0x3 << g->mux_bit);
+ val |= i << g->mux_bit;
+ pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
+
+ return 0;
+}
+
+static const struct pinmux_ops tegra_pinmux_ops = {
+ .get_functions_count = tegra_pinctrl_get_funcs_count,
+ .get_function_name = tegra_pinctrl_get_func_name,
+ .get_function_groups = tegra_pinctrl_get_func_groups,
+ .set_mux = tegra_pinctrl_set_mux,
+};
+
+static int tegra_pinconf_reg(struct tegra_pmx *pmx,
+ const struct tegra_pingroup *g,
+ enum tegra_pinconf_param param,
+ bool report_err,
+ s8 *bank, s16 *reg, s8 *bit, s8 *width)
+{
+ switch (param) {
+ case TEGRA_PINCONF_PARAM_PULL:
+ *bank = g->pupd_bank;
+ *reg = g->pupd_reg;
+ *bit = g->pupd_bit;
+ *width = 2;
+ break;
+ case TEGRA_PINCONF_PARAM_TRISTATE:
+ *bank = g->tri_bank;
+ *reg = g->tri_reg;
+ *bit = g->tri_bit;
+ *width = 1;
+ break;
+ case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
+ *bank = g->mux_bank;
+ *reg = g->mux_reg;
+ *bit = g->einput_bit;
+ *width = 1;
+ break;
+ case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
+ *bank = g->mux_bank;
+ *reg = g->mux_reg;
+ *bit = g->odrain_bit;
+ *width = 1;
+ break;
+ case TEGRA_PINCONF_PARAM_LOCK:
+ *bank = g->mux_bank;
+ *reg = g->mux_reg;
+ *bit = g->lock_bit;
+ *width = 1;
+ break;
+ case TEGRA_PINCONF_PARAM_IORESET:
+ *bank = g->mux_bank;
+ *reg = g->mux_reg;
+ *bit = g->ioreset_bit;
+ *width = 1;
+ break;
+ case TEGRA_PINCONF_PARAM_RCV_SEL:
+ *bank = g->mux_bank;
+ *reg = g->mux_reg;
+ *bit = g->rcv_sel_bit;
+ *width = 1;
+ break;
+ case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
+ if (pmx->soc->hsm_in_mux) {
+ *bank = g->mux_bank;
+ *reg = g->mux_reg;
+ } else {
+ *bank = g->drv_bank;
+ *reg = g->drv_reg;
+ }
+ *bit = g->hsm_bit;
+ *width = 1;
+ break;
+ case TEGRA_PINCONF_PARAM_SCHMITT:
+ if (pmx->soc->schmitt_in_mux) {
+ *bank = g->mux_bank;
+ *reg = g->mux_reg;
+ } else {
+ *bank = g->drv_bank;
+ *reg = g->drv_reg;
+ }
+ *bit = g->schmitt_bit;
+ *width = 1;
+ break;
+ case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
+ *bank = g->drv_bank;
+ *reg = g->drv_reg;
+ *bit = g->lpmd_bit;
+ *width = 2;
+ break;
+ case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
+ *bank = g->drv_bank;
+ *reg = g->drv_reg;
+ *bit = g->drvdn_bit;
+ *width = g->drvdn_width;
+ break;
+ case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
+ *bank = g->drv_bank;
+ *reg = g->drv_reg;
+ *bit = g->drvup_bit;
+ *width = g->drvup_width;
+ break;
+ case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
+ *bank = g->drv_bank;
+ *reg = g->drv_reg;
+ *bit = g->slwf_bit;
+ *width = g->slwf_width;
+ break;
+ case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
+ *bank = g->drv_bank;
+ *reg = g->drv_reg;
+ *bit = g->slwr_bit;
+ *width = g->slwr_width;
+ break;
+ case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
+ if (pmx->soc->drvtype_in_mux) {
+ *bank = g->mux_bank;
+ *reg = g->mux_reg;
+ } else {
+ *bank = g->drv_bank;
+ *reg = g->drv_reg;
+ }
+ *bit = g->drvtype_bit;
+ *width = 2;
+ break;
+ default:
+ dev_err(pmx->dev, "Invalid config param %04x\n", param);
+ return -ENOTSUPP;
+ }
+
+ if (*reg < 0 || *bit > 31) {
+ if (report_err) {
+ const char *prop = "unknown";
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
+ if (cfg_params[i].param == param) {
+ prop = cfg_params[i].property;
+ break;
+ }
+ }
+
+ dev_err(pmx->dev,
+ "Config param %04x (%s) not supported on group %s\n",
+ param, prop, g->name);
+ }
+ return -ENOTSUPP;
+ }
+
+ return 0;
+}
+
+static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin, unsigned long *config)
+{
+ dev_err(pctldev->dev, "pin_config_get op not supported\n");
+ return -ENOTSUPP;
+}
+
+static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin, unsigned long *configs,
+ unsigned num_configs)
+{
+ dev_err(pctldev->dev, "pin_config_set op not supported\n");
+ return -ENOTSUPP;
+}
+
+static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned group, unsigned long *config)
+{
+ struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+ enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
+ u16 arg;
+ const struct tegra_pingroup *g;
+ int ret;
+ s8 bank, bit, width;
+ s16 reg;
+ u32 val, mask;
+
+ g = &pmx->soc->groups[group];
+
+ ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
+ &width);
+ if (ret < 0)
+ return ret;
+
+ val = pmx_readl(pmx, bank, reg);
+ mask = (1 << width) - 1;
+ arg = (val >> bit) & mask;
+
+ *config = TEGRA_PINCONF_PACK(param, arg);
+
+ return 0;
+}
+
+static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
+ unsigned group, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+ enum tegra_pinconf_param param;
+ u16 arg;
+ const struct tegra_pingroup *g;
+ int ret, i;
+ s8 bank, bit, width;
+ s16 reg;
+ u32 val, mask;
+
+ g = &pmx->soc->groups[group];
+
+ for (i = 0; i < num_configs; i++) {
+ param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
+ arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
+
+ ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
+ &width);
+ if (ret < 0)
+ return ret;
+
+ val = pmx_readl(pmx, bank, reg);
+
+ /* LOCK can't be cleared */
+ if (param == TEGRA_PINCONF_PARAM_LOCK) {
+ if ((val & BIT(bit)) && !arg) {
+ dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
+ return -EINVAL;
+ }
+ }
+
+ /* Special-case Boolean values; allow any non-zero as true */
+ if (width == 1)
+ arg = !!arg;
+
+ /* Range-check user-supplied value */
+ mask = (1 << width) - 1;
+ if (arg & ~mask) {
+ dev_err(pctldev->dev,
+ "config %lx: %x too big for %d bit register\n",
+ configs[i], arg, width);
+ return -EINVAL;
+ }
+
+ /* Update register */
+ val &= ~(mask << bit);
+ val |= arg << bit;
+ pmx_writel(pmx, val, bank, reg);
+ } /* for each config */
+
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned offset)
+{
+}
+
+static const char *strip_prefix(const char *s)
+{
+ const char *comma = strchr(s, ',');
+ if (!comma)
+ return s;
+
+ return comma + 1;
+}
+
+static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned group)
+{
+ struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+ const struct tegra_pingroup *g;
+ int i, ret;
+ s8 bank, bit, width;
+ s16 reg;
+ u32 val;
+
+ g = &pmx->soc->groups[group];
+
+ for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
+ ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
+ &bank, ®, &bit, &width);
+ if (ret < 0)
+ continue;
+
+ val = pmx_readl(pmx, bank, reg);
+ val >>= bit;
+ val &= (1 << width) - 1;
+
+ seq_printf(s, "\n\t%s=%u",
+ strip_prefix(cfg_params[i].property), val);
+ }
+}
+
+static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s,
+ unsigned long config)
+{
+ enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
+ u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
+ const char *pname = "unknown";
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
+ if (cfg_params[i].param == param) {
+ pname = cfg_params[i].property;
+ break;
+ }
+ }
+
+ seq_printf(s, "%s=%d", strip_prefix(pname), arg);
+}
+#endif
+
+static const struct pinconf_ops tegra_pinconf_ops = {
+ .pin_config_get = tegra_pinconf_get,
+ .pin_config_set = tegra_pinconf_set,
+ .pin_config_group_get = tegra_pinconf_group_get,
+ .pin_config_group_set = tegra_pinconf_group_set,
+#ifdef CONFIG_DEBUG_FS
+ .pin_config_dbg_show = tegra_pinconf_dbg_show,
+ .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
+ .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
+#endif
+};
+
+static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
+ .name = "Tegra GPIOs",
+ .id = 0,
+ .base = 0,
+};
+
+static struct pinctrl_desc tegra_pinctrl_desc = {
+ .pctlops = &tegra_pinctrl_ops,
+ .pmxops = &tegra_pinmux_ops,
+ .confops = &tegra_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static bool gpio_node_has_range(void)
+{
+ struct device_node *np;
+ bool has_prop = false;
+
+ np = of_find_compatible_node(NULL, NULL, "nvidia,tegra30-gpio");
+ if (!np)
+ return has_prop;
+
+ has_prop = of_find_property(np, "gpio-ranges", NULL);
+
+ of_node_put(np);
+
+ return has_prop;
+}
+
+int tegra_pinctrl_probe(struct platform_device *pdev,
+ const struct tegra_pinctrl_soc_data *soc_data)
+{
+ struct tegra_pmx *pmx;
+ struct resource *res;
+ int i;
+ const char **group_pins;
+ int fn, gn, gfn;
+
+ pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
+ if (!pmx) {
+ dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
+ return -ENOMEM;
+ }
+ pmx->dev = &pdev->dev;
+ pmx->soc = soc_data;
+
+ /*
+ * Each mux group will appear in 4 functions' list of groups.
+ * This over-allocates slightly, since not all groups are mux groups.
+ */
+ pmx->group_pins = devm_kzalloc(&pdev->dev,
+ soc_data->ngroups * 4 * sizeof(*pmx->group_pins),
+ GFP_KERNEL);
+ if (!pmx->group_pins)
+ return -ENOMEM;
+
+ group_pins = pmx->group_pins;
+ for (fn = 0; fn < soc_data->nfunctions; fn++) {
+ struct tegra_function *func = &soc_data->functions[fn];
+
+ func->groups = group_pins;
+
+ for (gn = 0; gn < soc_data->ngroups; gn++) {
+ const struct tegra_pingroup *g = &soc_data->groups[gn];
+
+ if (g->mux_reg == -1)
+ continue;
+
+ for (gfn = 0; gfn < 4; gfn++)
+ if (g->funcs[gfn] == fn)
+ break;
+ if (gfn == 4)
+ continue;
+
+ BUG_ON(group_pins - pmx->group_pins >=
+ soc_data->ngroups * 4);
+ *group_pins++ = g->name;
+ func->ngroups++;
+ }
+ }
+
+ tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
+ tegra_pinctrl_desc.name = dev_name(&pdev->dev);
+ tegra_pinctrl_desc.pins = pmx->soc->pins;
+ tegra_pinctrl_desc.npins = pmx->soc->npins;
+
+ for (i = 0; ; i++) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+ if (!res)
+ break;
+ }
+ pmx->nbanks = i;
+
+ pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
+ GFP_KERNEL);
+ if (!pmx->regs) {
+ dev_err(&pdev->dev, "Can't alloc regs pointer\n");
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < pmx->nbanks; i++) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+ pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pmx->regs[i]))
+ return PTR_ERR(pmx->regs[i]);
+ }
+
+ pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
+ if (IS_ERR(pmx->pctl)) {
+ dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
+ return PTR_ERR(pmx->pctl);
+ }
+
+ if (!gpio_node_has_range())
+ pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
+
+ platform_set_drvdata(pdev, pmx);
+
+ dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
+
+int tegra_pinctrl_remove(struct platform_device *pdev)
+{
+ struct tegra_pmx *pmx = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(pmx->pctl);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
--- /dev/null
+/*
+ * Driver for the NVIDIA Tegra pinmux
+ *
+ * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __PINMUX_TEGRA_H__
+#define __PINMUX_TEGRA_H__
+
+enum tegra_pinconf_param {
+ /* argument: tegra_pinconf_pull */
+ TEGRA_PINCONF_PARAM_PULL,
+ /* argument: tegra_pinconf_tristate */
+ TEGRA_PINCONF_PARAM_TRISTATE,
+ /* argument: Boolean */
+ TEGRA_PINCONF_PARAM_ENABLE_INPUT,
+ /* argument: Boolean */
+ TEGRA_PINCONF_PARAM_OPEN_DRAIN,
+ /* argument: Boolean */
+ TEGRA_PINCONF_PARAM_LOCK,
+ /* argument: Boolean */
+ TEGRA_PINCONF_PARAM_IORESET,
+ /* argument: Boolean */
+ TEGRA_PINCONF_PARAM_RCV_SEL,
+ /* argument: Boolean */
+ TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
+ /* argument: Boolean */
+ TEGRA_PINCONF_PARAM_SCHMITT,
+ /* argument: Boolean */
+ TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
+ /* argument: Integer, range is HW-dependant */
+ TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
+ /* argument: Integer, range is HW-dependant */
+ TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
+ /* argument: Integer, range is HW-dependant */
+ TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
+ /* argument: Integer, range is HW-dependant */
+ TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
+ /* argument: Integer, range is HW-dependant */
+ TEGRA_PINCONF_PARAM_DRIVE_TYPE,
+};
+
+enum tegra_pinconf_pull {
+ TEGRA_PINCONFIG_PULL_NONE,
+ TEGRA_PINCONFIG_PULL_DOWN,
+ TEGRA_PINCONFIG_PULL_UP,
+};
+
+enum tegra_pinconf_tristate {
+ TEGRA_PINCONFIG_DRIVEN,
+ TEGRA_PINCONFIG_TRISTATE,
+};
+
+#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
+#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
+#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
+
+/**
+ * struct tegra_function - Tegra pinctrl mux function
+ * @name: The name of the function, exported to pinctrl core.
+ * @groups: An array of pin groups that may select this function.
+ * @ngroups: The number of entries in @groups.
+ */
+struct tegra_function {
+ const char *name;
+ const char **groups;
+ unsigned ngroups;
+};
+
+/**
+ * struct tegra_pingroup - Tegra pin group
+ * @name The name of the pin group.
+ * @pins An array of pin IDs included in this pin group.
+ * @npins The number of entries in @pins.
+ * @funcs The mux functions which can be muxed onto this group.
+ * @mux_reg: Mux register offset.
+ * This register contains the mux, einput, odrain, lock,
+ * ioreset, rcv_sel parameters.
+ * @mux_bank: Mux register bank.
+ * @mux_bit: Mux register bit.
+ * @pupd_reg: Pull-up/down register offset.
+ * @pupd_bank: Pull-up/down register bank.
+ * @pupd_bit: Pull-up/down register bit.
+ * @tri_reg: Tri-state register offset.
+ * @tri_bank: Tri-state register bank.
+ * @tri_bit: Tri-state register bit.
+ * @einput_bit: Enable-input register bit.
+ * @odrain_bit: Open-drain register bit.
+ * @lock_bit: Lock register bit.
+ * @ioreset_bit: IO reset register bit.
+ * @rcv_sel_bit: Receiver select bit.
+ * @drv_reg: Drive fields register offset.
+ * This register contains hsm, schmitt, lpmd, drvdn,
+ * drvup, slwr, slwf, and drvtype parameters.
+ * @drv_bank: Drive fields register bank.
+ * @hsm_bit: High Speed Mode register bit.
+ * @schmitt_bit: Scmitt register bit.
+ * @lpmd_bit: Low Power Mode register bit.
+ * @drvdn_bit: Drive Down register bit.
+ * @drvdn_width: Drive Down field width.
+ * @drvup_bit: Drive Up register bit.
+ * @drvup_width: Drive Up field width.
+ * @slwr_bit: Slew Rising register bit.
+ * @slwr_width: Slew Rising field width.
+ * @slwf_bit: Slew Falling register bit.
+ * @slwf_width: Slew Falling field width.
+ * @drvtype_bit: Drive type register bit.
+ *
+ * -1 in a *_reg field means that feature is unsupported for this group.
+ * *_bank and *_reg values are irrelevant when *_reg is -1.
+ * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
+ *
+ * A representation of a group of pins (possibly just one pin) in the Tegra
+ * pin controller. Each group allows some parameter or parameters to be
+ * configured. The most common is mux function selection. Many others exist
+ * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
+ * certain groups may only support configuring certain parameters, hence
+ * each parameter is optional.
+ */
+struct tegra_pingroup {
+ const char *name;
+ const unsigned *pins;
+ u8 npins;
+ u8 funcs[4];
+ s16 mux_reg;
+ s16 pupd_reg;
+ s16 tri_reg;
+ s16 drv_reg;
+ u32 mux_bank:2;
+ u32 pupd_bank:2;
+ u32 tri_bank:2;
+ u32 drv_bank:2;
+ s32 mux_bit:6;
+ s32 pupd_bit:6;
+ s32 tri_bit:6;
+ s32 einput_bit:6;
+ s32 odrain_bit:6;
+ s32 lock_bit:6;
+ s32 ioreset_bit:6;
+ s32 rcv_sel_bit:6;
+ s32 hsm_bit:6;
+ s32 schmitt_bit:6;
+ s32 lpmd_bit:6;
+ s32 drvdn_bit:6;
+ s32 drvup_bit:6;
+ s32 slwr_bit:6;
+ s32 slwf_bit:6;
+ s32 drvtype_bit:6;
+ s32 drvdn_width:6;
+ s32 drvup_width:6;
+ s32 slwr_width:6;
+ s32 slwf_width:6;
+};
+
+/**
+ * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
+ * @ngpios: The number of GPIO pins the pin controller HW affects.
+ * @pins: An array describing all pins the pin controller affects.
+ * All pins which are also GPIOs must be listed first within the
+ * array, and be numbered identically to the GPIO controller's
+ * numbering.
+ * @npins: The numbmer of entries in @pins.
+ * @functions: An array describing all mux functions the SoC supports.
+ * @nfunctions: The numbmer of entries in @functions.
+ * @groups: An array describing all pin groups the pin SoC supports.
+ * @ngroups: The numbmer of entries in @groups.
+ */
+struct tegra_pinctrl_soc_data {
+ unsigned ngpios;
+ const struct pinctrl_pin_desc *pins;
+ unsigned npins;
+ struct tegra_function *functions;
+ unsigned nfunctions;
+ const struct tegra_pingroup *groups;
+ unsigned ngroups;
+ bool hsm_in_mux;
+ bool schmitt_in_mux;
+ bool drvtype_in_mux;
+};
+
+int tegra_pinctrl_probe(struct platform_device *pdev,
+ const struct tegra_pinctrl_soc_data *soc_data);
+int tegra_pinctrl_remove(struct platform_device *pdev);
+
+#endif
--- /dev/null
+/*
+ * Pinctrl data for the NVIDIA Tegra114 pinmux
+ *
+ * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "pinctrl-tegra.h"
+
+/*
+ * Most pins affected by the pinmux can also be GPIOs. Define these first.
+ * These must match how the GPIO driver names/numbers its pins.
+ */
+#define _GPIO(offset) (offset)
+
+#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
+#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
+#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
+#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
+#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
+#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
+#define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
+#define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
+#define TEGRA_PIN_GMI_A17_PB0 _GPIO(8)
+#define TEGRA_PIN_GMI_A18_PB1 _GPIO(9)
+#define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
+#define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
+#define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
+#define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
+#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
+#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
+#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
+#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
+#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
+#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
+#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
+#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
+#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
+#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
+#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
+#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
+#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
+#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
+#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
+#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
+#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
+#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
+#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
+#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
+#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
+#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
+#define TEGRA_PIN_GMI_WR_N_PI0 _GPIO(64)
+#define TEGRA_PIN_GMI_OE_N_PI1 _GPIO(65)
+#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
+#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
+#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
+#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
+#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
+#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
+#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
+#define TEGRA_PIN_GMI_DQS_P_PJ3 _GPIO(75)
+#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
+#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
+#define TEGRA_PIN_GMI_A16_PJ7 _GPIO(79)
+#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
+#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
+#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
+#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
+#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
+#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
+#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
+#define TEGRA_PIN_GMI_A19_PK7 _GPIO(87)
+#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
+#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
+#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
+#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
+#define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108)
+#define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109)
+#define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
+#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
+#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
+#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
+#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
+#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
+#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
+#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
+#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
+#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
+#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
+#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
+#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
+#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
+#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
+#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
+#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
+#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
+#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
+#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
+#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
+#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
+#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
+#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
+#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
+#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
+#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
+#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
+#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
+#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
+#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
+#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
+#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
+#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
+#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
+#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
+#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
+#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
+#define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
+#define TEGRA_PIN_PU0 _GPIO(160)
+#define TEGRA_PIN_PU1 _GPIO(161)
+#define TEGRA_PIN_PU2 _GPIO(162)
+#define TEGRA_PIN_PU3 _GPIO(163)
+#define TEGRA_PIN_PU4 _GPIO(164)
+#define TEGRA_PIN_PU5 _GPIO(165)
+#define TEGRA_PIN_PU6 _GPIO(166)
+#define TEGRA_PIN_PV0 _GPIO(168)
+#define TEGRA_PIN_PV1 _GPIO(169)
+#define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170)
+#define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171)
+#define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
+#define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
+#define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178)
+#define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179)
+#define TEGRA_PIN_CLK1_OUT_PW4 _GPIO(180)
+#define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
+#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
+#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
+#define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184)
+#define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185)
+#define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186)
+#define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187)
+#define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188)
+#define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189)
+#define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190)
+#define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191)
+#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
+#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
+#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
+#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
+#define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
+#define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
+#define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
+#define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
+#define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
+#define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
+#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
+#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
+#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
+#define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
+#define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
+#define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
+#define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
+#define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
+#define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
+#define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
+#define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
+#define TEGRA_PIN_PBB0 _GPIO(216)
+#define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
+#define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
+#define TEGRA_PIN_PBB3 _GPIO(219)
+#define TEGRA_PIN_PBB4 _GPIO(220)
+#define TEGRA_PIN_PBB5 _GPIO(221)
+#define TEGRA_PIN_PBB6 _GPIO(222)
+#define TEGRA_PIN_PBB7 _GPIO(223)
+#define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
+#define TEGRA_PIN_PCC1 _GPIO(225)
+#define TEGRA_PIN_PCC2 _GPIO(226)
+#define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
+#define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
+#define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
+#define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
+#define TEGRA_PIN_CLK1_REQ_PEE2 _GPIO(242)
+#define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
+#define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244)
+#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
+
+/* All non-GPIO pins follow */
+#define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
+#define _PIN(offset) (NUM_GPIOS + (offset))
+
+/* Non-GPIO pins */
+#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
+#define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
+#define TEGRA_PIN_PWR_INT_N _PIN(2)
+#define TEGRA_PIN_RESET_OUT_N _PIN(3)
+#define TEGRA_PIN_OWR _PIN(4)
+#define TEGRA_PIN_JTAG_RTCK _PIN(5)
+#define TEGRA_PIN_CLK_32K_IN _PIN(6)
+#define TEGRA_PIN_GMI_CLK_LB _PIN(7)
+
+static const struct pinctrl_pin_desc tegra114_pins[] = {
+ PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
+ PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
+ PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_DQS_P_PJ3, "GMI_DQS_P PJ3"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
+ PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
+ PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
+ PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
+ PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
+ PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
+ PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
+ PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
+ PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
+ PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
+ PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
+ PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
+ PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
+ PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
+ PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
+ PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
+ PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
+ PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
+ PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
+ PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
+ PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
+ PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
+ PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
+ PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
+ PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
+ PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
+ PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
+ PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
+ PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
+ PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
+ PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
+ PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
+ PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
+ PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
+ PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
+ PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
+ PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
+ PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
+ PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
+ PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
+};
+
+static const unsigned clk_32k_out_pa0_pins[] = {
+ TEGRA_PIN_CLK_32K_OUT_PA0,
+};
+
+static const unsigned uart3_cts_n_pa1_pins[] = {
+ TEGRA_PIN_UART3_CTS_N_PA1,
+};
+
+static const unsigned dap2_fs_pa2_pins[] = {
+ TEGRA_PIN_DAP2_FS_PA2,
+};
+
+static const unsigned dap2_sclk_pa3_pins[] = {
+ TEGRA_PIN_DAP2_SCLK_PA3,
+};
+
+static const unsigned dap2_din_pa4_pins[] = {
+ TEGRA_PIN_DAP2_DIN_PA4,
+};
+
+static const unsigned dap2_dout_pa5_pins[] = {
+ TEGRA_PIN_DAP2_DOUT_PA5,
+};
+
+static const unsigned sdmmc3_clk_pa6_pins[] = {
+ TEGRA_PIN_SDMMC3_CLK_PA6,
+};
+
+static const unsigned sdmmc3_cmd_pa7_pins[] = {
+ TEGRA_PIN_SDMMC3_CMD_PA7,
+};
+
+static const unsigned gmi_a17_pb0_pins[] = {
+ TEGRA_PIN_GMI_A17_PB0,
+};
+
+static const unsigned gmi_a18_pb1_pins[] = {
+ TEGRA_PIN_GMI_A18_PB1,
+};
+
+static const unsigned sdmmc3_dat3_pb4_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT3_PB4,
+};
+
+static const unsigned sdmmc3_dat2_pb5_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT2_PB5,
+};
+
+static const unsigned sdmmc3_dat1_pb6_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT1_PB6,
+};
+
+static const unsigned sdmmc3_dat0_pb7_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT0_PB7,
+};
+
+static const unsigned uart3_rts_n_pc0_pins[] = {
+ TEGRA_PIN_UART3_RTS_N_PC0,
+};
+
+static const unsigned uart2_txd_pc2_pins[] = {
+ TEGRA_PIN_UART2_TXD_PC2,
+};
+
+static const unsigned uart2_rxd_pc3_pins[] = {
+ TEGRA_PIN_UART2_RXD_PC3,
+};
+
+static const unsigned gen1_i2c_scl_pc4_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SCL_PC4,
+};
+
+static const unsigned gen1_i2c_sda_pc5_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SDA_PC5,
+};
+
+static const unsigned gmi_wp_n_pc7_pins[] = {
+ TEGRA_PIN_GMI_WP_N_PC7,
+};
+
+static const unsigned gmi_ad0_pg0_pins[] = {
+ TEGRA_PIN_GMI_AD0_PG0,
+};
+
+static const unsigned gmi_ad1_pg1_pins[] = {
+ TEGRA_PIN_GMI_AD1_PG1,
+};
+
+static const unsigned gmi_ad2_pg2_pins[] = {
+ TEGRA_PIN_GMI_AD2_PG2,
+};
+
+static const unsigned gmi_ad3_pg3_pins[] = {
+ TEGRA_PIN_GMI_AD3_PG3,
+};
+
+static const unsigned gmi_ad4_pg4_pins[] = {
+ TEGRA_PIN_GMI_AD4_PG4,
+};
+
+static const unsigned gmi_ad5_pg5_pins[] = {
+ TEGRA_PIN_GMI_AD5_PG5,
+};
+
+static const unsigned gmi_ad6_pg6_pins[] = {
+ TEGRA_PIN_GMI_AD6_PG6,
+};
+
+static const unsigned gmi_ad7_pg7_pins[] = {
+ TEGRA_PIN_GMI_AD7_PG7,
+};
+
+static const unsigned gmi_ad8_ph0_pins[] = {
+ TEGRA_PIN_GMI_AD8_PH0,
+};
+
+static const unsigned gmi_ad9_ph1_pins[] = {
+ TEGRA_PIN_GMI_AD9_PH1,
+};
+
+static const unsigned gmi_ad10_ph2_pins[] = {
+ TEGRA_PIN_GMI_AD10_PH2,
+};
+
+static const unsigned gmi_ad11_ph3_pins[] = {
+ TEGRA_PIN_GMI_AD11_PH3,
+};
+
+static const unsigned gmi_ad12_ph4_pins[] = {
+ TEGRA_PIN_GMI_AD12_PH4,
+};
+
+static const unsigned gmi_ad13_ph5_pins[] = {
+ TEGRA_PIN_GMI_AD13_PH5,
+};
+
+static const unsigned gmi_ad14_ph6_pins[] = {
+ TEGRA_PIN_GMI_AD14_PH6,
+};
+
+static const unsigned gmi_ad15_ph7_pins[] = {
+ TEGRA_PIN_GMI_AD15_PH7,
+};
+
+static const unsigned gmi_wr_n_pi0_pins[] = {
+ TEGRA_PIN_GMI_WR_N_PI0,
+};
+
+static const unsigned gmi_oe_n_pi1_pins[] = {
+ TEGRA_PIN_GMI_OE_N_PI1,
+};
+
+static const unsigned gmi_cs6_n_pi3_pins[] = {
+ TEGRA_PIN_GMI_CS6_N_PI3,
+};
+
+static const unsigned gmi_rst_n_pi4_pins[] = {
+ TEGRA_PIN_GMI_RST_N_PI4,
+};
+
+static const unsigned gmi_iordy_pi5_pins[] = {
+ TEGRA_PIN_GMI_IORDY_PI5,
+};
+
+static const unsigned gmi_cs7_n_pi6_pins[] = {
+ TEGRA_PIN_GMI_CS7_N_PI6,
+};
+
+static const unsigned gmi_wait_pi7_pins[] = {
+ TEGRA_PIN_GMI_WAIT_PI7,
+};
+
+static const unsigned gmi_cs0_n_pj0_pins[] = {
+ TEGRA_PIN_GMI_CS0_N_PJ0,
+};
+
+static const unsigned gmi_cs1_n_pj2_pins[] = {
+ TEGRA_PIN_GMI_CS1_N_PJ2,
+};
+
+static const unsigned gmi_dqs_p_pj3_pins[] = {
+ TEGRA_PIN_GMI_DQS_P_PJ3,
+};
+
+static const unsigned uart2_cts_n_pj5_pins[] = {
+ TEGRA_PIN_UART2_CTS_N_PJ5,
+};
+
+static const unsigned uart2_rts_n_pj6_pins[] = {
+ TEGRA_PIN_UART2_RTS_N_PJ6,
+};
+
+static const unsigned gmi_a16_pj7_pins[] = {
+ TEGRA_PIN_GMI_A16_PJ7,
+};
+
+static const unsigned gmi_adv_n_pk0_pins[] = {
+ TEGRA_PIN_GMI_ADV_N_PK0,
+};
+
+static const unsigned gmi_clk_pk1_pins[] = {
+ TEGRA_PIN_GMI_CLK_PK1,
+};
+
+static const unsigned gmi_cs4_n_pk2_pins[] = {
+ TEGRA_PIN_GMI_CS4_N_PK2,
+};
+
+static const unsigned gmi_cs2_n_pk3_pins[] = {
+ TEGRA_PIN_GMI_CS2_N_PK3,
+};
+
+static const unsigned gmi_cs3_n_pk4_pins[] = {
+ TEGRA_PIN_GMI_CS3_N_PK4,
+};
+
+static const unsigned spdif_out_pk5_pins[] = {
+ TEGRA_PIN_SPDIF_OUT_PK5,
+};
+
+static const unsigned spdif_in_pk6_pins[] = {
+ TEGRA_PIN_SPDIF_IN_PK6,
+};
+
+static const unsigned gmi_a19_pk7_pins[] = {
+ TEGRA_PIN_GMI_A19_PK7,
+};
+
+static const unsigned dap1_fs_pn0_pins[] = {
+ TEGRA_PIN_DAP1_FS_PN0,
+};
+
+static const unsigned dap1_din_pn1_pins[] = {
+ TEGRA_PIN_DAP1_DIN_PN1,
+};
+
+static const unsigned dap1_dout_pn2_pins[] = {
+ TEGRA_PIN_DAP1_DOUT_PN2,
+};
+
+static const unsigned dap1_sclk_pn3_pins[] = {
+ TEGRA_PIN_DAP1_SCLK_PN3,
+};
+
+static const unsigned usb_vbus_en0_pn4_pins[] = {
+ TEGRA_PIN_USB_VBUS_EN0_PN4,
+};
+
+static const unsigned usb_vbus_en1_pn5_pins[] = {
+ TEGRA_PIN_USB_VBUS_EN1_PN5,
+};
+
+static const unsigned hdmi_int_pn7_pins[] = {
+ TEGRA_PIN_HDMI_INT_PN7,
+};
+
+static const unsigned ulpi_data7_po0_pins[] = {
+ TEGRA_PIN_ULPI_DATA7_PO0,
+};
+
+static const unsigned ulpi_data0_po1_pins[] = {
+ TEGRA_PIN_ULPI_DATA0_PO1,
+};
+
+static const unsigned ulpi_data1_po2_pins[] = {
+ TEGRA_PIN_ULPI_DATA1_PO2,
+};
+
+static const unsigned ulpi_data2_po3_pins[] = {
+ TEGRA_PIN_ULPI_DATA2_PO3,
+};
+
+static const unsigned ulpi_data3_po4_pins[] = {
+ TEGRA_PIN_ULPI_DATA3_PO4,
+};
+
+static const unsigned ulpi_data4_po5_pins[] = {
+ TEGRA_PIN_ULPI_DATA4_PO5,
+};
+
+static const unsigned ulpi_data5_po6_pins[] = {
+ TEGRA_PIN_ULPI_DATA5_PO6,
+};
+
+static const unsigned ulpi_data6_po7_pins[] = {
+ TEGRA_PIN_ULPI_DATA6_PO7,
+};
+
+static const unsigned dap3_fs_pp0_pins[] = {
+ TEGRA_PIN_DAP3_FS_PP0,
+};
+
+static const unsigned dap3_din_pp1_pins[] = {
+ TEGRA_PIN_DAP3_DIN_PP1,
+};
+
+static const unsigned dap3_dout_pp2_pins[] = {
+ TEGRA_PIN_DAP3_DOUT_PP2,
+};
+
+static const unsigned dap3_sclk_pp3_pins[] = {
+ TEGRA_PIN_DAP3_SCLK_PP3,
+};
+
+static const unsigned dap4_fs_pp4_pins[] = {
+ TEGRA_PIN_DAP4_FS_PP4,
+};
+
+static const unsigned dap4_din_pp5_pins[] = {
+ TEGRA_PIN_DAP4_DIN_PP5,
+};
+
+static const unsigned dap4_dout_pp6_pins[] = {
+ TEGRA_PIN_DAP4_DOUT_PP6,
+};
+
+static const unsigned dap4_sclk_pp7_pins[] = {
+ TEGRA_PIN_DAP4_SCLK_PP7,
+};
+
+static const unsigned kb_col0_pq0_pins[] = {
+ TEGRA_PIN_KB_COL0_PQ0,
+};
+
+static const unsigned kb_col1_pq1_pins[] = {
+ TEGRA_PIN_KB_COL1_PQ1,
+};
+
+static const unsigned kb_col2_pq2_pins[] = {
+ TEGRA_PIN_KB_COL2_PQ2,
+};
+
+static const unsigned kb_col3_pq3_pins[] = {
+ TEGRA_PIN_KB_COL3_PQ3,
+};
+
+static const unsigned kb_col4_pq4_pins[] = {
+ TEGRA_PIN_KB_COL4_PQ4,
+};
+
+static const unsigned kb_col5_pq5_pins[] = {
+ TEGRA_PIN_KB_COL5_PQ5,
+};
+
+static const unsigned kb_col6_pq6_pins[] = {
+ TEGRA_PIN_KB_COL6_PQ6,
+};
+
+static const unsigned kb_col7_pq7_pins[] = {
+ TEGRA_PIN_KB_COL7_PQ7,
+};
+
+static const unsigned kb_row0_pr0_pins[] = {
+ TEGRA_PIN_KB_ROW0_PR0,
+};
+
+static const unsigned kb_row1_pr1_pins[] = {
+ TEGRA_PIN_KB_ROW1_PR1,
+};
+
+static const unsigned kb_row2_pr2_pins[] = {
+ TEGRA_PIN_KB_ROW2_PR2,
+};
+
+static const unsigned kb_row3_pr3_pins[] = {
+ TEGRA_PIN_KB_ROW3_PR3,
+};
+
+static const unsigned kb_row4_pr4_pins[] = {
+ TEGRA_PIN_KB_ROW4_PR4,
+};
+
+static const unsigned kb_row5_pr5_pins[] = {
+ TEGRA_PIN_KB_ROW5_PR5,
+};
+
+static const unsigned kb_row6_pr6_pins[] = {
+ TEGRA_PIN_KB_ROW6_PR6,
+};
+
+static const unsigned kb_row7_pr7_pins[] = {
+ TEGRA_PIN_KB_ROW7_PR7,
+};
+
+static const unsigned kb_row8_ps0_pins[] = {
+ TEGRA_PIN_KB_ROW8_PS0,
+};
+
+static const unsigned kb_row9_ps1_pins[] = {
+ TEGRA_PIN_KB_ROW9_PS1,
+};
+
+static const unsigned kb_row10_ps2_pins[] = {
+ TEGRA_PIN_KB_ROW10_PS2,
+};
+
+static const unsigned gen2_i2c_scl_pt5_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SCL_PT5,
+};
+
+static const unsigned gen2_i2c_sda_pt6_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SDA_PT6,
+};
+
+static const unsigned sdmmc4_cmd_pt7_pins[] = {
+ TEGRA_PIN_SDMMC4_CMD_PT7,
+};
+
+static const unsigned pu0_pins[] = {
+ TEGRA_PIN_PU0,
+};
+
+static const unsigned pu1_pins[] = {
+ TEGRA_PIN_PU1,
+};
+
+static const unsigned pu2_pins[] = {
+ TEGRA_PIN_PU2,
+};
+
+static const unsigned pu3_pins[] = {
+ TEGRA_PIN_PU3,
+};
+
+static const unsigned pu4_pins[] = {
+ TEGRA_PIN_PU4,
+};
+
+static const unsigned pu5_pins[] = {
+ TEGRA_PIN_PU5,
+};
+
+static const unsigned pu6_pins[] = {
+ TEGRA_PIN_PU6,
+};
+
+static const unsigned pv0_pins[] = {
+ TEGRA_PIN_PV0,
+};
+
+static const unsigned pv1_pins[] = {
+ TEGRA_PIN_PV1,
+};
+
+static const unsigned sdmmc3_cd_n_pv2_pins[] = {
+ TEGRA_PIN_SDMMC3_CD_N_PV2,
+};
+
+static const unsigned sdmmc1_wp_n_pv3_pins[] = {
+ TEGRA_PIN_SDMMC1_WP_N_PV3,
+};
+
+static const unsigned ddc_scl_pv4_pins[] = {
+ TEGRA_PIN_DDC_SCL_PV4,
+};
+
+static const unsigned ddc_sda_pv5_pins[] = {
+ TEGRA_PIN_DDC_SDA_PV5,
+};
+
+static const unsigned gpio_w2_aud_pw2_pins[] = {
+ TEGRA_PIN_GPIO_W2_AUD_PW2,
+};
+
+static const unsigned gpio_w3_aud_pw3_pins[] = {
+ TEGRA_PIN_GPIO_W3_AUD_PW3,
+};
+
+static const unsigned clk1_out_pw4_pins[] = {
+ TEGRA_PIN_CLK1_OUT_PW4,
+};
+
+static const unsigned clk2_out_pw5_pins[] = {
+ TEGRA_PIN_CLK2_OUT_PW5,
+};
+
+static const unsigned uart3_txd_pw6_pins[] = {
+ TEGRA_PIN_UART3_TXD_PW6,
+};
+
+static const unsigned uart3_rxd_pw7_pins[] = {
+ TEGRA_PIN_UART3_RXD_PW7,
+};
+
+static const unsigned dvfs_pwm_px0_pins[] = {
+ TEGRA_PIN_DVFS_PWM_PX0,
+};
+
+static const unsigned gpio_x1_aud_px1_pins[] = {
+ TEGRA_PIN_GPIO_X1_AUD_PX1,
+};
+
+static const unsigned dvfs_clk_px2_pins[] = {
+ TEGRA_PIN_DVFS_CLK_PX2,
+};
+
+static const unsigned gpio_x3_aud_px3_pins[] = {
+ TEGRA_PIN_GPIO_X3_AUD_PX3,
+};
+
+static const unsigned gpio_x4_aud_px4_pins[] = {
+ TEGRA_PIN_GPIO_X4_AUD_PX4,
+};
+
+static const unsigned gpio_x5_aud_px5_pins[] = {
+ TEGRA_PIN_GPIO_X5_AUD_PX5,
+};
+
+static const unsigned gpio_x6_aud_px6_pins[] = {
+ TEGRA_PIN_GPIO_X6_AUD_PX6,
+};
+
+static const unsigned gpio_x7_aud_px7_pins[] = {
+ TEGRA_PIN_GPIO_X7_AUD_PX7,
+};
+
+static const unsigned ulpi_clk_py0_pins[] = {
+ TEGRA_PIN_ULPI_CLK_PY0,
+};
+
+static const unsigned ulpi_dir_py1_pins[] = {
+ TEGRA_PIN_ULPI_DIR_PY1,
+};
+
+static const unsigned ulpi_nxt_py2_pins[] = {
+ TEGRA_PIN_ULPI_NXT_PY2,
+};
+
+static const unsigned ulpi_stp_py3_pins[] = {
+ TEGRA_PIN_ULPI_STP_PY3,
+};
+
+static const unsigned sdmmc1_dat3_py4_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT3_PY4,
+};
+
+static const unsigned sdmmc1_dat2_py5_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT2_PY5,
+};
+
+static const unsigned sdmmc1_dat1_py6_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT1_PY6,
+};
+
+static const unsigned sdmmc1_dat0_py7_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT0_PY7,
+};
+
+static const unsigned sdmmc1_clk_pz0_pins[] = {
+ TEGRA_PIN_SDMMC1_CLK_PZ0,
+};
+
+static const unsigned sdmmc1_cmd_pz1_pins[] = {
+ TEGRA_PIN_SDMMC1_CMD_PZ1,
+};
+
+static const unsigned sys_clk_req_pz5_pins[] = {
+ TEGRA_PIN_SYS_CLK_REQ_PZ5,
+};
+
+static const unsigned pwr_i2c_scl_pz6_pins[] = {
+ TEGRA_PIN_PWR_I2C_SCL_PZ6,
+};
+
+static const unsigned pwr_i2c_sda_pz7_pins[] = {
+ TEGRA_PIN_PWR_I2C_SDA_PZ7,
+};
+
+static const unsigned sdmmc4_dat0_paa0_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT0_PAA0,
+};
+
+static const unsigned sdmmc4_dat1_paa1_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT1_PAA1,
+};
+
+static const unsigned sdmmc4_dat2_paa2_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT2_PAA2,
+};
+
+static const unsigned sdmmc4_dat3_paa3_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT3_PAA3,
+};
+
+static const unsigned sdmmc4_dat4_paa4_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT4_PAA4,
+};
+
+static const unsigned sdmmc4_dat5_paa5_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT5_PAA5,
+};
+
+static const unsigned sdmmc4_dat6_paa6_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT6_PAA6,
+};
+
+static const unsigned sdmmc4_dat7_paa7_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT7_PAA7,
+};
+
+static const unsigned pbb0_pins[] = {
+ TEGRA_PIN_PBB0,
+};
+
+static const unsigned cam_i2c_scl_pbb1_pins[] = {
+ TEGRA_PIN_CAM_I2C_SCL_PBB1,
+};
+
+static const unsigned cam_i2c_sda_pbb2_pins[] = {
+ TEGRA_PIN_CAM_I2C_SDA_PBB2,
+};
+
+static const unsigned pbb3_pins[] = {
+ TEGRA_PIN_PBB3,
+};
+
+static const unsigned pbb4_pins[] = {
+ TEGRA_PIN_PBB4,
+};
+
+static const unsigned pbb5_pins[] = {
+ TEGRA_PIN_PBB5,
+};
+
+static const unsigned pbb6_pins[] = {
+ TEGRA_PIN_PBB6,
+};
+
+static const unsigned pbb7_pins[] = {
+ TEGRA_PIN_PBB7,
+};
+
+static const unsigned cam_mclk_pcc0_pins[] = {
+ TEGRA_PIN_CAM_MCLK_PCC0,
+};
+
+static const unsigned pcc1_pins[] = {
+ TEGRA_PIN_PCC1,
+};
+
+static const unsigned pcc2_pins[] = {
+ TEGRA_PIN_PCC2,
+};
+
+static const unsigned sdmmc4_clk_pcc4_pins[] = {
+ TEGRA_PIN_SDMMC4_CLK_PCC4,
+};
+
+static const unsigned clk2_req_pcc5_pins[] = {
+ TEGRA_PIN_CLK2_REQ_PCC5,
+};
+
+static const unsigned clk3_out_pee0_pins[] = {
+ TEGRA_PIN_CLK3_OUT_PEE0,
+};
+
+static const unsigned clk3_req_pee1_pins[] = {
+ TEGRA_PIN_CLK3_REQ_PEE1,
+};
+
+static const unsigned clk1_req_pee2_pins[] = {
+ TEGRA_PIN_CLK1_REQ_PEE2,
+};
+
+static const unsigned hdmi_cec_pee3_pins[] = {
+ TEGRA_PIN_HDMI_CEC_PEE3,
+};
+
+static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
+ TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
+};
+
+static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
+ TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
+};
+
+static const unsigned core_pwr_req_pins[] = {
+ TEGRA_PIN_CORE_PWR_REQ,
+};
+
+static const unsigned cpu_pwr_req_pins[] = {
+ TEGRA_PIN_CPU_PWR_REQ,
+};
+
+static const unsigned pwr_int_n_pins[] = {
+ TEGRA_PIN_PWR_INT_N,
+};
+
+static const unsigned reset_out_n_pins[] = {
+ TEGRA_PIN_RESET_OUT_N,
+};
+
+static const unsigned owr_pins[] = {
+ TEGRA_PIN_OWR,
+};
+
+static const unsigned jtag_rtck_pins[] = {
+ TEGRA_PIN_JTAG_RTCK,
+};
+
+static const unsigned clk_32k_in_pins[] = {
+ TEGRA_PIN_CLK_32K_IN,
+};
+
+static const unsigned gmi_clk_lb_pins[] = {
+ TEGRA_PIN_GMI_CLK_LB,
+};
+
+static const unsigned drive_ao1_pins[] = {
+ TEGRA_PIN_KB_ROW0_PR0,
+ TEGRA_PIN_KB_ROW1_PR1,
+ TEGRA_PIN_KB_ROW2_PR2,
+ TEGRA_PIN_KB_ROW3_PR3,
+ TEGRA_PIN_KB_ROW4_PR4,
+ TEGRA_PIN_KB_ROW5_PR5,
+ TEGRA_PIN_KB_ROW6_PR6,
+ TEGRA_PIN_KB_ROW7_PR7,
+ TEGRA_PIN_PWR_I2C_SCL_PZ6,
+ TEGRA_PIN_PWR_I2C_SDA_PZ7,
+};
+
+static const unsigned drive_ao2_pins[] = {
+ TEGRA_PIN_CLK_32K_OUT_PA0,
+ TEGRA_PIN_KB_COL0_PQ0,
+ TEGRA_PIN_KB_COL1_PQ1,
+ TEGRA_PIN_KB_COL2_PQ2,
+ TEGRA_PIN_KB_COL3_PQ3,
+ TEGRA_PIN_KB_COL4_PQ4,
+ TEGRA_PIN_KB_COL5_PQ5,
+ TEGRA_PIN_KB_COL6_PQ6,
+ TEGRA_PIN_KB_COL7_PQ7,
+ TEGRA_PIN_KB_ROW8_PS0,
+ TEGRA_PIN_KB_ROW9_PS1,
+ TEGRA_PIN_KB_ROW10_PS2,
+ TEGRA_PIN_SYS_CLK_REQ_PZ5,
+ TEGRA_PIN_CORE_PWR_REQ,
+ TEGRA_PIN_CPU_PWR_REQ,
+ TEGRA_PIN_RESET_OUT_N,
+};
+
+static const unsigned drive_at1_pins[] = {
+ TEGRA_PIN_GMI_AD8_PH0,
+ TEGRA_PIN_GMI_AD9_PH1,
+ TEGRA_PIN_GMI_AD10_PH2,
+ TEGRA_PIN_GMI_AD11_PH3,
+ TEGRA_PIN_GMI_AD12_PH4,
+ TEGRA_PIN_GMI_AD13_PH5,
+ TEGRA_PIN_GMI_AD14_PH6,
+ TEGRA_PIN_GMI_AD15_PH7,
+ TEGRA_PIN_GMI_IORDY_PI5,
+ TEGRA_PIN_GMI_CS7_N_PI6,
+};
+
+static const unsigned drive_at2_pins[] = {
+ TEGRA_PIN_GMI_AD0_PG0,
+ TEGRA_PIN_GMI_AD1_PG1,
+ TEGRA_PIN_GMI_AD2_PG2,
+ TEGRA_PIN_GMI_AD3_PG3,
+ TEGRA_PIN_GMI_AD4_PG4,
+ TEGRA_PIN_GMI_AD5_PG5,
+ TEGRA_PIN_GMI_AD6_PG6,
+ TEGRA_PIN_GMI_AD7_PG7,
+ TEGRA_PIN_GMI_WR_N_PI0,
+ TEGRA_PIN_GMI_OE_N_PI1,
+ TEGRA_PIN_GMI_CS6_N_PI3,
+ TEGRA_PIN_GMI_RST_N_PI4,
+ TEGRA_PIN_GMI_WAIT_PI7,
+ TEGRA_PIN_GMI_DQS_P_PJ3,
+ TEGRA_PIN_GMI_ADV_N_PK0,
+ TEGRA_PIN_GMI_CLK_PK1,
+ TEGRA_PIN_GMI_CS4_N_PK2,
+ TEGRA_PIN_GMI_CS2_N_PK3,
+ TEGRA_PIN_GMI_CS3_N_PK4,
+};
+
+static const unsigned drive_at3_pins[] = {
+ TEGRA_PIN_GMI_WP_N_PC7,
+ TEGRA_PIN_GMI_CS0_N_PJ0,
+};
+
+static const unsigned drive_at4_pins[] = {
+ TEGRA_PIN_GMI_A17_PB0,
+ TEGRA_PIN_GMI_A18_PB1,
+ TEGRA_PIN_GMI_CS1_N_PJ2,
+ TEGRA_PIN_GMI_A16_PJ7,
+ TEGRA_PIN_GMI_A19_PK7,
+};
+
+static const unsigned drive_at5_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SCL_PT5,
+ TEGRA_PIN_GEN2_I2C_SDA_PT6,
+};
+
+static const unsigned drive_cdev1_pins[] = {
+ TEGRA_PIN_CLK1_OUT_PW4,
+ TEGRA_PIN_CLK1_REQ_PEE2,
+};
+
+static const unsigned drive_cdev2_pins[] = {
+ TEGRA_PIN_CLK2_OUT_PW5,
+ TEGRA_PIN_CLK2_REQ_PCC5,
+ TEGRA_PIN_SDMMC1_WP_N_PV3,
+};
+
+static const unsigned drive_dap1_pins[] = {
+ TEGRA_PIN_DAP1_FS_PN0,
+ TEGRA_PIN_DAP1_DIN_PN1,
+ TEGRA_PIN_DAP1_DOUT_PN2,
+ TEGRA_PIN_DAP1_SCLK_PN3,
+};
+
+static const unsigned drive_dap2_pins[] = {
+ TEGRA_PIN_DAP2_FS_PA2,
+ TEGRA_PIN_DAP2_SCLK_PA3,
+ TEGRA_PIN_DAP2_DIN_PA4,
+ TEGRA_PIN_DAP2_DOUT_PA5,
+};
+
+static const unsigned drive_dap3_pins[] = {
+ TEGRA_PIN_DAP3_FS_PP0,
+ TEGRA_PIN_DAP3_DIN_PP1,
+ TEGRA_PIN_DAP3_DOUT_PP2,
+ TEGRA_PIN_DAP3_SCLK_PP3,
+};
+
+static const unsigned drive_dap4_pins[] = {
+ TEGRA_PIN_DAP4_FS_PP4,
+ TEGRA_PIN_DAP4_DIN_PP5,
+ TEGRA_PIN_DAP4_DOUT_PP6,
+ TEGRA_PIN_DAP4_SCLK_PP7,
+};
+
+static const unsigned drive_dbg_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SCL_PC4,
+ TEGRA_PIN_GEN1_I2C_SDA_PC5,
+ TEGRA_PIN_PU0,
+ TEGRA_PIN_PU1,
+ TEGRA_PIN_PU2,
+ TEGRA_PIN_PU3,
+ TEGRA_PIN_PU4,
+ TEGRA_PIN_PU5,
+ TEGRA_PIN_PU6,
+};
+
+static const unsigned drive_sdio3_pins[] = {
+ TEGRA_PIN_SDMMC3_CLK_PA6,
+ TEGRA_PIN_SDMMC3_CMD_PA7,
+ TEGRA_PIN_SDMMC3_DAT3_PB4,
+ TEGRA_PIN_SDMMC3_DAT2_PB5,
+ TEGRA_PIN_SDMMC3_DAT1_PB6,
+ TEGRA_PIN_SDMMC3_DAT0_PB7,
+ TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
+ TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
+};
+
+static const unsigned drive_spi_pins[] = {
+ TEGRA_PIN_DVFS_PWM_PX0,
+ TEGRA_PIN_GPIO_X1_AUD_PX1,
+ TEGRA_PIN_DVFS_CLK_PX2,
+ TEGRA_PIN_GPIO_X3_AUD_PX3,
+ TEGRA_PIN_GPIO_X4_AUD_PX4,
+ TEGRA_PIN_GPIO_X5_AUD_PX5,
+ TEGRA_PIN_GPIO_X6_AUD_PX6,
+ TEGRA_PIN_GPIO_X7_AUD_PX7,
+ TEGRA_PIN_GPIO_W2_AUD_PW2,
+ TEGRA_PIN_GPIO_W3_AUD_PW3,
+};
+
+static const unsigned drive_uaa_pins[] = {
+ TEGRA_PIN_ULPI_DATA0_PO1,
+ TEGRA_PIN_ULPI_DATA1_PO2,
+ TEGRA_PIN_ULPI_DATA2_PO3,
+ TEGRA_PIN_ULPI_DATA3_PO4,
+};
+
+static const unsigned drive_uab_pins[] = {
+ TEGRA_PIN_ULPI_DATA7_PO0,
+ TEGRA_PIN_ULPI_DATA4_PO5,
+ TEGRA_PIN_ULPI_DATA5_PO6,
+ TEGRA_PIN_ULPI_DATA6_PO7,
+ TEGRA_PIN_PV0,
+ TEGRA_PIN_PV1,
+};
+
+static const unsigned drive_uart2_pins[] = {
+ TEGRA_PIN_UART2_TXD_PC2,
+ TEGRA_PIN_UART2_RXD_PC3,
+ TEGRA_PIN_UART2_CTS_N_PJ5,
+ TEGRA_PIN_UART2_RTS_N_PJ6,
+};
+
+static const unsigned drive_uart3_pins[] = {
+ TEGRA_PIN_UART3_CTS_N_PA1,
+ TEGRA_PIN_UART3_RTS_N_PC0,
+ TEGRA_PIN_UART3_TXD_PW6,
+ TEGRA_PIN_UART3_RXD_PW7,
+};
+
+static const unsigned drive_sdio1_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT3_PY4,
+ TEGRA_PIN_SDMMC1_DAT2_PY5,
+ TEGRA_PIN_SDMMC1_DAT1_PY6,
+ TEGRA_PIN_SDMMC1_DAT0_PY7,
+ TEGRA_PIN_SDMMC1_CLK_PZ0,
+ TEGRA_PIN_SDMMC1_CMD_PZ1,
+};
+
+static const unsigned drive_ddc_pins[] = {
+ TEGRA_PIN_DDC_SCL_PV4,
+ TEGRA_PIN_DDC_SDA_PV5,
+};
+
+static const unsigned drive_gma_pins[] = {
+ TEGRA_PIN_SDMMC4_CLK_PCC4,
+ TEGRA_PIN_SDMMC4_CMD_PT7,
+ TEGRA_PIN_SDMMC4_DAT0_PAA0,
+ TEGRA_PIN_SDMMC4_DAT1_PAA1,
+ TEGRA_PIN_SDMMC4_DAT2_PAA2,
+ TEGRA_PIN_SDMMC4_DAT3_PAA3,
+ TEGRA_PIN_SDMMC4_DAT4_PAA4,
+ TEGRA_PIN_SDMMC4_DAT5_PAA5,
+ TEGRA_PIN_SDMMC4_DAT6_PAA6,
+ TEGRA_PIN_SDMMC4_DAT7_PAA7,
+};
+
+static const unsigned drive_gme_pins[] = {
+ TEGRA_PIN_PBB0,
+ TEGRA_PIN_CAM_I2C_SCL_PBB1,
+ TEGRA_PIN_CAM_I2C_SDA_PBB2,
+ TEGRA_PIN_PBB3,
+ TEGRA_PIN_PCC2,
+};
+
+static const unsigned drive_gmf_pins[] = {
+ TEGRA_PIN_PBB4,
+ TEGRA_PIN_PBB5,
+ TEGRA_PIN_PBB6,
+ TEGRA_PIN_PBB7,
+};
+
+static const unsigned drive_gmg_pins[] = {
+ TEGRA_PIN_CAM_MCLK_PCC0,
+};
+
+static const unsigned drive_gmh_pins[] = {
+ TEGRA_PIN_PCC1,
+};
+
+static const unsigned drive_owr_pins[] = {
+ TEGRA_PIN_SDMMC3_CD_N_PV2,
+};
+
+static const unsigned drive_uda_pins[] = {
+ TEGRA_PIN_ULPI_CLK_PY0,
+ TEGRA_PIN_ULPI_DIR_PY1,
+ TEGRA_PIN_ULPI_NXT_PY2,
+ TEGRA_PIN_ULPI_STP_PY3,
+};
+
+static const unsigned drive_dev3_pins[] = {
+};
+
+static const unsigned drive_cec_pins[] = {
+};
+
+static const unsigned drive_at6_pins[] = {
+};
+
+static const unsigned drive_dap5_pins[] = {
+};
+
+static const unsigned drive_usb_vbus_en_pins[] = {
+};
+
+static const unsigned drive_ao3_pins[] = {
+};
+
+static const unsigned drive_hv0_pins[] = {
+};
+
+static const unsigned drive_sdio4_pins[] = {
+};
+
+static const unsigned drive_ao0_pins[] = {
+};
+
+enum tegra_mux {
+ TEGRA_MUX_BLINK,
+ TEGRA_MUX_CEC,
+ TEGRA_MUX_CLDVFS,
+ TEGRA_MUX_CLK,
+ TEGRA_MUX_CLK12,
+ TEGRA_MUX_CPU,
+ TEGRA_MUX_DAP,
+ TEGRA_MUX_DAP1,
+ TEGRA_MUX_DAP2,
+ TEGRA_MUX_DEV3,
+ TEGRA_MUX_DISPLAYA,
+ TEGRA_MUX_DISPLAYA_ALT,
+ TEGRA_MUX_DISPLAYB,
+ TEGRA_MUX_DTV,
+ TEGRA_MUX_EMC_DLL,
+ TEGRA_MUX_EXTPERIPH1,
+ TEGRA_MUX_EXTPERIPH2,
+ TEGRA_MUX_EXTPERIPH3,
+ TEGRA_MUX_GMI,
+ TEGRA_MUX_GMI_ALT,
+ TEGRA_MUX_HDA,
+ TEGRA_MUX_HSI,
+ TEGRA_MUX_I2C1,
+ TEGRA_MUX_I2C2,
+ TEGRA_MUX_I2C3,
+ TEGRA_MUX_I2C4,
+ TEGRA_MUX_I2CPWR,
+ TEGRA_MUX_I2S0,
+ TEGRA_MUX_I2S1,
+ TEGRA_MUX_I2S2,
+ TEGRA_MUX_I2S3,
+ TEGRA_MUX_I2S4,
+ TEGRA_MUX_IRDA,
+ TEGRA_MUX_KBC,
+ TEGRA_MUX_NAND,
+ TEGRA_MUX_NAND_ALT,
+ TEGRA_MUX_OWR,
+ TEGRA_MUX_PMI,
+ TEGRA_MUX_PWM0,
+ TEGRA_MUX_PWM1,
+ TEGRA_MUX_PWM2,
+ TEGRA_MUX_PWM3,
+ TEGRA_MUX_PWRON,
+ TEGRA_MUX_RESET_OUT_N,
+ TEGRA_MUX_RSVD1,
+ TEGRA_MUX_RSVD2,
+ TEGRA_MUX_RSVD3,
+ TEGRA_MUX_RSVD4,
+ TEGRA_MUX_RTCK,
+ TEGRA_MUX_SDMMC1,
+ TEGRA_MUX_SDMMC2,
+ TEGRA_MUX_SDMMC3,
+ TEGRA_MUX_SDMMC4,
+ TEGRA_MUX_SOC,
+ TEGRA_MUX_SPDIF,
+ TEGRA_MUX_SPI1,
+ TEGRA_MUX_SPI2,
+ TEGRA_MUX_SPI3,
+ TEGRA_MUX_SPI4,
+ TEGRA_MUX_SPI5,
+ TEGRA_MUX_SPI6,
+ TEGRA_MUX_SYSCLK,
+ TEGRA_MUX_TRACE,
+ TEGRA_MUX_UARTA,
+ TEGRA_MUX_UARTB,
+ TEGRA_MUX_UARTC,
+ TEGRA_MUX_UARTD,
+ TEGRA_MUX_ULPI,
+ TEGRA_MUX_USB,
+ TEGRA_MUX_VGP1,
+ TEGRA_MUX_VGP2,
+ TEGRA_MUX_VGP3,
+ TEGRA_MUX_VGP4,
+ TEGRA_MUX_VGP5,
+ TEGRA_MUX_VGP6,
+ TEGRA_MUX_VI,
+ TEGRA_MUX_VI_ALT1,
+ TEGRA_MUX_VI_ALT3,
+};
+
+#define FUNCTION(fname) \
+ { \
+ .name = #fname, \
+ }
+
+static struct tegra_function tegra114_functions[] = {
+ FUNCTION(blink),
+ FUNCTION(cec),
+ FUNCTION(cldvfs),
+ FUNCTION(clk),
+ FUNCTION(clk12),
+ FUNCTION(cpu),
+ FUNCTION(dap),
+ FUNCTION(dap1),
+ FUNCTION(dap2),
+ FUNCTION(dev3),
+ FUNCTION(displaya),
+ FUNCTION(displaya_alt),
+ FUNCTION(displayb),
+ FUNCTION(dtv),
+ FUNCTION(emc_dll),
+ FUNCTION(extperiph1),
+ FUNCTION(extperiph2),
+ FUNCTION(extperiph3),
+ FUNCTION(gmi),
+ FUNCTION(gmi_alt),
+ FUNCTION(hda),
+ FUNCTION(hsi),
+ FUNCTION(i2c1),
+ FUNCTION(i2c2),
+ FUNCTION(i2c3),
+ FUNCTION(i2c4),
+ FUNCTION(i2cpwr),
+ FUNCTION(i2s0),
+ FUNCTION(i2s1),
+ FUNCTION(i2s2),
+ FUNCTION(i2s3),
+ FUNCTION(i2s4),
+ FUNCTION(irda),
+ FUNCTION(kbc),
+ FUNCTION(nand),
+ FUNCTION(nand_alt),
+ FUNCTION(owr),
+ FUNCTION(pmi),
+ FUNCTION(pwm0),
+ FUNCTION(pwm1),
+ FUNCTION(pwm2),
+ FUNCTION(pwm3),
+ FUNCTION(pwron),
+ FUNCTION(reset_out_n),
+ FUNCTION(rsvd1),
+ FUNCTION(rsvd2),
+ FUNCTION(rsvd3),
+ FUNCTION(rsvd4),
+ FUNCTION(rtck),
+ FUNCTION(sdmmc1),
+ FUNCTION(sdmmc2),
+ FUNCTION(sdmmc3),
+ FUNCTION(sdmmc4),
+ FUNCTION(soc),
+ FUNCTION(spdif),
+ FUNCTION(spi1),
+ FUNCTION(spi2),
+ FUNCTION(spi3),
+ FUNCTION(spi4),
+ FUNCTION(spi5),
+ FUNCTION(spi6),
+ FUNCTION(sysclk),
+ FUNCTION(trace),
+ FUNCTION(uarta),
+ FUNCTION(uartb),
+ FUNCTION(uartc),
+ FUNCTION(uartd),
+ FUNCTION(ulpi),
+ FUNCTION(usb),
+ FUNCTION(vgp1),
+ FUNCTION(vgp2),
+ FUNCTION(vgp3),
+ FUNCTION(vgp4),
+ FUNCTION(vgp5),
+ FUNCTION(vgp6),
+ FUNCTION(vi),
+ FUNCTION(vi_alt1),
+ FUNCTION(vi_alt3),
+};
+
+#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
+#define PINGROUP_REG_A 0x3000 /* bank 1 */
+
+#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
+#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
+
+#define PINGROUP_BIT_Y(b) (b)
+#define PINGROUP_BIT_N(b) (-1)
+
+#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .funcs = { \
+ TEGRA_MUX_##f0, \
+ TEGRA_MUX_##f1, \
+ TEGRA_MUX_##f2, \
+ TEGRA_MUX_##f3, \
+ }, \
+ .mux_reg = PINGROUP_REG(r), \
+ .mux_bank = 1, \
+ .mux_bit = 0, \
+ .pupd_reg = PINGROUP_REG(r), \
+ .pupd_bank = 1, \
+ .pupd_bit = 2, \
+ .tri_reg = PINGROUP_REG(r), \
+ .tri_bank = 1, \
+ .tri_bit = 4, \
+ .einput_bit = 5, \
+ .odrain_bit = PINGROUP_BIT_##od(6), \
+ .lock_bit = 7, \
+ .ioreset_bit = PINGROUP_BIT_##ior(8), \
+ .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
+ .drv_reg = -1, \
+ }
+
+#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
+ drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
+ slwf_b, slwf_w, drvtype) \
+ { \
+ .name = "drive_" #pg_name, \
+ .pins = drive_##pg_name##_pins, \
+ .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
+ .mux_reg = -1, \
+ .pupd_reg = -1, \
+ .tri_reg = -1, \
+ .einput_bit = -1, \
+ .odrain_bit = -1, \
+ .lock_bit = -1, \
+ .ioreset_bit = -1, \
+ .rcv_sel_bit = -1, \
+ .drv_reg = DRV_PINGROUP_REG(r), \
+ .drv_bank = 0, \
+ .hsm_bit = hsm_b, \
+ .schmitt_bit = schmitt_b, \
+ .lpmd_bit = lpmd_b, \
+ .drvdn_bit = drvdn_b, \
+ .drvdn_width = drvdn_w, \
+ .drvup_bit = drvup_b, \
+ .drvup_width = drvup_w, \
+ .slwr_bit = slwr_b, \
+ .slwr_width = slwr_w, \
+ .slwf_bit = slwf_b, \
+ .slwf_width = slwf_w, \
+ .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
+ }
+
+static const struct tegra_pingroup tegra114_groups[] = {
+ /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
+ PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
+ PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N),
+ PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N),
+ PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N),
+ PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N),
+ PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N),
+ PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N),
+ PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N),
+ PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N),
+ PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N),
+ PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N),
+ PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N),
+ PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N),
+ PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N),
+ PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3038, N, N, N),
+ PINGROUP(dap3_sclk_pp3, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x303c, N, N, N),
+ PINGROUP(pv0, USB, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N),
+ PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N),
+ PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N),
+ PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N),
+ PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N),
+ PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N),
+ PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N),
+ PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N),
+ PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N),
+ PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N),
+ PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y),
+ PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y),
+ PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y),
+ PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N),
+ PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N),
+ PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, RSVD3, SPI4, 0x316c, N, N, N),
+ PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, RSVD3, SPI4, 0x3170, N, N, N),
+ PINGROUP(uart3_txd_pw6, UARTC, RSVD2, RSVD3, SPI4, 0x3174, N, N, N),
+ PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, RSVD3, SPI4, 0x3178, N, N, N),
+ PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, SPI4, 0x317c, N, N, N),
+ PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, DISPLAYA, 0x3180, N, N, N),
+ PINGROUP(pu0, OWR, UARTA, RSVD3, RSVD4, 0x3184, N, N, N),
+ PINGROUP(pu1, RSVD1, UARTA, RSVD3, RSVD4, 0x3188, N, N, N),
+ PINGROUP(pu2, RSVD1, UARTA, RSVD3, RSVD4, 0x318c, N, N, N),
+ PINGROUP(pu3, PWM0, UARTA, DISPLAYA, DISPLAYB, 0x3190, N, N, N),
+ PINGROUP(pu4, PWM1, UARTA, DISPLAYA, DISPLAYB, 0x3194, N, N, N),
+ PINGROUP(pu5, PWM2, UARTA, DISPLAYA, DISPLAYB, 0x3198, N, N, N),
+ PINGROUP(pu6, PWM3, UARTA, USB, DISPLAYB, 0x319c, N, N, N),
+ PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N),
+ PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N),
+ PINGROUP(dap4_fs_pp4, I2S3, RSVD2, DTV, RSVD4, 0x31a8, N, N, N),
+ PINGROUP(dap4_din_pp5, I2S3, RSVD2, RSVD3, RSVD4, 0x31ac, N, N, N),
+ PINGROUP(dap4_dout_pp6, I2S3, RSVD2, DTV, RSVD4, 0x31b0, N, N, N),
+ PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, RSVD3, RSVD4, 0x31b4, N, N, N),
+ PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N),
+ PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N),
+ PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N, N),
+ PINGROUP(gmi_iordy_pi5, SDMMC2, RSVD2, GMI, TRACE, 0x31c4, N, N, N),
+ PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, 0x31c8, N, N, N),
+ PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, 0x31cc, N, N, N),
+ PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, 0x31d0, N, N, N),
+ PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, 0x31d4, N, N, N),
+ PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, 0x31d8, N, N, N),
+ PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, 0x31dc, N, N, N),
+ PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, 0x31e0, N, N, N),
+ PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, 0x31e4, N, N, N),
+ PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, 0x31e8, N, N, N),
+ PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, SDMMC2, 0x31ec, N, N, N),
+ PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, N, N),
+ PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, N, N),
+ PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, N, N),
+ PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, N, N),
+ PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, N, N),
+ PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, SPI4, 0x3204, N, N, N),
+ PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, SPI4, 0x3208, N, N, N),
+ PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, SPI4, 0x320c, N, N, N),
+ PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, DTV, 0x3210, N, N, N),
+ PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, CLDVFS, 0x3214, N, N, N),
+ PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, CLDVFS, 0x3218, N, N, N),
+ PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, USB, 0x321c, N, N, N),
+ PINGROUP(gmi_ad12_ph4, SDMMC2, NAND, GMI, RSVD4, 0x3220, N, N, N),
+ PINGROUP(gmi_ad13_ph5, SDMMC2, NAND, GMI, RSVD4, 0x3224, N, N, N),
+ PINGROUP(gmi_ad14_ph6, SDMMC2, NAND, GMI, DTV, 0x3228, N, N, N),
+ PINGROUP(gmi_ad15_ph7, SDMMC2, NAND, GMI, DTV, 0x322c, N, N, N),
+ PINGROUP(gmi_a16_pj7, UARTD, TRACE, GMI, GMI_ALT, 0x3230, N, N, N),
+ PINGROUP(gmi_a17_pb0, UARTD, RSVD2, GMI, TRACE, 0x3234, N, N, N),
+ PINGROUP(gmi_a18_pb1, UARTD, RSVD2, GMI, TRACE, 0x3238, N, N, N),
+ PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, TRACE, 0x323c, N, N, N),
+ PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, SPI4, 0x3240, N, N, N),
+ PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, SOC, 0x3244, N, N, N),
+ PINGROUP(gmi_dqs_p_pj3, SDMMC2, NAND, GMI, TRACE, 0x3248, N, N, N),
+ PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, 0x324c, N, N, N),
+ PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N),
+ PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N),
+ PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N),
+ PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N),
+ PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N),
+ PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N),
+ PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N),
+ PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N),
+ PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N),
+ PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, GMI, RSVD4, 0x3274, N, Y, N),
+ PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N),
+ PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N),
+ PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, RSVD4, 0x3284, N, N, N),
+ PINGROUP(pcc1, I2S4, RSVD2, RSVD3, RSVD4, 0x3288, N, N, N),
+ PINGROUP(pbb0, I2S4, VI, VI_ALT1, VI_ALT3, 0x328c, N, N, N),
+ PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, RSVD4, 0x3290, Y, N, N),
+ PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, RSVD4, 0x3294, Y, N, N),
+ PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, RSVD4, 0x3298, N, N, N),
+ PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, RSVD4, 0x329c, N, N, N),
+ PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, RSVD4, 0x32a0, N, N, N),
+ PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, RSVD4, 0x32a4, N, N, N),
+ PINGROUP(pbb7, I2S4, RSVD2, RSVD3, RSVD4, 0x32a8, N, N, N),
+ PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, 0x32ac, N, N, N),
+ PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N),
+ PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N),
+ PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N),
+ PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N),
+ PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N),
+ PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N),
+ PINGROUP(kb_row3_pr3, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32c8, N, N, N),
+ PINGROUP(kb_row4_pr4, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32cc, N, N, N),
+ PINGROUP(kb_row5_pr5, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32d0, N, N, N),
+ PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N),
+ PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N),
+ PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N),
+ PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N),
+ PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N),
+ PINGROUP(kb_col0_pq0, KBC, USB, SPI2, EMC_DLL, 0x32fc, N, N, N),
+ PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, EMC_DLL, 0x3300, N, N, N),
+ PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N),
+ PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N),
+ PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N),
+ PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC1, RSVD4, 0x3310, N, N, N),
+ PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, RSVD4, 0x3314, N, N, N),
+ PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, RSVD4, 0x3318, N, N, N),
+ PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N),
+ PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N, N),
+ PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N),
+ PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N),
+ PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N),
+ PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N),
+ PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y),
+ PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N),
+ PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N),
+ PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, RSVD4, 0x3340, N, N, N),
+ PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N),
+ PINGROUP(clk1_req_pee2, DAP, DAP1, RSVD3, RSVD4, 0x3348, N, N, N),
+ PINGROUP(clk1_out_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N),
+ PINGROUP(spdif_in_pk6, SPDIF, USB, RSVD3, RSVD4, 0x3350, N, N, N),
+ PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, RSVD4, 0x3354, N, N, N),
+ PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, RSVD4, 0x3358, N, N, N),
+ PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, RSVD4, 0x335c, N, N, N),
+ PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, RSVD4, 0x3360, N, N, N),
+ PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, RSVD4, 0x3364, N, N, N),
+ PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, RSVD3, RSVD4, 0x3368, N, N, N),
+ PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, RSVD3, RSVD4, 0x336c, N, N, N),
+ PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, RSVD3, RSVD4, 0x3370, N, N, N),
+ PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, RSVD3, RSVD4, 0x3374, N, N, N),
+ PINGROUP(gpio_x4_aud_px4, RSVD1, SPI1, SPI2, DAP2, 0x3378, N, N, N),
+ PINGROUP(gpio_x5_aud_px5, RSVD1, SPI1, SPI2, RSVD4, 0x337c, N, N, N),
+ PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, RSVD4, 0x3380, N, N, N),
+ PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N),
+ PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N),
+ PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N),
+ PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N),
+ PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N),
+ PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N),
+ PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N),
+ PINGROUP(hdmi_cec_pee3, CEC, SDMMC3, RSVD3, SOC, 0x33e0, Y, N, N),
+ PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N),
+ PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N),
+ PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N),
+ PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N),
+ PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N),
+ PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N),
+ PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N),
+ PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N),
+ PINGROUP(gmi_clk_lb, SDMMC2, NAND, GMI, RSVD4, 0x3404, N, N, N),
+ PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N),
+
+ /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
+ DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(at1, 0x870, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
+ DRV_PINGROUP(at2, 0x874, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
+ DRV_PINGROUP(at3, 0x878, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
+ DRV_PINGROUP(at4, 0x87c, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
+ DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
+ DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
+ DRV_PINGROUP(ddc, 0x8fc, 2, 3, -1, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(gma, 0x900, 2, 3, -1, 14, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, Y),
+ DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(ao3, 0x9a0, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
+ DRV_PINGROUP(hv0, 0x9a4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
+ DRV_PINGROUP(sdio4, 0x9a8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(ao0, 0x9ac, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+};
+
+static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {
+ .ngpios = NUM_GPIOS,
+ .pins = tegra114_pins,
+ .npins = ARRAY_SIZE(tegra114_pins),
+ .functions = tegra114_functions,
+ .nfunctions = ARRAY_SIZE(tegra114_functions),
+ .groups = tegra114_groups,
+ .ngroups = ARRAY_SIZE(tegra114_groups),
+ .hsm_in_mux = false,
+ .schmitt_in_mux = false,
+ .drvtype_in_mux = false,
+};
+
+static int tegra114_pinctrl_probe(struct platform_device *pdev)
+{
+ return tegra_pinctrl_probe(pdev, &tegra114_pinctrl);
+}
+
+static const struct of_device_id tegra114_pinctrl_of_match[] = {
+ { .compatible = "nvidia,tegra114-pinmux", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, tegra114_pinctrl_of_match);
+
+static struct platform_driver tegra114_pinctrl_driver = {
+ .driver = {
+ .name = "tegra114-pinctrl",
+ .of_match_table = tegra114_pinctrl_of_match,
+ },
+ .probe = tegra114_pinctrl_probe,
+ .remove = tegra_pinctrl_remove,
+};
+module_platform_driver(tegra114_pinctrl_driver);
+
+MODULE_AUTHOR("Pritesh Raithatha <praithatha@nvidia.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra114 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * Pinctrl data for the NVIDIA Tegra124 pinmux
+ *
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "pinctrl-tegra.h"
+
+/*
+ * Most pins affected by the pinmux can also be GPIOs. Define these first.
+ * These must match how the GPIO driver names/numbers its pins.
+ */
+#define _GPIO(offset) (offset)
+
+#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
+#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
+#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
+#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
+#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
+#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
+#define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
+#define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
+#define TEGRA_PIN_PB0 _GPIO(8)
+#define TEGRA_PIN_PB1 _GPIO(9)
+#define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
+#define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
+#define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
+#define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
+#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
+#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
+#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
+#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
+#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
+#define TEGRA_PIN_PC7 _GPIO(23)
+#define TEGRA_PIN_PG0 _GPIO(48)
+#define TEGRA_PIN_PG1 _GPIO(49)
+#define TEGRA_PIN_PG2 _GPIO(50)
+#define TEGRA_PIN_PG3 _GPIO(51)
+#define TEGRA_PIN_PG4 _GPIO(52)
+#define TEGRA_PIN_PG5 _GPIO(53)
+#define TEGRA_PIN_PG6 _GPIO(54)
+#define TEGRA_PIN_PG7 _GPIO(55)
+#define TEGRA_PIN_PH0 _GPIO(56)
+#define TEGRA_PIN_PH1 _GPIO(57)
+#define TEGRA_PIN_PH2 _GPIO(58)
+#define TEGRA_PIN_PH3 _GPIO(59)
+#define TEGRA_PIN_PH4 _GPIO(60)
+#define TEGRA_PIN_PH5 _GPIO(61)
+#define TEGRA_PIN_PH6 _GPIO(62)
+#define TEGRA_PIN_PH7 _GPIO(63)
+#define TEGRA_PIN_PI0 _GPIO(64)
+#define TEGRA_PIN_PI1 _GPIO(65)
+#define TEGRA_PIN_PI2 _GPIO(66)
+#define TEGRA_PIN_PI3 _GPIO(67)
+#define TEGRA_PIN_PI4 _GPIO(68)
+#define TEGRA_PIN_PI5 _GPIO(69)
+#define TEGRA_PIN_PI6 _GPIO(70)
+#define TEGRA_PIN_PI7 _GPIO(71)
+#define TEGRA_PIN_PJ0 _GPIO(72)
+#define TEGRA_PIN_PJ2 _GPIO(74)
+#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
+#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
+#define TEGRA_PIN_PJ7 _GPIO(79)
+#define TEGRA_PIN_PK0 _GPIO(80)
+#define TEGRA_PIN_PK1 _GPIO(81)
+#define TEGRA_PIN_PK2 _GPIO(82)
+#define TEGRA_PIN_PK3 _GPIO(83)
+#define TEGRA_PIN_PK4 _GPIO(84)
+#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
+#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
+#define TEGRA_PIN_PK7 _GPIO(87)
+#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
+#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
+#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
+#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
+#define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108)
+#define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109)
+#define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
+#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
+#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
+#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
+#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
+#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
+#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
+#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
+#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
+#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
+#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
+#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
+#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
+#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
+#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
+#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
+#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
+#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
+#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
+#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
+#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
+#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
+#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
+#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
+#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
+#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
+#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
+#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
+#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
+#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
+#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
+#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
+#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
+#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
+#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
+#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
+#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
+#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
+#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
+#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
+#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
+#define TEGRA_PIN_KB_ROW16_PT0 _GPIO(152)
+#define TEGRA_PIN_KB_ROW17_PT1 _GPIO(153)
+#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
+#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
+#define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
+#define TEGRA_PIN_PU0 _GPIO(160)
+#define TEGRA_PIN_PU1 _GPIO(161)
+#define TEGRA_PIN_PU2 _GPIO(162)
+#define TEGRA_PIN_PU3 _GPIO(163)
+#define TEGRA_PIN_PU4 _GPIO(164)
+#define TEGRA_PIN_PU5 _GPIO(165)
+#define TEGRA_PIN_PU6 _GPIO(166)
+#define TEGRA_PIN_PV0 _GPIO(168)
+#define TEGRA_PIN_PV1 _GPIO(169)
+#define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170)
+#define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171)
+#define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
+#define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
+#define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178)
+#define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179)
+#define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
+#define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
+#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
+#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
+#define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184)
+#define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185)
+#define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186)
+#define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187)
+#define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188)
+#define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189)
+#define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190)
+#define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191)
+#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
+#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
+#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
+#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
+#define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
+#define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
+#define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
+#define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
+#define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
+#define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
+#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
+#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
+#define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
+#define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
+#define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
+#define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
+#define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
+#define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
+#define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
+#define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
+#define TEGRA_PIN_PBB0 _GPIO(216)
+#define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
+#define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
+#define TEGRA_PIN_PBB3 _GPIO(219)
+#define TEGRA_PIN_PBB4 _GPIO(220)
+#define TEGRA_PIN_PBB5 _GPIO(221)
+#define TEGRA_PIN_PBB6 _GPIO(222)
+#define TEGRA_PIN_PBB7 _GPIO(223)
+#define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
+#define TEGRA_PIN_PCC1 _GPIO(225)
+#define TEGRA_PIN_PCC2 _GPIO(226)
+#define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
+#define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
+#define TEGRA_PIN_PEX_L0_RST_N_PDD1 _GPIO(233)
+#define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2 _GPIO(234)
+#define TEGRA_PIN_PEX_WAKE_N_PDD3 _GPIO(235)
+#define TEGRA_PIN_PEX_L1_RST_N_PDD5 _GPIO(237)
+#define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6 _GPIO(238)
+#define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
+#define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
+#define TEGRA_PIN_DAP_MCLK1_REQ_PEE2 _GPIO(242)
+#define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
+#define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244)
+#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
+#define TEGRA_PIN_DP_HPD_PFF0 _GPIO(248)
+#define TEGRA_PIN_USB_VBUS_EN2_PFF1 _GPIO(249)
+#define TEGRA_PIN_PFF2 _GPIO(250)
+
+/* All non-GPIO pins follow */
+#define NUM_GPIOS (TEGRA_PIN_PFF2 + 1)
+#define _PIN(offset) (NUM_GPIOS + (offset))
+
+/* Non-GPIO pins */
+#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
+#define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
+#define TEGRA_PIN_PWR_INT_N _PIN(2)
+#define TEGRA_PIN_GMI_CLK_LB _PIN(3)
+#define TEGRA_PIN_RESET_OUT_N _PIN(4)
+#define TEGRA_PIN_OWR _PIN(5)
+#define TEGRA_PIN_CLK_32K_IN _PIN(6)
+#define TEGRA_PIN_JTAG_RTCK _PIN(7)
+#define TEGRA_PIN_DSI_B_CLK_P _PIN(8)
+#define TEGRA_PIN_DSI_B_CLK_N _PIN(9)
+#define TEGRA_PIN_DSI_B_D0_P _PIN(10)
+#define TEGRA_PIN_DSI_B_D0_N _PIN(11)
+#define TEGRA_PIN_DSI_B_D1_P _PIN(12)
+#define TEGRA_PIN_DSI_B_D1_N _PIN(13)
+#define TEGRA_PIN_DSI_B_D2_P _PIN(14)
+#define TEGRA_PIN_DSI_B_D2_N _PIN(15)
+#define TEGRA_PIN_DSI_B_D3_P _PIN(16)
+#define TEGRA_PIN_DSI_B_D3_N _PIN(17)
+
+static const struct pinctrl_pin_desc tegra124_pins[] = {
+ PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
+ PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"),
+ PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
+ PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
+ PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
+ PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"),
+ PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"),
+ PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"),
+ PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"),
+ PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"),
+ PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"),
+ PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"),
+ PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"),
+ PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"),
+ PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"),
+ PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"),
+ PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"),
+ PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"),
+ PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"),
+ PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"),
+ PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
+ PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"),
+ PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"),
+ PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"),
+ PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"),
+ PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"),
+ PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"),
+ PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"),
+ PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"),
+ PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"),
+ PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"),
+ PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
+ PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"),
+ PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
+ PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
+ PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
+ PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
+ PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
+ PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
+ PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
+ PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
+ PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
+ PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
+ PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW16 PT0"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW17 PT1"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
+ PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
+ PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
+ PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
+ PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
+ PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
+ PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
+ PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
+ PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
+ PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
+ PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
+ PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
+ PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
+ PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
+ PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
+ PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
+ PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
+ PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
+ PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
+ PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
+ PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
+ PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
+ PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
+ PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
+ PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
+ PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
+ PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"),
+ PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
+ PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
+ PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
+ PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
+ PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
+ PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
+ PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
+ PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
+ PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"),
+};
+
+static const unsigned clk_32k_out_pa0_pins[] = {
+ TEGRA_PIN_CLK_32K_OUT_PA0,
+};
+
+static const unsigned uart3_cts_n_pa1_pins[] = {
+ TEGRA_PIN_UART3_CTS_N_PA1,
+};
+
+static const unsigned dap2_fs_pa2_pins[] = {
+ TEGRA_PIN_DAP2_FS_PA2,
+};
+
+static const unsigned dap2_sclk_pa3_pins[] = {
+ TEGRA_PIN_DAP2_SCLK_PA3,
+};
+
+static const unsigned dap2_din_pa4_pins[] = {
+ TEGRA_PIN_DAP2_DIN_PA4,
+};
+
+static const unsigned dap2_dout_pa5_pins[] = {
+ TEGRA_PIN_DAP2_DOUT_PA5,
+};
+
+static const unsigned sdmmc3_clk_pa6_pins[] = {
+ TEGRA_PIN_SDMMC3_CLK_PA6,
+};
+
+static const unsigned sdmmc3_cmd_pa7_pins[] = {
+ TEGRA_PIN_SDMMC3_CMD_PA7,
+};
+
+static const unsigned pb0_pins[] = {
+ TEGRA_PIN_PB0,
+};
+
+static const unsigned pb1_pins[] = {
+ TEGRA_PIN_PB1,
+};
+
+static const unsigned sdmmc3_dat3_pb4_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT3_PB4,
+};
+
+static const unsigned sdmmc3_dat2_pb5_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT2_PB5,
+};
+
+static const unsigned sdmmc3_dat1_pb6_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT1_PB6,
+};
+
+static const unsigned sdmmc3_dat0_pb7_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT0_PB7,
+};
+
+static const unsigned uart3_rts_n_pc0_pins[] = {
+ TEGRA_PIN_UART3_RTS_N_PC0,
+};
+
+static const unsigned uart2_txd_pc2_pins[] = {
+ TEGRA_PIN_UART2_TXD_PC2,
+};
+
+static const unsigned uart2_rxd_pc3_pins[] = {
+ TEGRA_PIN_UART2_RXD_PC3,
+};
+
+static const unsigned gen1_i2c_scl_pc4_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SCL_PC4,
+};
+
+static const unsigned gen1_i2c_sda_pc5_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SDA_PC5,
+};
+
+static const unsigned pc7_pins[] = {
+ TEGRA_PIN_PC7,
+};
+
+static const unsigned pg0_pins[] = {
+ TEGRA_PIN_PG0,
+};
+
+static const unsigned pg1_pins[] = {
+ TEGRA_PIN_PG1,
+};
+
+static const unsigned pg2_pins[] = {
+ TEGRA_PIN_PG2,
+};
+
+static const unsigned pg3_pins[] = {
+ TEGRA_PIN_PG3,
+};
+
+static const unsigned pg4_pins[] = {
+ TEGRA_PIN_PG4,
+};
+
+static const unsigned pg5_pins[] = {
+ TEGRA_PIN_PG5,
+};
+
+static const unsigned pg6_pins[] = {
+ TEGRA_PIN_PG6,
+};
+
+static const unsigned pg7_pins[] = {
+ TEGRA_PIN_PG7,
+};
+
+static const unsigned ph0_pins[] = {
+ TEGRA_PIN_PH0,
+};
+
+static const unsigned ph1_pins[] = {
+ TEGRA_PIN_PH1,
+};
+
+static const unsigned ph2_pins[] = {
+ TEGRA_PIN_PH2,
+};
+
+static const unsigned ph3_pins[] = {
+ TEGRA_PIN_PH3,
+};
+
+static const unsigned ph4_pins[] = {
+ TEGRA_PIN_PH4,
+};
+
+static const unsigned ph5_pins[] = {
+ TEGRA_PIN_PH5,
+};
+
+static const unsigned ph6_pins[] = {
+ TEGRA_PIN_PH6,
+};
+
+static const unsigned ph7_pins[] = {
+ TEGRA_PIN_PH7,
+};
+
+static const unsigned pi0_pins[] = {
+ TEGRA_PIN_PI0,
+};
+
+static const unsigned pi1_pins[] = {
+ TEGRA_PIN_PI1,
+};
+
+static const unsigned pi2_pins[] = {
+ TEGRA_PIN_PI2,
+};
+
+static const unsigned pi3_pins[] = {
+ TEGRA_PIN_PI3,
+};
+
+static const unsigned pi4_pins[] = {
+ TEGRA_PIN_PI4,
+};
+
+static const unsigned pi5_pins[] = {
+ TEGRA_PIN_PI5,
+};
+
+static const unsigned pi6_pins[] = {
+ TEGRA_PIN_PI6,
+};
+
+static const unsigned pi7_pins[] = {
+ TEGRA_PIN_PI7,
+};
+
+static const unsigned pj0_pins[] = {
+ TEGRA_PIN_PJ0,
+};
+
+static const unsigned pj2_pins[] = {
+ TEGRA_PIN_PJ2,
+};
+
+static const unsigned uart2_cts_n_pj5_pins[] = {
+ TEGRA_PIN_UART2_CTS_N_PJ5,
+};
+
+static const unsigned uart2_rts_n_pj6_pins[] = {
+ TEGRA_PIN_UART2_RTS_N_PJ6,
+};
+
+static const unsigned pj7_pins[] = {
+ TEGRA_PIN_PJ7,
+};
+
+static const unsigned pk0_pins[] = {
+ TEGRA_PIN_PK0,
+};
+
+static const unsigned pk1_pins[] = {
+ TEGRA_PIN_PK1,
+};
+
+static const unsigned pk2_pins[] = {
+ TEGRA_PIN_PK2,
+};
+
+static const unsigned pk3_pins[] = {
+ TEGRA_PIN_PK3,
+};
+
+static const unsigned pk4_pins[] = {
+ TEGRA_PIN_PK4,
+};
+
+static const unsigned spdif_out_pk5_pins[] = {
+ TEGRA_PIN_SPDIF_OUT_PK5,
+};
+
+static const unsigned spdif_in_pk6_pins[] = {
+ TEGRA_PIN_SPDIF_IN_PK6,
+};
+
+static const unsigned pk7_pins[] = {
+ TEGRA_PIN_PK7,
+};
+
+static const unsigned dap1_fs_pn0_pins[] = {
+ TEGRA_PIN_DAP1_FS_PN0,
+};
+
+static const unsigned dap1_din_pn1_pins[] = {
+ TEGRA_PIN_DAP1_DIN_PN1,
+};
+
+static const unsigned dap1_dout_pn2_pins[] = {
+ TEGRA_PIN_DAP1_DOUT_PN2,
+};
+
+static const unsigned dap1_sclk_pn3_pins[] = {
+ TEGRA_PIN_DAP1_SCLK_PN3,
+};
+
+static const unsigned usb_vbus_en0_pn4_pins[] = {
+ TEGRA_PIN_USB_VBUS_EN0_PN4,
+};
+
+static const unsigned usb_vbus_en1_pn5_pins[] = {
+ TEGRA_PIN_USB_VBUS_EN1_PN5,
+};
+
+static const unsigned hdmi_int_pn7_pins[] = {
+ TEGRA_PIN_HDMI_INT_PN7,
+};
+
+static const unsigned ulpi_data7_po0_pins[] = {
+ TEGRA_PIN_ULPI_DATA7_PO0,
+};
+
+static const unsigned ulpi_data0_po1_pins[] = {
+ TEGRA_PIN_ULPI_DATA0_PO1,
+};
+
+static const unsigned ulpi_data1_po2_pins[] = {
+ TEGRA_PIN_ULPI_DATA1_PO2,
+};
+
+static const unsigned ulpi_data2_po3_pins[] = {
+ TEGRA_PIN_ULPI_DATA2_PO3,
+};
+
+static const unsigned ulpi_data3_po4_pins[] = {
+ TEGRA_PIN_ULPI_DATA3_PO4,
+};
+
+static const unsigned ulpi_data4_po5_pins[] = {
+ TEGRA_PIN_ULPI_DATA4_PO5,
+};
+
+static const unsigned ulpi_data5_po6_pins[] = {
+ TEGRA_PIN_ULPI_DATA5_PO6,
+};
+
+static const unsigned ulpi_data6_po7_pins[] = {
+ TEGRA_PIN_ULPI_DATA6_PO7,
+};
+
+static const unsigned dap3_fs_pp0_pins[] = {
+ TEGRA_PIN_DAP3_FS_PP0,
+};
+
+static const unsigned dap3_din_pp1_pins[] = {
+ TEGRA_PIN_DAP3_DIN_PP1,
+};
+
+static const unsigned dap3_dout_pp2_pins[] = {
+ TEGRA_PIN_DAP3_DOUT_PP2,
+};
+
+static const unsigned dap3_sclk_pp3_pins[] = {
+ TEGRA_PIN_DAP3_SCLK_PP3,
+};
+
+static const unsigned dap4_fs_pp4_pins[] = {
+ TEGRA_PIN_DAP4_FS_PP4,
+};
+
+static const unsigned dap4_din_pp5_pins[] = {
+ TEGRA_PIN_DAP4_DIN_PP5,
+};
+
+static const unsigned dap4_dout_pp6_pins[] = {
+ TEGRA_PIN_DAP4_DOUT_PP6,
+};
+
+static const unsigned dap4_sclk_pp7_pins[] = {
+ TEGRA_PIN_DAP4_SCLK_PP7,
+};
+
+static const unsigned kb_col0_pq0_pins[] = {
+ TEGRA_PIN_KB_COL0_PQ0,
+};
+
+static const unsigned kb_col1_pq1_pins[] = {
+ TEGRA_PIN_KB_COL1_PQ1,
+};
+
+static const unsigned kb_col2_pq2_pins[] = {
+ TEGRA_PIN_KB_COL2_PQ2,
+};
+
+static const unsigned kb_col3_pq3_pins[] = {
+ TEGRA_PIN_KB_COL3_PQ3,
+};
+
+static const unsigned kb_col4_pq4_pins[] = {
+ TEGRA_PIN_KB_COL4_PQ4,
+};
+
+static const unsigned kb_col5_pq5_pins[] = {
+ TEGRA_PIN_KB_COL5_PQ5,
+};
+
+static const unsigned kb_col6_pq6_pins[] = {
+ TEGRA_PIN_KB_COL6_PQ6,
+};
+
+static const unsigned kb_col7_pq7_pins[] = {
+ TEGRA_PIN_KB_COL7_PQ7,
+};
+
+static const unsigned kb_row0_pr0_pins[] = {
+ TEGRA_PIN_KB_ROW0_PR0,
+};
+
+static const unsigned kb_row1_pr1_pins[] = {
+ TEGRA_PIN_KB_ROW1_PR1,
+};
+
+static const unsigned kb_row2_pr2_pins[] = {
+ TEGRA_PIN_KB_ROW2_PR2,
+};
+
+static const unsigned kb_row3_pr3_pins[] = {
+ TEGRA_PIN_KB_ROW3_PR3,
+};
+
+static const unsigned kb_row4_pr4_pins[] = {
+ TEGRA_PIN_KB_ROW4_PR4,
+};
+
+static const unsigned kb_row5_pr5_pins[] = {
+ TEGRA_PIN_KB_ROW5_PR5,
+};
+
+static const unsigned kb_row6_pr6_pins[] = {
+ TEGRA_PIN_KB_ROW6_PR6,
+};
+
+static const unsigned kb_row7_pr7_pins[] = {
+ TEGRA_PIN_KB_ROW7_PR7,
+};
+
+static const unsigned kb_row8_ps0_pins[] = {
+ TEGRA_PIN_KB_ROW8_PS0,
+};
+
+static const unsigned kb_row9_ps1_pins[] = {
+ TEGRA_PIN_KB_ROW9_PS1,
+};
+
+static const unsigned kb_row10_ps2_pins[] = {
+ TEGRA_PIN_KB_ROW10_PS2,
+};
+
+static const unsigned kb_row11_ps3_pins[] = {
+ TEGRA_PIN_KB_ROW11_PS3,
+};
+
+static const unsigned kb_row12_ps4_pins[] = {
+ TEGRA_PIN_KB_ROW12_PS4,
+};
+
+static const unsigned kb_row13_ps5_pins[] = {
+ TEGRA_PIN_KB_ROW13_PS5,
+};
+
+static const unsigned kb_row14_ps6_pins[] = {
+ TEGRA_PIN_KB_ROW14_PS6,
+};
+
+static const unsigned kb_row15_ps7_pins[] = {
+ TEGRA_PIN_KB_ROW15_PS7,
+};
+
+static const unsigned kb_row16_pt0_pins[] = {
+ TEGRA_PIN_KB_ROW16_PT0,
+};
+
+static const unsigned kb_row17_pt1_pins[] = {
+ TEGRA_PIN_KB_ROW17_PT1,
+};
+
+static const unsigned gen2_i2c_scl_pt5_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SCL_PT5,
+};
+
+static const unsigned gen2_i2c_sda_pt6_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SDA_PT6,
+};
+
+static const unsigned sdmmc4_cmd_pt7_pins[] = {
+ TEGRA_PIN_SDMMC4_CMD_PT7,
+};
+
+static const unsigned pu0_pins[] = {
+ TEGRA_PIN_PU0,
+};
+
+static const unsigned pu1_pins[] = {
+ TEGRA_PIN_PU1,
+};
+
+static const unsigned pu2_pins[] = {
+ TEGRA_PIN_PU2,
+};
+
+static const unsigned pu3_pins[] = {
+ TEGRA_PIN_PU3,
+};
+
+static const unsigned pu4_pins[] = {
+ TEGRA_PIN_PU4,
+};
+
+static const unsigned pu5_pins[] = {
+ TEGRA_PIN_PU5,
+};
+
+static const unsigned pu6_pins[] = {
+ TEGRA_PIN_PU6,
+};
+
+static const unsigned pv0_pins[] = {
+ TEGRA_PIN_PV0,
+};
+
+static const unsigned pv1_pins[] = {
+ TEGRA_PIN_PV1,
+};
+
+static const unsigned sdmmc3_cd_n_pv2_pins[] = {
+ TEGRA_PIN_SDMMC3_CD_N_PV2,
+};
+
+static const unsigned sdmmc1_wp_n_pv3_pins[] = {
+ TEGRA_PIN_SDMMC1_WP_N_PV3,
+};
+
+static const unsigned ddc_scl_pv4_pins[] = {
+ TEGRA_PIN_DDC_SCL_PV4,
+};
+
+static const unsigned ddc_sda_pv5_pins[] = {
+ TEGRA_PIN_DDC_SDA_PV5,
+};
+
+static const unsigned gpio_w2_aud_pw2_pins[] = {
+ TEGRA_PIN_GPIO_W2_AUD_PW2,
+};
+
+static const unsigned gpio_w3_aud_pw3_pins[] = {
+ TEGRA_PIN_GPIO_W3_AUD_PW3,
+};
+
+static const unsigned dap_mclk1_pw4_pins[] = {
+ TEGRA_PIN_DAP_MCLK1_PW4,
+};
+
+static const unsigned clk2_out_pw5_pins[] = {
+ TEGRA_PIN_CLK2_OUT_PW5,
+};
+
+static const unsigned uart3_txd_pw6_pins[] = {
+ TEGRA_PIN_UART3_TXD_PW6,
+};
+
+static const unsigned uart3_rxd_pw7_pins[] = {
+ TEGRA_PIN_UART3_RXD_PW7,
+};
+
+static const unsigned dvfs_pwm_px0_pins[] = {
+ TEGRA_PIN_DVFS_PWM_PX0,
+};
+
+static const unsigned gpio_x1_aud_px1_pins[] = {
+ TEGRA_PIN_GPIO_X1_AUD_PX1,
+};
+
+static const unsigned dvfs_clk_px2_pins[] = {
+ TEGRA_PIN_DVFS_CLK_PX2,
+};
+
+static const unsigned gpio_x3_aud_px3_pins[] = {
+ TEGRA_PIN_GPIO_X3_AUD_PX3,
+};
+
+static const unsigned gpio_x4_aud_px4_pins[] = {
+ TEGRA_PIN_GPIO_X4_AUD_PX4,
+};
+
+static const unsigned gpio_x5_aud_px5_pins[] = {
+ TEGRA_PIN_GPIO_X5_AUD_PX5,
+};
+
+static const unsigned gpio_x6_aud_px6_pins[] = {
+ TEGRA_PIN_GPIO_X6_AUD_PX6,
+};
+
+static const unsigned gpio_x7_aud_px7_pins[] = {
+ TEGRA_PIN_GPIO_X7_AUD_PX7,
+};
+
+static const unsigned ulpi_clk_py0_pins[] = {
+ TEGRA_PIN_ULPI_CLK_PY0,
+};
+
+static const unsigned ulpi_dir_py1_pins[] = {
+ TEGRA_PIN_ULPI_DIR_PY1,
+};
+
+static const unsigned ulpi_nxt_py2_pins[] = {
+ TEGRA_PIN_ULPI_NXT_PY2,
+};
+
+static const unsigned ulpi_stp_py3_pins[] = {
+ TEGRA_PIN_ULPI_STP_PY3,
+};
+
+static const unsigned sdmmc1_dat3_py4_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT3_PY4,
+};
+
+static const unsigned sdmmc1_dat2_py5_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT2_PY5,
+};
+
+static const unsigned sdmmc1_dat1_py6_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT1_PY6,
+};
+
+static const unsigned sdmmc1_dat0_py7_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT0_PY7,
+};
+
+static const unsigned sdmmc1_clk_pz0_pins[] = {
+ TEGRA_PIN_SDMMC1_CLK_PZ0,
+};
+
+static const unsigned sdmmc1_cmd_pz1_pins[] = {
+ TEGRA_PIN_SDMMC1_CMD_PZ1,
+};
+
+static const unsigned pwr_i2c_scl_pz6_pins[] = {
+ TEGRA_PIN_PWR_I2C_SCL_PZ6,
+};
+
+static const unsigned pwr_i2c_sda_pz7_pins[] = {
+ TEGRA_PIN_PWR_I2C_SDA_PZ7,
+};
+
+static const unsigned sdmmc4_dat0_paa0_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT0_PAA0,
+};
+
+static const unsigned sdmmc4_dat1_paa1_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT1_PAA1,
+};
+
+static const unsigned sdmmc4_dat2_paa2_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT2_PAA2,
+};
+
+static const unsigned sdmmc4_dat3_paa3_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT3_PAA3,
+};
+
+static const unsigned sdmmc4_dat4_paa4_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT4_PAA4,
+};
+
+static const unsigned sdmmc4_dat5_paa5_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT5_PAA5,
+};
+
+static const unsigned sdmmc4_dat6_paa6_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT6_PAA6,
+};
+
+static const unsigned sdmmc4_dat7_paa7_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT7_PAA7,
+};
+
+static const unsigned pbb0_pins[] = {
+ TEGRA_PIN_PBB0,
+};
+
+static const unsigned cam_i2c_scl_pbb1_pins[] = {
+ TEGRA_PIN_CAM_I2C_SCL_PBB1,
+};
+
+static const unsigned cam_i2c_sda_pbb2_pins[] = {
+ TEGRA_PIN_CAM_I2C_SDA_PBB2,
+};
+
+static const unsigned pbb3_pins[] = {
+ TEGRA_PIN_PBB3,
+};
+
+static const unsigned pbb4_pins[] = {
+ TEGRA_PIN_PBB4,
+};
+
+static const unsigned pbb5_pins[] = {
+ TEGRA_PIN_PBB5,
+};
+
+static const unsigned pbb6_pins[] = {
+ TEGRA_PIN_PBB6,
+};
+
+static const unsigned pbb7_pins[] = {
+ TEGRA_PIN_PBB7,
+};
+
+static const unsigned cam_mclk_pcc0_pins[] = {
+ TEGRA_PIN_CAM_MCLK_PCC0,
+};
+
+static const unsigned pcc1_pins[] = {
+ TEGRA_PIN_PCC1,
+};
+
+static const unsigned pcc2_pins[] = {
+ TEGRA_PIN_PCC2,
+};
+
+static const unsigned sdmmc4_clk_pcc4_pins[] = {
+ TEGRA_PIN_SDMMC4_CLK_PCC4,
+};
+
+static const unsigned clk2_req_pcc5_pins[] = {
+ TEGRA_PIN_CLK2_REQ_PCC5,
+};
+
+static const unsigned pex_l0_rst_n_pdd1_pins[] = {
+ TEGRA_PIN_PEX_L0_RST_N_PDD1,
+};
+
+static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
+ TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
+};
+
+static const unsigned pex_wake_n_pdd3_pins[] = {
+ TEGRA_PIN_PEX_WAKE_N_PDD3,
+};
+
+static const unsigned pex_l1_rst_n_pdd5_pins[] = {
+ TEGRA_PIN_PEX_L1_RST_N_PDD5,
+};
+
+static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
+ TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
+};
+
+static const unsigned clk3_out_pee0_pins[] = {
+ TEGRA_PIN_CLK3_OUT_PEE0,
+};
+
+static const unsigned clk3_req_pee1_pins[] = {
+ TEGRA_PIN_CLK3_REQ_PEE1,
+};
+
+static const unsigned dap_mclk1_req_pee2_pins[] = {
+ TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
+};
+
+static const unsigned hdmi_cec_pee3_pins[] = {
+ TEGRA_PIN_HDMI_CEC_PEE3,
+};
+
+static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
+ TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
+};
+
+static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
+ TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
+};
+
+static const unsigned dp_hpd_pff0_pins[] = {
+ TEGRA_PIN_DP_HPD_PFF0,
+};
+
+static const unsigned usb_vbus_en2_pff1_pins[] = {
+ TEGRA_PIN_USB_VBUS_EN2_PFF1,
+};
+
+static const unsigned pff2_pins[] = {
+ TEGRA_PIN_PFF2,
+};
+
+static const unsigned core_pwr_req_pins[] = {
+ TEGRA_PIN_CORE_PWR_REQ,
+};
+
+static const unsigned cpu_pwr_req_pins[] = {
+ TEGRA_PIN_CPU_PWR_REQ,
+};
+
+static const unsigned pwr_int_n_pins[] = {
+ TEGRA_PIN_PWR_INT_N,
+};
+
+static const unsigned gmi_clk_lb_pins[] = {
+ TEGRA_PIN_GMI_CLK_LB,
+};
+
+static const unsigned reset_out_n_pins[] = {
+ TEGRA_PIN_RESET_OUT_N,
+};
+
+static const unsigned owr_pins[] = {
+ TEGRA_PIN_OWR,
+};
+
+static const unsigned clk_32k_in_pins[] = {
+ TEGRA_PIN_CLK_32K_IN,
+};
+
+static const unsigned jtag_rtck_pins[] = {
+ TEGRA_PIN_JTAG_RTCK,
+};
+
+static const unsigned drive_ao1_pins[] = {
+ TEGRA_PIN_KB_ROW0_PR0,
+ TEGRA_PIN_KB_ROW1_PR1,
+ TEGRA_PIN_KB_ROW2_PR2,
+ TEGRA_PIN_KB_ROW3_PR3,
+ TEGRA_PIN_KB_ROW4_PR4,
+ TEGRA_PIN_KB_ROW5_PR5,
+ TEGRA_PIN_KB_ROW6_PR6,
+ TEGRA_PIN_KB_ROW7_PR7,
+ TEGRA_PIN_PWR_I2C_SCL_PZ6,
+ TEGRA_PIN_PWR_I2C_SDA_PZ7,
+};
+
+static const unsigned drive_ao2_pins[] = {
+ TEGRA_PIN_CLK_32K_OUT_PA0,
+ TEGRA_PIN_CLK_32K_IN,
+ TEGRA_PIN_KB_COL0_PQ0,
+ TEGRA_PIN_KB_COL1_PQ1,
+ TEGRA_PIN_KB_COL2_PQ2,
+ TEGRA_PIN_KB_COL3_PQ3,
+ TEGRA_PIN_KB_COL4_PQ4,
+ TEGRA_PIN_KB_COL5_PQ5,
+ TEGRA_PIN_KB_COL6_PQ6,
+ TEGRA_PIN_KB_COL7_PQ7,
+ TEGRA_PIN_KB_ROW8_PS0,
+ TEGRA_PIN_KB_ROW9_PS1,
+ TEGRA_PIN_KB_ROW10_PS2,
+ TEGRA_PIN_KB_ROW11_PS3,
+ TEGRA_PIN_KB_ROW12_PS4,
+ TEGRA_PIN_KB_ROW13_PS5,
+ TEGRA_PIN_KB_ROW14_PS6,
+ TEGRA_PIN_KB_ROW15_PS7,
+ TEGRA_PIN_KB_ROW16_PT0,
+ TEGRA_PIN_KB_ROW17_PT1,
+ TEGRA_PIN_SDMMC3_CD_N_PV2,
+ TEGRA_PIN_CORE_PWR_REQ,
+ TEGRA_PIN_CPU_PWR_REQ,
+ TEGRA_PIN_PWR_INT_N,
+};
+
+static const unsigned drive_at1_pins[] = {
+ TEGRA_PIN_PH0,
+ TEGRA_PIN_PH1,
+ TEGRA_PIN_PH2,
+ TEGRA_PIN_PH3,
+};
+
+static const unsigned drive_at2_pins[] = {
+ TEGRA_PIN_PG0,
+ TEGRA_PIN_PG1,
+ TEGRA_PIN_PG2,
+ TEGRA_PIN_PG3,
+ TEGRA_PIN_PG4,
+ TEGRA_PIN_PG5,
+ TEGRA_PIN_PG6,
+ TEGRA_PIN_PG7,
+ TEGRA_PIN_PI0,
+ TEGRA_PIN_PI1,
+ TEGRA_PIN_PI3,
+ TEGRA_PIN_PI4,
+ TEGRA_PIN_PI7,
+ TEGRA_PIN_PK0,
+ TEGRA_PIN_PK2,
+};
+
+static const unsigned drive_at3_pins[] = {
+ TEGRA_PIN_PC7,
+ TEGRA_PIN_PJ0,
+};
+
+static const unsigned drive_at4_pins[] = {
+ TEGRA_PIN_PB0,
+ TEGRA_PIN_PB1,
+ TEGRA_PIN_PJ0,
+ TEGRA_PIN_PJ7,
+ TEGRA_PIN_PK7,
+};
+
+static const unsigned drive_at5_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SCL_PT5,
+ TEGRA_PIN_GEN2_I2C_SDA_PT6,
+};
+
+static const unsigned drive_cdev1_pins[] = {
+ TEGRA_PIN_DAP_MCLK1_PW4,
+ TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
+};
+
+static const unsigned drive_cdev2_pins[] = {
+ TEGRA_PIN_CLK2_OUT_PW5,
+ TEGRA_PIN_CLK2_REQ_PCC5,
+};
+
+static const unsigned drive_dap1_pins[] = {
+ TEGRA_PIN_DAP1_FS_PN0,
+ TEGRA_PIN_DAP1_DIN_PN1,
+ TEGRA_PIN_DAP1_DOUT_PN2,
+ TEGRA_PIN_DAP1_SCLK_PN3,
+};
+
+static const unsigned drive_dap2_pins[] = {
+ TEGRA_PIN_DAP2_FS_PA2,
+ TEGRA_PIN_DAP2_SCLK_PA3,
+ TEGRA_PIN_DAP2_DIN_PA4,
+ TEGRA_PIN_DAP2_DOUT_PA5,
+};
+
+static const unsigned drive_dap3_pins[] = {
+ TEGRA_PIN_DAP3_FS_PP0,
+ TEGRA_PIN_DAP3_DIN_PP1,
+ TEGRA_PIN_DAP3_DOUT_PP2,
+ TEGRA_PIN_DAP3_SCLK_PP3,
+};
+
+static const unsigned drive_dap4_pins[] = {
+ TEGRA_PIN_DAP4_FS_PP4,
+ TEGRA_PIN_DAP4_DIN_PP5,
+ TEGRA_PIN_DAP4_DOUT_PP6,
+ TEGRA_PIN_DAP4_SCLK_PP7,
+};
+
+static const unsigned drive_dbg_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SCL_PC4,
+ TEGRA_PIN_GEN1_I2C_SDA_PC5,
+ TEGRA_PIN_PU0,
+ TEGRA_PIN_PU1,
+ TEGRA_PIN_PU2,
+ TEGRA_PIN_PU3,
+ TEGRA_PIN_PU4,
+ TEGRA_PIN_PU5,
+ TEGRA_PIN_PU6,
+};
+
+static const unsigned drive_sdio3_pins[] = {
+ TEGRA_PIN_SDMMC3_CLK_PA6,
+ TEGRA_PIN_SDMMC3_CMD_PA7,
+ TEGRA_PIN_SDMMC3_DAT3_PB4,
+ TEGRA_PIN_SDMMC3_DAT2_PB5,
+ TEGRA_PIN_SDMMC3_DAT1_PB6,
+ TEGRA_PIN_SDMMC3_DAT0_PB7,
+ TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
+ TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
+};
+
+static const unsigned drive_spi_pins[] = {
+ TEGRA_PIN_DVFS_PWM_PX0,
+ TEGRA_PIN_GPIO_X1_AUD_PX1,
+ TEGRA_PIN_DVFS_CLK_PX2,
+ TEGRA_PIN_GPIO_X3_AUD_PX3,
+ TEGRA_PIN_GPIO_X4_AUD_PX4,
+ TEGRA_PIN_GPIO_X5_AUD_PX5,
+ TEGRA_PIN_GPIO_X6_AUD_PX6,
+ TEGRA_PIN_GPIO_X7_AUD_PX7,
+ TEGRA_PIN_GPIO_W2_AUD_PW2,
+ TEGRA_PIN_GPIO_W3_AUD_PW3,
+};
+
+static const unsigned drive_uaa_pins[] = {
+ TEGRA_PIN_ULPI_DATA0_PO1,
+ TEGRA_PIN_ULPI_DATA1_PO2,
+ TEGRA_PIN_ULPI_DATA2_PO3,
+ TEGRA_PIN_ULPI_DATA3_PO4,
+};
+
+static const unsigned drive_uab_pins[] = {
+ TEGRA_PIN_ULPI_DATA7_PO0,
+ TEGRA_PIN_ULPI_DATA4_PO5,
+ TEGRA_PIN_ULPI_DATA5_PO6,
+ TEGRA_PIN_ULPI_DATA6_PO7,
+ TEGRA_PIN_PV0,
+ TEGRA_PIN_PV1,
+};
+
+static const unsigned drive_uart2_pins[] = {
+ TEGRA_PIN_UART2_TXD_PC2,
+ TEGRA_PIN_UART2_RXD_PC3,
+ TEGRA_PIN_UART2_CTS_N_PJ5,
+ TEGRA_PIN_UART2_RTS_N_PJ6,
+};
+
+static const unsigned drive_uart3_pins[] = {
+ TEGRA_PIN_UART3_CTS_N_PA1,
+ TEGRA_PIN_UART3_RTS_N_PC0,
+ TEGRA_PIN_UART3_TXD_PW6,
+ TEGRA_PIN_UART3_RXD_PW7,
+};
+
+static const unsigned drive_sdio1_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT3_PY4,
+ TEGRA_PIN_SDMMC1_DAT2_PY5,
+ TEGRA_PIN_SDMMC1_DAT1_PY6,
+ TEGRA_PIN_SDMMC1_DAT0_PY7,
+ TEGRA_PIN_SDMMC1_CLK_PZ0,
+ TEGRA_PIN_SDMMC1_CMD_PZ1,
+};
+
+static const unsigned drive_ddc_pins[] = {
+ TEGRA_PIN_DDC_SCL_PV4,
+ TEGRA_PIN_DDC_SDA_PV5,
+};
+
+static const unsigned drive_gma_pins[] = {
+ TEGRA_PIN_SDMMC4_CLK_PCC4,
+ TEGRA_PIN_SDMMC4_CMD_PT7,
+ TEGRA_PIN_SDMMC4_DAT0_PAA0,
+ TEGRA_PIN_SDMMC4_DAT1_PAA1,
+ TEGRA_PIN_SDMMC4_DAT2_PAA2,
+ TEGRA_PIN_SDMMC4_DAT3_PAA3,
+ TEGRA_PIN_SDMMC4_DAT4_PAA4,
+ TEGRA_PIN_SDMMC4_DAT5_PAA5,
+ TEGRA_PIN_SDMMC4_DAT6_PAA6,
+ TEGRA_PIN_SDMMC4_DAT7_PAA7,
+};
+
+static const unsigned drive_gme_pins[] = {
+ TEGRA_PIN_PBB0,
+ TEGRA_PIN_CAM_I2C_SCL_PBB1,
+ TEGRA_PIN_CAM_I2C_SDA_PBB2,
+ TEGRA_PIN_PBB3,
+ TEGRA_PIN_PCC2,
+};
+
+static const unsigned drive_gmf_pins[] = {
+ TEGRA_PIN_PBB4,
+ TEGRA_PIN_PBB5,
+ TEGRA_PIN_PBB6,
+ TEGRA_PIN_PBB7,
+};
+
+static const unsigned drive_gmg_pins[] = {
+ TEGRA_PIN_CAM_MCLK_PCC0,
+};
+
+static const unsigned drive_gmh_pins[] = {
+ TEGRA_PIN_PCC1,
+};
+
+static const unsigned drive_owr_pins[] = {
+ TEGRA_PIN_SDMMC3_CD_N_PV2,
+ TEGRA_PIN_OWR,
+};
+
+static const unsigned drive_uda_pins[] = {
+ TEGRA_PIN_ULPI_CLK_PY0,
+ TEGRA_PIN_ULPI_DIR_PY1,
+ TEGRA_PIN_ULPI_NXT_PY2,
+ TEGRA_PIN_ULPI_STP_PY3,
+};
+
+static const unsigned drive_gpv_pins[] = {
+ TEGRA_PIN_PEX_L0_RST_N_PDD1,
+ TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
+ TEGRA_PIN_PEX_WAKE_N_PDD3,
+ TEGRA_PIN_PEX_L1_RST_N_PDD5,
+ TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
+ TEGRA_PIN_USB_VBUS_EN2_PFF1,
+ TEGRA_PIN_PFF2,
+};
+
+static const unsigned drive_dev3_pins[] = {
+ TEGRA_PIN_CLK3_OUT_PEE0,
+ TEGRA_PIN_CLK3_REQ_PEE1,
+};
+
+static const unsigned drive_cec_pins[] = {
+ TEGRA_PIN_HDMI_CEC_PEE3,
+};
+
+static const unsigned drive_at6_pins[] = {
+ TEGRA_PIN_PK1,
+ TEGRA_PIN_PK3,
+ TEGRA_PIN_PK4,
+ TEGRA_PIN_PI2,
+ TEGRA_PIN_PI5,
+ TEGRA_PIN_PI6,
+ TEGRA_PIN_PH4,
+ TEGRA_PIN_PH5,
+ TEGRA_PIN_PH6,
+ TEGRA_PIN_PH7,
+};
+
+static const unsigned drive_dap5_pins[] = {
+ TEGRA_PIN_SPDIF_IN_PK6,
+ TEGRA_PIN_SPDIF_OUT_PK5,
+ TEGRA_PIN_DP_HPD_PFF0,
+};
+
+static const unsigned drive_usb_vbus_en_pins[] = {
+ TEGRA_PIN_USB_VBUS_EN0_PN4,
+ TEGRA_PIN_USB_VBUS_EN1_PN5,
+};
+
+static const unsigned drive_ao3_pins[] = {
+ TEGRA_PIN_RESET_OUT_N,
+};
+
+static const unsigned drive_ao0_pins[] = {
+ TEGRA_PIN_JTAG_RTCK,
+};
+
+static const unsigned drive_hv0_pins[] = {
+ TEGRA_PIN_HDMI_INT_PN7,
+};
+
+static const unsigned drive_sdio4_pins[] = {
+ TEGRA_PIN_SDMMC1_WP_N_PV3,
+};
+
+static const unsigned drive_ao4_pins[] = {
+ TEGRA_PIN_JTAG_RTCK,
+};
+
+static const unsigned mipi_pad_ctrl_dsi_b_pins[] = {
+ TEGRA_PIN_DSI_B_CLK_P,
+ TEGRA_PIN_DSI_B_CLK_N,
+ TEGRA_PIN_DSI_B_D0_P,
+ TEGRA_PIN_DSI_B_D0_N,
+ TEGRA_PIN_DSI_B_D1_P,
+ TEGRA_PIN_DSI_B_D1_N,
+ TEGRA_PIN_DSI_B_D2_P,
+ TEGRA_PIN_DSI_B_D2_N,
+ TEGRA_PIN_DSI_B_D3_P,
+ TEGRA_PIN_DSI_B_D3_N,
+};
+
+enum tegra_mux {
+ TEGRA_MUX_BLINK,
+ TEGRA_MUX_CCLA,
+ TEGRA_MUX_CEC,
+ TEGRA_MUX_CLDVFS,
+ TEGRA_MUX_CLK,
+ TEGRA_MUX_CLK12,
+ TEGRA_MUX_CPU,
+ TEGRA_MUX_CSI,
+ TEGRA_MUX_DAP,
+ TEGRA_MUX_DAP1,
+ TEGRA_MUX_DAP2,
+ TEGRA_MUX_DEV3,
+ TEGRA_MUX_DISPLAYA,
+ TEGRA_MUX_DISPLAYA_ALT,
+ TEGRA_MUX_DISPLAYB,
+ TEGRA_MUX_DP,
+ TEGRA_MUX_DSI_B,
+ TEGRA_MUX_DTV,
+ TEGRA_MUX_EXTPERIPH1,
+ TEGRA_MUX_EXTPERIPH2,
+ TEGRA_MUX_EXTPERIPH3,
+ TEGRA_MUX_GMI,
+ TEGRA_MUX_GMI_ALT,
+ TEGRA_MUX_HDA,
+ TEGRA_MUX_HSI,
+ TEGRA_MUX_I2C1,
+ TEGRA_MUX_I2C2,
+ TEGRA_MUX_I2C3,
+ TEGRA_MUX_I2C4,
+ TEGRA_MUX_I2CPWR,
+ TEGRA_MUX_I2S0,
+ TEGRA_MUX_I2S1,
+ TEGRA_MUX_I2S2,
+ TEGRA_MUX_I2S3,
+ TEGRA_MUX_I2S4,
+ TEGRA_MUX_IRDA,
+ TEGRA_MUX_KBC,
+ TEGRA_MUX_OWR,
+ TEGRA_MUX_PE,
+ TEGRA_MUX_PE0,
+ TEGRA_MUX_PE1,
+ TEGRA_MUX_PMI,
+ TEGRA_MUX_PWM0,
+ TEGRA_MUX_PWM1,
+ TEGRA_MUX_PWM2,
+ TEGRA_MUX_PWM3,
+ TEGRA_MUX_PWRON,
+ TEGRA_MUX_RESET_OUT_N,
+ TEGRA_MUX_RSVD1,
+ TEGRA_MUX_RSVD2,
+ TEGRA_MUX_RSVD3,
+ TEGRA_MUX_RSVD4,
+ TEGRA_MUX_RTCK,
+ TEGRA_MUX_SATA,
+ TEGRA_MUX_SDMMC1,
+ TEGRA_MUX_SDMMC2,
+ TEGRA_MUX_SDMMC3,
+ TEGRA_MUX_SDMMC4,
+ TEGRA_MUX_SOC,
+ TEGRA_MUX_SPDIF,
+ TEGRA_MUX_SPI1,
+ TEGRA_MUX_SPI2,
+ TEGRA_MUX_SPI3,
+ TEGRA_MUX_SPI4,
+ TEGRA_MUX_SPI5,
+ TEGRA_MUX_SPI6,
+ TEGRA_MUX_SYS,
+ TEGRA_MUX_TMDS,
+ TEGRA_MUX_TRACE,
+ TEGRA_MUX_UARTA,
+ TEGRA_MUX_UARTB,
+ TEGRA_MUX_UARTC,
+ TEGRA_MUX_UARTD,
+ TEGRA_MUX_ULPI,
+ TEGRA_MUX_USB,
+ TEGRA_MUX_VGP1,
+ TEGRA_MUX_VGP2,
+ TEGRA_MUX_VGP3,
+ TEGRA_MUX_VGP4,
+ TEGRA_MUX_VGP5,
+ TEGRA_MUX_VGP6,
+ TEGRA_MUX_VI,
+ TEGRA_MUX_VI_ALT1,
+ TEGRA_MUX_VI_ALT3,
+ TEGRA_MUX_VIMCLK2,
+ TEGRA_MUX_VIMCLK2_ALT,
+};
+
+#define FUNCTION(fname) \
+ { \
+ .name = #fname, \
+ }
+
+static struct tegra_function tegra124_functions[] = {
+ FUNCTION(blink),
+ FUNCTION(ccla),
+ FUNCTION(cec),
+ FUNCTION(cldvfs),
+ FUNCTION(clk),
+ FUNCTION(clk12),
+ FUNCTION(cpu),
+ FUNCTION(csi),
+ FUNCTION(dap),
+ FUNCTION(dap1),
+ FUNCTION(dap2),
+ FUNCTION(dev3),
+ FUNCTION(displaya),
+ FUNCTION(displaya_alt),
+ FUNCTION(displayb),
+ FUNCTION(dp),
+ FUNCTION(dsi_b),
+ FUNCTION(dtv),
+ FUNCTION(extperiph1),
+ FUNCTION(extperiph2),
+ FUNCTION(extperiph3),
+ FUNCTION(gmi),
+ FUNCTION(gmi_alt),
+ FUNCTION(hda),
+ FUNCTION(hsi),
+ FUNCTION(i2c1),
+ FUNCTION(i2c2),
+ FUNCTION(i2c3),
+ FUNCTION(i2c4),
+ FUNCTION(i2cpwr),
+ FUNCTION(i2s0),
+ FUNCTION(i2s1),
+ FUNCTION(i2s2),
+ FUNCTION(i2s3),
+ FUNCTION(i2s4),
+ FUNCTION(irda),
+ FUNCTION(kbc),
+ FUNCTION(owr),
+ FUNCTION(pe),
+ FUNCTION(pe0),
+ FUNCTION(pe1),
+ FUNCTION(pmi),
+ FUNCTION(pwm0),
+ FUNCTION(pwm1),
+ FUNCTION(pwm2),
+ FUNCTION(pwm3),
+ FUNCTION(pwron),
+ FUNCTION(reset_out_n),
+ FUNCTION(rsvd1),
+ FUNCTION(rsvd2),
+ FUNCTION(rsvd3),
+ FUNCTION(rsvd4),
+ FUNCTION(rtck),
+ FUNCTION(sata),
+ FUNCTION(sdmmc1),
+ FUNCTION(sdmmc2),
+ FUNCTION(sdmmc3),
+ FUNCTION(sdmmc4),
+ FUNCTION(soc),
+ FUNCTION(spdif),
+ FUNCTION(spi1),
+ FUNCTION(spi2),
+ FUNCTION(spi3),
+ FUNCTION(spi4),
+ FUNCTION(spi5),
+ FUNCTION(spi6),
+ FUNCTION(sys),
+ FUNCTION(tmds),
+ FUNCTION(trace),
+ FUNCTION(uarta),
+ FUNCTION(uartb),
+ FUNCTION(uartc),
+ FUNCTION(uartd),
+ FUNCTION(ulpi),
+ FUNCTION(usb),
+ FUNCTION(vgp1),
+ FUNCTION(vgp2),
+ FUNCTION(vgp3),
+ FUNCTION(vgp4),
+ FUNCTION(vgp5),
+ FUNCTION(vgp6),
+ FUNCTION(vi),
+ FUNCTION(vi_alt1),
+ FUNCTION(vi_alt3),
+ FUNCTION(vimclk2),
+ FUNCTION(vimclk2_alt),
+};
+
+#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
+#define PINGROUP_REG_A 0x3000 /* bank 1 */
+#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
+
+#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
+#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
+#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
+
+#define PINGROUP_BIT_Y(b) (b)
+#define PINGROUP_BIT_N(b) (-1)
+
+#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .funcs = { \
+ TEGRA_MUX_##f0, \
+ TEGRA_MUX_##f1, \
+ TEGRA_MUX_##f2, \
+ TEGRA_MUX_##f3, \
+ }, \
+ .mux_reg = PINGROUP_REG(r), \
+ .mux_bank = 1, \
+ .mux_bit = 0, \
+ .pupd_reg = PINGROUP_REG(r), \
+ .pupd_bank = 1, \
+ .pupd_bit = 2, \
+ .tri_reg = PINGROUP_REG(r), \
+ .tri_bank = 1, \
+ .tri_bit = 4, \
+ .einput_bit = 5, \
+ .odrain_bit = PINGROUP_BIT_##od(6), \
+ .lock_bit = 7, \
+ .ioreset_bit = PINGROUP_BIT_##ior(8), \
+ .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
+ .drv_reg = -1, \
+ }
+
+#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
+ drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
+ slwf_b, slwf_w, drvtype) \
+ { \
+ .name = "drive_" #pg_name, \
+ .pins = drive_##pg_name##_pins, \
+ .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
+ .mux_reg = -1, \
+ .pupd_reg = -1, \
+ .tri_reg = -1, \
+ .einput_bit = -1, \
+ .odrain_bit = -1, \
+ .lock_bit = -1, \
+ .ioreset_bit = -1, \
+ .rcv_sel_bit = -1, \
+ .drv_reg = DRV_PINGROUP_REG(r), \
+ .drv_bank = 0, \
+ .hsm_bit = hsm_b, \
+ .schmitt_bit = schmitt_b, \
+ .lpmd_bit = lpmd_b, \
+ .drvdn_bit = drvdn_b, \
+ .drvdn_width = drvdn_w, \
+ .drvup_bit = drvup_b, \
+ .drvup_width = drvup_w, \
+ .slwr_bit = slwr_b, \
+ .slwr_width = slwr_w, \
+ .slwf_bit = slwf_b, \
+ .slwf_width = slwf_w, \
+ .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
+ }
+
+#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \
+ { \
+ .name = "mipi_pad_ctrl_" #pg_name, \
+ .pins = mipi_pad_ctrl_##pg_name##_pins, \
+ .npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins), \
+ .funcs = { \
+ TEGRA_MUX_ ## f0, \
+ TEGRA_MUX_ ## f1, \
+ TEGRA_MUX_RSVD3, \
+ TEGRA_MUX_RSVD4, \
+ }, \
+ .mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r), \
+ .mux_bank = 2, \
+ .mux_bit = b, \
+ .pupd_reg = -1, \
+ .tri_reg = -1, \
+ .einput_bit = -1, \
+ .odrain_bit = -1, \
+ .lock_bit = -1, \
+ .ioreset_bit = -1, \
+ .rcv_sel_bit = -1, \
+ .drv_reg = -1, \
+ }
+
+static const struct tegra_pingroup tegra124_groups[] = {
+ /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
+ PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
+ PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N),
+ PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N),
+ PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N),
+ PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N),
+ PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N),
+ PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N),
+ PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N),
+ PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N),
+ PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N),
+ PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N),
+ PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N),
+ PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N),
+ PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N),
+ PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, RSVD4, 0x3038, N, N, N),
+ PINGROUP(dap3_sclk_pp3, I2S2, SPI5, RSVD3, DISPLAYB, 0x303c, N, N, N),
+ PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N),
+ PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N),
+ PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N),
+ PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N),
+ PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N),
+ PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N),
+ PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N),
+ PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N),
+ PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N),
+ PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N),
+ PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y),
+ PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y),
+ PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y),
+ PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N),
+ PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N),
+ PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, 0x316c, N, N, N),
+ PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, 0x3170, N, N, N),
+ PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, SPI4, 0x3174, N, N, N),
+ PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, SPI4, 0x3178, N, N, N),
+ PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, GMI, 0x317c, N, N, N),
+ PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, GMI, 0x3180, N, N, N),
+ PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, 0x3184, N, N, N),
+ PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, 0x3188, N, N, N),
+ PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, 0x318c, N, N, N),
+ PINGROUP(pu3, PWM0, UARTA, GMI, DISPLAYB, 0x3190, N, N, N),
+ PINGROUP(pu4, PWM1, UARTA, GMI, DISPLAYB, 0x3194, N, N, N),
+ PINGROUP(pu5, PWM2, UARTA, GMI, DISPLAYB, 0x3198, N, N, N),
+ PINGROUP(pu6, PWM3, UARTA, RSVD3, GMI, 0x319c, N, N, N),
+ PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N),
+ PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N),
+ PINGROUP(dap4_fs_pp4, I2S3, GMI, DTV, RSVD4, 0x31a8, N, N, N),
+ PINGROUP(dap4_din_pp5, I2S3, GMI, RSVD3, RSVD4, 0x31ac, N, N, N),
+ PINGROUP(dap4_dout_pp6, I2S3, GMI, DTV, RSVD4, 0x31b0, N, N, N),
+ PINGROUP(dap4_sclk_pp7, I2S3, GMI, RSVD3, RSVD4, 0x31b4, N, N, N),
+ PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N),
+ PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N),
+ PINGROUP(pc7, RSVD1, RSVD2, GMI, GMI_ALT, 0x31c0, N, N, N),
+ PINGROUP(pi5, SDMMC2, RSVD2, GMI, RSVD4, 0x31c4, N, N, N),
+ PINGROUP(pi7, RSVD1, TRACE, GMI, DTV, 0x31c8, N, N, N),
+ PINGROUP(pk0, RSVD1, SDMMC3, GMI, SOC, 0x31cc, N, N, N),
+ PINGROUP(pk1, SDMMC2, TRACE, GMI, RSVD4, 0x31d0, N, N, N),
+ PINGROUP(pj0, RSVD1, RSVD2, GMI, USB, 0x31d4, N, N, N),
+ PINGROUP(pj2, RSVD1, RSVD2, GMI, SOC, 0x31d8, N, N, N),
+ PINGROUP(pk3, SDMMC2, TRACE, GMI, CCLA, 0x31dc, N, N, N),
+ PINGROUP(pk4, SDMMC2, RSVD2, GMI, GMI_ALT, 0x31e0, N, N, N),
+ PINGROUP(pk2, RSVD1, RSVD2, GMI, RSVD4, 0x31e4, N, N, N),
+ PINGROUP(pi3, RSVD1, RSVD2, GMI, SPI4, 0x31e8, N, N, N),
+ PINGROUP(pi6, RSVD1, RSVD2, GMI, SDMMC2, 0x31ec, N, N, N),
+ PINGROUP(pg0, RSVD1, RSVD2, GMI, RSVD4, 0x31f0, N, N, N),
+ PINGROUP(pg1, RSVD1, RSVD2, GMI, RSVD4, 0x31f4, N, N, N),
+ PINGROUP(pg2, RSVD1, TRACE, GMI, RSVD4, 0x31f8, N, N, N),
+ PINGROUP(pg3, RSVD1, TRACE, GMI, RSVD4, 0x31fc, N, N, N),
+ PINGROUP(pg4, RSVD1, TMDS, GMI, SPI4, 0x3200, N, N, N),
+ PINGROUP(pg5, RSVD1, RSVD2, GMI, SPI4, 0x3204, N, N, N),
+ PINGROUP(pg6, RSVD1, RSVD2, GMI, SPI4, 0x3208, N, N, N),
+ PINGROUP(pg7, RSVD1, RSVD2, GMI, SPI4, 0x320c, N, N, N),
+ PINGROUP(ph0, PWM0, TRACE, GMI, DTV, 0x3210, N, N, N),
+ PINGROUP(ph1, PWM1, TMDS, GMI, DISPLAYA, 0x3214, N, N, N),
+ PINGROUP(ph2, PWM2, TMDS, GMI, CLDVFS, 0x3218, N, N, N),
+ PINGROUP(ph3, PWM3, SPI4, GMI, CLDVFS, 0x321c, N, N, N),
+ PINGROUP(ph4, SDMMC2, RSVD2, GMI, RSVD4, 0x3220, N, N, N),
+ PINGROUP(ph5, SDMMC2, RSVD2, GMI, RSVD4, 0x3224, N, N, N),
+ PINGROUP(ph6, SDMMC2, TRACE, GMI, DTV, 0x3228, N, N, N),
+ PINGROUP(ph7, SDMMC2, TRACE, GMI, DTV, 0x322c, N, N, N),
+ PINGROUP(pj7, UARTD, RSVD2, GMI, GMI_ALT, 0x3230, N, N, N),
+ PINGROUP(pb0, UARTD, RSVD2, GMI, RSVD4, 0x3234, N, N, N),
+ PINGROUP(pb1, UARTD, RSVD2, GMI, RSVD4, 0x3238, N, N, N),
+ PINGROUP(pk7, UARTD, RSVD2, GMI, RSVD4, 0x323c, N, N, N),
+ PINGROUP(pi0, RSVD1, RSVD2, GMI, RSVD4, 0x3240, N, N, N),
+ PINGROUP(pi1, RSVD1, RSVD2, GMI, RSVD4, 0x3244, N, N, N),
+ PINGROUP(pi2, SDMMC2, TRACE, GMI, RSVD4, 0x3248, N, N, N),
+ PINGROUP(pi4, SPI4, TRACE, GMI, DISPLAYA, 0x324c, N, N, N),
+ PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N),
+ PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N),
+ PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N),
+ PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N),
+ PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N),
+ PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N),
+ PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N),
+ PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N),
+ PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N),
+ PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, 0x3274, N, Y, N),
+ PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N),
+ PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N),
+ PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, 0x3284, N, N, N),
+ PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC2, 0x3288, N, N, N),
+ PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, 0x328c, N, N, N),
+ PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, 0x3290, Y, N, N),
+ PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, 0x3294, Y, N, N),
+ PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC2, 0x3298, N, N, N),
+ PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC2, 0x329c, N, N, N),
+ PINGROUP(pbb5, VGP5, DISPLAYA, RSVD3, SDMMC2, 0x32a0, N, N, N),
+ PINGROUP(pbb6, I2S4, RSVD2, DISPLAYB, SDMMC2, 0x32a4, N, N, N),
+ PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC2, 0x32a8, N, N, N),
+ PINGROUP(pcc2, I2S4, RSVD2, SDMMC3, SDMMC2, 0x32ac, N, N, N),
+ PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N),
+ PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N),
+ PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N),
+ PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N),
+ PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N),
+ PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N),
+ PINGROUP(kb_row3_pr3, KBC, DISPLAYA, SYS, DISPLAYB, 0x32c8, N, N, N),
+ PINGROUP(kb_row4_pr4, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32cc, N, N, N),
+ PINGROUP(kb_row5_pr5, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32d0, N, N, N),
+ PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N),
+ PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N),
+ PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N),
+ PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N),
+ PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N),
+ PINGROUP(kb_row11_ps3, KBC, RSVD2, RSVD3, IRDA, 0x32e8, N, N, N),
+ PINGROUP(kb_row12_ps4, KBC, RSVD2, RSVD3, IRDA, 0x32ec, N, N, N),
+ PINGROUP(kb_row13_ps5, KBC, RSVD2, SPI2, RSVD4, 0x32f0, N, N, N),
+ PINGROUP(kb_row14_ps6, KBC, RSVD2, SPI2, RSVD4, 0x32f4, N, N, N),
+ PINGROUP(kb_row15_ps7, KBC, SOC, RSVD3, RSVD4, 0x32f8, N, N, N),
+ PINGROUP(kb_col0_pq0, KBC, RSVD2, SPI2, RSVD4, 0x32fc, N, N, N),
+ PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, RSVD4, 0x3300, N, N, N),
+ PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N),
+ PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N),
+ PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N),
+ PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC3, RSVD4, 0x3310, N, N, N),
+ PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, UARTD, 0x3314, N, N, N),
+ PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, UARTD, 0x3318, N, N, N),
+ PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N),
+ PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N),
+ PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N),
+ PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N),
+ PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N),
+ PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y),
+ PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N),
+ PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N),
+ PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SATA, 0x3340, N, N, N),
+ PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N),
+ PINGROUP(dap_mclk1_req_pee2, DAP, DAP1, SATA, RSVD4, 0x3348, N, N, N),
+ PINGROUP(dap_mclk1_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N),
+ PINGROUP(spdif_in_pk6, SPDIF, RSVD2, RSVD3, I2C3, 0x3350, N, N, N),
+ PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, I2C3, 0x3354, N, N, N),
+ PINGROUP(dap2_fs_pa2, I2S1, HDA, GMI, RSVD4, 0x3358, N, N, N),
+ PINGROUP(dap2_din_pa4, I2S1, HDA, GMI, RSVD4, 0x335c, N, N, N),
+ PINGROUP(dap2_dout_pa5, I2S1, HDA, GMI, RSVD4, 0x3360, N, N, N),
+ PINGROUP(dap2_sclk_pa3, I2S1, HDA, GMI, RSVD4, 0x3364, N, N, N),
+ PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, GMI, RSVD4, 0x3368, N, N, N),
+ PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, GMI, RSVD4, 0x336c, N, N, N),
+ PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, GMI, RSVD4, 0x3370, N, N, N),
+ PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, GMI, RSVD4, 0x3374, N, N, N),
+ PINGROUP(gpio_x4_aud_px4, GMI, SPI1, SPI2, DAP2, 0x3378, N, N, N),
+ PINGROUP(gpio_x5_aud_px5, GMI, SPI1, SPI2, RSVD4, 0x337c, N, N, N),
+ PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, GMI, 0x3380, N, N, N),
+ PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N),
+ PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N),
+ PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N),
+ PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N),
+ PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N),
+ PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N),
+ PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N),
+ PINGROUP(pex_l0_rst_n_pdd1, PE0, RSVD2, RSVD3, RSVD4, 0x33bc, N, N, N),
+ PINGROUP(pex_l0_clkreq_n_pdd2, PE0, RSVD2, RSVD3, RSVD4, 0x33c0, N, N, N),
+ PINGROUP(pex_wake_n_pdd3, PE, RSVD2, RSVD3, RSVD4, 0x33c4, N, N, N),
+ PINGROUP(pex_l1_rst_n_pdd5, PE1, RSVD2, RSVD3, RSVD4, 0x33cc, N, N, N),
+ PINGROUP(pex_l1_clkreq_n_pdd6, PE1, RSVD2, RSVD3, RSVD4, 0x33d0, N, N, N),
+ PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, 0x33e0, Y, N, N),
+ PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N),
+ PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N),
+ PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N),
+ PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N),
+ PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N),
+ PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N),
+ PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N),
+ PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N),
+ PINGROUP(gmi_clk_lb, SDMMC2, RSVD2, GMI, RSVD4, 0x3404, N, N, N),
+ PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N),
+ PINGROUP(kb_row16_pt0, KBC, RSVD2, RSVD3, UARTC, 0x340c, N, N, N),
+ PINGROUP(kb_row17_pt1, KBC, RSVD2, RSVD3, UARTC, 0x3410, N, N, N),
+ PINGROUP(usb_vbus_en2_pff1, USB, RSVD2, RSVD3, RSVD4, 0x3414, Y, N, N),
+ PINGROUP(pff2, SATA, RSVD2, RSVD3, RSVD4, 0x3418, Y, N, N),
+ PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, 0x3430, N, N, N),
+
+ /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
+ DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
+ DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
+ DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
+ DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
+ DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
+ DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
+ DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y),
+ DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
+ DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(ao3, 0x9a8, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
+ DRV_PINGROUP(ao0, 0x9b0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
+ DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
+ DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
+
+ /* pg_name, r, b, f0, f1 */
+ MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B),
+};
+
+static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
+ .ngpios = NUM_GPIOS,
+ .pins = tegra124_pins,
+ .npins = ARRAY_SIZE(tegra124_pins),
+ .functions = tegra124_functions,
+ .nfunctions = ARRAY_SIZE(tegra124_functions),
+ .groups = tegra124_groups,
+ .ngroups = ARRAY_SIZE(tegra124_groups),
+ .hsm_in_mux = false,
+ .schmitt_in_mux = false,
+ .drvtype_in_mux = false,
+};
+
+static int tegra124_pinctrl_probe(struct platform_device *pdev)
+{
+ return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
+}
+
+static const struct of_device_id tegra124_pinctrl_of_match[] = {
+ { .compatible = "nvidia,tegra124-pinmux", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, tegra124_pinctrl_of_match);
+
+static struct platform_driver tegra124_pinctrl_driver = {
+ .driver = {
+ .name = "tegra124-pinctrl",
+ .of_match_table = tegra124_pinctrl_of_match,
+ },
+ .probe = tegra124_pinctrl_probe,
+ .remove = tegra_pinctrl_remove,
+};
+module_platform_driver(tegra124_pinctrl_driver);
+
+MODULE_AUTHOR("Ashwini Ghuge <aghuge@nvidia.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra124 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * Pinctrl data for the NVIDIA Tegra20 pinmux
+ *
+ * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Derived from code:
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2010 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "pinctrl-tegra.h"
+
+/*
+ * Most pins affected by the pinmux can also be GPIOs. Define these first.
+ * These must match how the GPIO driver names/numbers its pins.
+ */
+#define _GPIO(offset) (offset)
+
+#define TEGRA_PIN_VI_GP6_PA0 _GPIO(0)
+#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
+#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
+#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
+#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
+#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
+#define TEGRA_PIN_SDIO3_CLK_PA6 _GPIO(6)
+#define TEGRA_PIN_SDIO3_CMD_PA7 _GPIO(7)
+#define TEGRA_PIN_GMI_AD17_PB0 _GPIO(8)
+#define TEGRA_PIN_GMI_AD18_PB1 _GPIO(9)
+#define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10)
+#define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11)
+#define TEGRA_PIN_SDIO3_DAT3_PB4 _GPIO(12)
+#define TEGRA_PIN_SDIO3_DAT2_PB5 _GPIO(13)
+#define TEGRA_PIN_SDIO3_DAT1_PB6 _GPIO(14)
+#define TEGRA_PIN_SDIO3_DAT0_PB7 _GPIO(15)
+#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
+#define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17)
+#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
+#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
+#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
+#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
+#define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22)
+#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
+#define TEGRA_PIN_SDIO3_DAT5_PD0 _GPIO(24)
+#define TEGRA_PIN_SDIO3_DAT4_PD1 _GPIO(25)
+#define TEGRA_PIN_VI_GP5_PD2 _GPIO(26)
+#define TEGRA_PIN_SDIO3_DAT6_PD3 _GPIO(27)
+#define TEGRA_PIN_SDIO3_DAT7_PD4 _GPIO(28)
+#define TEGRA_PIN_VI_D1_PD5 _GPIO(29)
+#define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30)
+#define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31)
+#define TEGRA_PIN_LCD_D0_PE0 _GPIO(32)
+#define TEGRA_PIN_LCD_D1_PE1 _GPIO(33)
+#define TEGRA_PIN_LCD_D2_PE2 _GPIO(34)
+#define TEGRA_PIN_LCD_D3_PE3 _GPIO(35)
+#define TEGRA_PIN_LCD_D4_PE4 _GPIO(36)
+#define TEGRA_PIN_LCD_D5_PE5 _GPIO(37)
+#define TEGRA_PIN_LCD_D6_PE6 _GPIO(38)
+#define TEGRA_PIN_LCD_D7_PE7 _GPIO(39)
+#define TEGRA_PIN_LCD_D8_PF0 _GPIO(40)
+#define TEGRA_PIN_LCD_D9_PF1 _GPIO(41)
+#define TEGRA_PIN_LCD_D10_PF2 _GPIO(42)
+#define TEGRA_PIN_LCD_D11_PF3 _GPIO(43)
+#define TEGRA_PIN_LCD_D12_PF4 _GPIO(44)
+#define TEGRA_PIN_LCD_D13_PF5 _GPIO(45)
+#define TEGRA_PIN_LCD_D14_PF6 _GPIO(46)
+#define TEGRA_PIN_LCD_D15_PF7 _GPIO(47)
+#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
+#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
+#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
+#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
+#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
+#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
+#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
+#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
+#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
+#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
+#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
+#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
+#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
+#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
+#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
+#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
+#define TEGRA_PIN_GMI_HIOW_N_PI0 _GPIO(64)
+#define TEGRA_PIN_GMI_HIOR_N_PI1 _GPIO(65)
+#define TEGRA_PIN_GMI_CS5_N_PI2 _GPIO(66)
+#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
+#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
+#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
+#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
+#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
+#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
+#define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73)
+#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
+#define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75)
+#define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76)
+#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
+#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
+#define TEGRA_PIN_GMI_AD16_PJ7 _GPIO(79)
+#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
+#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
+#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
+#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
+#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
+#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
+#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
+#define TEGRA_PIN_GMI_AD19_PK7 _GPIO(87)
+#define TEGRA_PIN_VI_D2_PL0 _GPIO(88)
+#define TEGRA_PIN_VI_D3_PL1 _GPIO(89)
+#define TEGRA_PIN_VI_D4_PL2 _GPIO(90)
+#define TEGRA_PIN_VI_D5_PL3 _GPIO(91)
+#define TEGRA_PIN_VI_D6_PL4 _GPIO(92)
+#define TEGRA_PIN_VI_D7_PL5 _GPIO(93)
+#define TEGRA_PIN_VI_D8_PL6 _GPIO(94)
+#define TEGRA_PIN_VI_D9_PL7 _GPIO(95)
+#define TEGRA_PIN_LCD_D16_PM0 _GPIO(96)
+#define TEGRA_PIN_LCD_D17_PM1 _GPIO(97)
+#define TEGRA_PIN_LCD_D18_PM2 _GPIO(98)
+#define TEGRA_PIN_LCD_D19_PM3 _GPIO(99)
+#define TEGRA_PIN_LCD_D20_PM4 _GPIO(100)
+#define TEGRA_PIN_LCD_D21_PM5 _GPIO(101)
+#define TEGRA_PIN_LCD_D22_PM6 _GPIO(102)
+#define TEGRA_PIN_LCD_D23_PM7 _GPIO(103)
+#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
+#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
+#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
+#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
+#define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108)
+#define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109)
+#define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110)
+#define TEGRA_PIN_HDMI_INT_N_PN7 _GPIO(111)
+#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
+#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
+#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
+#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
+#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
+#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
+#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
+#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
+#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
+#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
+#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
+#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
+#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
+#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
+#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
+#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
+#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
+#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
+#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
+#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
+#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
+#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
+#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
+#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
+#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
+#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
+#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
+#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
+#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
+#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
+#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
+#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
+#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
+#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
+#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
+#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
+#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
+#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
+#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
+#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
+#define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152)
+#define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153)
+#define TEGRA_PIN_VI_D10_PT2 _GPIO(154)
+#define TEGRA_PIN_VI_D11_PT3 _GPIO(155)
+#define TEGRA_PIN_VI_D0_PT4 _GPIO(156)
+#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
+#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
+#define TEGRA_PIN_GMI_DPD_PT7 _GPIO(159)
+#define TEGRA_PIN_PU0 _GPIO(160)
+#define TEGRA_PIN_PU1 _GPIO(161)
+#define TEGRA_PIN_PU2 _GPIO(162)
+#define TEGRA_PIN_PU3 _GPIO(163)
+#define TEGRA_PIN_PU4 _GPIO(164)
+#define TEGRA_PIN_PU5 _GPIO(165)
+#define TEGRA_PIN_PU6 _GPIO(166)
+#define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167)
+#define TEGRA_PIN_PV0 _GPIO(168)
+#define TEGRA_PIN_PV1 _GPIO(169)
+#define TEGRA_PIN_PV2 _GPIO(170)
+#define TEGRA_PIN_PV3 _GPIO(171)
+#define TEGRA_PIN_PV4 _GPIO(172)
+#define TEGRA_PIN_PV5 _GPIO(173)
+#define TEGRA_PIN_PV6 _GPIO(174)
+#define TEGRA_PIN_LCD_DC1_PV7 _GPIO(175)
+#define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176)
+#define TEGRA_PIN_LCD_M1_PW1 _GPIO(177)
+#define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178)
+#define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179)
+#define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
+#define TEGRA_PIN_DAP_MCLK2_PW5 _GPIO(181)
+#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
+#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
+#define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184)
+#define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185)
+#define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186)
+#define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187)
+#define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188)
+#define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189)
+#define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190)
+#define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191)
+#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
+#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
+#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
+#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
+#define TEGRA_PIN_SDIO1_DAT3_PY4 _GPIO(196)
+#define TEGRA_PIN_SDIO1_DAT2_PY5 _GPIO(197)
+#define TEGRA_PIN_SDIO1_DAT1_PY6 _GPIO(198)
+#define TEGRA_PIN_SDIO1_DAT0_PY7 _GPIO(199)
+#define TEGRA_PIN_SDIO1_CLK_PZ0 _GPIO(200)
+#define TEGRA_PIN_SDIO1_CMD_PZ1 _GPIO(201)
+#define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202)
+#define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203)
+#define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204)
+#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
+#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
+#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
+#define TEGRA_PIN_GMI_AD20_PAA0 _GPIO(208)
+#define TEGRA_PIN_GMI_AD21_PAA1 _GPIO(209)
+#define TEGRA_PIN_GMI_AD22_PAA2 _GPIO(210)
+#define TEGRA_PIN_GMI_AD23_PAA3 _GPIO(211)
+#define TEGRA_PIN_GMI_AD24_PAA4 _GPIO(212)
+#define TEGRA_PIN_GMI_AD25_PAA5 _GPIO(213)
+#define TEGRA_PIN_GMI_AD26_PAA6 _GPIO(214)
+#define TEGRA_PIN_GMI_AD27_PAA7 _GPIO(215)
+#define TEGRA_PIN_LED_BLINK_PBB0 _GPIO(216)
+#define TEGRA_PIN_VI_GP0_PBB1 _GPIO(217)
+#define TEGRA_PIN_CAM_I2C_SCL_PBB2 _GPIO(218)
+#define TEGRA_PIN_CAM_I2C_SDA_PBB3 _GPIO(219)
+#define TEGRA_PIN_VI_GP3_PBB4 _GPIO(220)
+#define TEGRA_PIN_VI_GP4_PBB5 _GPIO(221)
+#define TEGRA_PIN_PBB6 _GPIO(222)
+#define TEGRA_PIN_PBB7 _GPIO(223)
+
+/* All non-GPIO pins follow */
+#define NUM_GPIOS (TEGRA_PIN_PBB7 + 1)
+#define _PIN(offset) (NUM_GPIOS + (offset))
+
+#define TEGRA_PIN_CRT_HSYNC _PIN(30)
+#define TEGRA_PIN_CRT_VSYNC _PIN(31)
+#define TEGRA_PIN_DDC_SCL _PIN(32)
+#define TEGRA_PIN_DDC_SDA _PIN(33)
+#define TEGRA_PIN_OWC _PIN(34)
+#define TEGRA_PIN_CORE_PWR_REQ _PIN(35)
+#define TEGRA_PIN_CPU_PWR_REQ _PIN(36)
+#define TEGRA_PIN_PWR_INT_N _PIN(37)
+#define TEGRA_PIN_CLK_32_K_IN _PIN(38)
+#define TEGRA_PIN_DDR_COMP_PD _PIN(39)
+#define TEGRA_PIN_DDR_COMP_PU _PIN(40)
+#define TEGRA_PIN_DDR_A0 _PIN(41)
+#define TEGRA_PIN_DDR_A1 _PIN(42)
+#define TEGRA_PIN_DDR_A2 _PIN(43)
+#define TEGRA_PIN_DDR_A3 _PIN(44)
+#define TEGRA_PIN_DDR_A4 _PIN(45)
+#define TEGRA_PIN_DDR_A5 _PIN(46)
+#define TEGRA_PIN_DDR_A6 _PIN(47)
+#define TEGRA_PIN_DDR_A7 _PIN(48)
+#define TEGRA_PIN_DDR_A8 _PIN(49)
+#define TEGRA_PIN_DDR_A9 _PIN(50)
+#define TEGRA_PIN_DDR_A10 _PIN(51)
+#define TEGRA_PIN_DDR_A11 _PIN(52)
+#define TEGRA_PIN_DDR_A12 _PIN(53)
+#define TEGRA_PIN_DDR_A13 _PIN(54)
+#define TEGRA_PIN_DDR_A14 _PIN(55)
+#define TEGRA_PIN_DDR_CAS_N _PIN(56)
+#define TEGRA_PIN_DDR_BA0 _PIN(57)
+#define TEGRA_PIN_DDR_BA1 _PIN(58)
+#define TEGRA_PIN_DDR_BA2 _PIN(59)
+#define TEGRA_PIN_DDR_DQS0P _PIN(60)
+#define TEGRA_PIN_DDR_DQS0N _PIN(61)
+#define TEGRA_PIN_DDR_DQS1P _PIN(62)
+#define TEGRA_PIN_DDR_DQS1N _PIN(63)
+#define TEGRA_PIN_DDR_DQS2P _PIN(64)
+#define TEGRA_PIN_DDR_DQS2N _PIN(65)
+#define TEGRA_PIN_DDR_DQS3P _PIN(66)
+#define TEGRA_PIN_DDR_DQS3N _PIN(67)
+#define TEGRA_PIN_DDR_CKE0 _PIN(68)
+#define TEGRA_PIN_DDR_CKE1 _PIN(69)
+#define TEGRA_PIN_DDR_CLK _PIN(70)
+#define TEGRA_PIN_DDR_CLK_N _PIN(71)
+#define TEGRA_PIN_DDR_DM0 _PIN(72)
+#define TEGRA_PIN_DDR_DM1 _PIN(73)
+#define TEGRA_PIN_DDR_DM2 _PIN(74)
+#define TEGRA_PIN_DDR_DM3 _PIN(75)
+#define TEGRA_PIN_DDR_ODT _PIN(76)
+#define TEGRA_PIN_DDR_QUSE0 _PIN(77)
+#define TEGRA_PIN_DDR_QUSE1 _PIN(78)
+#define TEGRA_PIN_DDR_QUSE2 _PIN(79)
+#define TEGRA_PIN_DDR_QUSE3 _PIN(80)
+#define TEGRA_PIN_DDR_RAS_N _PIN(81)
+#define TEGRA_PIN_DDR_WE_N _PIN(82)
+#define TEGRA_PIN_DDR_DQ0 _PIN(83)
+#define TEGRA_PIN_DDR_DQ1 _PIN(84)
+#define TEGRA_PIN_DDR_DQ2 _PIN(85)
+#define TEGRA_PIN_DDR_DQ3 _PIN(86)
+#define TEGRA_PIN_DDR_DQ4 _PIN(87)
+#define TEGRA_PIN_DDR_DQ5 _PIN(88)
+#define TEGRA_PIN_DDR_DQ6 _PIN(89)
+#define TEGRA_PIN_DDR_DQ7 _PIN(90)
+#define TEGRA_PIN_DDR_DQ8 _PIN(91)
+#define TEGRA_PIN_DDR_DQ9 _PIN(92)
+#define TEGRA_PIN_DDR_DQ10 _PIN(93)
+#define TEGRA_PIN_DDR_DQ11 _PIN(94)
+#define TEGRA_PIN_DDR_DQ12 _PIN(95)
+#define TEGRA_PIN_DDR_DQ13 _PIN(96)
+#define TEGRA_PIN_DDR_DQ14 _PIN(97)
+#define TEGRA_PIN_DDR_DQ15 _PIN(98)
+#define TEGRA_PIN_DDR_DQ16 _PIN(99)
+#define TEGRA_PIN_DDR_DQ17 _PIN(100)
+#define TEGRA_PIN_DDR_DQ18 _PIN(101)
+#define TEGRA_PIN_DDR_DQ19 _PIN(102)
+#define TEGRA_PIN_DDR_DQ20 _PIN(103)
+#define TEGRA_PIN_DDR_DQ21 _PIN(104)
+#define TEGRA_PIN_DDR_DQ22 _PIN(105)
+#define TEGRA_PIN_DDR_DQ23 _PIN(106)
+#define TEGRA_PIN_DDR_DQ24 _PIN(107)
+#define TEGRA_PIN_DDR_DQ25 _PIN(108)
+#define TEGRA_PIN_DDR_DQ26 _PIN(109)
+#define TEGRA_PIN_DDR_DQ27 _PIN(110)
+#define TEGRA_PIN_DDR_DQ28 _PIN(111)
+#define TEGRA_PIN_DDR_DQ29 _PIN(112)
+#define TEGRA_PIN_DDR_DQ30 _PIN(113)
+#define TEGRA_PIN_DDR_DQ31 _PIN(114)
+#define TEGRA_PIN_DDR_CS0_N _PIN(115)
+#define TEGRA_PIN_DDR_CS1_N _PIN(116)
+#define TEGRA_PIN_SYS_RESET _PIN(117)
+#define TEGRA_PIN_JTAG_TRST_N _PIN(118)
+#define TEGRA_PIN_JTAG_TDO _PIN(119)
+#define TEGRA_PIN_JTAG_TMS _PIN(120)
+#define TEGRA_PIN_JTAG_TCK _PIN(121)
+#define TEGRA_PIN_JTAG_TDI _PIN(122)
+#define TEGRA_PIN_TEST_MODE_EN _PIN(123)
+
+static const struct pinctrl_pin_desc tegra20_pins[] = {
+ PINCTRL_PIN(TEGRA_PIN_VI_GP6_PA0, "VI_GP6 PA0"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO3_CLK_PA6, "SDIO3_CLK PA6"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO3_CMD_PA7, "SDIO3_CMD PA7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD17_PB0, "GMI_AD17 PB0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD18_PB1, "GMI_AD18 PB1"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT3_PB4, "SDIO3_DAT3 PB4"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT2_PB5, "SDIO3_DAT2 PB5"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT1_PB6, "SDIO3_DAT1 PB6"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT0_PB7, "SDIO3_DAT0 PB7"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
+ PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
+ PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT5_PD0, "SDIO3_DAT5 PD0"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT4_PD1, "SDIO3_DAT4 PD1"),
+ PINCTRL_PIN(TEGRA_PIN_VI_GP5_PD2, "VI_GP5 PD2"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT6_PD3, "SDIO3_DAT6 PD3"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT7_PD4, "SDIO3_DAT7 PD4"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
+ PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
+ PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_HIOW_N_PI0, "GMI_HIOW_N PI0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_HIOR_N_PI1, "GMI_HIOR_N PI1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS5_N_PI2, "GMI_CS5_N PI2"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD16_PJ7, "GMI_AD16 PJ7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
+ PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
+ PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD19_PK7, "GMI_AD19 PK7"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
+ PINCTRL_PIN(TEGRA_PIN_HDMI_INT_N_PN7, "HDMI_INT_N PN7"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
+ PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
+ PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VD_D10 PT2"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_DPD_PT7, "GMI_DPD PT7"),
+ /* PU0..6: GPIO only */
+ PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
+ PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
+ PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
+ PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
+ PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
+ PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
+ PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
+ /* PV0..1: GPIO only */
+ PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
+ PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
+ /* PV2..3: Balls are named after GPIO not function */
+ PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
+ PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
+ /* PV4..6: GPIO only */
+ PINCTRL_PIN(TEGRA_PIN_PV4, "PV4"),
+ PINCTRL_PIN(TEGRA_PIN_PV5, "PV5"),
+ PINCTRL_PIN(TEGRA_PIN_PV6, "PV6"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PV7, "LCD_DC1 PV7"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
+ PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
+ PINCTRL_PIN(TEGRA_PIN_DAP_MCLK2_PW5, "DAP_MCLK2 PW5"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT3_PY4, "SDIO1_DAT3 PY4"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT2_PY5, "SDIO1_DAT2 PY5"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT1_PY6, "SDIO1_DAT1 PY6"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT0_PY7, "SDIO1_DAT0 PY7"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO1_CLK_PZ0, "SDIO1_CLK PZ0"),
+ PINCTRL_PIN(TEGRA_PIN_SDIO1_CMD_PZ1, "SDIO1_CMD PZ1"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
+ PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD20_PAA0, "GMI_AD20 PAA0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD21_PAA1, "GMI_AD21 PAA1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD22_PAA2, "GMI_AD22 PAA2"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD23_PAA3, "GMI_AD23 PAA3"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD24_PAA4, "GMI_AD24 PAA4"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD25_PAA5, "GMI_AD25 PAA5"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD26_PAA6, "GMI_AD26 PAA6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD27_PAA7, "GMI_AD27 PAA7"),
+ PINCTRL_PIN(TEGRA_PIN_LED_BLINK_PBB0, "LED_BLINK PBB0"),
+ PINCTRL_PIN(TEGRA_PIN_VI_GP0_PBB1, "VI_GP0 PBB1"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB2, "CAM_I2C_SCL PBB2"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB3, "CAM_I2C_SDA PBB3"),
+ PINCTRL_PIN(TEGRA_PIN_VI_GP3_PBB4, "VI_GP3 PBB4"),
+ PINCTRL_PIN(TEGRA_PIN_VI_GP4_PBB5, "VI_GP4 PBB5"),
+ PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
+ PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
+ PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC, "CRT_HSYNC"),
+ PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC, "CRT_VSYNC"),
+ PINCTRL_PIN(TEGRA_PIN_DDC_SCL, "DDC_SCL"),
+ PINCTRL_PIN(TEGRA_PIN_DDC_SDA, "DDC_SDA"),
+ PINCTRL_PIN(TEGRA_PIN_OWC, "OWC"),
+ PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
+ PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
+ PINCTRL_PIN(TEGRA_PIN_CLK_32_K_IN, "CLK_32_K_IN"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PD, "DDR_COMP_PD"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PU, "DDR_COMP_PU"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A0, "DDR_A0"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A1, "DDR_A1"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A2, "DDR_A2"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A3, "DDR_A3"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A4, "DDR_A4"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A5, "DDR_A5"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A6, "DDR_A6"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A7, "DDR_A7"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A8, "DDR_A8"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A9, "DDR_A9"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A10, "DDR_A10"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A11, "DDR_A11"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A12, "DDR_A12"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A13, "DDR_A13"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_A14, "DDR_A14"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_CAS_N, "DDR_CAS_N"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_BA0, "DDR_BA0"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_BA1, "DDR_BA1"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_BA2, "DDR_BA2"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQS0P, "DDR_DQS0P"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQS0N, "DDR_DQS0N"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQS1P, "DDR_DQS1P"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQS1N, "DDR_DQS1N"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQS2P, "DDR_DQS2P"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQS2N, "DDR_DQS2N"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQS3P, "DDR_DQS3P"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQS3N, "DDR_DQS3N"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_CKE0, "DDR_CKE0"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_CKE1, "DDR_CKE1"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_CLK, "DDR_CLK"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_CLK_N, "DDR_CLK_N"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DM0, "DDR_DM0"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DM1, "DDR_DM1"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DM2, "DDR_DM2"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DM3, "DDR_DM3"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_ODT, "DDR_ODT"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_QUSE0, "DDR_QUSE0"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_QUSE1, "DDR_QUSE1"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_QUSE2, "DDR_QUSE2"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_QUSE3, "DDR_QUSE3"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_RAS_N, "DDR_RAS_N"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_WE_N, "DDR_WE_N"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ0, "DDR_DQ0"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ1, "DDR_DQ1"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ2, "DDR_DQ2"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ3, "DDR_DQ3"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ4, "DDR_DQ4"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ5, "DDR_DQ5"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ6, "DDR_DQ6"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ7, "DDR_DQ7"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ8, "DDR_DQ8"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ9, "DDR_DQ9"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ10, "DDR_DQ10"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ11, "DDR_DQ11"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ12, "DDR_DQ12"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ13, "DDR_DQ13"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ14, "DDR_DQ14"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ15, "DDR_DQ15"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ16, "DDR_DQ16"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ17, "DDR_DQ17"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ18, "DDR_DQ18"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ19, "DDR_DQ19"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ20, "DDR_DQ20"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ21, "DDR_DQ21"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ22, "DDR_DQ22"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ23, "DDR_DQ23"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ24, "DDR_DQ24"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ25, "DDR_DQ25"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ26, "DDR_DQ26"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ27, "DDR_DQ27"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ28, "DDR_DQ28"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ29, "DDR_DQ29"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ30, "DDR_DQ30"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_DQ31, "DDR_DQ31"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_CS0_N, "DDR_CS0_N"),
+ PINCTRL_PIN(TEGRA_PIN_DDR_CS1_N, "DDR_CS1_N"),
+ PINCTRL_PIN(TEGRA_PIN_SYS_RESET, "SYS_RESET"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
+ PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
+};
+
+static const unsigned ata_pins[] = {
+ TEGRA_PIN_GMI_CS6_N_PI3,
+ TEGRA_PIN_GMI_CS7_N_PI6,
+ TEGRA_PIN_GMI_RST_N_PI4,
+};
+
+static const unsigned atb_pins[] = {
+ TEGRA_PIN_GMI_CS5_N_PI2,
+ TEGRA_PIN_GMI_DPD_PT7,
+};
+
+static const unsigned atc_pins[] = {
+ TEGRA_PIN_GMI_IORDY_PI5,
+ TEGRA_PIN_GMI_WAIT_PI7,
+ TEGRA_PIN_GMI_ADV_N_PK0,
+ TEGRA_PIN_GMI_CLK_PK1,
+ TEGRA_PIN_GMI_CS2_N_PK3,
+ TEGRA_PIN_GMI_CS3_N_PK4,
+ TEGRA_PIN_GMI_CS4_N_PK2,
+ TEGRA_PIN_GMI_AD0_PG0,
+ TEGRA_PIN_GMI_AD1_PG1,
+ TEGRA_PIN_GMI_AD2_PG2,
+ TEGRA_PIN_GMI_AD3_PG3,
+ TEGRA_PIN_GMI_AD4_PG4,
+ TEGRA_PIN_GMI_AD5_PG5,
+ TEGRA_PIN_GMI_AD6_PG6,
+ TEGRA_PIN_GMI_AD7_PG7,
+ TEGRA_PIN_GMI_HIOW_N_PI0,
+ TEGRA_PIN_GMI_HIOR_N_PI1,
+};
+
+static const unsigned atd_pins[] = {
+ TEGRA_PIN_GMI_AD8_PH0,
+ TEGRA_PIN_GMI_AD9_PH1,
+ TEGRA_PIN_GMI_AD10_PH2,
+ TEGRA_PIN_GMI_AD11_PH3,
+};
+
+static const unsigned ate_pins[] = {
+ TEGRA_PIN_GMI_AD12_PH4,
+ TEGRA_PIN_GMI_AD13_PH5,
+ TEGRA_PIN_GMI_AD14_PH6,
+ TEGRA_PIN_GMI_AD15_PH7,
+};
+
+static const unsigned cdev1_pins[] = {
+ TEGRA_PIN_DAP_MCLK1_PW4,
+};
+
+static const unsigned cdev2_pins[] = {
+ TEGRA_PIN_DAP_MCLK2_PW5,
+};
+
+static const unsigned crtp_pins[] = {
+ TEGRA_PIN_CRT_HSYNC,
+ TEGRA_PIN_CRT_VSYNC,
+};
+
+static const unsigned csus_pins[] = {
+ TEGRA_PIN_VI_MCLK_PT1,
+};
+
+static const unsigned dap1_pins[] = {
+ TEGRA_PIN_DAP1_FS_PN0,
+ TEGRA_PIN_DAP1_DIN_PN1,
+ TEGRA_PIN_DAP1_DOUT_PN2,
+ TEGRA_PIN_DAP1_SCLK_PN3,
+};
+
+static const unsigned dap2_pins[] = {
+ TEGRA_PIN_DAP2_FS_PA2,
+ TEGRA_PIN_DAP2_SCLK_PA3,
+ TEGRA_PIN_DAP2_DIN_PA4,
+ TEGRA_PIN_DAP2_DOUT_PA5,
+};
+
+static const unsigned dap3_pins[] = {
+ TEGRA_PIN_DAP3_FS_PP0,
+ TEGRA_PIN_DAP3_DIN_PP1,
+ TEGRA_PIN_DAP3_DOUT_PP2,
+ TEGRA_PIN_DAP3_SCLK_PP3,
+};
+
+static const unsigned dap4_pins[] = {
+ TEGRA_PIN_DAP4_FS_PP4,
+ TEGRA_PIN_DAP4_DIN_PP5,
+ TEGRA_PIN_DAP4_DOUT_PP6,
+ TEGRA_PIN_DAP4_SCLK_PP7,
+};
+
+static const unsigned ddc_pins[] = {
+ TEGRA_PIN_DDC_SCL,
+ TEGRA_PIN_DDC_SDA,
+};
+
+static const unsigned dta_pins[] = {
+ TEGRA_PIN_VI_D0_PT4,
+ TEGRA_PIN_VI_D1_PD5,
+};
+
+static const unsigned dtb_pins[] = {
+ TEGRA_PIN_VI_D10_PT2,
+ TEGRA_PIN_VI_D11_PT3,
+};
+
+static const unsigned dtc_pins[] = {
+ TEGRA_PIN_VI_HSYNC_PD7,
+ TEGRA_PIN_VI_VSYNC_PD6,
+};
+
+static const unsigned dtd_pins[] = {
+ TEGRA_PIN_VI_PCLK_PT0,
+ TEGRA_PIN_VI_D2_PL0,
+ TEGRA_PIN_VI_D3_PL1,
+ TEGRA_PIN_VI_D4_PL2,
+ TEGRA_PIN_VI_D5_PL3,
+ TEGRA_PIN_VI_D6_PL4,
+ TEGRA_PIN_VI_D7_PL5,
+ TEGRA_PIN_VI_D8_PL6,
+ TEGRA_PIN_VI_D9_PL7,
+};
+
+static const unsigned dte_pins[] = {
+ TEGRA_PIN_VI_GP0_PBB1,
+ TEGRA_PIN_VI_GP3_PBB4,
+ TEGRA_PIN_VI_GP4_PBB5,
+ TEGRA_PIN_VI_GP5_PD2,
+ TEGRA_PIN_VI_GP6_PA0,
+};
+
+static const unsigned dtf_pins[] = {
+ TEGRA_PIN_CAM_I2C_SCL_PBB2,
+ TEGRA_PIN_CAM_I2C_SDA_PBB3,
+};
+
+static const unsigned gma_pins[] = {
+ TEGRA_PIN_GMI_AD20_PAA0,
+ TEGRA_PIN_GMI_AD21_PAA1,
+ TEGRA_PIN_GMI_AD22_PAA2,
+ TEGRA_PIN_GMI_AD23_PAA3,
+};
+
+static const unsigned gmb_pins[] = {
+ TEGRA_PIN_GMI_WP_N_PC7,
+};
+
+static const unsigned gmc_pins[] = {
+ TEGRA_PIN_GMI_AD16_PJ7,
+ TEGRA_PIN_GMI_AD17_PB0,
+ TEGRA_PIN_GMI_AD18_PB1,
+ TEGRA_PIN_GMI_AD19_PK7,
+};
+
+static const unsigned gmd_pins[] = {
+ TEGRA_PIN_GMI_CS0_N_PJ0,
+ TEGRA_PIN_GMI_CS1_N_PJ2,
+};
+
+static const unsigned gme_pins[] = {
+ TEGRA_PIN_GMI_AD24_PAA4,
+ TEGRA_PIN_GMI_AD25_PAA5,
+ TEGRA_PIN_GMI_AD26_PAA6,
+ TEGRA_PIN_GMI_AD27_PAA7,
+};
+
+static const unsigned gpu_pins[] = {
+ TEGRA_PIN_PU0,
+ TEGRA_PIN_PU1,
+ TEGRA_PIN_PU2,
+ TEGRA_PIN_PU3,
+ TEGRA_PIN_PU4,
+ TEGRA_PIN_PU5,
+ TEGRA_PIN_PU6,
+};
+
+static const unsigned gpu7_pins[] = {
+ TEGRA_PIN_JTAG_RTCK_PU7,
+};
+
+static const unsigned gpv_pins[] = {
+ TEGRA_PIN_PV4,
+ TEGRA_PIN_PV5,
+ TEGRA_PIN_PV6,
+};
+
+static const unsigned hdint_pins[] = {
+ TEGRA_PIN_HDMI_INT_N_PN7,
+};
+
+static const unsigned i2cp_pins[] = {
+ TEGRA_PIN_PWR_I2C_SCL_PZ6,
+ TEGRA_PIN_PWR_I2C_SDA_PZ7,
+};
+
+static const unsigned irrx_pins[] = {
+ TEGRA_PIN_UART2_RTS_N_PJ6,
+};
+
+static const unsigned irtx_pins[] = {
+ TEGRA_PIN_UART2_CTS_N_PJ5,
+};
+
+static const unsigned kbca_pins[] = {
+ TEGRA_PIN_KB_ROW0_PR0,
+ TEGRA_PIN_KB_ROW1_PR1,
+ TEGRA_PIN_KB_ROW2_PR2,
+};
+
+static const unsigned kbcb_pins[] = {
+ TEGRA_PIN_KB_ROW7_PR7,
+ TEGRA_PIN_KB_ROW8_PS0,
+ TEGRA_PIN_KB_ROW9_PS1,
+ TEGRA_PIN_KB_ROW10_PS2,
+ TEGRA_PIN_KB_ROW11_PS3,
+ TEGRA_PIN_KB_ROW12_PS4,
+ TEGRA_PIN_KB_ROW13_PS5,
+ TEGRA_PIN_KB_ROW14_PS6,
+ TEGRA_PIN_KB_ROW15_PS7,
+};
+
+static const unsigned kbcc_pins[] = {
+ TEGRA_PIN_KB_COL0_PQ0,
+ TEGRA_PIN_KB_COL1_PQ1,
+};
+
+static const unsigned kbcd_pins[] = {
+ TEGRA_PIN_KB_ROW3_PR3,
+ TEGRA_PIN_KB_ROW4_PR4,
+ TEGRA_PIN_KB_ROW5_PR5,
+ TEGRA_PIN_KB_ROW6_PR6,
+};
+
+static const unsigned kbce_pins[] = {
+ TEGRA_PIN_KB_COL7_PQ7,
+};
+
+static const unsigned kbcf_pins[] = {
+ TEGRA_PIN_KB_COL2_PQ2,
+ TEGRA_PIN_KB_COL3_PQ3,
+ TEGRA_PIN_KB_COL4_PQ4,
+ TEGRA_PIN_KB_COL5_PQ5,
+ TEGRA_PIN_KB_COL6_PQ6,
+};
+
+static const unsigned lcsn_pins[] = {
+ TEGRA_PIN_LCD_CS0_N_PN4,
+};
+
+static const unsigned ld0_pins[] = {
+ TEGRA_PIN_LCD_D0_PE0,
+};
+
+static const unsigned ld1_pins[] = {
+ TEGRA_PIN_LCD_D1_PE1,
+};
+
+static const unsigned ld2_pins[] = {
+ TEGRA_PIN_LCD_D2_PE2,
+};
+
+static const unsigned ld3_pins[] = {
+ TEGRA_PIN_LCD_D3_PE3,
+};
+
+static const unsigned ld4_pins[] = {
+ TEGRA_PIN_LCD_D4_PE4,
+};
+
+static const unsigned ld5_pins[] = {
+ TEGRA_PIN_LCD_D5_PE5,
+};
+
+static const unsigned ld6_pins[] = {
+ TEGRA_PIN_LCD_D6_PE6,
+};
+
+static const unsigned ld7_pins[] = {
+ TEGRA_PIN_LCD_D7_PE7,
+};
+
+static const unsigned ld8_pins[] = {
+ TEGRA_PIN_LCD_D8_PF0,
+};
+
+static const unsigned ld9_pins[] = {
+ TEGRA_PIN_LCD_D9_PF1,
+};
+
+static const unsigned ld10_pins[] = {
+ TEGRA_PIN_LCD_D10_PF2,
+};
+
+static const unsigned ld11_pins[] = {
+ TEGRA_PIN_LCD_D11_PF3,
+};
+
+static const unsigned ld12_pins[] = {
+ TEGRA_PIN_LCD_D12_PF4,
+};
+
+static const unsigned ld13_pins[] = {
+ TEGRA_PIN_LCD_D13_PF5,
+};
+
+static const unsigned ld14_pins[] = {
+ TEGRA_PIN_LCD_D14_PF6,
+};
+
+static const unsigned ld15_pins[] = {
+ TEGRA_PIN_LCD_D15_PF7,
+};
+
+static const unsigned ld16_pins[] = {
+ TEGRA_PIN_LCD_D16_PM0,
+};
+
+static const unsigned ld17_pins[] = {
+ TEGRA_PIN_LCD_D17_PM1,
+};
+
+static const unsigned ldc_pins[] = {
+ TEGRA_PIN_LCD_DC0_PN6,
+};
+
+static const unsigned ldi_pins[] = {
+ TEGRA_PIN_LCD_D22_PM6,
+};
+
+static const unsigned lhp0_pins[] = {
+ TEGRA_PIN_LCD_D21_PM5,
+};
+
+static const unsigned lhp1_pins[] = {
+ TEGRA_PIN_LCD_D18_PM2,
+};
+
+static const unsigned lhp2_pins[] = {
+ TEGRA_PIN_LCD_D19_PM3,
+};
+
+static const unsigned lhs_pins[] = {
+ TEGRA_PIN_LCD_HSYNC_PJ3,
+};
+
+static const unsigned lm0_pins[] = {
+ TEGRA_PIN_LCD_CS1_N_PW0,
+};
+
+static const unsigned lm1_pins[] = {
+ TEGRA_PIN_LCD_M1_PW1,
+};
+
+static const unsigned lpp_pins[] = {
+ TEGRA_PIN_LCD_D23_PM7,
+};
+
+static const unsigned lpw0_pins[] = {
+ TEGRA_PIN_LCD_PWR0_PB2,
+};
+
+static const unsigned lpw1_pins[] = {
+ TEGRA_PIN_LCD_PWR1_PC1,
+};
+
+static const unsigned lpw2_pins[] = {
+ TEGRA_PIN_LCD_PWR2_PC6,
+};
+
+static const unsigned lsc0_pins[] = {
+ TEGRA_PIN_LCD_PCLK_PB3,
+};
+
+static const unsigned lsc1_pins[] = {
+ TEGRA_PIN_LCD_WR_N_PZ3,
+};
+
+static const unsigned lsck_pins[] = {
+ TEGRA_PIN_LCD_SCK_PZ4,
+};
+
+static const unsigned lsda_pins[] = {
+ TEGRA_PIN_LCD_SDOUT_PN5,
+};
+
+static const unsigned lsdi_pins[] = {
+ TEGRA_PIN_LCD_SDIN_PZ2,
+};
+
+static const unsigned lspi_pins[] = {
+ TEGRA_PIN_LCD_DE_PJ1,
+};
+
+static const unsigned lvp0_pins[] = {
+ TEGRA_PIN_LCD_DC1_PV7,
+};
+
+static const unsigned lvp1_pins[] = {
+ TEGRA_PIN_LCD_D20_PM4,
+};
+
+static const unsigned lvs_pins[] = {
+ TEGRA_PIN_LCD_VSYNC_PJ4,
+};
+
+static const unsigned ls_pins[] = {
+ TEGRA_PIN_LCD_PWR0_PB2,
+ TEGRA_PIN_LCD_PWR1_PC1,
+ TEGRA_PIN_LCD_PWR2_PC6,
+ TEGRA_PIN_LCD_SDIN_PZ2,
+ TEGRA_PIN_LCD_SDOUT_PN5,
+ TEGRA_PIN_LCD_WR_N_PZ3,
+ TEGRA_PIN_LCD_CS0_N_PN4,
+ TEGRA_PIN_LCD_DC0_PN6,
+ TEGRA_PIN_LCD_SCK_PZ4,
+};
+
+static const unsigned lc_pins[] = {
+ TEGRA_PIN_LCD_PCLK_PB3,
+ TEGRA_PIN_LCD_DE_PJ1,
+ TEGRA_PIN_LCD_HSYNC_PJ3,
+ TEGRA_PIN_LCD_VSYNC_PJ4,
+ TEGRA_PIN_LCD_CS1_N_PW0,
+ TEGRA_PIN_LCD_M1_PW1,
+ TEGRA_PIN_LCD_DC1_PV7,
+ TEGRA_PIN_HDMI_INT_N_PN7,
+};
+
+static const unsigned ld17_0_pins[] = {
+ TEGRA_PIN_LCD_D0_PE0,
+ TEGRA_PIN_LCD_D1_PE1,
+ TEGRA_PIN_LCD_D2_PE2,
+ TEGRA_PIN_LCD_D3_PE3,
+ TEGRA_PIN_LCD_D4_PE4,
+ TEGRA_PIN_LCD_D5_PE5,
+ TEGRA_PIN_LCD_D6_PE6,
+ TEGRA_PIN_LCD_D7_PE7,
+ TEGRA_PIN_LCD_D8_PF0,
+ TEGRA_PIN_LCD_D9_PF1,
+ TEGRA_PIN_LCD_D10_PF2,
+ TEGRA_PIN_LCD_D11_PF3,
+ TEGRA_PIN_LCD_D12_PF4,
+ TEGRA_PIN_LCD_D13_PF5,
+ TEGRA_PIN_LCD_D14_PF6,
+ TEGRA_PIN_LCD_D15_PF7,
+ TEGRA_PIN_LCD_D16_PM0,
+ TEGRA_PIN_LCD_D17_PM1,
+};
+
+static const unsigned ld19_18_pins[] = {
+ TEGRA_PIN_LCD_D18_PM2,
+ TEGRA_PIN_LCD_D19_PM3,
+};
+
+static const unsigned ld21_20_pins[] = {
+ TEGRA_PIN_LCD_D20_PM4,
+ TEGRA_PIN_LCD_D21_PM5,
+};
+
+static const unsigned ld23_22_pins[] = {
+ TEGRA_PIN_LCD_D22_PM6,
+ TEGRA_PIN_LCD_D23_PM7,
+};
+
+static const unsigned owc_pins[] = {
+ TEGRA_PIN_OWC,
+};
+
+static const unsigned pmc_pins[] = {
+ TEGRA_PIN_LED_BLINK_PBB0,
+ TEGRA_PIN_SYS_CLK_REQ_PZ5,
+ TEGRA_PIN_CORE_PWR_REQ,
+ TEGRA_PIN_CPU_PWR_REQ,
+ TEGRA_PIN_PWR_INT_N,
+};
+
+static const unsigned pta_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SCL_PT5,
+ TEGRA_PIN_GEN2_I2C_SDA_PT6,
+};
+
+static const unsigned rm_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SCL_PC4,
+ TEGRA_PIN_GEN1_I2C_SDA_PC5,
+};
+
+static const unsigned sdb_pins[] = {
+ TEGRA_PIN_SDIO3_CMD_PA7,
+};
+
+static const unsigned sdc_pins[] = {
+ TEGRA_PIN_SDIO3_DAT0_PB7,
+ TEGRA_PIN_SDIO3_DAT1_PB6,
+ TEGRA_PIN_SDIO3_DAT2_PB5,
+ TEGRA_PIN_SDIO3_DAT3_PB4,
+};
+
+static const unsigned sdd_pins[] = {
+ TEGRA_PIN_SDIO3_CLK_PA6,
+};
+
+static const unsigned sdio1_pins[] = {
+ TEGRA_PIN_SDIO1_CLK_PZ0,
+ TEGRA_PIN_SDIO1_CMD_PZ1,
+ TEGRA_PIN_SDIO1_DAT0_PY7,
+ TEGRA_PIN_SDIO1_DAT1_PY6,
+ TEGRA_PIN_SDIO1_DAT2_PY5,
+ TEGRA_PIN_SDIO1_DAT3_PY4,
+};
+
+static const unsigned slxa_pins[] = {
+ TEGRA_PIN_SDIO3_DAT4_PD1,
+};
+
+static const unsigned slxc_pins[] = {
+ TEGRA_PIN_SDIO3_DAT6_PD3,
+};
+
+static const unsigned slxd_pins[] = {
+ TEGRA_PIN_SDIO3_DAT7_PD4,
+};
+
+static const unsigned slxk_pins[] = {
+ TEGRA_PIN_SDIO3_DAT5_PD0,
+};
+
+static const unsigned spdi_pins[] = {
+ TEGRA_PIN_SPDIF_IN_PK6,
+};
+
+static const unsigned spdo_pins[] = {
+ TEGRA_PIN_SPDIF_OUT_PK5,
+};
+
+static const unsigned spia_pins[] = {
+ TEGRA_PIN_SPI2_MOSI_PX0,
+};
+
+static const unsigned spib_pins[] = {
+ TEGRA_PIN_SPI2_MISO_PX1,
+};
+
+static const unsigned spic_pins[] = {
+ TEGRA_PIN_SPI2_CS0_N_PX3,
+ TEGRA_PIN_SPI2_SCK_PX2,
+};
+
+static const unsigned spid_pins[] = {
+ TEGRA_PIN_SPI1_MOSI_PX4,
+};
+
+static const unsigned spie_pins[] = {
+ TEGRA_PIN_SPI1_CS0_N_PX6,
+ TEGRA_PIN_SPI1_SCK_PX5,
+};
+
+static const unsigned spif_pins[] = {
+ TEGRA_PIN_SPI1_MISO_PX7,
+};
+
+static const unsigned spig_pins[] = {
+ TEGRA_PIN_SPI2_CS1_N_PW2,
+};
+
+static const unsigned spih_pins[] = {
+ TEGRA_PIN_SPI2_CS2_N_PW3,
+};
+
+static const unsigned uaa_pins[] = {
+ TEGRA_PIN_ULPI_DATA0_PO1,
+ TEGRA_PIN_ULPI_DATA1_PO2,
+ TEGRA_PIN_ULPI_DATA2_PO3,
+ TEGRA_PIN_ULPI_DATA3_PO4,
+};
+
+static const unsigned uab_pins[] = {
+ TEGRA_PIN_ULPI_DATA4_PO5,
+ TEGRA_PIN_ULPI_DATA5_PO6,
+ TEGRA_PIN_ULPI_DATA6_PO7,
+ TEGRA_PIN_ULPI_DATA7_PO0,
+};
+
+static const unsigned uac_pins[] = {
+ TEGRA_PIN_PV0,
+ TEGRA_PIN_PV1,
+ TEGRA_PIN_PV2,
+ TEGRA_PIN_PV3,
+};
+
+static const unsigned ck32_pins[] = {
+ TEGRA_PIN_CLK_32_K_IN,
+};
+
+static const unsigned uad_pins[] = {
+ TEGRA_PIN_UART2_RXD_PC3,
+ TEGRA_PIN_UART2_TXD_PC2,
+};
+
+static const unsigned uca_pins[] = {
+ TEGRA_PIN_UART3_RXD_PW7,
+ TEGRA_PIN_UART3_TXD_PW6,
+};
+
+static const unsigned ucb_pins[] = {
+ TEGRA_PIN_UART3_CTS_N_PA1,
+ TEGRA_PIN_UART3_RTS_N_PC0,
+};
+
+static const unsigned uda_pins[] = {
+ TEGRA_PIN_ULPI_CLK_PY0,
+ TEGRA_PIN_ULPI_DIR_PY1,
+ TEGRA_PIN_ULPI_NXT_PY2,
+ TEGRA_PIN_ULPI_STP_PY3,
+};
+
+static const unsigned ddrc_pins[] = {
+ TEGRA_PIN_DDR_COMP_PD,
+ TEGRA_PIN_DDR_COMP_PU,
+};
+
+static const unsigned pmca_pins[] = {
+ TEGRA_PIN_LED_BLINK_PBB0,
+};
+
+static const unsigned pmcb_pins[] = {
+ TEGRA_PIN_SYS_CLK_REQ_PZ5,
+};
+
+static const unsigned pmcc_pins[] = {
+ TEGRA_PIN_CORE_PWR_REQ,
+};
+
+static const unsigned pmcd_pins[] = {
+ TEGRA_PIN_CPU_PWR_REQ,
+};
+
+static const unsigned pmce_pins[] = {
+ TEGRA_PIN_PWR_INT_N,
+};
+
+static const unsigned xm2c_pins[] = {
+ TEGRA_PIN_DDR_A0,
+ TEGRA_PIN_DDR_A1,
+ TEGRA_PIN_DDR_A2,
+ TEGRA_PIN_DDR_A3,
+ TEGRA_PIN_DDR_A4,
+ TEGRA_PIN_DDR_A5,
+ TEGRA_PIN_DDR_A6,
+ TEGRA_PIN_DDR_A7,
+ TEGRA_PIN_DDR_A8,
+ TEGRA_PIN_DDR_A9,
+ TEGRA_PIN_DDR_A10,
+ TEGRA_PIN_DDR_A11,
+ TEGRA_PIN_DDR_A12,
+ TEGRA_PIN_DDR_A13,
+ TEGRA_PIN_DDR_A14,
+ TEGRA_PIN_DDR_CAS_N,
+ TEGRA_PIN_DDR_BA0,
+ TEGRA_PIN_DDR_BA1,
+ TEGRA_PIN_DDR_BA2,
+ TEGRA_PIN_DDR_DQS0P,
+ TEGRA_PIN_DDR_DQS0N,
+ TEGRA_PIN_DDR_DQS1P,
+ TEGRA_PIN_DDR_DQS1N,
+ TEGRA_PIN_DDR_DQS2P,
+ TEGRA_PIN_DDR_DQS2N,
+ TEGRA_PIN_DDR_DQS3P,
+ TEGRA_PIN_DDR_DQS3N,
+ TEGRA_PIN_DDR_CS0_N,
+ TEGRA_PIN_DDR_CS1_N,
+ TEGRA_PIN_DDR_CKE0,
+ TEGRA_PIN_DDR_CKE1,
+ TEGRA_PIN_DDR_CLK,
+ TEGRA_PIN_DDR_CLK_N,
+ TEGRA_PIN_DDR_DM0,
+ TEGRA_PIN_DDR_DM1,
+ TEGRA_PIN_DDR_DM2,
+ TEGRA_PIN_DDR_DM3,
+ TEGRA_PIN_DDR_ODT,
+ TEGRA_PIN_DDR_RAS_N,
+ TEGRA_PIN_DDR_WE_N,
+ TEGRA_PIN_DDR_QUSE0,
+ TEGRA_PIN_DDR_QUSE1,
+ TEGRA_PIN_DDR_QUSE2,
+ TEGRA_PIN_DDR_QUSE3,
+};
+
+static const unsigned xm2d_pins[] = {
+ TEGRA_PIN_DDR_DQ0,
+ TEGRA_PIN_DDR_DQ1,
+ TEGRA_PIN_DDR_DQ2,
+ TEGRA_PIN_DDR_DQ3,
+ TEGRA_PIN_DDR_DQ4,
+ TEGRA_PIN_DDR_DQ5,
+ TEGRA_PIN_DDR_DQ6,
+ TEGRA_PIN_DDR_DQ7,
+ TEGRA_PIN_DDR_DQ8,
+ TEGRA_PIN_DDR_DQ9,
+ TEGRA_PIN_DDR_DQ10,
+ TEGRA_PIN_DDR_DQ11,
+ TEGRA_PIN_DDR_DQ12,
+ TEGRA_PIN_DDR_DQ13,
+ TEGRA_PIN_DDR_DQ14,
+ TEGRA_PIN_DDR_DQ15,
+ TEGRA_PIN_DDR_DQ16,
+ TEGRA_PIN_DDR_DQ17,
+ TEGRA_PIN_DDR_DQ18,
+ TEGRA_PIN_DDR_DQ19,
+ TEGRA_PIN_DDR_DQ20,
+ TEGRA_PIN_DDR_DQ21,
+ TEGRA_PIN_DDR_DQ22,
+ TEGRA_PIN_DDR_DQ23,
+ TEGRA_PIN_DDR_DQ24,
+ TEGRA_PIN_DDR_DQ25,
+ TEGRA_PIN_DDR_DQ26,
+ TEGRA_PIN_DDR_DQ27,
+ TEGRA_PIN_DDR_DQ28,
+ TEGRA_PIN_DDR_DQ29,
+ TEGRA_PIN_DDR_DQ30,
+ TEGRA_PIN_DDR_DQ31,
+};
+
+static const unsigned drive_ao1_pins[] = {
+ TEGRA_PIN_SYS_RESET,
+ TEGRA_PIN_PWR_I2C_SCL_PZ6,
+ TEGRA_PIN_PWR_I2C_SDA_PZ7,
+ TEGRA_PIN_KB_ROW0_PR0,
+ TEGRA_PIN_KB_ROW1_PR1,
+ TEGRA_PIN_KB_ROW2_PR2,
+ TEGRA_PIN_KB_ROW3_PR3,
+ TEGRA_PIN_KB_ROW4_PR4,
+ TEGRA_PIN_KB_ROW5_PR5,
+ TEGRA_PIN_KB_ROW6_PR6,
+ TEGRA_PIN_KB_ROW7_PR7,
+};
+
+static const unsigned drive_ao2_pins[] = {
+ TEGRA_PIN_KB_ROW8_PS0,
+ TEGRA_PIN_KB_ROW9_PS1,
+ TEGRA_PIN_KB_ROW10_PS2,
+ TEGRA_PIN_KB_ROW11_PS3,
+ TEGRA_PIN_KB_ROW12_PS4,
+ TEGRA_PIN_KB_ROW13_PS5,
+ TEGRA_PIN_KB_ROW14_PS6,
+ TEGRA_PIN_KB_ROW15_PS7,
+ TEGRA_PIN_KB_COL0_PQ0,
+ TEGRA_PIN_KB_COL1_PQ1,
+ TEGRA_PIN_KB_COL2_PQ2,
+ TEGRA_PIN_KB_COL3_PQ3,
+ TEGRA_PIN_KB_COL4_PQ4,
+ TEGRA_PIN_KB_COL5_PQ5,
+ TEGRA_PIN_KB_COL6_PQ6,
+ TEGRA_PIN_KB_COL7_PQ7,
+ TEGRA_PIN_LED_BLINK_PBB0,
+ TEGRA_PIN_SYS_CLK_REQ_PZ5,
+ TEGRA_PIN_CORE_PWR_REQ,
+ TEGRA_PIN_CPU_PWR_REQ,
+ TEGRA_PIN_PWR_INT_N,
+ TEGRA_PIN_CLK_32_K_IN,
+};
+
+static const unsigned drive_at1_pins[] = {
+ TEGRA_PIN_GMI_IORDY_PI5,
+ TEGRA_PIN_GMI_AD8_PH0,
+ TEGRA_PIN_GMI_AD9_PH1,
+ TEGRA_PIN_GMI_AD10_PH2,
+ TEGRA_PIN_GMI_AD11_PH3,
+ TEGRA_PIN_GMI_AD12_PH4,
+ TEGRA_PIN_GMI_AD13_PH5,
+ TEGRA_PIN_GMI_AD14_PH6,
+ TEGRA_PIN_GMI_AD15_PH7,
+ TEGRA_PIN_GMI_CS7_N_PI6,
+ TEGRA_PIN_GMI_DPD_PT7,
+ TEGRA_PIN_GEN2_I2C_SCL_PT5,
+ TEGRA_PIN_GEN2_I2C_SDA_PT6,
+};
+
+static const unsigned drive_at2_pins[] = {
+ TEGRA_PIN_GMI_WAIT_PI7,
+ TEGRA_PIN_GMI_ADV_N_PK0,
+ TEGRA_PIN_GMI_CLK_PK1,
+ TEGRA_PIN_GMI_CS6_N_PI3,
+ TEGRA_PIN_GMI_CS5_N_PI2,
+ TEGRA_PIN_GMI_CS4_N_PK2,
+ TEGRA_PIN_GMI_CS3_N_PK4,
+ TEGRA_PIN_GMI_CS2_N_PK3,
+ TEGRA_PIN_GMI_AD0_PG0,
+ TEGRA_PIN_GMI_AD1_PG1,
+ TEGRA_PIN_GMI_AD2_PG2,
+ TEGRA_PIN_GMI_AD3_PG3,
+ TEGRA_PIN_GMI_AD4_PG4,
+ TEGRA_PIN_GMI_AD5_PG5,
+ TEGRA_PIN_GMI_AD6_PG6,
+ TEGRA_PIN_GMI_AD7_PG7,
+ TEGRA_PIN_GMI_HIOW_N_PI0,
+ TEGRA_PIN_GMI_HIOR_N_PI1,
+ TEGRA_PIN_GMI_RST_N_PI4,
+};
+
+static const unsigned drive_cdev1_pins[] = {
+ TEGRA_PIN_DAP_MCLK1_PW4,
+};
+
+static const unsigned drive_cdev2_pins[] = {
+ TEGRA_PIN_DAP_MCLK2_PW5,
+};
+
+static const unsigned drive_csus_pins[] = {
+ TEGRA_PIN_VI_MCLK_PT1,
+};
+
+static const unsigned drive_dap1_pins[] = {
+ TEGRA_PIN_DAP1_FS_PN0,
+ TEGRA_PIN_DAP1_DIN_PN1,
+ TEGRA_PIN_DAP1_DOUT_PN2,
+ TEGRA_PIN_DAP1_SCLK_PN3,
+ TEGRA_PIN_SPDIF_OUT_PK5,
+ TEGRA_PIN_SPDIF_IN_PK6,
+};
+
+static const unsigned drive_dap2_pins[] = {
+ TEGRA_PIN_DAP2_FS_PA2,
+ TEGRA_PIN_DAP2_SCLK_PA3,
+ TEGRA_PIN_DAP2_DIN_PA4,
+ TEGRA_PIN_DAP2_DOUT_PA5,
+};
+
+static const unsigned drive_dap3_pins[] = {
+ TEGRA_PIN_DAP3_FS_PP0,
+ TEGRA_PIN_DAP3_DIN_PP1,
+ TEGRA_PIN_DAP3_DOUT_PP2,
+ TEGRA_PIN_DAP3_SCLK_PP3,
+};
+
+static const unsigned drive_dap4_pins[] = {
+ TEGRA_PIN_DAP4_FS_PP4,
+ TEGRA_PIN_DAP4_DIN_PP5,
+ TEGRA_PIN_DAP4_DOUT_PP6,
+ TEGRA_PIN_DAP4_SCLK_PP7,
+};
+
+static const unsigned drive_dbg_pins[] = {
+ TEGRA_PIN_PU0,
+ TEGRA_PIN_PU1,
+ TEGRA_PIN_PU2,
+ TEGRA_PIN_PU3,
+ TEGRA_PIN_PU4,
+ TEGRA_PIN_PU5,
+ TEGRA_PIN_PU6,
+ TEGRA_PIN_JTAG_RTCK_PU7,
+ TEGRA_PIN_GEN1_I2C_SDA_PC5,
+ TEGRA_PIN_GEN1_I2C_SCL_PC4,
+ TEGRA_PIN_JTAG_TRST_N,
+ TEGRA_PIN_JTAG_TDO,
+ TEGRA_PIN_JTAG_TMS,
+ TEGRA_PIN_JTAG_TCK,
+ TEGRA_PIN_JTAG_TDI,
+ TEGRA_PIN_TEST_MODE_EN,
+};
+
+static const unsigned drive_lcd1_pins[] = {
+ TEGRA_PIN_LCD_PWR1_PC1,
+ TEGRA_PIN_LCD_PWR2_PC6,
+ TEGRA_PIN_LCD_SDIN_PZ2,
+ TEGRA_PIN_LCD_SDOUT_PN5,
+ TEGRA_PIN_LCD_WR_N_PZ3,
+ TEGRA_PIN_LCD_CS0_N_PN4,
+ TEGRA_PIN_LCD_DC0_PN6,
+ TEGRA_PIN_LCD_SCK_PZ4,
+};
+
+static const unsigned drive_lcd2_pins[] = {
+ TEGRA_PIN_LCD_PWR0_PB2,
+ TEGRA_PIN_LCD_PCLK_PB3,
+ TEGRA_PIN_LCD_DE_PJ1,
+ TEGRA_PIN_LCD_HSYNC_PJ3,
+ TEGRA_PIN_LCD_VSYNC_PJ4,
+ TEGRA_PIN_LCD_D0_PE0,
+ TEGRA_PIN_LCD_D1_PE1,
+ TEGRA_PIN_LCD_D2_PE2,
+ TEGRA_PIN_LCD_D3_PE3,
+ TEGRA_PIN_LCD_D4_PE4,
+ TEGRA_PIN_LCD_D5_PE5,
+ TEGRA_PIN_LCD_D6_PE6,
+ TEGRA_PIN_LCD_D7_PE7,
+ TEGRA_PIN_LCD_D8_PF0,
+ TEGRA_PIN_LCD_D9_PF1,
+ TEGRA_PIN_LCD_D10_PF2,
+ TEGRA_PIN_LCD_D11_PF3,
+ TEGRA_PIN_LCD_D12_PF4,
+ TEGRA_PIN_LCD_D13_PF5,
+ TEGRA_PIN_LCD_D14_PF6,
+ TEGRA_PIN_LCD_D15_PF7,
+ TEGRA_PIN_LCD_D16_PM0,
+ TEGRA_PIN_LCD_D17_PM1,
+ TEGRA_PIN_LCD_D18_PM2,
+ TEGRA_PIN_LCD_D19_PM3,
+ TEGRA_PIN_LCD_D20_PM4,
+ TEGRA_PIN_LCD_D21_PM5,
+ TEGRA_PIN_LCD_D22_PM6,
+ TEGRA_PIN_LCD_D23_PM7,
+ TEGRA_PIN_LCD_CS1_N_PW0,
+ TEGRA_PIN_LCD_M1_PW1,
+ TEGRA_PIN_LCD_DC1_PV7,
+ TEGRA_PIN_HDMI_INT_N_PN7,
+};
+
+static const unsigned drive_sdmmc2_pins[] = {
+ TEGRA_PIN_SDIO3_DAT4_PD1,
+ TEGRA_PIN_SDIO3_DAT5_PD0,
+ TEGRA_PIN_SDIO3_DAT6_PD3,
+ TEGRA_PIN_SDIO3_DAT7_PD4,
+};
+
+static const unsigned drive_sdmmc3_pins[] = {
+ TEGRA_PIN_SDIO3_CLK_PA6,
+ TEGRA_PIN_SDIO3_CMD_PA7,
+ TEGRA_PIN_SDIO3_DAT0_PB7,
+ TEGRA_PIN_SDIO3_DAT1_PB6,
+ TEGRA_PIN_SDIO3_DAT2_PB5,
+ TEGRA_PIN_SDIO3_DAT3_PB4,
+ TEGRA_PIN_PV4,
+ TEGRA_PIN_PV5,
+ TEGRA_PIN_PV6,
+};
+
+static const unsigned drive_spi_pins[] = {
+ TEGRA_PIN_SPI2_MOSI_PX0,
+ TEGRA_PIN_SPI2_MISO_PX1,
+ TEGRA_PIN_SPI2_SCK_PX2,
+ TEGRA_PIN_SPI2_CS0_N_PX3,
+ TEGRA_PIN_SPI1_MOSI_PX4,
+ TEGRA_PIN_SPI1_SCK_PX5,
+ TEGRA_PIN_SPI1_CS0_N_PX6,
+ TEGRA_PIN_SPI1_MISO_PX7,
+ TEGRA_PIN_SPI2_CS1_N_PW2,
+ TEGRA_PIN_SPI2_CS2_N_PW3,
+};
+
+static const unsigned drive_uaa_pins[] = {
+ TEGRA_PIN_ULPI_DATA0_PO1,
+ TEGRA_PIN_ULPI_DATA1_PO2,
+ TEGRA_PIN_ULPI_DATA2_PO3,
+ TEGRA_PIN_ULPI_DATA3_PO4,
+};
+
+static const unsigned drive_uab_pins[] = {
+ TEGRA_PIN_ULPI_DATA4_PO5,
+ TEGRA_PIN_ULPI_DATA5_PO6,
+ TEGRA_PIN_ULPI_DATA6_PO7,
+ TEGRA_PIN_ULPI_DATA7_PO0,
+ TEGRA_PIN_PV0,
+ TEGRA_PIN_PV1,
+ TEGRA_PIN_PV2,
+ TEGRA_PIN_PV3,
+};
+
+static const unsigned drive_uart2_pins[] = {
+ TEGRA_PIN_UART2_TXD_PC2,
+ TEGRA_PIN_UART2_RXD_PC3,
+ TEGRA_PIN_UART2_RTS_N_PJ6,
+ TEGRA_PIN_UART2_CTS_N_PJ5,
+};
+
+static const unsigned drive_uart3_pins[] = {
+ TEGRA_PIN_UART3_TXD_PW6,
+ TEGRA_PIN_UART3_RXD_PW7,
+ TEGRA_PIN_UART3_RTS_N_PC0,
+ TEGRA_PIN_UART3_CTS_N_PA1,
+};
+
+static const unsigned drive_vi1_pins[] = {
+ TEGRA_PIN_VI_D0_PT4,
+ TEGRA_PIN_VI_D1_PD5,
+ TEGRA_PIN_VI_D2_PL0,
+ TEGRA_PIN_VI_D3_PL1,
+ TEGRA_PIN_VI_D4_PL2,
+ TEGRA_PIN_VI_D5_PL3,
+ TEGRA_PIN_VI_D6_PL4,
+ TEGRA_PIN_VI_D7_PL5,
+ TEGRA_PIN_VI_D8_PL6,
+ TEGRA_PIN_VI_D9_PL7,
+ TEGRA_PIN_VI_D10_PT2,
+ TEGRA_PIN_VI_D11_PT3,
+ TEGRA_PIN_VI_PCLK_PT0,
+ TEGRA_PIN_VI_VSYNC_PD6,
+ TEGRA_PIN_VI_HSYNC_PD7,
+};
+
+static const unsigned drive_vi2_pins[] = {
+ TEGRA_PIN_VI_GP0_PBB1,
+ TEGRA_PIN_CAM_I2C_SCL_PBB2,
+ TEGRA_PIN_CAM_I2C_SDA_PBB3,
+ TEGRA_PIN_VI_GP3_PBB4,
+ TEGRA_PIN_VI_GP4_PBB5,
+ TEGRA_PIN_VI_GP5_PD2,
+ TEGRA_PIN_VI_GP6_PA0,
+};
+
+static const unsigned drive_xm2a_pins[] = {
+ TEGRA_PIN_DDR_A0,
+ TEGRA_PIN_DDR_A1,
+ TEGRA_PIN_DDR_A2,
+ TEGRA_PIN_DDR_A3,
+ TEGRA_PIN_DDR_A4,
+ TEGRA_PIN_DDR_A5,
+ TEGRA_PIN_DDR_A6,
+ TEGRA_PIN_DDR_A7,
+ TEGRA_PIN_DDR_A8,
+ TEGRA_PIN_DDR_A9,
+ TEGRA_PIN_DDR_A10,
+ TEGRA_PIN_DDR_A11,
+ TEGRA_PIN_DDR_A12,
+ TEGRA_PIN_DDR_A13,
+ TEGRA_PIN_DDR_A14,
+ TEGRA_PIN_DDR_BA0,
+ TEGRA_PIN_DDR_BA1,
+ TEGRA_PIN_DDR_BA2,
+ TEGRA_PIN_DDR_CS0_N,
+ TEGRA_PIN_DDR_CS1_N,
+ TEGRA_PIN_DDR_ODT,
+ TEGRA_PIN_DDR_RAS_N,
+ TEGRA_PIN_DDR_CAS_N,
+ TEGRA_PIN_DDR_WE_N,
+ TEGRA_PIN_DDR_CKE0,
+ TEGRA_PIN_DDR_CKE1,
+};
+
+static const unsigned drive_xm2c_pins[] = {
+ TEGRA_PIN_DDR_DQS0P,
+ TEGRA_PIN_DDR_DQS0N,
+ TEGRA_PIN_DDR_DQS1P,
+ TEGRA_PIN_DDR_DQS1N,
+ TEGRA_PIN_DDR_DQS2P,
+ TEGRA_PIN_DDR_DQS2N,
+ TEGRA_PIN_DDR_DQS3P,
+ TEGRA_PIN_DDR_DQS3N,
+ TEGRA_PIN_DDR_QUSE0,
+ TEGRA_PIN_DDR_QUSE1,
+ TEGRA_PIN_DDR_QUSE2,
+ TEGRA_PIN_DDR_QUSE3,
+};
+
+static const unsigned drive_xm2d_pins[] = {
+ TEGRA_PIN_DDR_DQ0,
+ TEGRA_PIN_DDR_DQ1,
+ TEGRA_PIN_DDR_DQ2,
+ TEGRA_PIN_DDR_DQ3,
+ TEGRA_PIN_DDR_DQ4,
+ TEGRA_PIN_DDR_DQ5,
+ TEGRA_PIN_DDR_DQ6,
+ TEGRA_PIN_DDR_DQ7,
+ TEGRA_PIN_DDR_DQ8,
+ TEGRA_PIN_DDR_DQ9,
+ TEGRA_PIN_DDR_DQ10,
+ TEGRA_PIN_DDR_DQ11,
+ TEGRA_PIN_DDR_DQ12,
+ TEGRA_PIN_DDR_DQ13,
+ TEGRA_PIN_DDR_DQ14,
+ TEGRA_PIN_DDR_DQ15,
+ TEGRA_PIN_DDR_DQ16,
+ TEGRA_PIN_DDR_DQ17,
+ TEGRA_PIN_DDR_DQ18,
+ TEGRA_PIN_DDR_DQ19,
+ TEGRA_PIN_DDR_DQ20,
+ TEGRA_PIN_DDR_DQ21,
+ TEGRA_PIN_DDR_DQ22,
+ TEGRA_PIN_DDR_DQ23,
+ TEGRA_PIN_DDR_DQ24,
+ TEGRA_PIN_DDR_DQ25,
+ TEGRA_PIN_DDR_DQ26,
+ TEGRA_PIN_DDR_DQ27,
+ TEGRA_PIN_DDR_DQ28,
+ TEGRA_PIN_DDR_DQ29,
+ TEGRA_PIN_DDR_DQ30,
+ TEGRA_PIN_DDR_DQ31,
+ TEGRA_PIN_DDR_DM0,
+ TEGRA_PIN_DDR_DM1,
+ TEGRA_PIN_DDR_DM2,
+ TEGRA_PIN_DDR_DM3,
+};
+
+static const unsigned drive_xm2clk_pins[] = {
+ TEGRA_PIN_DDR_CLK,
+ TEGRA_PIN_DDR_CLK_N,
+};
+
+static const unsigned drive_sdio1_pins[] = {
+ TEGRA_PIN_SDIO1_CLK_PZ0,
+ TEGRA_PIN_SDIO1_CMD_PZ1,
+ TEGRA_PIN_SDIO1_DAT0_PY7,
+ TEGRA_PIN_SDIO1_DAT1_PY6,
+ TEGRA_PIN_SDIO1_DAT2_PY5,
+ TEGRA_PIN_SDIO1_DAT3_PY4,
+};
+
+static const unsigned drive_crt_pins[] = {
+ TEGRA_PIN_CRT_HSYNC,
+ TEGRA_PIN_CRT_VSYNC,
+};
+
+static const unsigned drive_ddc_pins[] = {
+ TEGRA_PIN_DDC_SCL,
+ TEGRA_PIN_DDC_SDA,
+};
+
+static const unsigned drive_gma_pins[] = {
+ TEGRA_PIN_GMI_AD20_PAA0,
+ TEGRA_PIN_GMI_AD21_PAA1,
+ TEGRA_PIN_GMI_AD22_PAA2,
+ TEGRA_PIN_GMI_AD23_PAA3,
+};
+
+static const unsigned drive_gmb_pins[] = {
+ TEGRA_PIN_GMI_WP_N_PC7,
+};
+
+static const unsigned drive_gmc_pins[] = {
+ TEGRA_PIN_GMI_AD16_PJ7,
+ TEGRA_PIN_GMI_AD17_PB0,
+ TEGRA_PIN_GMI_AD18_PB1,
+ TEGRA_PIN_GMI_AD19_PK7,
+};
+
+static const unsigned drive_gmd_pins[] = {
+ TEGRA_PIN_GMI_CS0_N_PJ0,
+ TEGRA_PIN_GMI_CS1_N_PJ2,
+};
+
+static const unsigned drive_gme_pins[] = {
+ TEGRA_PIN_GMI_AD24_PAA4,
+ TEGRA_PIN_GMI_AD25_PAA5,
+ TEGRA_PIN_GMI_AD26_PAA6,
+ TEGRA_PIN_GMI_AD27_PAA7,
+};
+
+static const unsigned drive_owr_pins[] = {
+ TEGRA_PIN_OWC,
+};
+
+static const unsigned drive_uda_pins[] = {
+ TEGRA_PIN_ULPI_CLK_PY0,
+ TEGRA_PIN_ULPI_DIR_PY1,
+ TEGRA_PIN_ULPI_NXT_PY2,
+ TEGRA_PIN_ULPI_STP_PY3,
+};
+
+enum tegra_mux {
+ TEGRA_MUX_AHB_CLK,
+ TEGRA_MUX_APB_CLK,
+ TEGRA_MUX_AUDIO_SYNC,
+ TEGRA_MUX_CRT,
+ TEGRA_MUX_DAP1,
+ TEGRA_MUX_DAP2,
+ TEGRA_MUX_DAP3,
+ TEGRA_MUX_DAP4,
+ TEGRA_MUX_DAP5,
+ TEGRA_MUX_DISPLAYA,
+ TEGRA_MUX_DISPLAYB,
+ TEGRA_MUX_EMC_TEST0_DLL,
+ TEGRA_MUX_EMC_TEST1_DLL,
+ TEGRA_MUX_GMI,
+ TEGRA_MUX_GMI_INT,
+ TEGRA_MUX_HDMI,
+ TEGRA_MUX_I2CP,
+ TEGRA_MUX_I2C1,
+ TEGRA_MUX_I2C2,
+ TEGRA_MUX_I2C3,
+ TEGRA_MUX_IDE,
+ TEGRA_MUX_IRDA,
+ TEGRA_MUX_KBC,
+ TEGRA_MUX_MIO,
+ TEGRA_MUX_MIPI_HS,
+ TEGRA_MUX_NAND,
+ TEGRA_MUX_OSC,
+ TEGRA_MUX_OWR,
+ TEGRA_MUX_PCIE,
+ TEGRA_MUX_PLLA_OUT,
+ TEGRA_MUX_PLLC_OUT1,
+ TEGRA_MUX_PLLM_OUT1,
+ TEGRA_MUX_PLLP_OUT2,
+ TEGRA_MUX_PLLP_OUT3,
+ TEGRA_MUX_PLLP_OUT4,
+ TEGRA_MUX_PWM,
+ TEGRA_MUX_PWR_INTR,
+ TEGRA_MUX_PWR_ON,
+ TEGRA_MUX_RSVD1,
+ TEGRA_MUX_RSVD2,
+ TEGRA_MUX_RSVD3,
+ TEGRA_MUX_RSVD4,
+ TEGRA_MUX_RTCK,
+ TEGRA_MUX_SDIO1,
+ TEGRA_MUX_SDIO2,
+ TEGRA_MUX_SDIO3,
+ TEGRA_MUX_SDIO4,
+ TEGRA_MUX_SFLASH,
+ TEGRA_MUX_SPDIF,
+ TEGRA_MUX_SPI1,
+ TEGRA_MUX_SPI2,
+ TEGRA_MUX_SPI2_ALT,
+ TEGRA_MUX_SPI3,
+ TEGRA_MUX_SPI4,
+ TEGRA_MUX_TRACE,
+ TEGRA_MUX_TWC,
+ TEGRA_MUX_UARTA,
+ TEGRA_MUX_UARTB,
+ TEGRA_MUX_UARTC,
+ TEGRA_MUX_UARTD,
+ TEGRA_MUX_UARTE,
+ TEGRA_MUX_ULPI,
+ TEGRA_MUX_VI,
+ TEGRA_MUX_VI_SENSOR_CLK,
+ TEGRA_MUX_XIO,
+};
+
+#define FUNCTION(fname) \
+ { \
+ .name = #fname, \
+ }
+
+static struct tegra_function tegra20_functions[] = {
+ FUNCTION(ahb_clk),
+ FUNCTION(apb_clk),
+ FUNCTION(audio_sync),
+ FUNCTION(crt),
+ FUNCTION(dap1),
+ FUNCTION(dap2),
+ FUNCTION(dap3),
+ FUNCTION(dap4),
+ FUNCTION(dap5),
+ FUNCTION(displaya),
+ FUNCTION(displayb),
+ FUNCTION(emc_test0_dll),
+ FUNCTION(emc_test1_dll),
+ FUNCTION(gmi),
+ FUNCTION(gmi_int),
+ FUNCTION(hdmi),
+ FUNCTION(i2cp),
+ FUNCTION(i2c1),
+ FUNCTION(i2c2),
+ FUNCTION(i2c3),
+ FUNCTION(ide),
+ FUNCTION(irda),
+ FUNCTION(kbc),
+ FUNCTION(mio),
+ FUNCTION(mipi_hs),
+ FUNCTION(nand),
+ FUNCTION(osc),
+ FUNCTION(owr),
+ FUNCTION(pcie),
+ FUNCTION(plla_out),
+ FUNCTION(pllc_out1),
+ FUNCTION(pllm_out1),
+ FUNCTION(pllp_out2),
+ FUNCTION(pllp_out3),
+ FUNCTION(pllp_out4),
+ FUNCTION(pwm),
+ FUNCTION(pwr_intr),
+ FUNCTION(pwr_on),
+ FUNCTION(rsvd1),
+ FUNCTION(rsvd2),
+ FUNCTION(rsvd3),
+ FUNCTION(rsvd4),
+ FUNCTION(rtck),
+ FUNCTION(sdio1),
+ FUNCTION(sdio2),
+ FUNCTION(sdio3),
+ FUNCTION(sdio4),
+ FUNCTION(sflash),
+ FUNCTION(spdif),
+ FUNCTION(spi1),
+ FUNCTION(spi2),
+ FUNCTION(spi2_alt),
+ FUNCTION(spi3),
+ FUNCTION(spi4),
+ FUNCTION(trace),
+ FUNCTION(twc),
+ FUNCTION(uarta),
+ FUNCTION(uartb),
+ FUNCTION(uartc),
+ FUNCTION(uartd),
+ FUNCTION(uarte),
+ FUNCTION(ulpi),
+ FUNCTION(vi),
+ FUNCTION(vi_sensor_clk),
+ FUNCTION(xio),
+};
+
+#define TRISTATE_REG_A 0x14
+#define PIN_MUX_CTL_REG_A 0x80
+#define PULLUPDOWN_REG_A 0xa0
+#define PINGROUP_REG_A 0x868
+
+/* Pin group with mux control, and typically tri-state and pull-up/down too */
+#define MUX_PG(pg_name, f0, f1, f2, f3, \
+ tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .funcs = { \
+ TEGRA_MUX_ ## f0, \
+ TEGRA_MUX_ ## f1, \
+ TEGRA_MUX_ ## f2, \
+ TEGRA_MUX_ ## f3, \
+ }, \
+ .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
+ .mux_bank = 1, \
+ .mux_bit = mux_b, \
+ .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
+ .pupd_bank = 2, \
+ .pupd_bit = pupd_b, \
+ .tri_reg = ((tri_r) - TRISTATE_REG_A), \
+ .tri_bank = 0, \
+ .tri_bit = tri_b, \
+ .einput_bit = -1, \
+ .odrain_bit = -1, \
+ .lock_bit = -1, \
+ .ioreset_bit = -1, \
+ .rcv_sel_bit = -1, \
+ .drv_reg = -1, \
+ }
+
+/* Pin groups with only pull up and pull down control */
+#define PULL_PG(pg_name, pupd_r, pupd_b) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .mux_reg = -1, \
+ .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
+ .pupd_bank = 2, \
+ .pupd_bit = pupd_b, \
+ .drv_reg = -1, \
+ }
+
+/* Pin groups for drive strength registers (configurable version) */
+#define DRV_PG_EXT(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
+ drvdn_b, drvup_b, \
+ slwr_b, slwr_w, slwf_b, slwf_w) \
+ { \
+ .name = "drive_" #pg_name, \
+ .pins = drive_##pg_name##_pins, \
+ .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
+ .mux_reg = -1, \
+ .pupd_reg = -1, \
+ .tri_reg = -1, \
+ .drv_reg = ((r) - PINGROUP_REG_A), \
+ .drv_bank = 3, \
+ .hsm_bit = hsm_b, \
+ .schmitt_bit = schmitt_b, \
+ .lpmd_bit = lpmd_b, \
+ .drvdn_bit = drvdn_b, \
+ .drvdn_width = 5, \
+ .drvup_bit = drvup_b, \
+ .drvup_width = 5, \
+ .slwr_bit = slwr_b, \
+ .slwr_width = slwr_w, \
+ .slwf_bit = slwf_b, \
+ .slwf_width = slwf_w, \
+ .drvtype_bit = -1, \
+ }
+
+/* Pin groups for drive strength registers (simple version) */
+#define DRV_PG(pg_name, r) \
+ DRV_PG_EXT(pg_name, r, 2, 3, 4, 12, 20, 28, 2, 30, 2)
+
+static const struct tegra_pingroup tegra20_groups[] = {
+ /* name, f0, f1, f2, f3, tri r/b, mux r/b, pupd r/b */
+ MUX_PG(ata, IDE, NAND, GMI, RSVD4, 0x14, 0, 0x80, 24, 0xa0, 0),
+ MUX_PG(atb, IDE, NAND, GMI, SDIO4, 0x14, 1, 0x80, 16, 0xa0, 2),
+ MUX_PG(atc, IDE, NAND, GMI, SDIO4, 0x14, 2, 0x80, 22, 0xa0, 4),
+ MUX_PG(atd, IDE, NAND, GMI, SDIO4, 0x14, 3, 0x80, 20, 0xa0, 6),
+ MUX_PG(ate, IDE, NAND, GMI, RSVD4, 0x18, 25, 0x80, 12, 0xa0, 8),
+ MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, 0x14, 4, 0x88, 2, 0xa8, 0),
+ MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, 0x14, 5, 0x88, 4, 0xa8, 2),
+ MUX_PG(crtp, CRT, RSVD2, RSVD3, RSVD4, 0x20, 14, 0x98, 20, 0xa4, 24),
+ MUX_PG(csus, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, 0x14, 6, 0x88, 6, 0xac, 24),
+ MUX_PG(dap1, DAP1, RSVD2, GMI, SDIO2, 0x14, 7, 0x88, 20, 0xa0, 10),
+ MUX_PG(dap2, DAP2, TWC, RSVD3, GMI, 0x14, 8, 0x88, 22, 0xa0, 12),
+ MUX_PG(dap3, DAP3, RSVD2, RSVD3, RSVD4, 0x14, 9, 0x88, 24, 0xa0, 14),
+ MUX_PG(dap4, DAP4, RSVD2, GMI, RSVD4, 0x14, 10, 0x88, 26, 0xa0, 16),
+ MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28),
+ MUX_PG(dta, RSVD1, SDIO2, VI, RSVD4, 0x14, 11, 0x84, 20, 0xa0, 18),
+ MUX_PG(dtb, RSVD1, RSVD2, VI, SPI1, 0x14, 12, 0x84, 22, 0xa0, 20),
+ MUX_PG(dtc, RSVD1, RSVD2, VI, RSVD4, 0x14, 13, 0x84, 26, 0xa0, 22),
+ MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, 0x14, 14, 0x84, 28, 0xa0, 24),
+ MUX_PG(dte, RSVD1, RSVD2, VI, SPI1, 0x14, 15, 0x84, 30, 0xa0, 26),
+ MUX_PG(dtf, I2C3, RSVD2, VI, RSVD4, 0x20, 12, 0x98, 30, 0xa0, 28),
+ MUX_PG(gma, UARTE, SPI3, GMI, SDIO4, 0x14, 28, 0x84, 0, 0xb0, 20),
+ MUX_PG(gmb, IDE, NAND, GMI, GMI_INT, 0x18, 29, 0x88, 28, 0xb0, 22),
+ MUX_PG(gmc, UARTD, SPI4, GMI, SFLASH, 0x14, 29, 0x84, 2, 0xb0, 24),
+ MUX_PG(gmd, RSVD1, NAND, GMI, SFLASH, 0x18, 30, 0x88, 30, 0xb0, 26),
+ MUX_PG(gme, RSVD1, DAP5, GMI, SDIO4, 0x18, 0, 0x8c, 0, 0xa8, 24),
+ MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20),
+ MUX_PG(gpu7, RTCK, RSVD2, RSVD3, RSVD4, 0x20, 11, 0x98, 28, 0xa4, 6),
+ MUX_PG(gpv, PCIE, RSVD2, RSVD3, RSVD4, 0x14, 17, 0x8c, 2, 0xa0, 30),
+ MUX_PG(hdint, HDMI, RSVD2, RSVD3, RSVD4, 0x1c, 23, 0x84, 4, -1, -1),
+ MUX_PG(i2cp, I2CP, RSVD2, RSVD3, RSVD4, 0x14, 18, 0x88, 8, 0xa4, 2),
+ MUX_PG(irrx, UARTA, UARTB, GMI, SPI4, 0x14, 20, 0x88, 18, 0xa8, 22),
+ MUX_PG(irtx, UARTA, UARTB, GMI, SPI4, 0x14, 19, 0x88, 16, 0xa8, 20),
+ MUX_PG(kbca, KBC, NAND, SDIO2, EMC_TEST0_DLL, 0x14, 22, 0x88, 10, 0xa4, 8),
+ MUX_PG(kbcb, KBC, NAND, SDIO2, MIO, 0x14, 21, 0x88, 12, 0xa4, 10),
+ MUX_PG(kbcc, KBC, NAND, TRACE, EMC_TEST1_DLL, 0x18, 26, 0x88, 14, 0xa4, 12),
+ MUX_PG(kbcd, KBC, NAND, SDIO2, MIO, 0x20, 10, 0x98, 26, 0xa4, 14),
+ MUX_PG(kbce, KBC, NAND, OWR, RSVD4, 0x14, 26, 0x80, 28, 0xb0, 2),
+ MUX_PG(kbcf, KBC, NAND, TRACE, MIO, 0x14, 27, 0x80, 26, 0xb0, 0),
+ MUX_PG(lcsn, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 31, 0x90, 12, -1, -1),
+ MUX_PG(ld0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 0, 0x94, 0, -1, -1),
+ MUX_PG(ld1, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 1, 0x94, 2, -1, -1),
+ MUX_PG(ld2, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 2, 0x94, 4, -1, -1),
+ MUX_PG(ld3, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 3, 0x94, 6, -1, -1),
+ MUX_PG(ld4, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 4, 0x94, 8, -1, -1),
+ MUX_PG(ld5, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 5, 0x94, 10, -1, -1),
+ MUX_PG(ld6, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 6, 0x94, 12, -1, -1),
+ MUX_PG(ld7, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 7, 0x94, 14, -1, -1),
+ MUX_PG(ld8, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 8, 0x94, 16, -1, -1),
+ MUX_PG(ld9, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 9, 0x94, 18, -1, -1),
+ MUX_PG(ld10, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 10, 0x94, 20, -1, -1),
+ MUX_PG(ld11, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 11, 0x94, 22, -1, -1),
+ MUX_PG(ld12, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 12, 0x94, 24, -1, -1),
+ MUX_PG(ld13, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 13, 0x94, 26, -1, -1),
+ MUX_PG(ld14, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 14, 0x94, 28, -1, -1),
+ MUX_PG(ld15, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 15, 0x94, 30, -1, -1),
+ MUX_PG(ld16, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 16, 0x98, 0, -1, -1),
+ MUX_PG(ld17, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 17, 0x98, 2, -1, -1),
+ MUX_PG(ldc, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 30, 0x90, 14, -1, -1),
+ MUX_PG(ldi, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 6, 0x98, 16, -1, -1),
+ MUX_PG(lhp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 18, 0x98, 10, -1, -1),
+ MUX_PG(lhp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 19, 0x98, 4, -1, -1),
+ MUX_PG(lhp2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 20, 0x98, 6, -1, -1),
+ MUX_PG(lhs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x20, 7, 0x90, 22, -1, -1),
+ MUX_PG(lm0, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 24, 0x90, 26, -1, -1),
+ MUX_PG(lm1, DISPLAYA, DISPLAYB, RSVD3, CRT, 0x1c, 25, 0x90, 28, -1, -1),
+ MUX_PG(lpp, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 8, 0x98, 14, -1, -1),
+ MUX_PG(lpw0, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 3, 0x90, 0, -1, -1),
+ MUX_PG(lpw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 4, 0x90, 2, -1, -1),
+ MUX_PG(lpw2, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 5, 0x90, 4, -1, -1),
+ MUX_PG(lsc0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 27, 0x90, 18, -1, -1),
+ MUX_PG(lsc1, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 28, 0x90, 20, -1, -1),
+ MUX_PG(lsck, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 29, 0x90, 16, -1, -1),
+ MUX_PG(lsda, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 1, 0x90, 8, -1, -1),
+ MUX_PG(lsdi, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x20, 2, 0x90, 6, -1, -1),
+ MUX_PG(lspi, DISPLAYA, DISPLAYB, XIO, HDMI, 0x20, 0, 0x90, 10, -1, -1),
+ MUX_PG(lvp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 21, 0x90, 30, -1, -1),
+ MUX_PG(lvp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 22, 0x98, 8, -1, -1),
+ MUX_PG(lvs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 26, 0x90, 24, -1, -1),
+ MUX_PG(owc, OWR, RSVD2, RSVD3, RSVD4, 0x14, 31, 0x84, 8, 0xb0, 30),
+ MUX_PG(pmc, PWR_ON, PWR_INTR, RSVD3, RSVD4, 0x14, 23, 0x98, 18, -1, -1),
+ MUX_PG(pta, I2C2, HDMI, GMI, RSVD4, 0x14, 24, 0x98, 22, 0xa4, 4),
+ MUX_PG(rm, I2C1, RSVD2, RSVD3, RSVD4, 0x14, 25, 0x80, 14, 0xa4, 0),
+ MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, 0x20, 15, 0x8c, 10, -1, -1),
+ MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, 0x18, 1, 0x8c, 12, 0xac, 28),
+ MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, 0x18, 2, 0x8c, 14, 0xac, 30),
+ MUX_PG(sdio1, SDIO1, RSVD2, UARTE, UARTA, 0x14, 30, 0x80, 30, 0xb0, 18),
+ MUX_PG(slxa, PCIE, SPI4, SDIO3, SPI2, 0x18, 3, 0x84, 6, 0xa4, 22),
+ MUX_PG(slxc, SPDIF, SPI4, SDIO3, SPI2, 0x18, 5, 0x84, 10, 0xa4, 26),
+ MUX_PG(slxd, SPDIF, SPI4, SDIO3, SPI2, 0x18, 6, 0x84, 12, 0xa4, 28),
+ MUX_PG(slxk, PCIE, SPI4, SDIO3, SPI2, 0x18, 7, 0x84, 14, 0xa4, 30),
+ MUX_PG(spdi, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 8, 0x8c, 8, 0xa4, 16),
+ MUX_PG(spdo, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 9, 0x8c, 6, 0xa4, 18),
+ MUX_PG(spia, SPI1, SPI2, SPI3, GMI, 0x18, 10, 0x8c, 30, 0xa8, 4),
+ MUX_PG(spib, SPI1, SPI2, SPI3, GMI, 0x18, 11, 0x8c, 28, 0xa8, 6),
+ MUX_PG(spic, SPI1, SPI2, SPI3, GMI, 0x18, 12, 0x8c, 26, 0xa8, 8),
+ MUX_PG(spid, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 13, 0x8c, 24, 0xa8, 10),
+ MUX_PG(spie, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 14, 0x8c, 22, 0xa8, 12),
+ MUX_PG(spif, SPI3, SPI1, SPI2, RSVD4, 0x18, 15, 0x8c, 20, 0xa8, 14),
+ MUX_PG(spig, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 16, 0x8c, 18, 0xa8, 16),
+ MUX_PG(spih, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 17, 0x8c, 16, 0xa8, 18),
+ MUX_PG(uaa, SPI3, MIPI_HS, UARTA, ULPI, 0x18, 18, 0x80, 0, 0xac, 0),
+ MUX_PG(uab, SPI2, MIPI_HS, UARTA, ULPI, 0x18, 19, 0x80, 2, 0xac, 2),
+ MUX_PG(uac, OWR, RSVD2, RSVD3, RSVD4, 0x18, 20, 0x80, 4, 0xac, 4),
+ MUX_PG(uad, IRDA, SPDIF, UARTA, SPI4, 0x18, 21, 0x80, 6, 0xac, 6),
+ MUX_PG(uca, UARTC, RSVD2, GMI, RSVD4, 0x18, 22, 0x84, 16, 0xac, 8),
+ MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10),
+ MUX_PG(uda, SPI1, RSVD2, UARTD, ULPI, 0x20, 13, 0x80, 8, 0xb0, 16),
+ /* pg_name, pupd_r/b */
+ PULL_PG(ck32, 0xb0, 14),
+ PULL_PG(ddrc, 0xac, 26),
+ PULL_PG(pmca, 0xb0, 4),
+ PULL_PG(pmcb, 0xb0, 6),
+ PULL_PG(pmcc, 0xb0, 8),
+ PULL_PG(pmcd, 0xb0, 10),
+ PULL_PG(pmce, 0xb0, 12),
+ PULL_PG(xm2c, 0xa8, 30),
+ PULL_PG(xm2d, 0xa8, 28),
+ PULL_PG(ls, 0xac, 20),
+ PULL_PG(lc, 0xac, 22),
+ PULL_PG(ld17_0, 0xac, 12),
+ PULL_PG(ld19_18, 0xac, 14),
+ PULL_PG(ld21_20, 0xac, 16),
+ PULL_PG(ld23_22, 0xac, 18),
+ /* pg_name, r */
+ DRV_PG(ao1, 0x868),
+ DRV_PG(ao2, 0x86c),
+ DRV_PG(at1, 0x870),
+ DRV_PG(at2, 0x874),
+ DRV_PG(cdev1, 0x878),
+ DRV_PG(cdev2, 0x87c),
+ DRV_PG(csus, 0x880),
+ DRV_PG(dap1, 0x884),
+ DRV_PG(dap2, 0x888),
+ DRV_PG(dap3, 0x88c),
+ DRV_PG(dap4, 0x890),
+ DRV_PG(dbg, 0x894),
+ DRV_PG(lcd1, 0x898),
+ DRV_PG(lcd2, 0x89c),
+ DRV_PG(sdmmc2, 0x8a0),
+ DRV_PG(sdmmc3, 0x8a4),
+ DRV_PG(spi, 0x8a8),
+ DRV_PG(uaa, 0x8ac),
+ DRV_PG(uab, 0x8b0),
+ DRV_PG(uart2, 0x8b4),
+ DRV_PG(uart3, 0x8b8),
+ DRV_PG(vi1, 0x8bc),
+ DRV_PG(vi2, 0x8c0),
+ /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvup_b, slwr_b, slwr_w, slwf_b, slwf_w */
+ DRV_PG_EXT(xm2a, 0x8c4, -1, -1, 4, 14, 19, 24, 4, 28, 4),
+ DRV_PG_EXT(xm2c, 0x8c8, -1, 3, -1, 14, 19, 24, 4, 28, 4),
+ DRV_PG_EXT(xm2d, 0x8cc, -1, 3, -1, 14, 19, 24, 4, 28, 4),
+ DRV_PG_EXT(xm2clk, 0x8d0, -1, -1, -1, 14, 19, 24, 4, 28, 4),
+ /* pg_name, r */
+ DRV_PG(sdio1, 0x8e0),
+ DRV_PG(crt, 0x8ec),
+ DRV_PG(ddc, 0x8f0),
+ DRV_PG(gma, 0x8f4),
+ DRV_PG(gmb, 0x8f8),
+ DRV_PG(gmc, 0x8fc),
+ DRV_PG(gmd, 0x900),
+ DRV_PG(gme, 0x904),
+ DRV_PG(owr, 0x908),
+ DRV_PG(uda, 0x90c),
+};
+
+static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
+ .ngpios = NUM_GPIOS,
+ .pins = tegra20_pins,
+ .npins = ARRAY_SIZE(tegra20_pins),
+ .functions = tegra20_functions,
+ .nfunctions = ARRAY_SIZE(tegra20_functions),
+ .groups = tegra20_groups,
+ .ngroups = ARRAY_SIZE(tegra20_groups),
+ .hsm_in_mux = false,
+ .schmitt_in_mux = false,
+ .drvtype_in_mux = false,
+};
+
+static int tegra20_pinctrl_probe(struct platform_device *pdev)
+{
+ return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
+}
+
+static const struct of_device_id tegra20_pinctrl_of_match[] = {
+ { .compatible = "nvidia,tegra20-pinmux", },
+ { },
+};
+
+static struct platform_driver tegra20_pinctrl_driver = {
+ .driver = {
+ .name = "tegra20-pinctrl",
+ .of_match_table = tegra20_pinctrl_of_match,
+ },
+ .probe = tegra20_pinctrl_probe,
+ .remove = tegra_pinctrl_remove,
+};
+module_platform_driver(tegra20_pinctrl_driver);
+
+MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, tegra20_pinctrl_of_match);
--- /dev/null
+/*
+ * Pinctrl data for the NVIDIA Tegra210 pinmux
+ *
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "pinctrl-tegra.h"
+
+/*
+ * Most pins affected by the pinmux can also be GPIOs. Define these first.
+ * These must match how the GPIO driver names/numbers its pins.
+ */
+#define _GPIO(offset) (offset)
+
+#define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0)
+#define TEGRA_PIN_PEX_L0_CLKREQ_N_PA1 _GPIO(1)
+#define TEGRA_PIN_PEX_WAKE_N_PA2 _GPIO(2)
+#define TEGRA_PIN_PEX_L1_RST_N_PA3 _GPIO(3)
+#define TEGRA_PIN_PEX_L1_CLKREQ_N_PA4 _GPIO(4)
+#define TEGRA_PIN_SATA_LED_ACTIVE_PA5 _GPIO(5)
+#define TEGRA_PIN_PA6 _GPIO(6)
+#define TEGRA_PIN_DAP1_FS_PB0 _GPIO(8)
+#define TEGRA_PIN_DAP1_DIN_PB1 _GPIO(9)
+#define TEGRA_PIN_DAP1_DOUT_PB2 _GPIO(10)
+#define TEGRA_PIN_DAP1_SCLK_PB3 _GPIO(11)
+#define TEGRA_PIN_SPI2_MOSI_PB4 _GPIO(12)
+#define TEGRA_PIN_SPI2_MISO_PB5 _GPIO(13)
+#define TEGRA_PIN_SPI2_SCK_PB6 _GPIO(14)
+#define TEGRA_PIN_SPI2_CS0_PB7 _GPIO(15)
+#define TEGRA_PIN_SPI1_MOSI_PC0 _GPIO(16)
+#define TEGRA_PIN_SPI1_MISO_PC1 _GPIO(17)
+#define TEGRA_PIN_SPI1_SCK_PC2 _GPIO(18)
+#define TEGRA_PIN_SPI1_CS0_PC3 _GPIO(19)
+#define TEGRA_PIN_SPI1_CS1_PC4 _GPIO(20)
+#define TEGRA_PIN_SPI4_SCK_PC5 _GPIO(21)
+#define TEGRA_PIN_SPI4_CS0_PC6 _GPIO(22)
+#define TEGRA_PIN_SPI4_MOSI_PC7 _GPIO(23)
+#define TEGRA_PIN_SPI4_MISO_PD0 _GPIO(24)
+#define TEGRA_PIN_UART3_TX_PD1 _GPIO(25)
+#define TEGRA_PIN_UART3_RX_PD2 _GPIO(26)
+#define TEGRA_PIN_UART3_RTS_PD3 _GPIO(27)
+#define TEGRA_PIN_UART3_CTS_PD4 _GPIO(28)
+#define TEGRA_PIN_DMIC1_CLK_PE0 _GPIO(32)
+#define TEGRA_PIN_DMIC1_DAT_PE1 _GPIO(33)
+#define TEGRA_PIN_DMIC2_CLK_PE2 _GPIO(34)
+#define TEGRA_PIN_DMIC2_DAT_PE3 _GPIO(35)
+#define TEGRA_PIN_DMIC3_CLK_PE4 _GPIO(36)
+#define TEGRA_PIN_DMIC3_DAT_PE5 _GPIO(37)
+#define TEGRA_PIN_PE6 _GPIO(38)
+#define TEGRA_PIN_PE7 _GPIO(39)
+#define TEGRA_PIN_GEN3_I2C_SCL_PF0 _GPIO(40)
+#define TEGRA_PIN_GEN3_I2C_SDA_PF1 _GPIO(41)
+#define TEGRA_PIN_UART2_TX_PG0 _GPIO(48)
+#define TEGRA_PIN_UART2_RX_PG1 _GPIO(49)
+#define TEGRA_PIN_UART2_RTS_PG2 _GPIO(50)
+#define TEGRA_PIN_UART2_CTS_PG3 _GPIO(51)
+#define TEGRA_PIN_WIFI_EN_PH0 _GPIO(56)
+#define TEGRA_PIN_WIFI_RST_PH1 _GPIO(57)
+#define TEGRA_PIN_WIFI_WAKE_AP_PH2 _GPIO(58)
+#define TEGRA_PIN_AP_WAKE_BT_PH3 _GPIO(59)
+#define TEGRA_PIN_BT_RST_PH4 _GPIO(60)
+#define TEGRA_PIN_BT_WAKE_AP_PH5 _GPIO(61)
+#define TEGRA_PIN_PH6 _GPIO(62)
+#define TEGRA_PIN_AP_WAKE_NFC_PH7 _GPIO(63)
+#define TEGRA_PIN_NFC_EN_PI0 _GPIO(64)
+#define TEGRA_PIN_NFC_INT_PI1 _GPIO(65)
+#define TEGRA_PIN_GPS_EN_PI2 _GPIO(66)
+#define TEGRA_PIN_GPS_RST_PI3 _GPIO(67)
+#define TEGRA_PIN_UART4_TX_PI4 _GPIO(68)
+#define TEGRA_PIN_UART4_RX_PI5 _GPIO(69)
+#define TEGRA_PIN_UART4_RTS_PI6 _GPIO(70)
+#define TEGRA_PIN_UART4_CTS_PI7 _GPIO(71)
+#define TEGRA_PIN_GEN1_I2C_SDA_PJ0 _GPIO(72)
+#define TEGRA_PIN_GEN1_I2C_SCL_PJ1 _GPIO(73)
+#define TEGRA_PIN_GEN2_I2C_SCL_PJ2 _GPIO(74)
+#define TEGRA_PIN_GEN2_I2C_SDA_PJ3 _GPIO(75)
+#define TEGRA_PIN_DAP4_FS_PJ4 _GPIO(76)
+#define TEGRA_PIN_DAP4_DIN_PJ5 _GPIO(77)
+#define TEGRA_PIN_DAP4_DOUT_PJ6 _GPIO(78)
+#define TEGRA_PIN_DAP4_SCLK_PJ7 _GPIO(79)
+#define TEGRA_PIN_PK0 _GPIO(80)
+#define TEGRA_PIN_PK1 _GPIO(81)
+#define TEGRA_PIN_PK2 _GPIO(82)
+#define TEGRA_PIN_PK3 _GPIO(83)
+#define TEGRA_PIN_PK4 _GPIO(84)
+#define TEGRA_PIN_PK5 _GPIO(85)
+#define TEGRA_PIN_PK6 _GPIO(86)
+#define TEGRA_PIN_PK7 _GPIO(87)
+#define TEGRA_PIN_PL0 _GPIO(88)
+#define TEGRA_PIN_PL1 _GPIO(89)
+#define TEGRA_PIN_SDMMC1_CLK_PM0 _GPIO(96)
+#define TEGRA_PIN_SDMMC1_CMD_PM1 _GPIO(97)
+#define TEGRA_PIN_SDMMC1_DAT3_PM2 _GPIO(98)
+#define TEGRA_PIN_SDMMC1_DAT2_PM3 _GPIO(99)
+#define TEGRA_PIN_SDMMC1_DAT1_PM4 _GPIO(100)
+#define TEGRA_PIN_SDMMC1_DAT0_PM5 _GPIO(101)
+#define TEGRA_PIN_SDMMC3_CLK_PP0 _GPIO(120)
+#define TEGRA_PIN_SDMMC3_CMD_PP1 _GPIO(121)
+#define TEGRA_PIN_SDMMC3_DAT3_PP2 _GPIO(122)
+#define TEGRA_PIN_SDMMC3_DAT2_PP3 _GPIO(123)
+#define TEGRA_PIN_SDMMC3_DAT1_PP4 _GPIO(124)
+#define TEGRA_PIN_SDMMC3_DAT0_PP5 _GPIO(125)
+#define TEGRA_PIN_CAM1_MCLK_PS0 _GPIO(144)
+#define TEGRA_PIN_CAM2_MCLK_PS1 _GPIO(145)
+#define TEGRA_PIN_CAM_I2C_SCL_PS2 _GPIO(146)
+#define TEGRA_PIN_CAM_I2C_SDA_PS3 _GPIO(147)
+#define TEGRA_PIN_CAM_RST_PS4 _GPIO(148)
+#define TEGRA_PIN_CAM_AF_EN_PS5 _GPIO(149)
+#define TEGRA_PIN_CAM_FLASH_EN_PS6 _GPIO(150)
+#define TEGRA_PIN_CAM1_PWDN_PS7 _GPIO(151)
+#define TEGRA_PIN_CAM2_PWDN_PT0 _GPIO(152)
+#define TEGRA_PIN_CAM1_STROBE_PT1 _GPIO(153)
+#define TEGRA_PIN_UART1_TX_PU0 _GPIO(160)
+#define TEGRA_PIN_UART1_RX_PU1 _GPIO(161)
+#define TEGRA_PIN_UART1_RTS_PU2 _GPIO(162)
+#define TEGRA_PIN_UART1_CTS_PU3 _GPIO(163)
+#define TEGRA_PIN_LCD_BL_PWM_PV0 _GPIO(168)
+#define TEGRA_PIN_LCD_BL_EN_PV1 _GPIO(169)
+#define TEGRA_PIN_LCD_RST_PV2 _GPIO(170)
+#define TEGRA_PIN_LCD_GPIO1_PV3 _GPIO(171)
+#define TEGRA_PIN_LCD_GPIO2_PV4 _GPIO(172)
+#define TEGRA_PIN_AP_READY_PV5 _GPIO(173)
+#define TEGRA_PIN_TOUCH_RST_PV6 _GPIO(174)
+#define TEGRA_PIN_TOUCH_CLK_PV7 _GPIO(175)
+#define TEGRA_PIN_MODEM_WAKE_AP_PX0 _GPIO(184)
+#define TEGRA_PIN_TOUCH_INT_PX1 _GPIO(185)
+#define TEGRA_PIN_MOTION_INT_PX2 _GPIO(186)
+#define TEGRA_PIN_ALS_PROX_INT_PX3 _GPIO(187)
+#define TEGRA_PIN_TEMP_ALERT_PX4 _GPIO(188)
+#define TEGRA_PIN_BUTTON_POWER_ON_PX5 _GPIO(189)
+#define TEGRA_PIN_BUTTON_VOL_UP_PX6 _GPIO(190)
+#define TEGRA_PIN_BUTTON_VOL_DOWN_PX7 _GPIO(191)
+#define TEGRA_PIN_BUTTON_SLIDE_SW_PY0 _GPIO(192)
+#define TEGRA_PIN_BUTTON_HOME_PY1 _GPIO(193)
+#define TEGRA_PIN_LCD_TE_PY2 _GPIO(194)
+#define TEGRA_PIN_PWR_I2C_SCL_PY3 _GPIO(195)
+#define TEGRA_PIN_PWR_I2C_SDA_PY4 _GPIO(196)
+#define TEGRA_PIN_CLK_32K_OUT_PY5 _GPIO(197)
+#define TEGRA_PIN_PZ0 _GPIO(200)
+#define TEGRA_PIN_PZ1 _GPIO(201)
+#define TEGRA_PIN_PZ2 _GPIO(202)
+#define TEGRA_PIN_PZ3 _GPIO(203)
+#define TEGRA_PIN_PZ4 _GPIO(204)
+#define TEGRA_PIN_PZ5 _GPIO(205)
+#define TEGRA_PIN_DAP2_FS_PAA0 _GPIO(208)
+#define TEGRA_PIN_DAP2_SCLK_PAA1 _GPIO(209)
+#define TEGRA_PIN_DAP2_DIN_PAA2 _GPIO(210)
+#define TEGRA_PIN_DAP2_DOUT_PAA3 _GPIO(211)
+#define TEGRA_PIN_AUD_MCLK_PBB0 _GPIO(216)
+#define TEGRA_PIN_DVFS_PWM_PBB1 _GPIO(217)
+#define TEGRA_PIN_DVFS_CLK_PBB2 _GPIO(218)
+#define TEGRA_PIN_GPIO_X1_AUD_PBB3 _GPIO(219)
+#define TEGRA_PIN_GPIO_X3_AUD_PBB4 _GPIO(220)
+#define TEGRA_PIN_HDMI_CEC_PCC0 _GPIO(224)
+#define TEGRA_PIN_HDMI_INT_DP_HPD_PCC1 _GPIO(225)
+#define TEGRA_PIN_SPDIF_OUT_PCC2 _GPIO(226)
+#define TEGRA_PIN_SPDIF_IN_PCC3 _GPIO(227)
+#define TEGRA_PIN_USB_VBUS_EN0_PCC4 _GPIO(228)
+#define TEGRA_PIN_USB_VBUS_EN1_PCC5 _GPIO(229)
+#define TEGRA_PIN_DP_HPD0_PCC6 _GPIO(230)
+#define TEGRA_PIN_PCC7 _GPIO(231)
+#define TEGRA_PIN_SPI2_CS1_PDD0 _GPIO(232)
+#define TEGRA_PIN_QSPI_SCK_PEE0 _GPIO(240)
+#define TEGRA_PIN_QSPI_CS_N_PEE1 _GPIO(241)
+#define TEGRA_PIN_QSPI_IO0_PEE2 _GPIO(242)
+#define TEGRA_PIN_QSPI_IO1_PEE3 _GPIO(243)
+#define TEGRA_PIN_QSPI_IO2_PEE4 _GPIO(244)
+#define TEGRA_PIN_QSPI_IO3_PEE5 _GPIO(245)
+
+/* All non-GPIO pins follow */
+#define NUM_GPIOS (TEGRA_PIN_QSPI_IO3_PEE5 + 1)
+#define _PIN(offset) (NUM_GPIOS + (offset))
+
+/* Non-GPIO pins */
+#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
+#define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
+#define TEGRA_PIN_PWR_INT_N _PIN(2)
+#define TEGRA_PIN_CLK_32K_IN _PIN(3)
+#define TEGRA_PIN_JTAG_RTCK _PIN(4)
+#define TEGRA_PIN_BATT_BCL _PIN(5)
+#define TEGRA_PIN_CLK_REQ _PIN(6)
+#define TEGRA_PIN_SHUTDOWN _PIN(7)
+
+static const struct pinctrl_pin_desc tegra210_pins[] = {
+ PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PA0, "PEX_L0_RST_N PA0"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, "PEX_L0_CLKREQ_N PA1"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PA2, "PEX_WAKE_N PA2"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PA3, "PEX_L1_RST_N PA3"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, "PEX_L1_CLKREQ_N PA4"),
+ PINCTRL_PIN(TEGRA_PIN_SATA_LED_ACTIVE_PA5, "SATA_LED_ACTIVE PA5"),
+ PINCTRL_PIN(TEGRA_PIN_PA6, "PA6"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PB0, "DAP1_FS PB0"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PB1, "DAP1_DIN PB1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PB2, "DAP1_DOUT PB2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PB3, "DAP1_SCLK PB3"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PB4, "SPI2_MOSI PB4"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PB5, "SPI2_MISO PB5"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PB6, "SPI2_SCK PB6"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PB7, "SPI2_CS0 PB7"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PC0, "SPI1_MOSI PC0"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PC1, "SPI1_MISO PC1"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PC2, "SPI1_SCK PC2"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PC3, "SPI1_CS0 PC3"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PC4, "SPI1_CS1 PC4"),
+ PINCTRL_PIN(TEGRA_PIN_SPI4_SCK_PC5, "SPI4_SCK PC5"),
+ PINCTRL_PIN(TEGRA_PIN_SPI4_CS0_PC6, "SPI4_CS0 PC6"),
+ PINCTRL_PIN(TEGRA_PIN_SPI4_MOSI_PC7, "SPI4_MOSI PC7"),
+ PINCTRL_PIN(TEGRA_PIN_SPI4_MISO_PD0, "SPI4_MISO PD0"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_TX_PD1, "UART3_TX PD1"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_RX_PD2, "UART3_RX PD2"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_RTS_PD3, "UART3_RTS PD3"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_CTS_PD4, "UART3_CTS PD4"),
+ PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PE0, "DMIC1_CLK PE0"),
+ PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PE1, "DMIC1_DAT PE1"),
+ PINCTRL_PIN(TEGRA_PIN_DMIC2_CLK_PE2, "DMIC2_CLK PE2"),
+ PINCTRL_PIN(TEGRA_PIN_DMIC2_DAT_PE3, "DMIC2_DAT PE3"),
+ PINCTRL_PIN(TEGRA_PIN_DMIC3_CLK_PE4, "DMIC3_CLK PE4"),
+ PINCTRL_PIN(TEGRA_PIN_DMIC3_DAT_PE5, "DMIC3_DAT PE5"),
+ PINCTRL_PIN(TEGRA_PIN_PE6, "PE6"),
+ PINCTRL_PIN(TEGRA_PIN_PE7, "PE7"),
+ PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SCL_PF0, "GEN3_I2C_SCL PF0"),
+ PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SDA_PF1, "GEN3_I2C_SDA PF1"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_TX_PG0, "UART2_TX PG0"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_RX_PG1, "UART2_RX PG1"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PG2, "UART2_RTS PG2"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PG3, "UART2_CTS PG3"),
+ PINCTRL_PIN(TEGRA_PIN_WIFI_EN_PH0, "WIFI_EN PH0"),
+ PINCTRL_PIN(TEGRA_PIN_WIFI_RST_PH1, "WIFI_RST PH1"),
+ PINCTRL_PIN(TEGRA_PIN_WIFI_WAKE_AP_PH2, "WIFI_WAKE_AP PH2"),
+ PINCTRL_PIN(TEGRA_PIN_AP_WAKE_BT_PH3, "AP_WAKE_BT PH3"),
+ PINCTRL_PIN(TEGRA_PIN_BT_RST_PH4, "BT_RST PH4"),
+ PINCTRL_PIN(TEGRA_PIN_BT_WAKE_AP_PH5, "BT_WAKE_AP PH5"),
+ PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
+ PINCTRL_PIN(TEGRA_PIN_AP_WAKE_NFC_PH7, "AP_WAKE_NFC PH7"),
+ PINCTRL_PIN(TEGRA_PIN_NFC_EN_PI0, "NFC_EN PI0"),
+ PINCTRL_PIN(TEGRA_PIN_NFC_INT_PI1, "NFC_INT PI1"),
+ PINCTRL_PIN(TEGRA_PIN_GPS_EN_PI2, "GPS_EN PI2"),
+ PINCTRL_PIN(TEGRA_PIN_GPS_RST_PI3, "GPS_RST PI3"),
+ PINCTRL_PIN(TEGRA_PIN_UART4_TX_PI4, "UART4_TX PI4"),
+ PINCTRL_PIN(TEGRA_PIN_UART4_RX_PI5, "UART4_RX PI5"),
+ PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PI6, "UART4_RTS PI6"),
+ PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PI7, "UART4_CTS PI7"),
+ PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PJ0, "GEN1_I2C_SDA PJ0"),
+ PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PJ1, "GEN1_I2C_SCL PJ1"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PJ2, "GEN2_I2C_SCL PJ2"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PJ3, "GEN2_I2C_SDA PJ3"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PJ4, "DAP4_FS PJ4"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PJ5, "DAP4_DIN PJ5"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PJ6, "DAP4_DOUT PJ6"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PJ7, "DAP4_SCLK PJ7"),
+ PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
+ PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
+ PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
+ PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
+ PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
+ PINCTRL_PIN(TEGRA_PIN_PK5, "PK5"),
+ PINCTRL_PIN(TEGRA_PIN_PK6, "PK6"),
+ PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
+ PINCTRL_PIN(TEGRA_PIN_PL0, "PL0"),
+ PINCTRL_PIN(TEGRA_PIN_PL1, "PL1"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PM0, "SDMMC1_CLK PM0"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PM1, "SDMMC1_CMD PM1"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PM2, "SDMMC1_DAT3 PM2"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PM3, "SDMMC1_DAT2 PM3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PM4, "SDMMC1_DAT1 PM4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PM5, "SDMMC1_DAT0 PM5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PP0, "SDMMC3_CLK PP0"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PP1, "SDMMC3_CMD PP1"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PP2, "SDMMC3_DAT3 PP2"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PP3, "SDMMC3_DAT2 PP3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PP4, "SDMMC3_DAT1 PP4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PP5, "SDMMC3_DAT0 PP5"),
+ PINCTRL_PIN(TEGRA_PIN_CAM1_MCLK_PS0, "CAM1_MCLK PS0"),
+ PINCTRL_PIN(TEGRA_PIN_CAM2_MCLK_PS1, "CAM2_MCLK PS1"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PS2, "CAM_I2C_SCL PS2"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PS3, "CAM_I2C_SDA PS3"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_RST_PS4, "CAM_RST PS4"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_AF_EN_PS5, "CAM_AF_EN PS5"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_FLASH_EN_PS6, "CAM_FLASH_EN PS6"),
+ PINCTRL_PIN(TEGRA_PIN_CAM1_PWDN_PS7, "CAM1_PWDN PS7"),
+ PINCTRL_PIN(TEGRA_PIN_CAM2_PWDN_PT0, "CAM2_PWDN PT0"),
+ PINCTRL_PIN(TEGRA_PIN_CAM1_STROBE_PT1, "CAM1_STROBE PT1"),
+ PINCTRL_PIN(TEGRA_PIN_UART1_TX_PU0, "UART1_TX PU0"),
+ PINCTRL_PIN(TEGRA_PIN_UART1_RX_PU1, "UART1_RX PU1"),
+ PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PU2, "UART1_RTS PU2"),
+ PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PU3, "UART1_CTS PU3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_BL_PWM_PV0, "LCD_BL_PWM PV0"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_BL_EN_PV1, "LCD_BL_EN PV1"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_RST_PV2, "LCD_RST PV2"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_GPIO1_PV3, "LCD_GPIO1 PV3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_GPIO2_PV4, "LCD_GPIO2 PV4"),
+ PINCTRL_PIN(TEGRA_PIN_AP_READY_PV5, "AP_READY PV5"),
+ PINCTRL_PIN(TEGRA_PIN_TOUCH_RST_PV6, "TOUCH_RST PV6"),
+ PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PV7, "TOUCH_CLK PV7"),
+ PINCTRL_PIN(TEGRA_PIN_MODEM_WAKE_AP_PX0, "MODEM_WAKE_AP PX0"),
+ PINCTRL_PIN(TEGRA_PIN_TOUCH_INT_PX1, "TOUCH_INT PX1"),
+ PINCTRL_PIN(TEGRA_PIN_MOTION_INT_PX2, "MOTION_INT PX2"),
+ PINCTRL_PIN(TEGRA_PIN_ALS_PROX_INT_PX3, "ALS_PROX_INT PX3"),
+ PINCTRL_PIN(TEGRA_PIN_TEMP_ALERT_PX4, "TEMP_ALERT PX4"),
+ PINCTRL_PIN(TEGRA_PIN_BUTTON_POWER_ON_PX5, "BUTTON_POWER_ON PX5"),
+ PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_UP_PX6, "BUTTON_VOL_UP PX6"),
+ PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_DOWN_PX7, "BUTTON_VOL_DOWN PX7"),
+ PINCTRL_PIN(TEGRA_PIN_BUTTON_SLIDE_SW_PY0, "BUTTON_SLIDE_SW PY0"),
+ PINCTRL_PIN(TEGRA_PIN_BUTTON_HOME_PY1, "BUTTON_HOME PY1"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_TE_PY2, "LCD_TE PY2"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PY3, "PWR_I2C_SCL PY3"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PY4, "PWR_I2C_SDA PY4"),
+ PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PY5, "CLK_32K_OUT PY5"),
+ PINCTRL_PIN(TEGRA_PIN_PZ0, "PZ0"),
+ PINCTRL_PIN(TEGRA_PIN_PZ1, "PZ1"),
+ PINCTRL_PIN(TEGRA_PIN_PZ2, "PZ2"),
+ PINCTRL_PIN(TEGRA_PIN_PZ3, "PZ3"),
+ PINCTRL_PIN(TEGRA_PIN_PZ4, "PZ4"),
+ PINCTRL_PIN(TEGRA_PIN_PZ5, "PZ5"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PAA0, "DAP2_FS PAA0"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PAA1, "DAP2_SCLK PAA1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PAA2, "DAP2_DIN PAA2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PAA3, "DAP2_DOUT PAA3"),
+ PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PBB0, "AUD_MCLK PBB0"),
+ PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PBB1, "DVFS_PWM PBB1"),
+ PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PBB2, "DVFS_CLK PBB2"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PBB3, "GPIO_X1_AUD PBB3"),
+ PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PBB4, "GPIO_X3_AUD PBB4"),
+ PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PCC0, "HDMI_CEC PCC0"),
+ PINCTRL_PIN(TEGRA_PIN_HDMI_INT_DP_HPD_PCC1, "HDMI_INT_DP_HPD PCC1"),
+ PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PCC2, "SPDIF_OUT PCC2"),
+ PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PCC3, "SPDIF_IN PCC3"),
+ PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PCC4, "USB_VBUS_EN0 PCC4"),
+ PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PCC5, "USB_VBUS_EN1 PCC5"),
+ PINCTRL_PIN(TEGRA_PIN_DP_HPD0_PCC6, "DP_HPD0 PCC6"),
+ PINCTRL_PIN(TEGRA_PIN_PCC7, "PCC7"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_PDD0, "SPI2_CS1 PDD0"),
+ PINCTRL_PIN(TEGRA_PIN_QSPI_SCK_PEE0, "QSPI_SCK PEE0"),
+ PINCTRL_PIN(TEGRA_PIN_QSPI_CS_N_PEE1, "QSPI_CS_N PEE1"),
+ PINCTRL_PIN(TEGRA_PIN_QSPI_IO0_PEE2, "QSPI_IO0 PEE2"),
+ PINCTRL_PIN(TEGRA_PIN_QSPI_IO1_PEE3, "QSPI_IO1 PEE3"),
+ PINCTRL_PIN(TEGRA_PIN_QSPI_IO2_PEE4, "QSPI_IO2 PEE4"),
+ PINCTRL_PIN(TEGRA_PIN_QSPI_IO3_PEE5, "QSPI_IO3 PEE5"),
+ PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
+ PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
+ PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
+ PINCTRL_PIN(TEGRA_PIN_BATT_BCL, "BATT_BCL"),
+ PINCTRL_PIN(TEGRA_PIN_CLK_REQ, "CLK_REQ"),
+ PINCTRL_PIN(TEGRA_PIN_SHUTDOWN, "SHUTDOWN"),
+};
+
+static const unsigned pex_l0_rst_n_pa0_pins[] = {
+ TEGRA_PIN_PEX_L0_RST_N_PA0,
+};
+
+static const unsigned pex_l0_clkreq_n_pa1_pins[] = {
+ TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
+};
+
+static const unsigned pex_wake_n_pa2_pins[] = {
+ TEGRA_PIN_PEX_WAKE_N_PA2,
+};
+
+static const unsigned pex_l1_rst_n_pa3_pins[] = {
+ TEGRA_PIN_PEX_L1_RST_N_PA3,
+};
+
+static const unsigned pex_l1_clkreq_n_pa4_pins[] = {
+ TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
+};
+
+static const unsigned sata_led_active_pa5_pins[] = {
+ TEGRA_PIN_SATA_LED_ACTIVE_PA5,
+};
+
+static const unsigned pa6_pins[] = {
+ TEGRA_PIN_PA6,
+};
+
+static const unsigned dap1_fs_pb0_pins[] = {
+ TEGRA_PIN_DAP1_FS_PB0,
+};
+
+static const unsigned dap1_din_pb1_pins[] = {
+ TEGRA_PIN_DAP1_DIN_PB1,
+};
+
+static const unsigned dap1_dout_pb2_pins[] = {
+ TEGRA_PIN_DAP1_DOUT_PB2,
+};
+
+static const unsigned dap1_sclk_pb3_pins[] = {
+ TEGRA_PIN_DAP1_SCLK_PB3,
+};
+
+static const unsigned spi2_mosi_pb4_pins[] = {
+ TEGRA_PIN_SPI2_MOSI_PB4,
+};
+
+static const unsigned spi2_miso_pb5_pins[] = {
+ TEGRA_PIN_SPI2_MISO_PB5,
+};
+
+static const unsigned spi2_sck_pb6_pins[] = {
+ TEGRA_PIN_SPI2_SCK_PB6,
+};
+
+static const unsigned spi2_cs0_pb7_pins[] = {
+ TEGRA_PIN_SPI2_CS0_PB7,
+};
+
+static const unsigned spi1_mosi_pc0_pins[] = {
+ TEGRA_PIN_SPI1_MOSI_PC0,
+};
+
+static const unsigned spi1_miso_pc1_pins[] = {
+ TEGRA_PIN_SPI1_MISO_PC1,
+};
+
+static const unsigned spi1_sck_pc2_pins[] = {
+ TEGRA_PIN_SPI1_SCK_PC2,
+};
+
+static const unsigned spi1_cs0_pc3_pins[] = {
+ TEGRA_PIN_SPI1_CS0_PC3,
+};
+
+static const unsigned spi1_cs1_pc4_pins[] = {
+ TEGRA_PIN_SPI1_CS1_PC4,
+};
+
+static const unsigned spi4_sck_pc5_pins[] = {
+ TEGRA_PIN_SPI4_SCK_PC5,
+};
+
+static const unsigned spi4_cs0_pc6_pins[] = {
+ TEGRA_PIN_SPI4_CS0_PC6,
+};
+
+static const unsigned spi4_mosi_pc7_pins[] = {
+ TEGRA_PIN_SPI4_MOSI_PC7,
+};
+
+static const unsigned spi4_miso_pd0_pins[] = {
+ TEGRA_PIN_SPI4_MISO_PD0,
+};
+
+static const unsigned uart3_tx_pd1_pins[] = {
+ TEGRA_PIN_UART3_TX_PD1,
+};
+
+static const unsigned uart3_rx_pd2_pins[] = {
+ TEGRA_PIN_UART3_RX_PD2,
+};
+
+static const unsigned uart3_rts_pd3_pins[] = {
+ TEGRA_PIN_UART3_RTS_PD3,
+};
+
+static const unsigned uart3_cts_pd4_pins[] = {
+ TEGRA_PIN_UART3_CTS_PD4,
+};
+
+static const unsigned dmic1_clk_pe0_pins[] = {
+ TEGRA_PIN_DMIC1_CLK_PE0,
+};
+
+static const unsigned dmic1_dat_pe1_pins[] = {
+ TEGRA_PIN_DMIC1_DAT_PE1,
+};
+
+static const unsigned dmic2_clk_pe2_pins[] = {
+ TEGRA_PIN_DMIC2_CLK_PE2,
+};
+
+static const unsigned dmic2_dat_pe3_pins[] = {
+ TEGRA_PIN_DMIC2_DAT_PE3,
+};
+
+static const unsigned dmic3_clk_pe4_pins[] = {
+ TEGRA_PIN_DMIC3_CLK_PE4,
+};
+
+static const unsigned dmic3_dat_pe5_pins[] = {
+ TEGRA_PIN_DMIC3_DAT_PE5,
+};
+
+static const unsigned pe6_pins[] = {
+ TEGRA_PIN_PE6,
+};
+
+static const unsigned pe7_pins[] = {
+ TEGRA_PIN_PE7,
+};
+
+static const unsigned gen3_i2c_scl_pf0_pins[] = {
+ TEGRA_PIN_GEN3_I2C_SCL_PF0,
+};
+
+static const unsigned gen3_i2c_sda_pf1_pins[] = {
+ TEGRA_PIN_GEN3_I2C_SDA_PF1,
+};
+
+static const unsigned uart2_tx_pg0_pins[] = {
+ TEGRA_PIN_UART2_TX_PG0,
+};
+
+static const unsigned uart2_rx_pg1_pins[] = {
+ TEGRA_PIN_UART2_RX_PG1,
+};
+
+static const unsigned uart2_rts_pg2_pins[] = {
+ TEGRA_PIN_UART2_RTS_PG2,
+};
+
+static const unsigned uart2_cts_pg3_pins[] = {
+ TEGRA_PIN_UART2_CTS_PG3,
+};
+
+static const unsigned wifi_en_ph0_pins[] = {
+ TEGRA_PIN_WIFI_EN_PH0,
+};
+
+static const unsigned wifi_rst_ph1_pins[] = {
+ TEGRA_PIN_WIFI_RST_PH1,
+};
+
+static const unsigned wifi_wake_ap_ph2_pins[] = {
+ TEGRA_PIN_WIFI_WAKE_AP_PH2,
+};
+
+static const unsigned ap_wake_bt_ph3_pins[] = {
+ TEGRA_PIN_AP_WAKE_BT_PH3,
+};
+
+static const unsigned bt_rst_ph4_pins[] = {
+ TEGRA_PIN_BT_RST_PH4,
+};
+
+static const unsigned bt_wake_ap_ph5_pins[] = {
+ TEGRA_PIN_BT_WAKE_AP_PH5,
+};
+
+static const unsigned ph6_pins[] = {
+ TEGRA_PIN_PH6,
+};
+
+static const unsigned ap_wake_nfc_ph7_pins[] = {
+ TEGRA_PIN_AP_WAKE_NFC_PH7,
+};
+
+static const unsigned nfc_en_pi0_pins[] = {
+ TEGRA_PIN_NFC_EN_PI0,
+};
+
+static const unsigned nfc_int_pi1_pins[] = {
+ TEGRA_PIN_NFC_INT_PI1,
+};
+
+static const unsigned gps_en_pi2_pins[] = {
+ TEGRA_PIN_GPS_EN_PI2,
+};
+
+static const unsigned gps_rst_pi3_pins[] = {
+ TEGRA_PIN_GPS_RST_PI3,
+};
+
+static const unsigned uart4_tx_pi4_pins[] = {
+ TEGRA_PIN_UART4_TX_PI4,
+};
+
+static const unsigned uart4_rx_pi5_pins[] = {
+ TEGRA_PIN_UART4_RX_PI5,
+};
+
+static const unsigned uart4_rts_pi6_pins[] = {
+ TEGRA_PIN_UART4_RTS_PI6,
+};
+
+static const unsigned uart4_cts_pi7_pins[] = {
+ TEGRA_PIN_UART4_CTS_PI7,
+};
+
+static const unsigned gen1_i2c_sda_pj0_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SDA_PJ0,
+};
+
+static const unsigned gen1_i2c_scl_pj1_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SCL_PJ1,
+};
+
+static const unsigned gen2_i2c_scl_pj2_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SCL_PJ2,
+};
+
+static const unsigned gen2_i2c_sda_pj3_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SDA_PJ3,
+};
+
+static const unsigned dap4_fs_pj4_pins[] = {
+ TEGRA_PIN_DAP4_FS_PJ4,
+};
+
+static const unsigned dap4_din_pj5_pins[] = {
+ TEGRA_PIN_DAP4_DIN_PJ5,
+};
+
+static const unsigned dap4_dout_pj6_pins[] = {
+ TEGRA_PIN_DAP4_DOUT_PJ6,
+};
+
+static const unsigned dap4_sclk_pj7_pins[] = {
+ TEGRA_PIN_DAP4_SCLK_PJ7,
+};
+
+static const unsigned pk0_pins[] = {
+ TEGRA_PIN_PK0,
+};
+
+static const unsigned pk1_pins[] = {
+ TEGRA_PIN_PK1,
+};
+
+static const unsigned pk2_pins[] = {
+ TEGRA_PIN_PK2,
+};
+
+static const unsigned pk3_pins[] = {
+ TEGRA_PIN_PK3,
+};
+
+static const unsigned pk4_pins[] = {
+ TEGRA_PIN_PK4,
+};
+
+static const unsigned pk5_pins[] = {
+ TEGRA_PIN_PK5,
+};
+
+static const unsigned pk6_pins[] = {
+ TEGRA_PIN_PK6,
+};
+
+static const unsigned pk7_pins[] = {
+ TEGRA_PIN_PK7,
+};
+
+static const unsigned pl0_pins[] = {
+ TEGRA_PIN_PL0,
+};
+
+static const unsigned pl1_pins[] = {
+ TEGRA_PIN_PL1,
+};
+
+static const unsigned sdmmc1_clk_pm0_pins[] = {
+ TEGRA_PIN_SDMMC1_CLK_PM0,
+};
+
+static const unsigned sdmmc1_cmd_pm1_pins[] = {
+ TEGRA_PIN_SDMMC1_CMD_PM1,
+};
+
+static const unsigned sdmmc1_dat3_pm2_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT3_PM2,
+};
+
+static const unsigned sdmmc1_dat2_pm3_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT2_PM3,
+};
+
+static const unsigned sdmmc1_dat1_pm4_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT1_PM4,
+};
+
+static const unsigned sdmmc1_dat0_pm5_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT0_PM5,
+};
+
+static const unsigned sdmmc3_clk_pp0_pins[] = {
+ TEGRA_PIN_SDMMC3_CLK_PP0,
+};
+
+static const unsigned sdmmc3_cmd_pp1_pins[] = {
+ TEGRA_PIN_SDMMC3_CMD_PP1,
+};
+
+static const unsigned sdmmc3_dat3_pp2_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT3_PP2,
+};
+
+static const unsigned sdmmc3_dat2_pp3_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT2_PP3,
+};
+
+static const unsigned sdmmc3_dat1_pp4_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT1_PP4,
+};
+
+static const unsigned sdmmc3_dat0_pp5_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT0_PP5,
+};
+
+static const unsigned cam1_mclk_ps0_pins[] = {
+ TEGRA_PIN_CAM1_MCLK_PS0,
+};
+
+static const unsigned cam2_mclk_ps1_pins[] = {
+ TEGRA_PIN_CAM2_MCLK_PS1,
+};
+
+static const unsigned cam_i2c_scl_ps2_pins[] = {
+ TEGRA_PIN_CAM_I2C_SCL_PS2,
+};
+
+static const unsigned cam_i2c_sda_ps3_pins[] = {
+ TEGRA_PIN_CAM_I2C_SDA_PS3,
+};
+
+static const unsigned cam_rst_ps4_pins[] = {
+ TEGRA_PIN_CAM_RST_PS4,
+};
+
+static const unsigned cam_af_en_ps5_pins[] = {
+ TEGRA_PIN_CAM_AF_EN_PS5,
+};
+
+static const unsigned cam_flash_en_ps6_pins[] = {
+ TEGRA_PIN_CAM_FLASH_EN_PS6,
+};
+
+static const unsigned cam1_pwdn_ps7_pins[] = {
+ TEGRA_PIN_CAM1_PWDN_PS7,
+};
+
+static const unsigned cam2_pwdn_pt0_pins[] = {
+ TEGRA_PIN_CAM2_PWDN_PT0,
+};
+
+static const unsigned cam1_strobe_pt1_pins[] = {
+ TEGRA_PIN_CAM1_STROBE_PT1,
+};
+
+static const unsigned uart1_tx_pu0_pins[] = {
+ TEGRA_PIN_UART1_TX_PU0,
+};
+
+static const unsigned uart1_rx_pu1_pins[] = {
+ TEGRA_PIN_UART1_RX_PU1,
+};
+
+static const unsigned uart1_rts_pu2_pins[] = {
+ TEGRA_PIN_UART1_RTS_PU2,
+};
+
+static const unsigned uart1_cts_pu3_pins[] = {
+ TEGRA_PIN_UART1_CTS_PU3,
+};
+
+static const unsigned lcd_bl_pwm_pv0_pins[] = {
+ TEGRA_PIN_LCD_BL_PWM_PV0,
+};
+
+static const unsigned lcd_bl_en_pv1_pins[] = {
+ TEGRA_PIN_LCD_BL_EN_PV1,
+};
+
+static const unsigned lcd_rst_pv2_pins[] = {
+ TEGRA_PIN_LCD_RST_PV2,
+};
+
+static const unsigned lcd_gpio1_pv3_pins[] = {
+ TEGRA_PIN_LCD_GPIO1_PV3,
+};
+
+static const unsigned lcd_gpio2_pv4_pins[] = {
+ TEGRA_PIN_LCD_GPIO2_PV4,
+};
+
+static const unsigned ap_ready_pv5_pins[] = {
+ TEGRA_PIN_AP_READY_PV5,
+};
+
+static const unsigned touch_rst_pv6_pins[] = {
+ TEGRA_PIN_TOUCH_RST_PV6,
+};
+
+static const unsigned touch_clk_pv7_pins[] = {
+ TEGRA_PIN_TOUCH_CLK_PV7,
+};
+
+static const unsigned modem_wake_ap_px0_pins[] = {
+ TEGRA_PIN_MODEM_WAKE_AP_PX0,
+};
+
+static const unsigned touch_int_px1_pins[] = {
+ TEGRA_PIN_TOUCH_INT_PX1,
+};
+
+static const unsigned motion_int_px2_pins[] = {
+ TEGRA_PIN_MOTION_INT_PX2,
+};
+
+static const unsigned als_prox_int_px3_pins[] = {
+ TEGRA_PIN_ALS_PROX_INT_PX3,
+};
+
+static const unsigned temp_alert_px4_pins[] = {
+ TEGRA_PIN_TEMP_ALERT_PX4,
+};
+
+static const unsigned button_power_on_px5_pins[] = {
+ TEGRA_PIN_BUTTON_POWER_ON_PX5,
+};
+
+static const unsigned button_vol_up_px6_pins[] = {
+ TEGRA_PIN_BUTTON_VOL_UP_PX6,
+};
+
+static const unsigned button_vol_down_px7_pins[] = {
+ TEGRA_PIN_BUTTON_VOL_DOWN_PX7,
+};
+
+static const unsigned button_slide_sw_py0_pins[] = {
+ TEGRA_PIN_BUTTON_SLIDE_SW_PY0,
+};
+
+static const unsigned button_home_py1_pins[] = {
+ TEGRA_PIN_BUTTON_HOME_PY1,
+};
+
+static const unsigned lcd_te_py2_pins[] = {
+ TEGRA_PIN_LCD_TE_PY2,
+};
+
+static const unsigned pwr_i2c_scl_py3_pins[] = {
+ TEGRA_PIN_PWR_I2C_SCL_PY3,
+};
+
+static const unsigned pwr_i2c_sda_py4_pins[] = {
+ TEGRA_PIN_PWR_I2C_SDA_PY4,
+};
+
+static const unsigned clk_32k_out_py5_pins[] = {
+ TEGRA_PIN_CLK_32K_OUT_PY5,
+};
+
+static const unsigned pz0_pins[] = {
+ TEGRA_PIN_PZ0,
+};
+
+static const unsigned pz1_pins[] = {
+ TEGRA_PIN_PZ1,
+};
+
+static const unsigned pz2_pins[] = {
+ TEGRA_PIN_PZ2,
+};
+
+static const unsigned pz3_pins[] = {
+ TEGRA_PIN_PZ3,
+};
+
+static const unsigned pz4_pins[] = {
+ TEGRA_PIN_PZ4,
+};
+
+static const unsigned pz5_pins[] = {
+ TEGRA_PIN_PZ5,
+};
+
+static const unsigned dap2_fs_paa0_pins[] = {
+ TEGRA_PIN_DAP2_FS_PAA0,
+};
+
+static const unsigned dap2_sclk_paa1_pins[] = {
+ TEGRA_PIN_DAP2_SCLK_PAA1,
+};
+
+static const unsigned dap2_din_paa2_pins[] = {
+ TEGRA_PIN_DAP2_DIN_PAA2,
+};
+
+static const unsigned dap2_dout_paa3_pins[] = {
+ TEGRA_PIN_DAP2_DOUT_PAA3,
+};
+
+static const unsigned aud_mclk_pbb0_pins[] = {
+ TEGRA_PIN_AUD_MCLK_PBB0,
+};
+
+static const unsigned dvfs_pwm_pbb1_pins[] = {
+ TEGRA_PIN_DVFS_PWM_PBB1,
+};
+
+static const unsigned dvfs_clk_pbb2_pins[] = {
+ TEGRA_PIN_DVFS_CLK_PBB2,
+};
+
+static const unsigned gpio_x1_aud_pbb3_pins[] = {
+ TEGRA_PIN_GPIO_X1_AUD_PBB3,
+};
+
+static const unsigned gpio_x3_aud_pbb4_pins[] = {
+ TEGRA_PIN_GPIO_X3_AUD_PBB4,
+};
+
+static const unsigned hdmi_cec_pcc0_pins[] = {
+ TEGRA_PIN_HDMI_CEC_PCC0,
+};
+
+static const unsigned hdmi_int_dp_hpd_pcc1_pins[] = {
+ TEGRA_PIN_HDMI_INT_DP_HPD_PCC1,
+};
+
+static const unsigned spdif_out_pcc2_pins[] = {
+ TEGRA_PIN_SPDIF_OUT_PCC2,
+};
+
+static const unsigned spdif_in_pcc3_pins[] = {
+ TEGRA_PIN_SPDIF_IN_PCC3,
+};
+
+static const unsigned usb_vbus_en0_pcc4_pins[] = {
+ TEGRA_PIN_USB_VBUS_EN0_PCC4,
+};
+
+static const unsigned usb_vbus_en1_pcc5_pins[] = {
+ TEGRA_PIN_USB_VBUS_EN1_PCC5,
+};
+
+static const unsigned dp_hpd0_pcc6_pins[] = {
+ TEGRA_PIN_DP_HPD0_PCC6,
+};
+
+static const unsigned pcc7_pins[] = {
+ TEGRA_PIN_PCC7,
+};
+
+static const unsigned spi2_cs1_pdd0_pins[] = {
+ TEGRA_PIN_SPI2_CS1_PDD0,
+};
+
+static const unsigned qspi_sck_pee0_pins[] = {
+ TEGRA_PIN_QSPI_SCK_PEE0,
+};
+
+static const unsigned qspi_cs_n_pee1_pins[] = {
+ TEGRA_PIN_QSPI_CS_N_PEE1,
+};
+
+static const unsigned qspi_io0_pee2_pins[] = {
+ TEGRA_PIN_QSPI_IO0_PEE2,
+};
+
+static const unsigned qspi_io1_pee3_pins[] = {
+ TEGRA_PIN_QSPI_IO1_PEE3,
+};
+
+static const unsigned qspi_io2_pee4_pins[] = {
+ TEGRA_PIN_QSPI_IO2_PEE4,
+};
+
+static const unsigned qspi_io3_pee5_pins[] = {
+ TEGRA_PIN_QSPI_IO3_PEE5,
+};
+
+static const unsigned core_pwr_req_pins[] = {
+ TEGRA_PIN_CORE_PWR_REQ,
+};
+
+static const unsigned cpu_pwr_req_pins[] = {
+ TEGRA_PIN_CPU_PWR_REQ,
+};
+
+static const unsigned pwr_int_n_pins[] = {
+ TEGRA_PIN_PWR_INT_N,
+};
+
+static const unsigned clk_32k_in_pins[] = {
+ TEGRA_PIN_CLK_32K_IN,
+};
+
+static const unsigned jtag_rtck_pins[] = {
+ TEGRA_PIN_JTAG_RTCK,
+};
+
+static const unsigned batt_bcl_pins[] = {
+ TEGRA_PIN_BATT_BCL,
+};
+
+static const unsigned clk_req_pins[] = {
+ TEGRA_PIN_CLK_REQ,
+};
+
+static const unsigned shutdown_pins[] = {
+ TEGRA_PIN_SHUTDOWN,
+};
+
+static const unsigned drive_pa6_pins[] = {
+ TEGRA_PIN_PA6,
+};
+
+static const unsigned drive_pcc7_pins[] = {
+ TEGRA_PIN_PCC7,
+};
+
+static const unsigned drive_pe6_pins[] = {
+ TEGRA_PIN_PE6,
+};
+
+static const unsigned drive_pe7_pins[] = {
+ TEGRA_PIN_PE7,
+};
+
+static const unsigned drive_ph6_pins[] = {
+ TEGRA_PIN_PH6,
+};
+
+static const unsigned drive_pk0_pins[] = {
+ TEGRA_PIN_PK0,
+};
+
+static const unsigned drive_pk1_pins[] = {
+ TEGRA_PIN_PK1,
+};
+
+static const unsigned drive_pk2_pins[] = {
+ TEGRA_PIN_PK2,
+};
+
+static const unsigned drive_pk3_pins[] = {
+ TEGRA_PIN_PK3,
+};
+
+static const unsigned drive_pk4_pins[] = {
+ TEGRA_PIN_PK4,
+};
+
+static const unsigned drive_pk5_pins[] = {
+ TEGRA_PIN_PK5,
+};
+
+static const unsigned drive_pk6_pins[] = {
+ TEGRA_PIN_PK6,
+};
+
+static const unsigned drive_pk7_pins[] = {
+ TEGRA_PIN_PK7,
+};
+
+static const unsigned drive_pl0_pins[] = {
+ TEGRA_PIN_PL0,
+};
+
+static const unsigned drive_pl1_pins[] = {
+ TEGRA_PIN_PL1,
+};
+
+static const unsigned drive_pz0_pins[] = {
+ TEGRA_PIN_PZ0,
+};
+
+static const unsigned drive_pz1_pins[] = {
+ TEGRA_PIN_PZ1,
+};
+
+static const unsigned drive_pz2_pins[] = {
+ TEGRA_PIN_PZ2,
+};
+
+static const unsigned drive_pz3_pins[] = {
+ TEGRA_PIN_PZ3,
+};
+
+static const unsigned drive_pz4_pins[] = {
+ TEGRA_PIN_PZ4,
+};
+
+static const unsigned drive_pz5_pins[] = {
+ TEGRA_PIN_PZ5,
+};
+
+static const unsigned drive_sdmmc1_pins[] = {
+ TEGRA_PIN_SDMMC1_CLK_PM0,
+ TEGRA_PIN_SDMMC1_CMD_PM1,
+ TEGRA_PIN_SDMMC1_DAT3_PM2,
+ TEGRA_PIN_SDMMC1_DAT2_PM3,
+ TEGRA_PIN_SDMMC1_DAT1_PM4,
+ TEGRA_PIN_SDMMC1_DAT0_PM5,
+};
+
+static const unsigned drive_sdmmc2_pins[] = {
+};
+
+static const unsigned drive_sdmmc3_pins[] = {
+ TEGRA_PIN_SDMMC3_CLK_PP0,
+ TEGRA_PIN_SDMMC3_CMD_PP1,
+ TEGRA_PIN_SDMMC3_DAT3_PP2,
+ TEGRA_PIN_SDMMC3_DAT2_PP3,
+ TEGRA_PIN_SDMMC3_DAT1_PP4,
+ TEGRA_PIN_SDMMC3_DAT0_PP5,
+};
+
+static const unsigned drive_sdmmc4_pins[] = {
+};
+
+enum tegra_mux {
+ TEGRA_MUX_AUD,
+ TEGRA_MUX_BCL,
+ TEGRA_MUX_BLINK,
+ TEGRA_MUX_CCLA,
+ TEGRA_MUX_CEC,
+ TEGRA_MUX_CLDVFS,
+ TEGRA_MUX_CLK,
+ TEGRA_MUX_CORE,
+ TEGRA_MUX_CPU,
+ TEGRA_MUX_DISPLAYA,
+ TEGRA_MUX_DISPLAYB,
+ TEGRA_MUX_DMIC1,
+ TEGRA_MUX_DMIC2,
+ TEGRA_MUX_DMIC3,
+ TEGRA_MUX_DP,
+ TEGRA_MUX_DTV,
+ TEGRA_MUX_EXTPERIPH3,
+ TEGRA_MUX_I2C1,
+ TEGRA_MUX_I2C2,
+ TEGRA_MUX_I2C3,
+ TEGRA_MUX_I2CPMU,
+ TEGRA_MUX_I2CVI,
+ TEGRA_MUX_I2S1,
+ TEGRA_MUX_I2S2,
+ TEGRA_MUX_I2S3,
+ TEGRA_MUX_I2S4A,
+ TEGRA_MUX_I2S4B,
+ TEGRA_MUX_I2S5A,
+ TEGRA_MUX_I2S5B,
+ TEGRA_MUX_IQC0,
+ TEGRA_MUX_IQC1,
+ TEGRA_MUX_JTAG,
+ TEGRA_MUX_PE,
+ TEGRA_MUX_PE0,
+ TEGRA_MUX_PE1,
+ TEGRA_MUX_PMI,
+ TEGRA_MUX_PWM0,
+ TEGRA_MUX_PWM1,
+ TEGRA_MUX_PWM2,
+ TEGRA_MUX_PWM3,
+ TEGRA_MUX_QSPI,
+ TEGRA_MUX_RSVD0,
+ TEGRA_MUX_RSVD1,
+ TEGRA_MUX_RSVD2,
+ TEGRA_MUX_RSVD3,
+ TEGRA_MUX_SATA,
+ TEGRA_MUX_SDMMC1,
+ TEGRA_MUX_SDMMC3,
+ TEGRA_MUX_SHUTDOWN,
+ TEGRA_MUX_SOC,
+ TEGRA_MUX_SOR0,
+ TEGRA_MUX_SOR1,
+ TEGRA_MUX_SPDIF,
+ TEGRA_MUX_SPI1,
+ TEGRA_MUX_SPI2,
+ TEGRA_MUX_SPI3,
+ TEGRA_MUX_SPI4,
+ TEGRA_MUX_SYS,
+ TEGRA_MUX_TOUCH,
+ TEGRA_MUX_UART,
+ TEGRA_MUX_UARTA,
+ TEGRA_MUX_UARTB,
+ TEGRA_MUX_UARTC,
+ TEGRA_MUX_UARTD,
+ TEGRA_MUX_USB,
+ TEGRA_MUX_VGP1,
+ TEGRA_MUX_VGP2,
+ TEGRA_MUX_VGP3,
+ TEGRA_MUX_VGP4,
+ TEGRA_MUX_VGP5,
+ TEGRA_MUX_VGP6,
+ TEGRA_MUX_VIMCLK,
+ TEGRA_MUX_VIMCLK2,
+};
+
+#define FUNCTION(fname) \
+ { \
+ .name = #fname, \
+ }
+
+static struct tegra_function tegra210_functions[] = {
+ FUNCTION(aud),
+ FUNCTION(bcl),
+ FUNCTION(blink),
+ FUNCTION(ccla),
+ FUNCTION(cec),
+ FUNCTION(cldvfs),
+ FUNCTION(clk),
+ FUNCTION(core),
+ FUNCTION(cpu),
+ FUNCTION(displaya),
+ FUNCTION(displayb),
+ FUNCTION(dmic1),
+ FUNCTION(dmic2),
+ FUNCTION(dmic3),
+ FUNCTION(dp),
+ FUNCTION(dtv),
+ FUNCTION(extperiph3),
+ FUNCTION(i2c1),
+ FUNCTION(i2c2),
+ FUNCTION(i2c3),
+ FUNCTION(i2cpmu),
+ FUNCTION(i2cvi),
+ FUNCTION(i2s1),
+ FUNCTION(i2s2),
+ FUNCTION(i2s3),
+ FUNCTION(i2s4a),
+ FUNCTION(i2s4b),
+ FUNCTION(i2s5a),
+ FUNCTION(i2s5b),
+ FUNCTION(iqc0),
+ FUNCTION(iqc1),
+ FUNCTION(jtag),
+ FUNCTION(pe),
+ FUNCTION(pe0),
+ FUNCTION(pe1),
+ FUNCTION(pmi),
+ FUNCTION(pwm0),
+ FUNCTION(pwm1),
+ FUNCTION(pwm2),
+ FUNCTION(pwm3),
+ FUNCTION(qspi),
+ FUNCTION(rsvd0),
+ FUNCTION(rsvd1),
+ FUNCTION(rsvd2),
+ FUNCTION(rsvd3),
+ FUNCTION(sata),
+ FUNCTION(sdmmc1),
+ FUNCTION(sdmmc3),
+ FUNCTION(shutdown),
+ FUNCTION(soc),
+ FUNCTION(sor0),
+ FUNCTION(sor1),
+ FUNCTION(spdif),
+ FUNCTION(spi1),
+ FUNCTION(spi2),
+ FUNCTION(spi3),
+ FUNCTION(spi4),
+ FUNCTION(sys),
+ FUNCTION(touch),
+ FUNCTION(uart),
+ FUNCTION(uarta),
+ FUNCTION(uartb),
+ FUNCTION(uartc),
+ FUNCTION(uartd),
+ FUNCTION(usb),
+ FUNCTION(vgp1),
+ FUNCTION(vgp2),
+ FUNCTION(vgp3),
+ FUNCTION(vgp4),
+ FUNCTION(vgp5),
+ FUNCTION(vgp6),
+ FUNCTION(vimclk),
+ FUNCTION(vimclk2),
+};
+
+#define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */
+#define PINGROUP_REG_A 0x3000 /* bank 1 */
+
+#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
+#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
+
+#define PINGROUP_BIT_Y(b) (b)
+#define PINGROUP_BIT_N(b) (-1)
+
+#define PINGROUP(pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, \
+ rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, \
+ slwr_w, slwf_b, slwf_w) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .funcs = { \
+ TEGRA_MUX_##f0, \
+ TEGRA_MUX_##f1, \
+ TEGRA_MUX_##f2, \
+ TEGRA_MUX_##f3, \
+ }, \
+ .mux_reg = PINGROUP_REG(r), \
+ .mux_bank = 1, \
+ .mux_bit = 0, \
+ .pupd_reg = PINGROUP_REG(r), \
+ .pupd_bank = 1, \
+ .pupd_bit = 2, \
+ .tri_reg = PINGROUP_REG(r), \
+ .tri_bank = 1, \
+ .tri_bit = 4, \
+ .einput_bit = 6, \
+ .odrain_bit = 11, \
+ .lock_bit = 7, \
+ .ioreset_bit = -1, \
+ .rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10), \
+ .hsm_bit = PINGROUP_BIT_##hsm(9), \
+ .schmitt_bit = 12, \
+ .drvtype_bit = PINGROUP_BIT_##drvtype(13), \
+ .drv_reg = DRV_PINGROUP_REG(rdrv), \
+ .drv_bank = 0, \
+ .lpmd_bit = -1, \
+ .drvdn_bit = drvdn_b, \
+ .drvdn_width = drvdn_w, \
+ .drvup_bit = drvup_b, \
+ .drvup_width = drvup_w, \
+ .slwr_bit = slwr_b, \
+ .slwr_width = slwr_w, \
+ .slwf_bit = slwf_b, \
+ .slwf_width = slwf_w, \
+ }
+
+#define DRV_PINGROUP(pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, \
+ slwr_b, slwr_w, slwf_b, slwf_w) \
+ { \
+ .name = "drive_" #pg_name, \
+ .pins = drive_##pg_name##_pins, \
+ .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
+ .mux_reg = -1, \
+ .pupd_reg = -1, \
+ .tri_reg = -1, \
+ .einput_bit = -1, \
+ .odrain_bit = -1, \
+ .lock_bit = -1, \
+ .ioreset_bit = -1, \
+ .rcv_sel_bit = -1, \
+ .drv_reg = DRV_PINGROUP_REG(r), \
+ .drv_bank = 0, \
+ .hsm_bit = -1, \
+ .schmitt_bit = -1, \
+ .lpmd_bit = -1, \
+ .drvdn_bit = drvdn_b, \
+ .drvdn_width = drvdn_w, \
+ .drvup_bit = drvup_b, \
+ .drvup_width = drvup_w, \
+ .slwr_bit = slwr_b, \
+ .slwr_width = slwr_w, \
+ .slwf_bit = slwf_b, \
+ .slwf_width = slwf_w, \
+ .drvtype_bit = -1, \
+ }
+
+static const struct tegra_pingroup tegra210_groups[] = {
+ /* pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
+ PINGROUP(sdmmc1_clk_pm0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3000, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(sdmmc1_cmd_pm1, SDMMC1, SPI3, RSVD2, RSVD3, 0x3004, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(sdmmc1_dat3_pm2, SDMMC1, SPI3, RSVD2, RSVD3, 0x3008, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(sdmmc1_dat2_pm3, SDMMC1, SPI3, RSVD2, RSVD3, 0x300c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(sdmmc1_dat1_pm4, SDMMC1, SPI3, RSVD2, RSVD3, 0x3010, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(sdmmc1_dat0_pm5, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3014, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(sdmmc3_clk_pp0, SDMMC3, RSVD1, RSVD2, RSVD3, 0x301c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(sdmmc3_cmd_pp1, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3020, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(sdmmc3_dat0_pp5, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3024, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(sdmmc3_dat1_pp4, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3028, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(sdmmc3_dat2_pp3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x302c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(sdmmc3_dat3_pp2, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3030, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pex_l0_rst_n_pa0, PE0, RSVD1, RSVD2, RSVD3, 0x3038, N, N, Y, 0xa5c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(pex_l0_clkreq_n_pa1, PE0, RSVD1, RSVD2, RSVD3, 0x303c, N, N, Y, 0xa58, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(pex_wake_n_pa2, PE, RSVD1, RSVD2, RSVD3, 0x3040, N, N, Y, 0xa68, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(pex_l1_rst_n_pa3, PE1, RSVD1, RSVD2, RSVD3, 0x3044, N, N, Y, 0xa64, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(pex_l1_clkreq_n_pa4, PE1, RSVD1, RSVD2, RSVD3, 0x3048, N, N, Y, 0xa60, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(sata_led_active_pa5, SATA, RSVD1, RSVD2, RSVD3, 0x304c, N, N, N, 0xa94, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(spi1_mosi_pc0, SPI1, RSVD1, RSVD2, RSVD3, 0x3050, Y, Y, N, 0xae0, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(spi1_miso_pc1, SPI1, RSVD1, RSVD2, RSVD3, 0x3054, Y, Y, N, 0xadc, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(spi1_sck_pc2, SPI1, RSVD1, RSVD2, RSVD3, 0x3058, Y, Y, N, 0xae4, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(spi1_cs0_pc3, SPI1, RSVD1, RSVD2, RSVD3, 0x305c, Y, Y, N, 0xad4, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(spi1_cs1_pc4, SPI1, RSVD1, RSVD2, RSVD3, 0x3060, Y, Y, N, 0xad8, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(spi2_mosi_pb4, SPI2, DTV, RSVD2, RSVD3, 0x3064, Y, Y, N, 0xaf4, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(spi2_miso_pb5, SPI2, DTV, RSVD2, RSVD3, 0x3068, Y, Y, N, 0xaf0, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(spi2_sck_pb6, SPI2, DTV, RSVD2, RSVD3, 0x306c, Y, Y, N, 0xaf8, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(spi2_cs0_pb7, SPI2, DTV, RSVD2, RSVD3, 0x3070, Y, Y, N, 0xae8, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(spi2_cs1_pdd0, SPI2, RSVD1, RSVD2, RSVD3, 0x3074, Y, Y, N, 0xaec, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(spi4_mosi_pc7, SPI4, RSVD1, RSVD2, RSVD3, 0x3078, Y, Y, N, 0xb04, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(spi4_miso_pd0, SPI4, RSVD1, RSVD2, RSVD3, 0x307c, Y, Y, N, 0xb00, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(spi4_sck_pc5, SPI4, RSVD1, RSVD2, RSVD3, 0x3080, Y, Y, N, 0xb08, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(spi4_cs0_pc6, SPI4, RSVD1, RSVD2, RSVD3, 0x3084, Y, Y, N, 0xafc, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(qspi_sck_pee0, QSPI, RSVD1, RSVD2, RSVD3, 0x3088, Y, Y, N, 0xa90, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(qspi_cs_n_pee1, QSPI, RSVD1, RSVD2, RSVD3, 0x308c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(qspi_io0_pee2, QSPI, RSVD1, RSVD2, RSVD3, 0x3090, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(qspi_io1_pee3, QSPI, RSVD1, RSVD2, RSVD3, 0x3094, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(qspi_io2_pee4, QSPI, RSVD1, RSVD2, RSVD3, 0x3098, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(qspi_io3_pee5, QSPI, RSVD1, RSVD2, RSVD3, 0x309c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(dmic1_clk_pe0, DMIC1, I2S3, RSVD2, RSVD3, 0x30a4, N, N, N, 0x984, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(dmic1_dat_pe1, DMIC1, I2S3, RSVD2, RSVD3, 0x30a8, N, N, N, 0x988, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(dmic2_clk_pe2, DMIC2, I2S3, RSVD2, RSVD3, 0x30ac, N, N, N, 0x98c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(dmic2_dat_pe3, DMIC2, I2S3, RSVD2, RSVD3, 0x30b0, N, N, N, 0x990, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(dmic3_clk_pe4, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b4, N, N, N, 0x994, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(dmic3_dat_pe5, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b8, N, N, N, 0x998, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(gen1_i2c_scl_pj1, I2C1, RSVD1, RSVD2, RSVD3, 0x30bc, N, N, Y, 0x9a8, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(gen1_i2c_sda_pj0, I2C1, RSVD1, RSVD2, RSVD3, 0x30c0, N, N, Y, 0x9ac, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(gen2_i2c_scl_pj2, I2C2, RSVD1, RSVD2, RSVD3, 0x30c4, N, N, Y, 0x9b0, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(gen2_i2c_sda_pj3, I2C2, RSVD1, RSVD2, RSVD3, 0x30c8, N, N, Y, 0x9b4, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(gen3_i2c_scl_pf0, I2C3, RSVD1, RSVD2, RSVD3, 0x30cc, N, N, Y, 0x9b8, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(gen3_i2c_sda_pf1, I2C3, RSVD1, RSVD2, RSVD3, 0x30d0, N, N, Y, 0x9bc, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(cam_i2c_scl_ps2, I2C3, I2CVI, RSVD2, RSVD3, 0x30d4, N, N, Y, 0x934, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(cam_i2c_sda_ps3, I2C3, I2CVI, RSVD2, RSVD3, 0x30d8, N, N, Y, 0x938, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(pwr_i2c_scl_py3, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30dc, N, N, Y, 0xa6c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(pwr_i2c_sda_py4, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30e0, N, N, Y, 0xa70, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart1_tx_pu0, UARTA, RSVD1, RSVD2, RSVD3, 0x30e4, N, N, N, 0xb28, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart1_rx_pu1, UARTA, RSVD1, RSVD2, RSVD3, 0x30e8, N, N, N, 0xb24, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart1_rts_pu2, UARTA, RSVD1, RSVD2, RSVD3, 0x30ec, N, N, N, 0xb20, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart1_cts_pu3, UARTA, RSVD1, RSVD2, RSVD3, 0x30f0, N, N, N, 0xb1c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart2_tx_pg0, UARTB, I2S4A, SPDIF, UART, 0x30f4, N, N, N, 0xb38, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart2_rx_pg1, UARTB, I2S4A, SPDIF, UART, 0x30f8, N, N, N, 0xb34, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart2_rts_pg2, UARTB, I2S4A, RSVD2, UART, 0x30fc, N, N, N, 0xb30, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart2_cts_pg3, UARTB, I2S4A, RSVD2, UART, 0x3100, N, N, N, 0xb2c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart3_tx_pd1, UARTC, SPI4, RSVD2, RSVD3, 0x3104, N, N, N, 0xb48, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart3_rx_pd2, UARTC, SPI4, RSVD2, RSVD3, 0x3108, N, N, N, 0xb44, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart3_rts_pd3, UARTC, SPI4, RSVD2, RSVD3, 0x310c, N, N, N, 0xb40, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart3_cts_pd4, UARTC, SPI4, RSVD2, RSVD3, 0x3110, N, N, N, 0xb3c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart4_tx_pi4, UARTD, UART, RSVD2, RSVD3, 0x3114, N, N, N, 0xb58, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart4_rx_pi5, UARTD, UART, RSVD2, RSVD3, 0x3118, N, N, N, 0xb54, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart4_rts_pi6, UARTD, UART, RSVD2, RSVD3, 0x311c, N, N, N, 0xb50, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(uart4_cts_pi7, UARTD, UART, RSVD2, RSVD3, 0x3120, N, N, N, 0xb4c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(dap1_fs_pb0, I2S1, RSVD1, RSVD2, RSVD3, 0x3124, Y, Y, N, 0x95c, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(dap1_din_pb1, I2S1, RSVD1, RSVD2, RSVD3, 0x3128, Y, Y, N, 0x954, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(dap1_dout_pb2, I2S1, RSVD1, RSVD2, RSVD3, 0x312c, Y, Y, N, 0x958, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(dap1_sclk_pb3, I2S1, RSVD1, RSVD2, RSVD3, 0x3130, Y, Y, N, 0x960, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(dap2_fs_paa0, I2S2, RSVD1, RSVD2, RSVD3, 0x3134, Y, Y, N, 0x96c, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(dap2_din_paa2, I2S2, RSVD1, RSVD2, RSVD3, 0x3138, Y, Y, N, 0x964, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(dap2_dout_paa3, I2S2, RSVD1, RSVD2, RSVD3, 0x313c, Y, Y, N, 0x968, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(dap2_sclk_paa1, I2S2, RSVD1, RSVD2, RSVD3, 0x3140, Y, Y, N, 0x970, -1, -1, -1, -1, 28, 2, 30, 2),
+ PINGROUP(dap4_fs_pj4, I2S4B, RSVD1, RSVD2, RSVD3, 0x3144, N, N, N, 0x97c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(dap4_din_pj5, I2S4B, RSVD1, RSVD2, RSVD3, 0x3148, N, N, N, 0x974, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(dap4_dout_pj6, I2S4B, RSVD1, RSVD2, RSVD3, 0x314c, N, N, N, 0x978, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(dap4_sclk_pj7, I2S4B, RSVD1, RSVD2, RSVD3, 0x3150, N, N, N, 0x980, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(cam1_mclk_ps0, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3154, N, N, N, 0x918, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(cam2_mclk_ps1, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3158, N, N, N, 0x924, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(jtag_rtck, JTAG, RSVD1, RSVD2, RSVD3, 0x315c, N, N, N, 0xa2c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(clk_32k_in, CLK, RSVD1, RSVD2, RSVD3, 0x3160, N, N, N, 0x940, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(clk_32k_out_py5, SOC, BLINK, RSVD2, RSVD3, 0x3164, N, N, N, 0x944, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(batt_bcl, BCL, RSVD1, RSVD2, RSVD3, 0x3168, N, N, Y, 0x8f8, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(clk_req, SYS, RSVD1, RSVD2, RSVD3, 0x316c, N, N, N, 0x948, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(cpu_pwr_req, CPU, RSVD1, RSVD2, RSVD3, 0x3170, N, N, N, 0x950, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(pwr_int_n, PMI, RSVD1, RSVD2, RSVD3, 0x3174, N, N, N, 0xa74, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(shutdown, SHUTDOWN, RSVD1, RSVD2, RSVD3, 0x3178, N, N, N, 0xac8, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(core_pwr_req, CORE, RSVD1, RSVD2, RSVD3, 0x317c, N, N, N, 0x94c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(aud_mclk_pbb0, AUD, RSVD1, RSVD2, RSVD3, 0x3180, N, N, N, 0x8f4, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(dvfs_pwm_pbb1, RSVD0, CLDVFS, SPI3, RSVD3, 0x3184, N, N, N, 0x9a4, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(dvfs_clk_pbb2, RSVD0, CLDVFS, SPI3, RSVD3, 0x3188, N, N, N, 0x9a0, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(gpio_x1_aud_pbb3, RSVD0, RSVD1, SPI3, RSVD3, 0x318c, N, N, N, 0xa14, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(gpio_x3_aud_pbb4, RSVD0, RSVD1, SPI3, RSVD3, 0x3190, N, N, N, 0xa18, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(pcc7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3194, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(hdmi_cec_pcc0, CEC, RSVD1, RSVD2, RSVD3, 0x3198, N, N, Y, 0xa24, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(hdmi_int_dp_hpd_pcc1, DP, RSVD1, RSVD2, RSVD3, 0x319c, N, N, Y, 0xa28, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(spdif_out_pcc2, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a0, N, N, N, 0xad0, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(spdif_in_pcc3, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a4, N, N, N, 0xacc, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(usb_vbus_en0_pcc4, USB, RSVD1, RSVD2, RSVD3, 0x31a8, N, N, Y, 0xb5c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(usb_vbus_en1_pcc5, USB, RSVD1, RSVD2, RSVD3, 0x31ac, N, N, Y, 0xb60, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(dp_hpd0_pcc6, DP, RSVD1, RSVD2, RSVD3, 0x31b0, N, N, N, 0x99c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(wifi_en_ph0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b4, N, N, N, 0xb64, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(wifi_rst_ph1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b8, N, N, N, 0xb68, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(wifi_wake_ap_ph2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31bc, N, N, N, 0xb6c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(ap_wake_bt_ph3, RSVD0, UARTB, SPDIF, RSVD3, 0x31c0, N, N, N, 0x8ec, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(bt_rst_ph4, RSVD0, UARTB, SPDIF, RSVD3, 0x31c4, N, N, N, 0x8fc, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(bt_wake_ap_ph5, RSVD0, RSVD1, RSVD2, RSVD3, 0x31c8, N, N, N, 0x900, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(ap_wake_nfc_ph7, RSVD0, RSVD1, RSVD2, RSVD3, 0x31cc, N, N, N, 0x8f0, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(nfc_en_pi0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d0, N, N, N, 0xa50, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(nfc_int_pi1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d4, N, N, N, 0xa54, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(gps_en_pi2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d8, N, N, N, 0xa1c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(gps_rst_pi3, RSVD0, RSVD1, RSVD2, RSVD3, 0x31dc, N, N, N, 0xa20, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(cam_rst_ps4, VGP1, RSVD1, RSVD2, RSVD3, 0x31e0, N, N, N, 0x93c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(cam_af_en_ps5, VIMCLK, VGP2, RSVD2, RSVD3, 0x31e4, N, N, N, 0x92c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(cam_flash_en_ps6, VIMCLK, VGP3, RSVD2, RSVD3, 0x31e8, N, N, N, 0x930, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(cam1_pwdn_ps7, VGP4, RSVD1, RSVD2, RSVD3, 0x31ec, N, N, N, 0x91c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(cam2_pwdn_pt0, VGP5, RSVD1, RSVD2, RSVD3, 0x31f0, N, N, N, 0x928, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(cam1_strobe_pt1, VGP6, RSVD1, RSVD2, RSVD3, 0x31f4, N, N, N, 0x920, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(lcd_te_py2, DISPLAYA, RSVD1, RSVD2, RSVD3, 0x31f8, N, N, N, 0xa44, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(lcd_bl_pwm_pv0, DISPLAYA, PWM0, SOR0, RSVD3, 0x31fc, N, N, N, 0xa34, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(lcd_bl_en_pv1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3200, N, N, N, 0xa30, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(lcd_rst_pv2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3204, N, N, N, 0xa40, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(lcd_gpio1_pv3, DISPLAYB, RSVD1, RSVD2, RSVD3, 0x3208, N, N, N, 0xa38, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(lcd_gpio2_pv4, DISPLAYB, PWM1, RSVD2, SOR1, 0x320c, N, N, N, 0xa3c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(ap_ready_pv5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3210, N, N, N, 0x8e8, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(touch_rst_pv6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3214, N, N, N, 0xb18, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(touch_clk_pv7, TOUCH, RSVD1, RSVD2, RSVD3, 0x3218, N, N, N, 0xb10, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(modem_wake_ap_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0x321c, N, N, N, 0xa48, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(touch_int_px1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3220, N, N, N, 0xb14, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(motion_int_px2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3224, N, N, N, 0xa4c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(als_prox_int_px3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3228, N, N, N, 0x8e4, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(temp_alert_px4, RSVD0, RSVD1, RSVD2, RSVD3, 0x322c, N, N, N, 0xb0c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(button_power_on_px5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3230, N, N, N, 0x908, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(button_vol_up_px6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3234, N, N, N, 0x914, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(button_vol_down_px7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3238, N, N, N, 0x910, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(button_slide_sw_py0, RSVD0, RSVD1, RSVD2, RSVD3, 0x323c, N, N, N, 0x90c, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(button_home_py1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3240, N, N, N, 0x904, 12, 5, 20, 5, -1, -1, -1, -1),
+ PINGROUP(pa6, SATA, RSVD1, RSVD2, RSVD3, 0x3244, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pe6, RSVD0, I2S5A, PWM2, RSVD3, 0x3248, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pe7, RSVD0, I2S5A, PWM3, RSVD3, 0x324c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(ph6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3250, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pk0, IQC0, I2S5B, RSVD2, RSVD3, 0x3254, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pk1, IQC0, I2S5B, RSVD2, RSVD3, 0x3258, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pk2, IQC0, I2S5B, RSVD2, RSVD3, 0x325c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pk3, IQC0, I2S5B, RSVD2, RSVD3, 0x3260, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pk4, IQC1, RSVD1, RSVD2, RSVD3, 0x3264, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pk5, IQC1, RSVD1, RSVD2, RSVD3, 0x3268, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pk6, IQC1, RSVD1, RSVD2, RSVD3, 0x326c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pk7, IQC1, RSVD1, RSVD2, RSVD3, 0x3270, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pl0, RSVD0, RSVD1, RSVD2, RSVD3, 0x3274, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pl1, SOC, RSVD1, RSVD2, RSVD3, 0x3278, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pz0, VIMCLK2, RSVD1, RSVD2, RSVD3, 0x327c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pz1, VIMCLK2, SDMMC1, RSVD2, RSVD3, 0x3280, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pz2, SDMMC3, CCLA, RSVD2, RSVD3, 0x3284, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pz3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3288, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pz4, SDMMC1, RSVD1, RSVD2, RSVD3, 0x328c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(pz5, SOC, RSVD1, RSVD2, RSVD3, 0x3290, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
+
+ /* pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
+ DRV_PINGROUP(pa6, 0x9c0, 12, 5, 20, 5, -1, -1, -1, -1),
+ DRV_PINGROUP(pcc7, 0x9c4, 12, 5, 20, 5, -1, -1, -1, -1),
+ DRV_PINGROUP(pe6, 0x9c8, 12, 5, 20, 5, -1, -1, -1, -1),
+ DRV_PINGROUP(pe7, 0x9cc, 12, 5, 20, 5, -1, -1, -1, -1),
+ DRV_PINGROUP(ph6, 0x9d0, 12, 5, 20, 5, -1, -1, -1, -1),
+ DRV_PINGROUP(pk0, 0x9d4, -1, -1, -1, -1, 28, 2, 30, 2),
+ DRV_PINGROUP(pk1, 0x9d8, -1, -1, -1, -1, 28, 2, 30, 2),
+ DRV_PINGROUP(pk2, 0x9dc, -1, -1, -1, -1, 28, 2, 30, 2),
+ DRV_PINGROUP(pk3, 0x9e0, -1, -1, -1, -1, 28, 2, 30, 2),
+ DRV_PINGROUP(pk4, 0x9e4, -1, -1, -1, -1, 28, 2, 30, 2),
+ DRV_PINGROUP(pk5, 0x9e8, -1, -1, -1, -1, 28, 2, 30, 2),
+ DRV_PINGROUP(pk6, 0x9ec, -1, -1, -1, -1, 28, 2, 30, 2),
+ DRV_PINGROUP(pk7, 0x9f0, -1, -1, -1, -1, 28, 2, 30, 2),
+ DRV_PINGROUP(pl0, 0x9f4, -1, -1, -1, -1, 28, 2, 30, 2),
+ DRV_PINGROUP(pl1, 0x9f8, -1, -1, -1, -1, 28, 2, 30, 2),
+ DRV_PINGROUP(pz0, 0x9fc, 12, 7, 20, 7, -1, -1, -1, -1),
+ DRV_PINGROUP(pz1, 0xa00, 12, 7, 20, 7, -1, -1, -1, -1),
+ DRV_PINGROUP(pz2, 0xa04, 12, 7, 20, 7, -1, -1, -1, -1),
+ DRV_PINGROUP(pz3, 0xa08, 12, 7, 20, 7, -1, -1, -1, -1),
+ DRV_PINGROUP(pz4, 0xa0c, 12, 7, 20, 7, -1, -1, -1, -1),
+ DRV_PINGROUP(pz5, 0xa10, 12, 7, 20, 7, -1, -1, -1, -1),
+ DRV_PINGROUP(sdmmc1, 0xa98, 12, 7, 20, 7, 28, 2, 30, 2),
+ DRV_PINGROUP(sdmmc2, 0xa9c, 2, 6, 8, 6, 28, 2, 30, 2),
+ DRV_PINGROUP(sdmmc3, 0xab0, 12, 7, 20, 7, 28, 2, 30, 2),
+ DRV_PINGROUP(sdmmc4, 0xab4, 2, 6, 8, 6, 28, 2, 30, 2),
+};
+
+static const struct tegra_pinctrl_soc_data tegra210_pinctrl = {
+ .ngpios = NUM_GPIOS,
+ .pins = tegra210_pins,
+ .npins = ARRAY_SIZE(tegra210_pins),
+ .functions = tegra210_functions,
+ .nfunctions = ARRAY_SIZE(tegra210_functions),
+ .groups = tegra210_groups,
+ .ngroups = ARRAY_SIZE(tegra210_groups),
+ .hsm_in_mux = true,
+ .schmitt_in_mux = true,
+ .drvtype_in_mux = true,
+};
+
+static int tegra210_pinctrl_probe(struct platform_device *pdev)
+{
+ return tegra_pinctrl_probe(pdev, &tegra210_pinctrl);
+}
+
+static const struct of_device_id tegra210_pinctrl_of_match[] = {
+ { .compatible = "nvidia,tegra210-pinmux", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, tegra210_pinctrl_of_match);
+
+static struct platform_driver tegra210_pinctrl_driver = {
+ .driver = {
+ .name = "tegra210-pinctrl",
+ .of_match_table = tegra210_pinctrl_of_match,
+ },
+ .probe = tegra210_pinctrl_probe,
+ .remove = tegra_pinctrl_remove,
+};
+module_platform_driver(tegra210_pinctrl_driver);
+
+MODULE_AUTHOR("NVIDIA");
+MODULE_DESCRIPTION("NVIDIA Tegra210 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * Pinctrl data for the NVIDIA Tegra30 pinmux
+ *
+ * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "pinctrl-tegra.h"
+
+/*
+ * Most pins affected by the pinmux can also be GPIOs. Define these first.
+ * These must match how the GPIO driver names/numbers its pins.
+ */
+#define _GPIO(offset) (offset)
+
+#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
+#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
+#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
+#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
+#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
+#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
+#define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
+#define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
+#define TEGRA_PIN_GMI_A17_PB0 _GPIO(8)
+#define TEGRA_PIN_GMI_A18_PB1 _GPIO(9)
+#define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10)
+#define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11)
+#define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
+#define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
+#define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
+#define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
+#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
+#define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17)
+#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
+#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
+#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
+#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
+#define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22)
+#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
+#define TEGRA_PIN_SDMMC3_DAT5_PD0 _GPIO(24)
+#define TEGRA_PIN_SDMMC3_DAT4_PD1 _GPIO(25)
+#define TEGRA_PIN_LCD_DC1_PD2 _GPIO(26)
+#define TEGRA_PIN_SDMMC3_DAT6_PD3 _GPIO(27)
+#define TEGRA_PIN_SDMMC3_DAT7_PD4 _GPIO(28)
+#define TEGRA_PIN_VI_D1_PD5 _GPIO(29)
+#define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30)
+#define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31)
+#define TEGRA_PIN_LCD_D0_PE0 _GPIO(32)
+#define TEGRA_PIN_LCD_D1_PE1 _GPIO(33)
+#define TEGRA_PIN_LCD_D2_PE2 _GPIO(34)
+#define TEGRA_PIN_LCD_D3_PE3 _GPIO(35)
+#define TEGRA_PIN_LCD_D4_PE4 _GPIO(36)
+#define TEGRA_PIN_LCD_D5_PE5 _GPIO(37)
+#define TEGRA_PIN_LCD_D6_PE6 _GPIO(38)
+#define TEGRA_PIN_LCD_D7_PE7 _GPIO(39)
+#define TEGRA_PIN_LCD_D8_PF0 _GPIO(40)
+#define TEGRA_PIN_LCD_D9_PF1 _GPIO(41)
+#define TEGRA_PIN_LCD_D10_PF2 _GPIO(42)
+#define TEGRA_PIN_LCD_D11_PF3 _GPIO(43)
+#define TEGRA_PIN_LCD_D12_PF4 _GPIO(44)
+#define TEGRA_PIN_LCD_D13_PF5 _GPIO(45)
+#define TEGRA_PIN_LCD_D14_PF6 _GPIO(46)
+#define TEGRA_PIN_LCD_D15_PF7 _GPIO(47)
+#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
+#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
+#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
+#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
+#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
+#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
+#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
+#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
+#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
+#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
+#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
+#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
+#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
+#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
+#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
+#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
+#define TEGRA_PIN_GMI_WR_N_PI0 _GPIO(64)
+#define TEGRA_PIN_GMI_OE_N_PI1 _GPIO(65)
+#define TEGRA_PIN_GMI_DQS_PI2 _GPIO(66)
+#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
+#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
+#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
+#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
+#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
+#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
+#define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73)
+#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
+#define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75)
+#define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76)
+#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
+#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
+#define TEGRA_PIN_GMI_A16_PJ7 _GPIO(79)
+#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
+#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
+#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
+#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
+#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
+#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
+#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
+#define TEGRA_PIN_GMI_A19_PK7 _GPIO(87)
+#define TEGRA_PIN_VI_D2_PL0 _GPIO(88)
+#define TEGRA_PIN_VI_D3_PL1 _GPIO(89)
+#define TEGRA_PIN_VI_D4_PL2 _GPIO(90)
+#define TEGRA_PIN_VI_D5_PL3 _GPIO(91)
+#define TEGRA_PIN_VI_D6_PL4 _GPIO(92)
+#define TEGRA_PIN_VI_D7_PL5 _GPIO(93)
+#define TEGRA_PIN_VI_D8_PL6 _GPIO(94)
+#define TEGRA_PIN_VI_D9_PL7 _GPIO(95)
+#define TEGRA_PIN_LCD_D16_PM0 _GPIO(96)
+#define TEGRA_PIN_LCD_D17_PM1 _GPIO(97)
+#define TEGRA_PIN_LCD_D18_PM2 _GPIO(98)
+#define TEGRA_PIN_LCD_D19_PM3 _GPIO(99)
+#define TEGRA_PIN_LCD_D20_PM4 _GPIO(100)
+#define TEGRA_PIN_LCD_D21_PM5 _GPIO(101)
+#define TEGRA_PIN_LCD_D22_PM6 _GPIO(102)
+#define TEGRA_PIN_LCD_D23_PM7 _GPIO(103)
+#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
+#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
+#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
+#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
+#define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108)
+#define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109)
+#define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110)
+#define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
+#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
+#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
+#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
+#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
+#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
+#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
+#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
+#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
+#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
+#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
+#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
+#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
+#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
+#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
+#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
+#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
+#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
+#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
+#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
+#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
+#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
+#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
+#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
+#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
+#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
+#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
+#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
+#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
+#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
+#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
+#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
+#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
+#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
+#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
+#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
+#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
+#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
+#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
+#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
+#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
+#define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152)
+#define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153)
+#define TEGRA_PIN_VI_D10_PT2 _GPIO(154)
+#define TEGRA_PIN_VI_D11_PT3 _GPIO(155)
+#define TEGRA_PIN_VI_D0_PT4 _GPIO(156)
+#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
+#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
+#define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
+#define TEGRA_PIN_PU0 _GPIO(160)
+#define TEGRA_PIN_PU1 _GPIO(161)
+#define TEGRA_PIN_PU2 _GPIO(162)
+#define TEGRA_PIN_PU3 _GPIO(163)
+#define TEGRA_PIN_PU4 _GPIO(164)
+#define TEGRA_PIN_PU5 _GPIO(165)
+#define TEGRA_PIN_PU6 _GPIO(166)
+#define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167)
+#define TEGRA_PIN_PV0 _GPIO(168)
+#define TEGRA_PIN_PV1 _GPIO(169)
+#define TEGRA_PIN_PV2 _GPIO(170)
+#define TEGRA_PIN_PV3 _GPIO(171)
+#define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
+#define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
+#define TEGRA_PIN_CRT_HSYNC_PV6 _GPIO(174)
+#define TEGRA_PIN_CRT_VSYNC_PV7 _GPIO(175)
+#define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176)
+#define TEGRA_PIN_LCD_M1_PW1 _GPIO(177)
+#define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178)
+#define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179)
+#define TEGRA_PIN_CLK1_OUT_PW4 _GPIO(180)
+#define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
+#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
+#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
+#define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184)
+#define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185)
+#define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186)
+#define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187)
+#define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188)
+#define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189)
+#define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190)
+#define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191)
+#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
+#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
+#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
+#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
+#define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
+#define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
+#define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
+#define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
+#define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
+#define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
+#define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202)
+#define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203)
+#define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204)
+#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
+#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
+#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
+#define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
+#define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
+#define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
+#define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
+#define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
+#define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
+#define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
+#define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
+#define TEGRA_PIN_PBB0 _GPIO(216)
+#define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
+#define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
+#define TEGRA_PIN_PBB3 _GPIO(219)
+#define TEGRA_PIN_PBB4 _GPIO(220)
+#define TEGRA_PIN_PBB5 _GPIO(221)
+#define TEGRA_PIN_PBB6 _GPIO(222)
+#define TEGRA_PIN_PBB7 _GPIO(223)
+#define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
+#define TEGRA_PIN_PCC1 _GPIO(225)
+#define TEGRA_PIN_PCC2 _GPIO(226)
+#define TEGRA_PIN_SDMMC4_RST_N_PCC3 _GPIO(227)
+#define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
+#define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
+#define TEGRA_PIN_PEX_L2_RST_N_PCC6 _GPIO(230)
+#define TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7 _GPIO(231)
+#define TEGRA_PIN_PEX_L0_PRSNT_N_PDD0 _GPIO(232)
+#define TEGRA_PIN_PEX_L0_RST_N_PDD1 _GPIO(233)
+#define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2 _GPIO(234)
+#define TEGRA_PIN_PEX_WAKE_N_PDD3 _GPIO(235)
+#define TEGRA_PIN_PEX_L1_PRSNT_N_PDD4 _GPIO(236)
+#define TEGRA_PIN_PEX_L1_RST_N_PDD5 _GPIO(237)
+#define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6 _GPIO(238)
+#define TEGRA_PIN_PEX_L2_PRSNT_N_PDD7 _GPIO(239)
+#define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
+#define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
+#define TEGRA_PIN_CLK1_REQ_PEE2 _GPIO(242)
+#define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
+#define TEGRA_PIN_PEE4 _GPIO(244)
+#define TEGRA_PIN_PEE5 _GPIO(245)
+#define TEGRA_PIN_PEE6 _GPIO(246)
+#define TEGRA_PIN_PEE7 _GPIO(247)
+
+/* All non-GPIO pins follow */
+#define NUM_GPIOS (TEGRA_PIN_PEE7 + 1)
+#define _PIN(offset) (NUM_GPIOS + (offset))
+
+/* Non-GPIO pins */
+#define TEGRA_PIN_CLK_32K_IN _PIN(0)
+#define TEGRA_PIN_CORE_PWR_REQ _PIN(1)
+#define TEGRA_PIN_CPU_PWR_REQ _PIN(2)
+#define TEGRA_PIN_JTAG_TCK _PIN(3)
+#define TEGRA_PIN_JTAG_TDI _PIN(4)
+#define TEGRA_PIN_JTAG_TDO _PIN(5)
+#define TEGRA_PIN_JTAG_TMS _PIN(6)
+#define TEGRA_PIN_JTAG_TRST_N _PIN(7)
+#define TEGRA_PIN_OWR _PIN(8)
+#define TEGRA_PIN_PWR_INT_N _PIN(9)
+#define TEGRA_PIN_SYS_RESET_N _PIN(10)
+#define TEGRA_PIN_TEST_MODE_EN _PIN(11)
+
+static const struct pinctrl_pin_desc tegra30_pins[] = {
+ PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
+ PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
+ PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT5_PD0, "SDMMC3_DAT5 PD0"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, "SDMMC3_DAT4 PD1"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, "LCD_DC1 PD2"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, "SDMMC3_DAT6 PD3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, "SDMMC3_DAT7 PD4"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
+ PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
+ PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_DQS_PI2, "GMI_DQS PI2"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
+ PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
+ PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
+ PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
+ PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
+ PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
+ PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
+ PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
+ PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
+ PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VI_D10 PT2"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
+ PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
+ PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
+ PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
+ PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
+ PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
+ PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
+ PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
+ PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
+ PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
+ PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
+ PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
+ PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
+ PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
+ PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
+ PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC_PV6, "CRT_HSYNC PV6"),
+ PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC_PV7, "CRT_VSYNC PV7"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
+ PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
+ PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
+ PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
+ PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
+ PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
+ PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
+ PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
+ PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
+ PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
+ PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
+ PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
+ PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
+ PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
+ PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_RST_N_PCC3, "SDMMC4_RST_N PCC3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
+ PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PCC6, "PEX_L2_RST_N PCC6"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7, "PEX_L2_CLKREQ_N PCC7"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L0_PRSNT_N_PDD0, "PEX_L0_PRSNT_N PDD0"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L1_PRSNT_N_PDD4, "PEX_L1_PRSNT_N PDD4"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L2_PRSNT_N_PDD7, "PEX_L2_PRSNT_N PDD7"),
+ PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
+ PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
+ PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
+ PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
+ PINCTRL_PIN(TEGRA_PIN_PEE4, "PEE4"),
+ PINCTRL_PIN(TEGRA_PIN_PEE5, "PEE5"),
+ PINCTRL_PIN(TEGRA_PIN_PEE6, "PEE6"),
+ PINCTRL_PIN(TEGRA_PIN_PEE7, "PEE7"),
+ PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
+ PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
+ PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
+ PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
+ PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
+ PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
+ PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
+};
+
+static const unsigned clk_32k_out_pa0_pins[] = {
+ TEGRA_PIN_CLK_32K_OUT_PA0,
+};
+
+static const unsigned uart3_cts_n_pa1_pins[] = {
+ TEGRA_PIN_UART3_CTS_N_PA1,
+};
+
+static const unsigned dap2_fs_pa2_pins[] = {
+ TEGRA_PIN_DAP2_FS_PA2,
+};
+
+static const unsigned dap2_sclk_pa3_pins[] = {
+ TEGRA_PIN_DAP2_SCLK_PA3,
+};
+
+static const unsigned dap2_din_pa4_pins[] = {
+ TEGRA_PIN_DAP2_DIN_PA4,
+};
+
+static const unsigned dap2_dout_pa5_pins[] = {
+ TEGRA_PIN_DAP2_DOUT_PA5,
+};
+
+static const unsigned sdmmc3_clk_pa6_pins[] = {
+ TEGRA_PIN_SDMMC3_CLK_PA6,
+};
+
+static const unsigned sdmmc3_cmd_pa7_pins[] = {
+ TEGRA_PIN_SDMMC3_CMD_PA7,
+};
+
+static const unsigned gmi_a17_pb0_pins[] = {
+ TEGRA_PIN_GMI_A17_PB0,
+};
+
+static const unsigned gmi_a18_pb1_pins[] = {
+ TEGRA_PIN_GMI_A18_PB1,
+};
+
+static const unsigned lcd_pwr0_pb2_pins[] = {
+ TEGRA_PIN_LCD_PWR0_PB2,
+};
+
+static const unsigned lcd_pclk_pb3_pins[] = {
+ TEGRA_PIN_LCD_PCLK_PB3,
+};
+
+static const unsigned sdmmc3_dat3_pb4_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT3_PB4,
+};
+
+static const unsigned sdmmc3_dat2_pb5_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT2_PB5,
+};
+
+static const unsigned sdmmc3_dat1_pb6_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT1_PB6,
+};
+
+static const unsigned sdmmc3_dat0_pb7_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT0_PB7,
+};
+
+static const unsigned uart3_rts_n_pc0_pins[] = {
+ TEGRA_PIN_UART3_RTS_N_PC0,
+};
+
+static const unsigned lcd_pwr1_pc1_pins[] = {
+ TEGRA_PIN_LCD_PWR1_PC1,
+};
+
+static const unsigned uart2_txd_pc2_pins[] = {
+ TEGRA_PIN_UART2_TXD_PC2,
+};
+
+static const unsigned uart2_rxd_pc3_pins[] = {
+ TEGRA_PIN_UART2_RXD_PC3,
+};
+
+static const unsigned gen1_i2c_scl_pc4_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SCL_PC4,
+};
+
+static const unsigned gen1_i2c_sda_pc5_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SDA_PC5,
+};
+
+static const unsigned lcd_pwr2_pc6_pins[] = {
+ TEGRA_PIN_LCD_PWR2_PC6,
+};
+
+static const unsigned gmi_wp_n_pc7_pins[] = {
+ TEGRA_PIN_GMI_WP_N_PC7,
+};
+
+static const unsigned sdmmc3_dat5_pd0_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT5_PD0,
+};
+
+static const unsigned sdmmc3_dat4_pd1_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT4_PD1,
+};
+
+static const unsigned lcd_dc1_pd2_pins[] = {
+ TEGRA_PIN_LCD_DC1_PD2,
+};
+
+static const unsigned sdmmc3_dat6_pd3_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT6_PD3,
+};
+
+static const unsigned sdmmc3_dat7_pd4_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT7_PD4,
+};
+
+static const unsigned vi_d1_pd5_pins[] = {
+ TEGRA_PIN_VI_D1_PD5,
+};
+
+static const unsigned vi_vsync_pd6_pins[] = {
+ TEGRA_PIN_VI_VSYNC_PD6,
+};
+
+static const unsigned vi_hsync_pd7_pins[] = {
+ TEGRA_PIN_VI_HSYNC_PD7,
+};
+
+static const unsigned lcd_d0_pe0_pins[] = {
+ TEGRA_PIN_LCD_D0_PE0,
+};
+
+static const unsigned lcd_d1_pe1_pins[] = {
+ TEGRA_PIN_LCD_D1_PE1,
+};
+
+static const unsigned lcd_d2_pe2_pins[] = {
+ TEGRA_PIN_LCD_D2_PE2,
+};
+
+static const unsigned lcd_d3_pe3_pins[] = {
+ TEGRA_PIN_LCD_D3_PE3,
+};
+
+static const unsigned lcd_d4_pe4_pins[] = {
+ TEGRA_PIN_LCD_D4_PE4,
+};
+
+static const unsigned lcd_d5_pe5_pins[] = {
+ TEGRA_PIN_LCD_D5_PE5,
+};
+
+static const unsigned lcd_d6_pe6_pins[] = {
+ TEGRA_PIN_LCD_D6_PE6,
+};
+
+static const unsigned lcd_d7_pe7_pins[] = {
+ TEGRA_PIN_LCD_D7_PE7,
+};
+
+static const unsigned lcd_d8_pf0_pins[] = {
+ TEGRA_PIN_LCD_D8_PF0,
+};
+
+static const unsigned lcd_d9_pf1_pins[] = {
+ TEGRA_PIN_LCD_D9_PF1,
+};
+
+static const unsigned lcd_d10_pf2_pins[] = {
+ TEGRA_PIN_LCD_D10_PF2,
+};
+
+static const unsigned lcd_d11_pf3_pins[] = {
+ TEGRA_PIN_LCD_D11_PF3,
+};
+
+static const unsigned lcd_d12_pf4_pins[] = {
+ TEGRA_PIN_LCD_D12_PF4,
+};
+
+static const unsigned lcd_d13_pf5_pins[] = {
+ TEGRA_PIN_LCD_D13_PF5,
+};
+
+static const unsigned lcd_d14_pf6_pins[] = {
+ TEGRA_PIN_LCD_D14_PF6,
+};
+
+static const unsigned lcd_d15_pf7_pins[] = {
+ TEGRA_PIN_LCD_D15_PF7,
+};
+
+static const unsigned gmi_ad0_pg0_pins[] = {
+ TEGRA_PIN_GMI_AD0_PG0,
+};
+
+static const unsigned gmi_ad1_pg1_pins[] = {
+ TEGRA_PIN_GMI_AD1_PG1,
+};
+
+static const unsigned gmi_ad2_pg2_pins[] = {
+ TEGRA_PIN_GMI_AD2_PG2,
+};
+
+static const unsigned gmi_ad3_pg3_pins[] = {
+ TEGRA_PIN_GMI_AD3_PG3,
+};
+
+static const unsigned gmi_ad4_pg4_pins[] = {
+ TEGRA_PIN_GMI_AD4_PG4,
+};
+
+static const unsigned gmi_ad5_pg5_pins[] = {
+ TEGRA_PIN_GMI_AD5_PG5,
+};
+
+static const unsigned gmi_ad6_pg6_pins[] = {
+ TEGRA_PIN_GMI_AD6_PG6,
+};
+
+static const unsigned gmi_ad7_pg7_pins[] = {
+ TEGRA_PIN_GMI_AD7_PG7,
+};
+
+static const unsigned gmi_ad8_ph0_pins[] = {
+ TEGRA_PIN_GMI_AD8_PH0,
+};
+
+static const unsigned gmi_ad9_ph1_pins[] = {
+ TEGRA_PIN_GMI_AD9_PH1,
+};
+
+static const unsigned gmi_ad10_ph2_pins[] = {
+ TEGRA_PIN_GMI_AD10_PH2,
+};
+
+static const unsigned gmi_ad11_ph3_pins[] = {
+ TEGRA_PIN_GMI_AD11_PH3,
+};
+
+static const unsigned gmi_ad12_ph4_pins[] = {
+ TEGRA_PIN_GMI_AD12_PH4,
+};
+
+static const unsigned gmi_ad13_ph5_pins[] = {
+ TEGRA_PIN_GMI_AD13_PH5,
+};
+
+static const unsigned gmi_ad14_ph6_pins[] = {
+ TEGRA_PIN_GMI_AD14_PH6,
+};
+
+static const unsigned gmi_ad15_ph7_pins[] = {
+ TEGRA_PIN_GMI_AD15_PH7,
+};
+
+static const unsigned gmi_wr_n_pi0_pins[] = {
+ TEGRA_PIN_GMI_WR_N_PI0,
+};
+
+static const unsigned gmi_oe_n_pi1_pins[] = {
+ TEGRA_PIN_GMI_OE_N_PI1,
+};
+
+static const unsigned gmi_dqs_pi2_pins[] = {
+ TEGRA_PIN_GMI_DQS_PI2,
+};
+
+static const unsigned gmi_cs6_n_pi3_pins[] = {
+ TEGRA_PIN_GMI_CS6_N_PI3,
+};
+
+static const unsigned gmi_rst_n_pi4_pins[] = {
+ TEGRA_PIN_GMI_RST_N_PI4,
+};
+
+static const unsigned gmi_iordy_pi5_pins[] = {
+ TEGRA_PIN_GMI_IORDY_PI5,
+};
+
+static const unsigned gmi_cs7_n_pi6_pins[] = {
+ TEGRA_PIN_GMI_CS7_N_PI6,
+};
+
+static const unsigned gmi_wait_pi7_pins[] = {
+ TEGRA_PIN_GMI_WAIT_PI7,
+};
+
+static const unsigned gmi_cs0_n_pj0_pins[] = {
+ TEGRA_PIN_GMI_CS0_N_PJ0,
+};
+
+static const unsigned lcd_de_pj1_pins[] = {
+ TEGRA_PIN_LCD_DE_PJ1,
+};
+
+static const unsigned gmi_cs1_n_pj2_pins[] = {
+ TEGRA_PIN_GMI_CS1_N_PJ2,
+};
+
+static const unsigned lcd_hsync_pj3_pins[] = {
+ TEGRA_PIN_LCD_HSYNC_PJ3,
+};
+
+static const unsigned lcd_vsync_pj4_pins[] = {
+ TEGRA_PIN_LCD_VSYNC_PJ4,
+};
+
+static const unsigned uart2_cts_n_pj5_pins[] = {
+ TEGRA_PIN_UART2_CTS_N_PJ5,
+};
+
+static const unsigned uart2_rts_n_pj6_pins[] = {
+ TEGRA_PIN_UART2_RTS_N_PJ6,
+};
+
+static const unsigned gmi_a16_pj7_pins[] = {
+ TEGRA_PIN_GMI_A16_PJ7,
+};
+
+static const unsigned gmi_adv_n_pk0_pins[] = {
+ TEGRA_PIN_GMI_ADV_N_PK0,
+};
+
+static const unsigned gmi_clk_pk1_pins[] = {
+ TEGRA_PIN_GMI_CLK_PK1,
+};
+
+static const unsigned gmi_cs4_n_pk2_pins[] = {
+ TEGRA_PIN_GMI_CS4_N_PK2,
+};
+
+static const unsigned gmi_cs2_n_pk3_pins[] = {
+ TEGRA_PIN_GMI_CS2_N_PK3,
+};
+
+static const unsigned gmi_cs3_n_pk4_pins[] = {
+ TEGRA_PIN_GMI_CS3_N_PK4,
+};
+
+static const unsigned spdif_out_pk5_pins[] = {
+ TEGRA_PIN_SPDIF_OUT_PK5,
+};
+
+static const unsigned spdif_in_pk6_pins[] = {
+ TEGRA_PIN_SPDIF_IN_PK6,
+};
+
+static const unsigned gmi_a19_pk7_pins[] = {
+ TEGRA_PIN_GMI_A19_PK7,
+};
+
+static const unsigned vi_d2_pl0_pins[] = {
+ TEGRA_PIN_VI_D2_PL0,
+};
+
+static const unsigned vi_d3_pl1_pins[] = {
+ TEGRA_PIN_VI_D3_PL1,
+};
+
+static const unsigned vi_d4_pl2_pins[] = {
+ TEGRA_PIN_VI_D4_PL2,
+};
+
+static const unsigned vi_d5_pl3_pins[] = {
+ TEGRA_PIN_VI_D5_PL3,
+};
+
+static const unsigned vi_d6_pl4_pins[] = {
+ TEGRA_PIN_VI_D6_PL4,
+};
+
+static const unsigned vi_d7_pl5_pins[] = {
+ TEGRA_PIN_VI_D7_PL5,
+};
+
+static const unsigned vi_d8_pl6_pins[] = {
+ TEGRA_PIN_VI_D8_PL6,
+};
+
+static const unsigned vi_d9_pl7_pins[] = {
+ TEGRA_PIN_VI_D9_PL7,
+};
+
+static const unsigned lcd_d16_pm0_pins[] = {
+ TEGRA_PIN_LCD_D16_PM0,
+};
+
+static const unsigned lcd_d17_pm1_pins[] = {
+ TEGRA_PIN_LCD_D17_PM1,
+};
+
+static const unsigned lcd_d18_pm2_pins[] = {
+ TEGRA_PIN_LCD_D18_PM2,
+};
+
+static const unsigned lcd_d19_pm3_pins[] = {
+ TEGRA_PIN_LCD_D19_PM3,
+};
+
+static const unsigned lcd_d20_pm4_pins[] = {
+ TEGRA_PIN_LCD_D20_PM4,
+};
+
+static const unsigned lcd_d21_pm5_pins[] = {
+ TEGRA_PIN_LCD_D21_PM5,
+};
+
+static const unsigned lcd_d22_pm6_pins[] = {
+ TEGRA_PIN_LCD_D22_PM6,
+};
+
+static const unsigned lcd_d23_pm7_pins[] = {
+ TEGRA_PIN_LCD_D23_PM7,
+};
+
+static const unsigned dap1_fs_pn0_pins[] = {
+ TEGRA_PIN_DAP1_FS_PN0,
+};
+
+static const unsigned dap1_din_pn1_pins[] = {
+ TEGRA_PIN_DAP1_DIN_PN1,
+};
+
+static const unsigned dap1_dout_pn2_pins[] = {
+ TEGRA_PIN_DAP1_DOUT_PN2,
+};
+
+static const unsigned dap1_sclk_pn3_pins[] = {
+ TEGRA_PIN_DAP1_SCLK_PN3,
+};
+
+static const unsigned lcd_cs0_n_pn4_pins[] = {
+ TEGRA_PIN_LCD_CS0_N_PN4,
+};
+
+static const unsigned lcd_sdout_pn5_pins[] = {
+ TEGRA_PIN_LCD_SDOUT_PN5,
+};
+
+static const unsigned lcd_dc0_pn6_pins[] = {
+ TEGRA_PIN_LCD_DC0_PN6,
+};
+
+static const unsigned hdmi_int_pn7_pins[] = {
+ TEGRA_PIN_HDMI_INT_PN7,
+};
+
+static const unsigned ulpi_data7_po0_pins[] = {
+ TEGRA_PIN_ULPI_DATA7_PO0,
+};
+
+static const unsigned ulpi_data0_po1_pins[] = {
+ TEGRA_PIN_ULPI_DATA0_PO1,
+};
+
+static const unsigned ulpi_data1_po2_pins[] = {
+ TEGRA_PIN_ULPI_DATA1_PO2,
+};
+
+static const unsigned ulpi_data2_po3_pins[] = {
+ TEGRA_PIN_ULPI_DATA2_PO3,
+};
+
+static const unsigned ulpi_data3_po4_pins[] = {
+ TEGRA_PIN_ULPI_DATA3_PO4,
+};
+
+static const unsigned ulpi_data4_po5_pins[] = {
+ TEGRA_PIN_ULPI_DATA4_PO5,
+};
+
+static const unsigned ulpi_data5_po6_pins[] = {
+ TEGRA_PIN_ULPI_DATA5_PO6,
+};
+
+static const unsigned ulpi_data6_po7_pins[] = {
+ TEGRA_PIN_ULPI_DATA6_PO7,
+};
+
+static const unsigned dap3_fs_pp0_pins[] = {
+ TEGRA_PIN_DAP3_FS_PP0,
+};
+
+static const unsigned dap3_din_pp1_pins[] = {
+ TEGRA_PIN_DAP3_DIN_PP1,
+};
+
+static const unsigned dap3_dout_pp2_pins[] = {
+ TEGRA_PIN_DAP3_DOUT_PP2,
+};
+
+static const unsigned dap3_sclk_pp3_pins[] = {
+ TEGRA_PIN_DAP3_SCLK_PP3,
+};
+
+static const unsigned dap4_fs_pp4_pins[] = {
+ TEGRA_PIN_DAP4_FS_PP4,
+};
+
+static const unsigned dap4_din_pp5_pins[] = {
+ TEGRA_PIN_DAP4_DIN_PP5,
+};
+
+static const unsigned dap4_dout_pp6_pins[] = {
+ TEGRA_PIN_DAP4_DOUT_PP6,
+};
+
+static const unsigned dap4_sclk_pp7_pins[] = {
+ TEGRA_PIN_DAP4_SCLK_PP7,
+};
+
+static const unsigned kb_col0_pq0_pins[] = {
+ TEGRA_PIN_KB_COL0_PQ0,
+};
+
+static const unsigned kb_col1_pq1_pins[] = {
+ TEGRA_PIN_KB_COL1_PQ1,
+};
+
+static const unsigned kb_col2_pq2_pins[] = {
+ TEGRA_PIN_KB_COL2_PQ2,
+};
+
+static const unsigned kb_col3_pq3_pins[] = {
+ TEGRA_PIN_KB_COL3_PQ3,
+};
+
+static const unsigned kb_col4_pq4_pins[] = {
+ TEGRA_PIN_KB_COL4_PQ4,
+};
+
+static const unsigned kb_col5_pq5_pins[] = {
+ TEGRA_PIN_KB_COL5_PQ5,
+};
+
+static const unsigned kb_col6_pq6_pins[] = {
+ TEGRA_PIN_KB_COL6_PQ6,
+};
+
+static const unsigned kb_col7_pq7_pins[] = {
+ TEGRA_PIN_KB_COL7_PQ7,
+};
+
+static const unsigned kb_row0_pr0_pins[] = {
+ TEGRA_PIN_KB_ROW0_PR0,
+};
+
+static const unsigned kb_row1_pr1_pins[] = {
+ TEGRA_PIN_KB_ROW1_PR1,
+};
+
+static const unsigned kb_row2_pr2_pins[] = {
+ TEGRA_PIN_KB_ROW2_PR2,
+};
+
+static const unsigned kb_row3_pr3_pins[] = {
+ TEGRA_PIN_KB_ROW3_PR3,
+};
+
+static const unsigned kb_row4_pr4_pins[] = {
+ TEGRA_PIN_KB_ROW4_PR4,
+};
+
+static const unsigned kb_row5_pr5_pins[] = {
+ TEGRA_PIN_KB_ROW5_PR5,
+};
+
+static const unsigned kb_row6_pr6_pins[] = {
+ TEGRA_PIN_KB_ROW6_PR6,
+};
+
+static const unsigned kb_row7_pr7_pins[] = {
+ TEGRA_PIN_KB_ROW7_PR7,
+};
+
+static const unsigned kb_row8_ps0_pins[] = {
+ TEGRA_PIN_KB_ROW8_PS0,
+};
+
+static const unsigned kb_row9_ps1_pins[] = {
+ TEGRA_PIN_KB_ROW9_PS1,
+};
+
+static const unsigned kb_row10_ps2_pins[] = {
+ TEGRA_PIN_KB_ROW10_PS2,
+};
+
+static const unsigned kb_row11_ps3_pins[] = {
+ TEGRA_PIN_KB_ROW11_PS3,
+};
+
+static const unsigned kb_row12_ps4_pins[] = {
+ TEGRA_PIN_KB_ROW12_PS4,
+};
+
+static const unsigned kb_row13_ps5_pins[] = {
+ TEGRA_PIN_KB_ROW13_PS5,
+};
+
+static const unsigned kb_row14_ps6_pins[] = {
+ TEGRA_PIN_KB_ROW14_PS6,
+};
+
+static const unsigned kb_row15_ps7_pins[] = {
+ TEGRA_PIN_KB_ROW15_PS7,
+};
+
+static const unsigned vi_pclk_pt0_pins[] = {
+ TEGRA_PIN_VI_PCLK_PT0,
+};
+
+static const unsigned vi_mclk_pt1_pins[] = {
+ TEGRA_PIN_VI_MCLK_PT1,
+};
+
+static const unsigned vi_d10_pt2_pins[] = {
+ TEGRA_PIN_VI_D10_PT2,
+};
+
+static const unsigned vi_d11_pt3_pins[] = {
+ TEGRA_PIN_VI_D11_PT3,
+};
+
+static const unsigned vi_d0_pt4_pins[] = {
+ TEGRA_PIN_VI_D0_PT4,
+};
+
+static const unsigned gen2_i2c_scl_pt5_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SCL_PT5,
+};
+
+static const unsigned gen2_i2c_sda_pt6_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SDA_PT6,
+};
+
+static const unsigned sdmmc4_cmd_pt7_pins[] = {
+ TEGRA_PIN_SDMMC4_CMD_PT7,
+};
+
+static const unsigned pu0_pins[] = {
+ TEGRA_PIN_PU0,
+};
+
+static const unsigned pu1_pins[] = {
+ TEGRA_PIN_PU1,
+};
+
+static const unsigned pu2_pins[] = {
+ TEGRA_PIN_PU2,
+};
+
+static const unsigned pu3_pins[] = {
+ TEGRA_PIN_PU3,
+};
+
+static const unsigned pu4_pins[] = {
+ TEGRA_PIN_PU4,
+};
+
+static const unsigned pu5_pins[] = {
+ TEGRA_PIN_PU5,
+};
+
+static const unsigned pu6_pins[] = {
+ TEGRA_PIN_PU6,
+};
+
+static const unsigned jtag_rtck_pu7_pins[] = {
+ TEGRA_PIN_JTAG_RTCK_PU7,
+};
+
+static const unsigned pv0_pins[] = {
+ TEGRA_PIN_PV0,
+};
+
+static const unsigned pv1_pins[] = {
+ TEGRA_PIN_PV1,
+};
+
+static const unsigned pv2_pins[] = {
+ TEGRA_PIN_PV2,
+};
+
+static const unsigned pv3_pins[] = {
+ TEGRA_PIN_PV3,
+};
+
+static const unsigned ddc_scl_pv4_pins[] = {
+ TEGRA_PIN_DDC_SCL_PV4,
+};
+
+static const unsigned ddc_sda_pv5_pins[] = {
+ TEGRA_PIN_DDC_SDA_PV5,
+};
+
+static const unsigned crt_hsync_pv6_pins[] = {
+ TEGRA_PIN_CRT_HSYNC_PV6,
+};
+
+static const unsigned crt_vsync_pv7_pins[] = {
+ TEGRA_PIN_CRT_VSYNC_PV7,
+};
+
+static const unsigned lcd_cs1_n_pw0_pins[] = {
+ TEGRA_PIN_LCD_CS1_N_PW0,
+};
+
+static const unsigned lcd_m1_pw1_pins[] = {
+ TEGRA_PIN_LCD_M1_PW1,
+};
+
+static const unsigned spi2_cs1_n_pw2_pins[] = {
+ TEGRA_PIN_SPI2_CS1_N_PW2,
+};
+
+static const unsigned spi2_cs2_n_pw3_pins[] = {
+ TEGRA_PIN_SPI2_CS2_N_PW3,
+};
+
+static const unsigned clk1_out_pw4_pins[] = {
+ TEGRA_PIN_CLK1_OUT_PW4,
+};
+
+static const unsigned clk2_out_pw5_pins[] = {
+ TEGRA_PIN_CLK2_OUT_PW5,
+};
+
+static const unsigned uart3_txd_pw6_pins[] = {
+ TEGRA_PIN_UART3_TXD_PW6,
+};
+
+static const unsigned uart3_rxd_pw7_pins[] = {
+ TEGRA_PIN_UART3_RXD_PW7,
+};
+
+static const unsigned spi2_mosi_px0_pins[] = {
+ TEGRA_PIN_SPI2_MOSI_PX0,
+};
+
+static const unsigned spi2_miso_px1_pins[] = {
+ TEGRA_PIN_SPI2_MISO_PX1,
+};
+
+static const unsigned spi2_sck_px2_pins[] = {
+ TEGRA_PIN_SPI2_SCK_PX2,
+};
+
+static const unsigned spi2_cs0_n_px3_pins[] = {
+ TEGRA_PIN_SPI2_CS0_N_PX3,
+};
+
+static const unsigned spi1_mosi_px4_pins[] = {
+ TEGRA_PIN_SPI1_MOSI_PX4,
+};
+
+static const unsigned spi1_sck_px5_pins[] = {
+ TEGRA_PIN_SPI1_SCK_PX5,
+};
+
+static const unsigned spi1_cs0_n_px6_pins[] = {
+ TEGRA_PIN_SPI1_CS0_N_PX6,
+};
+
+static const unsigned spi1_miso_px7_pins[] = {
+ TEGRA_PIN_SPI1_MISO_PX7,
+};
+
+static const unsigned ulpi_clk_py0_pins[] = {
+ TEGRA_PIN_ULPI_CLK_PY0,
+};
+
+static const unsigned ulpi_dir_py1_pins[] = {
+ TEGRA_PIN_ULPI_DIR_PY1,
+};
+
+static const unsigned ulpi_nxt_py2_pins[] = {
+ TEGRA_PIN_ULPI_NXT_PY2,
+};
+
+static const unsigned ulpi_stp_py3_pins[] = {
+ TEGRA_PIN_ULPI_STP_PY3,
+};
+
+static const unsigned sdmmc1_dat3_py4_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT3_PY4,
+};
+
+static const unsigned sdmmc1_dat2_py5_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT2_PY5,
+};
+
+static const unsigned sdmmc1_dat1_py6_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT1_PY6,
+};
+
+static const unsigned sdmmc1_dat0_py7_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT0_PY7,
+};
+
+static const unsigned sdmmc1_clk_pz0_pins[] = {
+ TEGRA_PIN_SDMMC1_CLK_PZ0,
+};
+
+static const unsigned sdmmc1_cmd_pz1_pins[] = {
+ TEGRA_PIN_SDMMC1_CMD_PZ1,
+};
+
+static const unsigned lcd_sdin_pz2_pins[] = {
+ TEGRA_PIN_LCD_SDIN_PZ2,
+};
+
+static const unsigned lcd_wr_n_pz3_pins[] = {
+ TEGRA_PIN_LCD_WR_N_PZ3,
+};
+
+static const unsigned lcd_sck_pz4_pins[] = {
+ TEGRA_PIN_LCD_SCK_PZ4,
+};
+
+static const unsigned sys_clk_req_pz5_pins[] = {
+ TEGRA_PIN_SYS_CLK_REQ_PZ5,
+};
+
+static const unsigned pwr_i2c_scl_pz6_pins[] = {
+ TEGRA_PIN_PWR_I2C_SCL_PZ6,
+};
+
+static const unsigned pwr_i2c_sda_pz7_pins[] = {
+ TEGRA_PIN_PWR_I2C_SDA_PZ7,
+};
+
+static const unsigned sdmmc4_dat0_paa0_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT0_PAA0,
+};
+
+static const unsigned sdmmc4_dat1_paa1_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT1_PAA1,
+};
+
+static const unsigned sdmmc4_dat2_paa2_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT2_PAA2,
+};
+
+static const unsigned sdmmc4_dat3_paa3_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT3_PAA3,
+};
+
+static const unsigned sdmmc4_dat4_paa4_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT4_PAA4,
+};
+
+static const unsigned sdmmc4_dat5_paa5_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT5_PAA5,
+};
+
+static const unsigned sdmmc4_dat6_paa6_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT6_PAA6,
+};
+
+static const unsigned sdmmc4_dat7_paa7_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT7_PAA7,
+};
+
+static const unsigned pbb0_pins[] = {
+ TEGRA_PIN_PBB0,
+};
+
+static const unsigned cam_i2c_scl_pbb1_pins[] = {
+ TEGRA_PIN_CAM_I2C_SCL_PBB1,
+};
+
+static const unsigned cam_i2c_sda_pbb2_pins[] = {
+ TEGRA_PIN_CAM_I2C_SDA_PBB2,
+};
+
+static const unsigned pbb3_pins[] = {
+ TEGRA_PIN_PBB3,
+};
+
+static const unsigned pbb4_pins[] = {
+ TEGRA_PIN_PBB4,
+};
+
+static const unsigned pbb5_pins[] = {
+ TEGRA_PIN_PBB5,
+};
+
+static const unsigned pbb6_pins[] = {
+ TEGRA_PIN_PBB6,
+};
+
+static const unsigned pbb7_pins[] = {
+ TEGRA_PIN_PBB7,
+};
+
+static const unsigned cam_mclk_pcc0_pins[] = {
+ TEGRA_PIN_CAM_MCLK_PCC0,
+};
+
+static const unsigned pcc1_pins[] = {
+ TEGRA_PIN_PCC1,
+};
+
+static const unsigned pcc2_pins[] = {
+ TEGRA_PIN_PCC2,
+};
+
+static const unsigned sdmmc4_rst_n_pcc3_pins[] = {
+ TEGRA_PIN_SDMMC4_RST_N_PCC3,
+};
+
+static const unsigned sdmmc4_clk_pcc4_pins[] = {
+ TEGRA_PIN_SDMMC4_CLK_PCC4,
+};
+
+static const unsigned clk2_req_pcc5_pins[] = {
+ TEGRA_PIN_CLK2_REQ_PCC5,
+};
+
+static const unsigned pex_l2_rst_n_pcc6_pins[] = {
+ TEGRA_PIN_PEX_L2_RST_N_PCC6,
+};
+
+static const unsigned pex_l2_clkreq_n_pcc7_pins[] = {
+ TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
+};
+
+static const unsigned pex_l0_prsnt_n_pdd0_pins[] = {
+ TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
+};
+
+static const unsigned pex_l0_rst_n_pdd1_pins[] = {
+ TEGRA_PIN_PEX_L0_RST_N_PDD1,
+};
+
+static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
+ TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
+};
+
+static const unsigned pex_wake_n_pdd3_pins[] = {
+ TEGRA_PIN_PEX_WAKE_N_PDD3,
+};
+
+static const unsigned pex_l1_prsnt_n_pdd4_pins[] = {
+ TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
+};
+
+static const unsigned pex_l1_rst_n_pdd5_pins[] = {
+ TEGRA_PIN_PEX_L1_RST_N_PDD5,
+};
+
+static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
+ TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
+};
+
+static const unsigned pex_l2_prsnt_n_pdd7_pins[] = {
+ TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
+};
+
+static const unsigned clk3_out_pee0_pins[] = {
+ TEGRA_PIN_CLK3_OUT_PEE0,
+};
+
+static const unsigned clk3_req_pee1_pins[] = {
+ TEGRA_PIN_CLK3_REQ_PEE1,
+};
+
+static const unsigned clk1_req_pee2_pins[] = {
+ TEGRA_PIN_CLK1_REQ_PEE2,
+};
+
+static const unsigned hdmi_cec_pee3_pins[] = {
+ TEGRA_PIN_HDMI_CEC_PEE3,
+};
+
+static const unsigned clk_32k_in_pins[] = {
+ TEGRA_PIN_CLK_32K_IN,
+};
+
+static const unsigned core_pwr_req_pins[] = {
+ TEGRA_PIN_CORE_PWR_REQ,
+};
+
+static const unsigned cpu_pwr_req_pins[] = {
+ TEGRA_PIN_CPU_PWR_REQ,
+};
+
+static const unsigned owr_pins[] = {
+ TEGRA_PIN_OWR,
+};
+
+static const unsigned pwr_int_n_pins[] = {
+ TEGRA_PIN_PWR_INT_N,
+};
+
+static const unsigned drive_ao1_pins[] = {
+ TEGRA_PIN_KB_ROW0_PR0,
+ TEGRA_PIN_KB_ROW1_PR1,
+ TEGRA_PIN_KB_ROW2_PR2,
+ TEGRA_PIN_KB_ROW3_PR3,
+ TEGRA_PIN_KB_ROW4_PR4,
+ TEGRA_PIN_KB_ROW5_PR5,
+ TEGRA_PIN_KB_ROW6_PR6,
+ TEGRA_PIN_KB_ROW7_PR7,
+ TEGRA_PIN_PWR_I2C_SCL_PZ6,
+ TEGRA_PIN_PWR_I2C_SDA_PZ7,
+ TEGRA_PIN_SYS_RESET_N,
+};
+
+static const unsigned drive_ao2_pins[] = {
+ TEGRA_PIN_CLK_32K_OUT_PA0,
+ TEGRA_PIN_KB_COL0_PQ0,
+ TEGRA_PIN_KB_COL1_PQ1,
+ TEGRA_PIN_KB_COL2_PQ2,
+ TEGRA_PIN_KB_COL3_PQ3,
+ TEGRA_PIN_KB_COL4_PQ4,
+ TEGRA_PIN_KB_COL5_PQ5,
+ TEGRA_PIN_KB_COL6_PQ6,
+ TEGRA_PIN_KB_COL7_PQ7,
+ TEGRA_PIN_KB_ROW8_PS0,
+ TEGRA_PIN_KB_ROW9_PS1,
+ TEGRA_PIN_KB_ROW10_PS2,
+ TEGRA_PIN_KB_ROW11_PS3,
+ TEGRA_PIN_KB_ROW12_PS4,
+ TEGRA_PIN_KB_ROW13_PS5,
+ TEGRA_PIN_KB_ROW14_PS6,
+ TEGRA_PIN_KB_ROW15_PS7,
+ TEGRA_PIN_SYS_CLK_REQ_PZ5,
+ TEGRA_PIN_CLK_32K_IN,
+ TEGRA_PIN_CORE_PWR_REQ,
+ TEGRA_PIN_CPU_PWR_REQ,
+ TEGRA_PIN_PWR_INT_N,
+};
+
+static const unsigned drive_at1_pins[] = {
+ TEGRA_PIN_GMI_AD8_PH0,
+ TEGRA_PIN_GMI_AD9_PH1,
+ TEGRA_PIN_GMI_AD10_PH2,
+ TEGRA_PIN_GMI_AD11_PH3,
+ TEGRA_PIN_GMI_AD12_PH4,
+ TEGRA_PIN_GMI_AD13_PH5,
+ TEGRA_PIN_GMI_AD14_PH6,
+ TEGRA_PIN_GMI_AD15_PH7,
+ TEGRA_PIN_GMI_IORDY_PI5,
+ TEGRA_PIN_GMI_CS7_N_PI6,
+};
+
+static const unsigned drive_at2_pins[] = {
+ TEGRA_PIN_GMI_AD0_PG0,
+ TEGRA_PIN_GMI_AD1_PG1,
+ TEGRA_PIN_GMI_AD2_PG2,
+ TEGRA_PIN_GMI_AD3_PG3,
+ TEGRA_PIN_GMI_AD4_PG4,
+ TEGRA_PIN_GMI_AD5_PG5,
+ TEGRA_PIN_GMI_AD6_PG6,
+ TEGRA_PIN_GMI_AD7_PG7,
+ TEGRA_PIN_GMI_WR_N_PI0,
+ TEGRA_PIN_GMI_OE_N_PI1,
+ TEGRA_PIN_GMI_DQS_PI2,
+ TEGRA_PIN_GMI_CS6_N_PI3,
+ TEGRA_PIN_GMI_RST_N_PI4,
+ TEGRA_PIN_GMI_WAIT_PI7,
+ TEGRA_PIN_GMI_ADV_N_PK0,
+ TEGRA_PIN_GMI_CLK_PK1,
+ TEGRA_PIN_GMI_CS4_N_PK2,
+ TEGRA_PIN_GMI_CS2_N_PK3,
+ TEGRA_PIN_GMI_CS3_N_PK4,
+};
+
+static const unsigned drive_at3_pins[] = {
+ TEGRA_PIN_GMI_WP_N_PC7,
+ TEGRA_PIN_GMI_CS0_N_PJ0,
+};
+
+static const unsigned drive_at4_pins[] = {
+ TEGRA_PIN_GMI_A17_PB0,
+ TEGRA_PIN_GMI_A18_PB1,
+ TEGRA_PIN_GMI_CS1_N_PJ2,
+ TEGRA_PIN_GMI_A16_PJ7,
+ TEGRA_PIN_GMI_A19_PK7,
+};
+
+static const unsigned drive_at5_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SCL_PT5,
+ TEGRA_PIN_GEN2_I2C_SDA_PT6,
+};
+
+static const unsigned drive_cdev1_pins[] = {
+ TEGRA_PIN_CLK1_OUT_PW4,
+ TEGRA_PIN_CLK1_REQ_PEE2,
+};
+
+static const unsigned drive_cdev2_pins[] = {
+ TEGRA_PIN_CLK2_OUT_PW5,
+ TEGRA_PIN_CLK2_REQ_PCC5,
+};
+
+static const unsigned drive_cec_pins[] = {
+ TEGRA_PIN_HDMI_CEC_PEE3,
+};
+
+static const unsigned drive_crt_pins[] = {
+ TEGRA_PIN_CRT_HSYNC_PV6,
+ TEGRA_PIN_CRT_VSYNC_PV7,
+};
+
+static const unsigned drive_csus_pins[] = {
+ TEGRA_PIN_VI_MCLK_PT1,
+};
+
+static const unsigned drive_dap1_pins[] = {
+ TEGRA_PIN_SPDIF_OUT_PK5,
+ TEGRA_PIN_SPDIF_IN_PK6,
+ TEGRA_PIN_DAP1_FS_PN0,
+ TEGRA_PIN_DAP1_DIN_PN1,
+ TEGRA_PIN_DAP1_DOUT_PN2,
+ TEGRA_PIN_DAP1_SCLK_PN3,
+};
+
+static const unsigned drive_dap2_pins[] = {
+ TEGRA_PIN_DAP2_FS_PA2,
+ TEGRA_PIN_DAP2_SCLK_PA3,
+ TEGRA_PIN_DAP2_DIN_PA4,
+ TEGRA_PIN_DAP2_DOUT_PA5,
+};
+
+static const unsigned drive_dap3_pins[] = {
+ TEGRA_PIN_DAP3_FS_PP0,
+ TEGRA_PIN_DAP3_DIN_PP1,
+ TEGRA_PIN_DAP3_DOUT_PP2,
+ TEGRA_PIN_DAP3_SCLK_PP3,
+};
+
+static const unsigned drive_dap4_pins[] = {
+ TEGRA_PIN_DAP4_FS_PP4,
+ TEGRA_PIN_DAP4_DIN_PP5,
+ TEGRA_PIN_DAP4_DOUT_PP6,
+ TEGRA_PIN_DAP4_SCLK_PP7,
+};
+
+static const unsigned drive_dbg_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SCL_PC4,
+ TEGRA_PIN_GEN1_I2C_SDA_PC5,
+ TEGRA_PIN_PU0,
+ TEGRA_PIN_PU1,
+ TEGRA_PIN_PU2,
+ TEGRA_PIN_PU3,
+ TEGRA_PIN_PU4,
+ TEGRA_PIN_PU5,
+ TEGRA_PIN_PU6,
+ TEGRA_PIN_JTAG_RTCK_PU7,
+ TEGRA_PIN_JTAG_TCK,
+ TEGRA_PIN_JTAG_TDI,
+ TEGRA_PIN_JTAG_TDO,
+ TEGRA_PIN_JTAG_TMS,
+ TEGRA_PIN_JTAG_TRST_N,
+ TEGRA_PIN_TEST_MODE_EN,
+};
+
+static const unsigned drive_ddc_pins[] = {
+ TEGRA_PIN_DDC_SCL_PV4,
+ TEGRA_PIN_DDC_SDA_PV5,
+};
+
+static const unsigned drive_dev3_pins[] = {
+ TEGRA_PIN_CLK3_OUT_PEE0,
+ TEGRA_PIN_CLK3_REQ_PEE1,
+};
+
+static const unsigned drive_gma_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT0_PAA0,
+ TEGRA_PIN_SDMMC4_DAT1_PAA1,
+ TEGRA_PIN_SDMMC4_DAT2_PAA2,
+ TEGRA_PIN_SDMMC4_DAT3_PAA3,
+ TEGRA_PIN_SDMMC4_RST_N_PCC3,
+};
+
+static const unsigned drive_gmb_pins[] = {
+ TEGRA_PIN_SDMMC4_DAT4_PAA4,
+ TEGRA_PIN_SDMMC4_DAT5_PAA5,
+ TEGRA_PIN_SDMMC4_DAT6_PAA6,
+ TEGRA_PIN_SDMMC4_DAT7_PAA7,
+};
+
+static const unsigned drive_gmc_pins[] = {
+ TEGRA_PIN_SDMMC4_CLK_PCC4,
+};
+
+static const unsigned drive_gmd_pins[] = {
+ TEGRA_PIN_SDMMC4_CMD_PT7,
+};
+
+static const unsigned drive_gme_pins[] = {
+ TEGRA_PIN_PBB0,
+ TEGRA_PIN_CAM_I2C_SCL_PBB1,
+ TEGRA_PIN_CAM_I2C_SDA_PBB2,
+ TEGRA_PIN_PBB3,
+ TEGRA_PIN_PCC2,
+};
+
+static const unsigned drive_gmf_pins[] = {
+ TEGRA_PIN_PBB4,
+ TEGRA_PIN_PBB5,
+ TEGRA_PIN_PBB6,
+ TEGRA_PIN_PBB7,
+};
+
+static const unsigned drive_gmg_pins[] = {
+ TEGRA_PIN_CAM_MCLK_PCC0,
+};
+
+static const unsigned drive_gmh_pins[] = {
+ TEGRA_PIN_PCC1,
+};
+
+static const unsigned drive_gpv_pins[] = {
+ TEGRA_PIN_PEX_L2_RST_N_PCC6,
+ TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
+ TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
+ TEGRA_PIN_PEX_L0_RST_N_PDD1,
+ TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
+ TEGRA_PIN_PEX_WAKE_N_PDD3,
+ TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
+ TEGRA_PIN_PEX_L1_RST_N_PDD5,
+ TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
+ TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
+};
+
+static const unsigned drive_lcd1_pins[] = {
+ TEGRA_PIN_LCD_PWR1_PC1,
+ TEGRA_PIN_LCD_PWR2_PC6,
+ TEGRA_PIN_LCD_CS0_N_PN4,
+ TEGRA_PIN_LCD_SDOUT_PN5,
+ TEGRA_PIN_LCD_DC0_PN6,
+ TEGRA_PIN_LCD_SDIN_PZ2,
+ TEGRA_PIN_LCD_WR_N_PZ3,
+ TEGRA_PIN_LCD_SCK_PZ4,
+};
+
+static const unsigned drive_lcd2_pins[] = {
+ TEGRA_PIN_LCD_PWR0_PB2,
+ TEGRA_PIN_LCD_PCLK_PB3,
+ TEGRA_PIN_LCD_DC1_PD2,
+ TEGRA_PIN_LCD_D0_PE0,
+ TEGRA_PIN_LCD_D1_PE1,
+ TEGRA_PIN_LCD_D2_PE2,
+ TEGRA_PIN_LCD_D3_PE3,
+ TEGRA_PIN_LCD_D4_PE4,
+ TEGRA_PIN_LCD_D5_PE5,
+ TEGRA_PIN_LCD_D6_PE6,
+ TEGRA_PIN_LCD_D7_PE7,
+ TEGRA_PIN_LCD_D8_PF0,
+ TEGRA_PIN_LCD_D9_PF1,
+ TEGRA_PIN_LCD_D10_PF2,
+ TEGRA_PIN_LCD_D11_PF3,
+ TEGRA_PIN_LCD_D12_PF4,
+ TEGRA_PIN_LCD_D13_PF5,
+ TEGRA_PIN_LCD_D14_PF6,
+ TEGRA_PIN_LCD_D15_PF7,
+ TEGRA_PIN_LCD_DE_PJ1,
+ TEGRA_PIN_LCD_HSYNC_PJ3,
+ TEGRA_PIN_LCD_VSYNC_PJ4,
+ TEGRA_PIN_LCD_D16_PM0,
+ TEGRA_PIN_LCD_D17_PM1,
+ TEGRA_PIN_LCD_D18_PM2,
+ TEGRA_PIN_LCD_D19_PM3,
+ TEGRA_PIN_LCD_D20_PM4,
+ TEGRA_PIN_LCD_D21_PM5,
+ TEGRA_PIN_LCD_D22_PM6,
+ TEGRA_PIN_LCD_D23_PM7,
+ TEGRA_PIN_HDMI_INT_PN7,
+ TEGRA_PIN_LCD_CS1_N_PW0,
+ TEGRA_PIN_LCD_M1_PW1,
+};
+
+static const unsigned drive_owr_pins[] = {
+ TEGRA_PIN_OWR,
+};
+
+static const unsigned drive_sdio1_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT3_PY4,
+ TEGRA_PIN_SDMMC1_DAT2_PY5,
+ TEGRA_PIN_SDMMC1_DAT1_PY6,
+ TEGRA_PIN_SDMMC1_DAT0_PY7,
+ TEGRA_PIN_SDMMC1_CLK_PZ0,
+ TEGRA_PIN_SDMMC1_CMD_PZ1,
+};
+
+static const unsigned drive_sdio2_pins[] = {
+ TEGRA_PIN_SDMMC3_DAT5_PD0,
+ TEGRA_PIN_SDMMC3_DAT4_PD1,
+ TEGRA_PIN_SDMMC3_DAT6_PD3,
+ TEGRA_PIN_SDMMC3_DAT7_PD4,
+};
+
+static const unsigned drive_sdio3_pins[] = {
+ TEGRA_PIN_SDMMC3_CLK_PA6,
+ TEGRA_PIN_SDMMC3_CMD_PA7,
+ TEGRA_PIN_SDMMC3_DAT3_PB4,
+ TEGRA_PIN_SDMMC3_DAT2_PB5,
+ TEGRA_PIN_SDMMC3_DAT1_PB6,
+ TEGRA_PIN_SDMMC3_DAT0_PB7,
+};
+
+static const unsigned drive_spi_pins[] = {
+ TEGRA_PIN_SPI2_CS1_N_PW2,
+ TEGRA_PIN_SPI2_CS2_N_PW3,
+ TEGRA_PIN_SPI2_MOSI_PX0,
+ TEGRA_PIN_SPI2_MISO_PX1,
+ TEGRA_PIN_SPI2_SCK_PX2,
+ TEGRA_PIN_SPI2_CS0_N_PX3,
+ TEGRA_PIN_SPI1_MOSI_PX4,
+ TEGRA_PIN_SPI1_SCK_PX5,
+ TEGRA_PIN_SPI1_CS0_N_PX6,
+ TEGRA_PIN_SPI1_MISO_PX7,
+};
+
+static const unsigned drive_uaa_pins[] = {
+ TEGRA_PIN_ULPI_DATA0_PO1,
+ TEGRA_PIN_ULPI_DATA1_PO2,
+ TEGRA_PIN_ULPI_DATA2_PO3,
+ TEGRA_PIN_ULPI_DATA3_PO4,
+};
+
+static const unsigned drive_uab_pins[] = {
+ TEGRA_PIN_ULPI_DATA7_PO0,
+ TEGRA_PIN_ULPI_DATA4_PO5,
+ TEGRA_PIN_ULPI_DATA5_PO6,
+ TEGRA_PIN_ULPI_DATA6_PO7,
+ TEGRA_PIN_PV0,
+ TEGRA_PIN_PV1,
+ TEGRA_PIN_PV2,
+ TEGRA_PIN_PV3,
+};
+
+static const unsigned drive_uart2_pins[] = {
+ TEGRA_PIN_UART2_TXD_PC2,
+ TEGRA_PIN_UART2_RXD_PC3,
+ TEGRA_PIN_UART2_CTS_N_PJ5,
+ TEGRA_PIN_UART2_RTS_N_PJ6,
+};
+
+static const unsigned drive_uart3_pins[] = {
+ TEGRA_PIN_UART3_CTS_N_PA1,
+ TEGRA_PIN_UART3_RTS_N_PC0,
+ TEGRA_PIN_UART3_TXD_PW6,
+ TEGRA_PIN_UART3_RXD_PW7,
+};
+
+static const unsigned drive_uda_pins[] = {
+ TEGRA_PIN_ULPI_CLK_PY0,
+ TEGRA_PIN_ULPI_DIR_PY1,
+ TEGRA_PIN_ULPI_NXT_PY2,
+ TEGRA_PIN_ULPI_STP_PY3,
+};
+
+static const unsigned drive_vi1_pins[] = {
+ TEGRA_PIN_VI_D1_PD5,
+ TEGRA_PIN_VI_VSYNC_PD6,
+ TEGRA_PIN_VI_HSYNC_PD7,
+ TEGRA_PIN_VI_D2_PL0,
+ TEGRA_PIN_VI_D3_PL1,
+ TEGRA_PIN_VI_D4_PL2,
+ TEGRA_PIN_VI_D5_PL3,
+ TEGRA_PIN_VI_D6_PL4,
+ TEGRA_PIN_VI_D7_PL5,
+ TEGRA_PIN_VI_D8_PL6,
+ TEGRA_PIN_VI_D9_PL7,
+ TEGRA_PIN_VI_PCLK_PT0,
+ TEGRA_PIN_VI_D10_PT2,
+ TEGRA_PIN_VI_D11_PT3,
+ TEGRA_PIN_VI_D0_PT4,
+};
+
+enum tegra_mux {
+ TEGRA_MUX_BLINK,
+ TEGRA_MUX_CEC,
+ TEGRA_MUX_CLK_12M_OUT,
+ TEGRA_MUX_CLK_32K_IN,
+ TEGRA_MUX_CORE_PWR_REQ,
+ TEGRA_MUX_CPU_PWR_REQ,
+ TEGRA_MUX_CRT,
+ TEGRA_MUX_DAP,
+ TEGRA_MUX_DDR,
+ TEGRA_MUX_DEV3,
+ TEGRA_MUX_DISPLAYA,
+ TEGRA_MUX_DISPLAYB,
+ TEGRA_MUX_DTV,
+ TEGRA_MUX_EXTPERIPH1,
+ TEGRA_MUX_EXTPERIPH2,
+ TEGRA_MUX_EXTPERIPH3,
+ TEGRA_MUX_GMI,
+ TEGRA_MUX_GMI_ALT,
+ TEGRA_MUX_HDA,
+ TEGRA_MUX_HDCP,
+ TEGRA_MUX_HDMI,
+ TEGRA_MUX_HSI,
+ TEGRA_MUX_I2C1,
+ TEGRA_MUX_I2C2,
+ TEGRA_MUX_I2C3,
+ TEGRA_MUX_I2C4,
+ TEGRA_MUX_I2CPWR,
+ TEGRA_MUX_I2S0,
+ TEGRA_MUX_I2S1,
+ TEGRA_MUX_I2S2,
+ TEGRA_MUX_I2S3,
+ TEGRA_MUX_I2S4,
+ TEGRA_MUX_INVALID,
+ TEGRA_MUX_KBC,
+ TEGRA_MUX_MIO,
+ TEGRA_MUX_NAND,
+ TEGRA_MUX_NAND_ALT,
+ TEGRA_MUX_OWR,
+ TEGRA_MUX_PCIE,
+ TEGRA_MUX_PWM0,
+ TEGRA_MUX_PWM1,
+ TEGRA_MUX_PWM2,
+ TEGRA_MUX_PWM3,
+ TEGRA_MUX_PWR_INT_N,
+ TEGRA_MUX_RSVD1,
+ TEGRA_MUX_RSVD2,
+ TEGRA_MUX_RSVD3,
+ TEGRA_MUX_RSVD4,
+ TEGRA_MUX_RTCK,
+ TEGRA_MUX_SATA,
+ TEGRA_MUX_SDMMC1,
+ TEGRA_MUX_SDMMC2,
+ TEGRA_MUX_SDMMC3,
+ TEGRA_MUX_SDMMC4,
+ TEGRA_MUX_SPDIF,
+ TEGRA_MUX_SPI1,
+ TEGRA_MUX_SPI2,
+ TEGRA_MUX_SPI2_ALT,
+ TEGRA_MUX_SPI3,
+ TEGRA_MUX_SPI4,
+ TEGRA_MUX_SPI5,
+ TEGRA_MUX_SPI6,
+ TEGRA_MUX_SYSCLK,
+ TEGRA_MUX_TEST,
+ TEGRA_MUX_TRACE,
+ TEGRA_MUX_UARTA,
+ TEGRA_MUX_UARTB,
+ TEGRA_MUX_UARTC,
+ TEGRA_MUX_UARTD,
+ TEGRA_MUX_UARTE,
+ TEGRA_MUX_ULPI,
+ TEGRA_MUX_VGP1,
+ TEGRA_MUX_VGP2,
+ TEGRA_MUX_VGP3,
+ TEGRA_MUX_VGP4,
+ TEGRA_MUX_VGP5,
+ TEGRA_MUX_VGP6,
+ TEGRA_MUX_VI,
+ TEGRA_MUX_VI_ALT1,
+ TEGRA_MUX_VI_ALT2,
+ TEGRA_MUX_VI_ALT3,
+};
+
+#define FUNCTION(fname) \
+ { \
+ .name = #fname, \
+ }
+
+static struct tegra_function tegra30_functions[] = {
+ FUNCTION(blink),
+ FUNCTION(cec),
+ FUNCTION(clk_12m_out),
+ FUNCTION(clk_32k_in),
+ FUNCTION(core_pwr_req),
+ FUNCTION(cpu_pwr_req),
+ FUNCTION(crt),
+ FUNCTION(dap),
+ FUNCTION(ddr),
+ FUNCTION(dev3),
+ FUNCTION(displaya),
+ FUNCTION(displayb),
+ FUNCTION(dtv),
+ FUNCTION(extperiph1),
+ FUNCTION(extperiph2),
+ FUNCTION(extperiph3),
+ FUNCTION(gmi),
+ FUNCTION(gmi_alt),
+ FUNCTION(hda),
+ FUNCTION(hdcp),
+ FUNCTION(hdmi),
+ FUNCTION(hsi),
+ FUNCTION(i2c1),
+ FUNCTION(i2c2),
+ FUNCTION(i2c3),
+ FUNCTION(i2c4),
+ FUNCTION(i2cpwr),
+ FUNCTION(i2s0),
+ FUNCTION(i2s1),
+ FUNCTION(i2s2),
+ FUNCTION(i2s3),
+ FUNCTION(i2s4),
+ FUNCTION(invalid),
+ FUNCTION(kbc),
+ FUNCTION(mio),
+ FUNCTION(nand),
+ FUNCTION(nand_alt),
+ FUNCTION(owr),
+ FUNCTION(pcie),
+ FUNCTION(pwm0),
+ FUNCTION(pwm1),
+ FUNCTION(pwm2),
+ FUNCTION(pwm3),
+ FUNCTION(pwr_int_n),
+ FUNCTION(rsvd1),
+ FUNCTION(rsvd2),
+ FUNCTION(rsvd3),
+ FUNCTION(rsvd4),
+ FUNCTION(rtck),
+ FUNCTION(sata),
+ FUNCTION(sdmmc1),
+ FUNCTION(sdmmc2),
+ FUNCTION(sdmmc3),
+ FUNCTION(sdmmc4),
+ FUNCTION(spdif),
+ FUNCTION(spi1),
+ FUNCTION(spi2),
+ FUNCTION(spi2_alt),
+ FUNCTION(spi3),
+ FUNCTION(spi4),
+ FUNCTION(spi5),
+ FUNCTION(spi6),
+ FUNCTION(sysclk),
+ FUNCTION(test),
+ FUNCTION(trace),
+ FUNCTION(uarta),
+ FUNCTION(uartb),
+ FUNCTION(uartc),
+ FUNCTION(uartd),
+ FUNCTION(uarte),
+ FUNCTION(ulpi),
+ FUNCTION(vgp1),
+ FUNCTION(vgp2),
+ FUNCTION(vgp3),
+ FUNCTION(vgp4),
+ FUNCTION(vgp5),
+ FUNCTION(vgp6),
+ FUNCTION(vi),
+ FUNCTION(vi_alt1),
+ FUNCTION(vi_alt2),
+ FUNCTION(vi_alt3),
+};
+
+#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
+#define PINGROUP_REG_A 0x3000 /* bank 1 */
+
+#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
+#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
+
+#define PINGROUP_BIT_Y(b) (b)
+#define PINGROUP_BIT_N(b) (-1)
+
+#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .funcs = { \
+ TEGRA_MUX_##f0, \
+ TEGRA_MUX_##f1, \
+ TEGRA_MUX_##f2, \
+ TEGRA_MUX_##f3, \
+ }, \
+ .mux_reg = PINGROUP_REG(r), \
+ .mux_bank = 1, \
+ .mux_bit = 0, \
+ .pupd_reg = PINGROUP_REG(r), \
+ .pupd_bank = 1, \
+ .pupd_bit = 2, \
+ .tri_reg = PINGROUP_REG(r), \
+ .tri_bank = 1, \
+ .tri_bit = 4, \
+ .einput_bit = 5, \
+ .odrain_bit = PINGROUP_BIT_##od(6), \
+ .lock_bit = 7, \
+ .ioreset_bit = PINGROUP_BIT_##ior(8), \
+ .rcv_sel_bit = -1, \
+ .drv_reg = -1, \
+ }
+
+#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
+ drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
+ slwf_b, slwf_w) \
+ { \
+ .name = "drive_" #pg_name, \
+ .pins = drive_##pg_name##_pins, \
+ .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
+ .mux_reg = -1, \
+ .pupd_reg = -1, \
+ .tri_reg = -1, \
+ .einput_bit = -1, \
+ .odrain_bit = -1, \
+ .lock_bit = -1, \
+ .ioreset_bit = -1, \
+ .rcv_sel_bit = -1, \
+ .drv_reg = DRV_PINGROUP_REG(r), \
+ .drv_bank = 0, \
+ .hsm_bit = hsm_b, \
+ .schmitt_bit = schmitt_b, \
+ .lpmd_bit = lpmd_b, \
+ .drvdn_bit = drvdn_b, \
+ .drvdn_width = drvdn_w, \
+ .drvup_bit = drvup_b, \
+ .drvup_width = drvup_w, \
+ .slwr_bit = slwr_b, \
+ .slwr_width = slwr_w, \
+ .slwf_bit = slwf_b, \
+ .slwf_width = slwf_w, \
+ .drvtype_bit = -1, \
+ }
+
+static const struct tegra_pingroup tegra30_groups[] = {
+ /* pg_name, f0, f1, f2, f3, r, od, ior */
+ PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, 0x331c, N, N),
+ PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, 0x317c, N, N),
+ PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, GMI, 0x3358, N, N),
+ PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, GMI, 0x3364, N, N),
+ PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, GMI, 0x335c, N, N),
+ PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, GMI, 0x3360, N, N),
+ PINGROUP(sdmmc3_clk_pa6, UARTA, PWM2, SDMMC3, SPI3, 0x3390, N, N),
+ PINGROUP(sdmmc3_cmd_pa7, UARTA, PWM3, SDMMC3, SPI2, 0x3394, N, N),
+ PINGROUP(gmi_a17_pb0, UARTD, SPI4, GMI, DTV, 0x3234, N, N),
+ PINGROUP(gmi_a18_pb1, UARTD, SPI4, GMI, DTV, 0x3238, N, N),
+ PINGROUP(lcd_pwr0_pb2, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3090, N, N),
+ PINGROUP(lcd_pclk_pb3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3094, N, N),
+ PINGROUP(sdmmc3_dat3_pb4, RSVD1, PWM0, SDMMC3, SPI3, 0x33a4, N, N),
+ PINGROUP(sdmmc3_dat2_pb5, RSVD1, PWM1, SDMMC3, SPI3, 0x33a0, N, N),
+ PINGROUP(sdmmc3_dat1_pb6, RSVD1, RSVD2, SDMMC3, SPI3, 0x339c, N, N),
+ PINGROUP(sdmmc3_dat0_pb7, RSVD1, RSVD2, SDMMC3, SPI3, 0x3398, N, N),
+ PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, GMI, RSVD4, 0x3180, N, N),
+ PINGROUP(lcd_pwr1_pc1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3070, N, N),
+ PINGROUP(uart2_txd_pc2, UARTB, SPDIF, UARTA, SPI4, 0x3168, N, N),
+ PINGROUP(uart2_rxd_pc3, UARTB, SPDIF, UARTA, SPI4, 0x3164, N, N),
+ PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N),
+ PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N),
+ PINGROUP(lcd_pwr2_pc6, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3074, N, N),
+ PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N),
+ PINGROUP(sdmmc3_dat5_pd0, PWM0, SPI4, SDMMC3, SPI2, 0x33ac, N, N),
+ PINGROUP(sdmmc3_dat4_pd1, PWM1, SPI4, SDMMC3, SPI2, 0x33a8, N, N),
+ PINGROUP(lcd_dc1_pd2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x310c, N, N),
+ PINGROUP(sdmmc3_dat6_pd3, SPDIF, SPI4, SDMMC3, SPI2, 0x33b0, N, N),
+ PINGROUP(sdmmc3_dat7_pd4, SPDIF, SPI4, SDMMC3, SPI2, 0x33b4, N, N),
+ PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, Y),
+ PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, Y),
+ PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, Y),
+ PINGROUP(lcd_d0_pe0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a4, N, N),
+ PINGROUP(lcd_d1_pe1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a8, N, N),
+ PINGROUP(lcd_d2_pe2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30ac, N, N),
+ PINGROUP(lcd_d3_pe3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b0, N, N),
+ PINGROUP(lcd_d4_pe4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b4, N, N),
+ PINGROUP(lcd_d5_pe5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b8, N, N),
+ PINGROUP(lcd_d6_pe6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30bc, N, N),
+ PINGROUP(lcd_d7_pe7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c0, N, N),
+ PINGROUP(lcd_d8_pf0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c4, N, N),
+ PINGROUP(lcd_d9_pf1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c8, N, N),
+ PINGROUP(lcd_d10_pf2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30cc, N, N),
+ PINGROUP(lcd_d11_pf3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d0, N, N),
+ PINGROUP(lcd_d12_pf4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d4, N, N),
+ PINGROUP(lcd_d13_pf5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d8, N, N),
+ PINGROUP(lcd_d14_pf6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30dc, N, N),
+ PINGROUP(lcd_d15_pf7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e0, N, N),
+ PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, N),
+ PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, N),
+ PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, N),
+ PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, N),
+ PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, N),
+ PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, 0x3204, N, N),
+ PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, 0x3208, N, N),
+ PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, 0x320c, N, N),
+ PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, N),
+ PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, RSVD4, 0x3214, N, N),
+ PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, RSVD4, 0x3218, N, N),
+ PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, RSVD4, 0x321c, N, N),
+ PINGROUP(gmi_ad12_ph4, RSVD1, NAND, GMI, RSVD4, 0x3220, N, N),
+ PINGROUP(gmi_ad13_ph5, RSVD1, NAND, GMI, RSVD4, 0x3224, N, N),
+ PINGROUP(gmi_ad14_ph6, RSVD1, NAND, GMI, RSVD4, 0x3228, N, N),
+ PINGROUP(gmi_ad15_ph7, RSVD1, NAND, GMI, RSVD4, 0x322c, N, N),
+ PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, RSVD4, 0x3240, N, N),
+ PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, RSVD4, 0x3244, N, N),
+ PINGROUP(gmi_dqs_pi2, RSVD1, NAND, GMI, RSVD4, 0x3248, N, N),
+ PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SATA, 0x31e8, N, N),
+ PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, 0x324c, N, N),
+ PINGROUP(gmi_iordy_pi5, RSVD1, NAND, GMI, RSVD4, 0x31c4, N, N),
+ PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, GMI_ALT, 0x31ec, N, N),
+ PINGROUP(gmi_wait_pi7, RSVD1, NAND, GMI, RSVD4, 0x31c8, N, N),
+ PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, DTV, 0x31d4, N, N),
+ PINGROUP(lcd_de_pj1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3098, N, N),
+ PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, DTV, 0x31d8, N, N),
+ PINGROUP(lcd_hsync_pj3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x309c, N, N),
+ PINGROUP(lcd_vsync_pj4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a0, N, N),
+ PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, 0x3170, N, N),
+ PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, 0x316c, N, N),
+ PINGROUP(gmi_a16_pj7, UARTD, SPI4, GMI, GMI_ALT, 0x3230, N, N),
+ PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, RSVD4, 0x31cc, N, N),
+ PINGROUP(gmi_clk_pk1, RSVD1, NAND, GMI, RSVD4, 0x31d0, N, N),
+ PINGROUP(gmi_cs4_n_pk2, RSVD1, NAND, GMI, RSVD4, 0x31e4, N, N),
+ PINGROUP(gmi_cs2_n_pk3, RSVD1, NAND, GMI, RSVD4, 0x31dc, N, N),
+ PINGROUP(gmi_cs3_n_pk4, RSVD1, NAND, GMI, GMI_ALT, 0x31e0, N, N),
+ PINGROUP(spdif_out_pk5, SPDIF, RSVD2, I2C1, SDMMC2, 0x3354, N, N),
+ PINGROUP(spdif_in_pk6, SPDIF, HDA, I2C1, SDMMC2, 0x3350, N, N),
+ PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, RSVD4, 0x323c, N, N),
+ PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, Y),
+ PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, Y),
+ PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, Y),
+ PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, Y),
+ PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, Y),
+ PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, Y),
+ PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, 0x3144, N, Y),
+ PINGROUP(vi_d9_pl7, DDR, SDMMC2, VI, RSVD4, 0x3148, N, Y),
+ PINGROUP(lcd_d16_pm0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e4, N, N),
+ PINGROUP(lcd_d17_pm1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e8, N, N),
+ PINGROUP(lcd_d18_pm2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30ec, N, N),
+ PINGROUP(lcd_d19_pm3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f0, N, N),
+ PINGROUP(lcd_d20_pm4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f4, N, N),
+ PINGROUP(lcd_d21_pm5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f8, N, N),
+ PINGROUP(lcd_d22_pm6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30fc, N, N),
+ PINGROUP(lcd_d23_pm7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3100, N, N),
+ PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, SDMMC2, 0x3338, N, N),
+ PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, SDMMC2, 0x333c, N, N),
+ PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SDMMC2, 0x3340, N, N),
+ PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, SDMMC2, 0x3344, N, N),
+ PINGROUP(lcd_cs0_n_pn4, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3084, N, N),
+ PINGROUP(lcd_sdout_pn5, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x307c, N, N),
+ PINGROUP(lcd_dc0_pn6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3088, N, N),
+ PINGROUP(hdmi_int_pn7, HDMI, RSVD2, RSVD3, RSVD4, 0x3110, N, N),
+ PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N),
+ PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N),
+ PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N),
+ PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N),
+ PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N),
+ PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N),
+ PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N),
+ PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N),
+ PINGROUP(dap3_fs_pp0, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3030, N, N),
+ PINGROUP(dap3_din_pp1, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3034, N, N),
+ PINGROUP(dap3_dout_pp2, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3038, N, N),
+ PINGROUP(dap3_sclk_pp3, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x303c, N, N),
+ PINGROUP(dap4_fs_pp4, I2S3, RSVD2, GMI, RSVD4, 0x31a8, N, N),
+ PINGROUP(dap4_din_pp5, I2S3, RSVD2, GMI, RSVD4, 0x31ac, N, N),
+ PINGROUP(dap4_dout_pp6, I2S3, RSVD2, GMI, RSVD4, 0x31b0, N, N),
+ PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, GMI, RSVD4, 0x31b4, N, N),
+ PINGROUP(kb_col0_pq0, KBC, NAND, TRACE, TEST, 0x32fc, N, N),
+ PINGROUP(kb_col1_pq1, KBC, NAND, TRACE, TEST, 0x3300, N, N),
+ PINGROUP(kb_col2_pq2, KBC, NAND, TRACE, RSVD4, 0x3304, N, N),
+ PINGROUP(kb_col3_pq3, KBC, NAND, TRACE, RSVD4, 0x3308, N, N),
+ PINGROUP(kb_col4_pq4, KBC, NAND, TRACE, RSVD4, 0x330c, N, N),
+ PINGROUP(kb_col5_pq5, KBC, NAND, TRACE, RSVD4, 0x3310, N, N),
+ PINGROUP(kb_col6_pq6, KBC, NAND, TRACE, MIO, 0x3314, N, N),
+ PINGROUP(kb_col7_pq7, KBC, NAND, TRACE, MIO, 0x3318, N, N),
+ PINGROUP(kb_row0_pr0, KBC, NAND, RSVD3, RSVD4, 0x32bc, N, N),
+ PINGROUP(kb_row1_pr1, KBC, NAND, RSVD3, RSVD4, 0x32c0, N, N),
+ PINGROUP(kb_row2_pr2, KBC, NAND, RSVD3, RSVD4, 0x32c4, N, N),
+ PINGROUP(kb_row3_pr3, KBC, NAND, RSVD3, INVALID, 0x32c8, N, N),
+ PINGROUP(kb_row4_pr4, KBC, NAND, TRACE, RSVD4, 0x32cc, N, N),
+ PINGROUP(kb_row5_pr5, KBC, NAND, TRACE, OWR, 0x32d0, N, N),
+ PINGROUP(kb_row6_pr6, KBC, NAND, SDMMC2, MIO, 0x32d4, N, N),
+ PINGROUP(kb_row7_pr7, KBC, NAND, SDMMC2, MIO, 0x32d8, N, N),
+ PINGROUP(kb_row8_ps0, KBC, NAND, SDMMC2, MIO, 0x32dc, N, N),
+ PINGROUP(kb_row9_ps1, KBC, NAND, SDMMC2, MIO, 0x32e0, N, N),
+ PINGROUP(kb_row10_ps2, KBC, NAND, SDMMC2, MIO, 0x32e4, N, N),
+ PINGROUP(kb_row11_ps3, KBC, NAND, SDMMC2, MIO, 0x32e8, N, N),
+ PINGROUP(kb_row12_ps4, KBC, NAND, SDMMC2, MIO, 0x32ec, N, N),
+ PINGROUP(kb_row13_ps5, KBC, NAND, SDMMC2, MIO, 0x32f0, N, N),
+ PINGROUP(kb_row14_ps6, KBC, NAND, SDMMC2, MIO, 0x32f4, N, N),
+ PINGROUP(kb_row15_ps7, KBC, NAND, SDMMC2, MIO, 0x32f8, N, N),
+ PINGROUP(vi_pclk_pt0, RSVD1, SDMMC2, VI, RSVD4, 0x3154, N, Y),
+ PINGROUP(vi_mclk_pt1, VI, VI_ALT1, VI_ALT2, VI_ALT3, 0x3158, N, Y),
+ PINGROUP(vi_d10_pt2, DDR, RSVD2, VI, RSVD4, 0x314c, N, Y),
+ PINGROUP(vi_d11_pt3, DDR, RSVD2, VI, RSVD4, 0x3150, N, Y),
+ PINGROUP(vi_d0_pt4, DDR, RSVD2, VI, RSVD4, 0x3124, N, Y),
+ PINGROUP(gen2_i2c_scl_pt5, I2C2, HDCP, GMI, RSVD4, 0x3250, Y, N),
+ PINGROUP(gen2_i2c_sda_pt6, I2C2, HDCP, GMI, RSVD4, 0x3254, Y, N),
+ PINGROUP(sdmmc4_cmd_pt7, I2C3, NAND, GMI, SDMMC4, 0x325c, N, Y),
+ PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, 0x3184, N, N),
+ PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, 0x3188, N, N),
+ PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, 0x318c, N, N),
+ PINGROUP(pu3, PWM0, UARTA, GMI, RSVD4, 0x3190, N, N),
+ PINGROUP(pu4, PWM1, UARTA, GMI, RSVD4, 0x3194, N, N),
+ PINGROUP(pu5, PWM2, UARTA, GMI, RSVD4, 0x3198, N, N),
+ PINGROUP(pu6, PWM3, UARTA, GMI, RSVD4, 0x319c, N, N),
+ PINGROUP(jtag_rtck_pu7, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N),
+ PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, 0x3040, N, N),
+ PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N),
+ PINGROUP(pv2, OWR, RSVD2, RSVD3, RSVD4, 0x3060, N, N),
+ PINGROUP(pv3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4, 0x3064, N, N),
+ PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N),
+ PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N),
+ PINGROUP(crt_hsync_pv6, CRT, RSVD2, RSVD3, RSVD4, 0x311c, N, N),
+ PINGROUP(crt_vsync_pv7, CRT, RSVD2, RSVD3, RSVD4, 0x3120, N, N),
+ PINGROUP(lcd_cs1_n_pw0, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3104, N, N),
+ PINGROUP(lcd_m1_pw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3108, N, N),
+ PINGROUP(spi2_cs1_n_pw2, SPI3, SPI2, SPI2_ALT, I2C1, 0x3388, N, N),
+ PINGROUP(spi2_cs2_n_pw3, SPI3, SPI2, SPI2_ALT, I2C1, 0x338c, N, N),
+ PINGROUP(clk1_out_pw4, EXTPERIPH1, RSVD2, RSVD3, RSVD4, 0x334c, N, N),
+ PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N),
+ PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, RSVD4, 0x3174, N, N),
+ PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, RSVD4, 0x3178, N, N),
+ PINGROUP(spi2_mosi_px0, SPI6, SPI2, SPI3, GMI, 0x3368, N, N),
+ PINGROUP(spi2_miso_px1, SPI6, SPI2, SPI3, GMI, 0x336c, N, N),
+ PINGROUP(spi2_sck_px2, SPI6, SPI2, SPI3, GMI, 0x3374, N, N),
+ PINGROUP(spi2_cs0_n_px3, SPI6, SPI2, SPI3, GMI, 0x3370, N, N),
+ PINGROUP(spi1_mosi_px4, SPI2, SPI1, SPI2_ALT, GMI, 0x3378, N, N),
+ PINGROUP(spi1_sck_px5, SPI2, SPI1, SPI2_ALT, GMI, 0x337c, N, N),
+ PINGROUP(spi1_cs0_n_px6, SPI2, SPI1, SPI2_ALT, GMI, 0x3380, N, N),
+ PINGROUP(spi1_miso_px7, SPI3, SPI1, SPI2_ALT, RSVD4, 0x3384, N, N),
+ PINGROUP(ulpi_clk_py0, SPI1, RSVD2, UARTD, ULPI, 0x3020, N, N),
+ PINGROUP(ulpi_dir_py1, SPI1, RSVD2, UARTD, ULPI, 0x3024, N, N),
+ PINGROUP(ulpi_nxt_py2, SPI1, RSVD2, UARTD, ULPI, 0x3028, N, N),
+ PINGROUP(ulpi_stp_py3, SPI1, RSVD2, UARTD, ULPI, 0x302c, N, N),
+ PINGROUP(sdmmc1_dat3_py4, SDMMC1, RSVD2, UARTE, UARTA, 0x3050, N, N),
+ PINGROUP(sdmmc1_dat2_py5, SDMMC1, RSVD2, UARTE, UARTA, 0x3054, N, N),
+ PINGROUP(sdmmc1_dat1_py6, SDMMC1, RSVD2, UARTE, UARTA, 0x3058, N, N),
+ PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, UARTE, UARTA, 0x305c, N, N),
+ PINGROUP(sdmmc1_clk_pz0, SDMMC1, RSVD2, RSVD3, UARTA, 0x3048, N, N),
+ PINGROUP(sdmmc1_cmd_pz1, SDMMC1, RSVD2, RSVD3, UARTA, 0x304c, N, N),
+ PINGROUP(lcd_sdin_pz2, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3078, N, N),
+ PINGROUP(lcd_wr_n_pz3, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3080, N, N),
+ PINGROUP(lcd_sck_pz4, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x308c, N, N),
+ PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N),
+ PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N),
+ PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N),
+ PINGROUP(sdmmc4_dat0_paa0, UARTE, SPI3, GMI, SDMMC4, 0x3260, N, Y),
+ PINGROUP(sdmmc4_dat1_paa1, UARTE, SPI3, GMI, SDMMC4, 0x3264, N, Y),
+ PINGROUP(sdmmc4_dat2_paa2, UARTE, SPI3, GMI, SDMMC4, 0x3268, N, Y),
+ PINGROUP(sdmmc4_dat3_paa3, UARTE, SPI3, GMI, SDMMC4, 0x326c, N, Y),
+ PINGROUP(sdmmc4_dat4_paa4, I2C3, I2S4, GMI, SDMMC4, 0x3270, N, Y),
+ PINGROUP(sdmmc4_dat5_paa5, VGP3, I2S4, GMI, SDMMC4, 0x3274, N, Y),
+ PINGROUP(sdmmc4_dat6_paa6, VGP4, I2S4, GMI, SDMMC4, 0x3278, N, Y),
+ PINGROUP(sdmmc4_dat7_paa7, VGP5, I2S4, GMI, SDMMC4, 0x327c, N, Y),
+ PINGROUP(pbb0, I2S4, RSVD2, RSVD3, SDMMC4, 0x328c, N, N),
+ PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC4, 0x3290, Y, N),
+ PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC4, 0x3294, Y, N),
+ PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC4, 0x3298, N, N),
+ PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC4, 0x329c, N, N),
+ PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, SDMMC4, 0x32a0, N, N),
+ PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, SDMMC4, 0x32a4, N, N),
+ PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC4, 0x32a8, N, N),
+ PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC4, 0x3284, N, N),
+ PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC4, 0x3288, N, N),
+ PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, 0x32ac, N, N),
+ PINGROUP(sdmmc4_rst_n_pcc3, VGP6, RSVD2, RSVD3, SDMMC4, 0x3280, N, Y),
+ PINGROUP(sdmmc4_clk_pcc4, INVALID, NAND, GMI, SDMMC4, 0x3258, N, Y),
+ PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N),
+ PINGROUP(pex_l2_rst_n_pcc6, PCIE, HDA, RSVD3, RSVD4, 0x33d8, N, N),
+ PINGROUP(pex_l2_clkreq_n_pcc7, PCIE, HDA, RSVD3, RSVD4, 0x33dc, N, N),
+ PINGROUP(pex_l0_prsnt_n_pdd0, PCIE, HDA, RSVD3, RSVD4, 0x33b8, N, N),
+ PINGROUP(pex_l0_rst_n_pdd1, PCIE, HDA, RSVD3, RSVD4, 0x33bc, N, N),
+ PINGROUP(pex_l0_clkreq_n_pdd2, PCIE, HDA, RSVD3, RSVD4, 0x33c0, N, N),
+ PINGROUP(pex_wake_n_pdd3, PCIE, HDA, RSVD3, RSVD4, 0x33c4, N, N),
+ PINGROUP(pex_l1_prsnt_n_pdd4, PCIE, HDA, RSVD3, RSVD4, 0x33c8, N, N),
+ PINGROUP(pex_l1_rst_n_pdd5, PCIE, HDA, RSVD3, RSVD4, 0x33cc, N, N),
+ PINGROUP(pex_l1_clkreq_n_pdd6, PCIE, HDA, RSVD3, RSVD4, 0x33d0, N, N),
+ PINGROUP(pex_l2_prsnt_n_pdd7, PCIE, HDA, RSVD3, RSVD4, 0x33d4, N, N),
+ PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N),
+ PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N),
+ PINGROUP(clk1_req_pee2, DAP, HDA, RSVD3, RSVD4, 0x3348, N, N),
+ PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, 0x33e0, Y, N),
+ PINGROUP(clk_32k_in, CLK_32K_IN, RSVD2, RSVD3, RSVD4, 0x3330, N, N),
+ PINGROUP(core_pwr_req, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4, 0x3324, N, N),
+ PINGROUP(cpu_pwr_req, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4, 0x3328, N, N),
+ PINGROUP(owr, OWR, CEC, RSVD3, RSVD4, 0x3334, N, N),
+ PINGROUP(pwr_int_n, PWR_INT_N, RSVD2, RSVD3, RSVD4, 0x332c, N, N),
+ /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
+ DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(at1, 0x870, 2, 3, 4, 14, 5, 19, 5, 24, 2, 28, 2),
+ DRV_PINGROUP(at2, 0x874, 2, 3, 4, 14, 5, 19, 5, 24, 2, 28, 2),
+ DRV_PINGROUP(at3, 0x878, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(crt, 0x8f8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(csus, 0x88c, -1, -1, -1, 12, 5, 19, 5, 24, 4, 28, 4),
+ DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(gma, 0x900, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
+ DRV_PINGROUP(gmb, 0x904, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
+ DRV_PINGROUP(gmc, 0x908, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
+ DRV_PINGROUP(gmd, 0x90c, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
+ DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(lcd1, 0x8a4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(lcd2, 0x8a8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2),
+ DRV_PINGROUP(sdio2, 0x8ac, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2),
+ DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2),
+ DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
+ DRV_PINGROUP(vi1, 0x8c8, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
+};
+
+static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
+ .ngpios = NUM_GPIOS,
+ .pins = tegra30_pins,
+ .npins = ARRAY_SIZE(tegra30_pins),
+ .functions = tegra30_functions,
+ .nfunctions = ARRAY_SIZE(tegra30_functions),
+ .groups = tegra30_groups,
+ .ngroups = ARRAY_SIZE(tegra30_groups),
+ .hsm_in_mux = false,
+ .schmitt_in_mux = false,
+ .drvtype_in_mux = false,
+};
+
+static int tegra30_pinctrl_probe(struct platform_device *pdev)
+{
+ return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
+}
+
+static const struct of_device_id tegra30_pinctrl_of_match[] = {
+ { .compatible = "nvidia,tegra30-pinmux", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
+
+static struct platform_driver tegra30_pinctrl_driver = {
+ .driver = {
+ .name = "tegra30-pinctrl",
+ .of_match_table = tegra30_pinctrl_of_match,
+ },
+ .probe = tegra30_pinctrl_probe,
+ .remove = tegra_pinctrl_remove,
+};
+module_platform_driver(tegra30_pinctrl_driver);
+
+MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver");
+MODULE_LICENSE("GPL v2");
menuconfig PINCTRL_UNIPHIER
bool "UniPhier SoC pinctrl drivers"
- depends on ARCH_UNIPHIER
+ depends on ARCH_UNIPHIER || COMPILE_TEST
depends on OF && MFD_SYSCON
default y
select PINMUX
if PINCTRL_UNIPHIER
-config PINCTRL_UNIPHIER_PH1_LD4
+config PINCTRL_UNIPHIER_LD4
tristate "UniPhier PH1-LD4 SoC pinctrl driver"
default y
-config PINCTRL_UNIPHIER_PH1_PRO4
+config PINCTRL_UNIPHIER_PRO4
tristate "UniPhier PH1-Pro4 SoC pinctrl driver"
default y
-config PINCTRL_UNIPHIER_PH1_SLD8
+config PINCTRL_UNIPHIER_SLD8
tristate "UniPhier PH1-sLD8 SoC pinctrl driver"
default y
-config PINCTRL_UNIPHIER_PH1_PRO5
+config PINCTRL_UNIPHIER_PRO5
tristate "UniPhier PH1-Pro5 SoC pinctrl driver"
default y
-config PINCTRL_UNIPHIER_PROXSTREAM2
+config PINCTRL_UNIPHIER_PXS2
tristate "UniPhier ProXstream2 SoC pinctrl driver"
default y
-config PINCTRL_UNIPHIER_PH1_LD6B
+config PINCTRL_UNIPHIER_LD6B
tristate "UniPhier PH1-LD6b SoC pinctrl driver"
default y
-obj-y += pinctrl-uniphier-core.o
+obj-y += pinctrl-uniphier-core.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD6B) += pinctrl-ph1-ld6b.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD4) += pinctrl-uniphier-ld4.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4) += pinctrl-uniphier-pro4.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8) += pinctrl-uniphier-sld8.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PRO5) += pinctrl-uniphier-pro5.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PXS2) += pinctrl-uniphier-pxs2.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B) += pinctrl-uniphier-ld6b.o
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-
-#include "pinctrl-uniphier.h"
-
-#define DRIVER_NAME "ph1-ld4-pinctrl"
-
-static const struct pinctrl_pin_desc ph1_ld4_pins[] = {
- UNIPHIER_PINCTRL_PIN(0, "EA1", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_4_8,
- 8, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(1, "EA2", UNIPHIER_PIN_IECTRL_NONE,
- 9, UNIPHIER_PIN_DRV_4_8,
- 9, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(2, "EA3", UNIPHIER_PIN_IECTRL_NONE,
- 10, UNIPHIER_PIN_DRV_4_8,
- 10, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(3, "EA4", UNIPHIER_PIN_IECTRL_NONE,
- 11, UNIPHIER_PIN_DRV_4_8,
- 11, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(4, "EA5", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_4_8,
- 12, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(5, "EA6", UNIPHIER_PIN_IECTRL_NONE,
- 13, UNIPHIER_PIN_DRV_4_8,
- 13, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(6, "EA7", UNIPHIER_PIN_IECTRL_NONE,
- 14, UNIPHIER_PIN_DRV_4_8,
- 14, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(7, "EA8", 0,
- 15, UNIPHIER_PIN_DRV_4_8,
- 15, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(8, "EA9", 0,
- 16, UNIPHIER_PIN_DRV_4_8,
- 16, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(9, "EA10", 0,
- 17, UNIPHIER_PIN_DRV_4_8,
- 17, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(10, "EA11", 0,
- 18, UNIPHIER_PIN_DRV_4_8,
- 18, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(11, "EA12", 0,
- 19, UNIPHIER_PIN_DRV_4_8,
- 19, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(12, "EA13", 0,
- 20, UNIPHIER_PIN_DRV_4_8,
- 20, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(13, "EA14", 0,
- 21, UNIPHIER_PIN_DRV_4_8,
- 21, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(14, "EA15", 0,
- 22, UNIPHIER_PIN_DRV_4_8,
- 22, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(15, "ECLK", UNIPHIER_PIN_IECTRL_NONE,
- 23, UNIPHIER_PIN_DRV_4_8,
- 23, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(16, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
- 24, UNIPHIER_PIN_DRV_4_8,
- 24, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(17, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
- 25, UNIPHIER_PIN_DRV_4_8,
- 25, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(18, "ES0", UNIPHIER_PIN_IECTRL_NONE,
- 27, UNIPHIER_PIN_DRV_4_8,
- 27, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(19, "ES1", UNIPHIER_PIN_IECTRL_NONE,
- 28, UNIPHIER_PIN_DRV_4_8,
- 28, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(20, "ES2", UNIPHIER_PIN_IECTRL_NONE,
- 29, UNIPHIER_PIN_DRV_4_8,
- 29, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(21, "XERST", UNIPHIER_PIN_IECTRL_NONE,
- 38, UNIPHIER_PIN_DRV_4_8,
- 38, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(22, "MMCCLK", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_8_12_16_20,
- 146, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(23, "MMCCMD", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_8_12_16_20,
- 147, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(24, "MMCDAT0", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_8_12_16_20,
- 148, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(25, "MMCDAT1", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_8_12_16_20,
- 149, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(26, "MMCDAT2", UNIPHIER_PIN_IECTRL_NONE,
- 16, UNIPHIER_PIN_DRV_8_12_16_20,
- 150, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(27, "MMCDAT3", UNIPHIER_PIN_IECTRL_NONE,
- 20, UNIPHIER_PIN_DRV_8_12_16_20,
- 151, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(28, "MMCDAT4", UNIPHIER_PIN_IECTRL_NONE,
- 24, UNIPHIER_PIN_DRV_8_12_16_20,
- 152, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(29, "MMCDAT5", UNIPHIER_PIN_IECTRL_NONE,
- 28, UNIPHIER_PIN_DRV_8_12_16_20,
- 153, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(30, "MMCDAT6", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_8_12_16_20,
- 154, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(31, "MMCDAT7", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_8_12_16_20,
- 155, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(32, "RMII_RXD0", 6,
- 39, UNIPHIER_PIN_DRV_4_8,
- 39, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(33, "RMII_RXD1", 6,
- 40, UNIPHIER_PIN_DRV_4_8,
- 40, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(34, "RMII_CRS_DV", 6,
- 41, UNIPHIER_PIN_DRV_4_8,
- 41, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(35, "RMII_RXER", 6,
- 42, UNIPHIER_PIN_DRV_4_8,
- 42, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(36, "RMII_REFCLK", 6,
- 43, UNIPHIER_PIN_DRV_4_8,
- 43, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(37, "RMII_TXD0", 6,
- 44, UNIPHIER_PIN_DRV_4_8,
- 44, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(38, "RMII_TXD1", 6,
- 45, UNIPHIER_PIN_DRV_4_8,
- 45, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(39, "RMII_TXEN", 6,
- 46, UNIPHIER_PIN_DRV_4_8,
- 46, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(40, "MDC", 6,
- 47, UNIPHIER_PIN_DRV_4_8,
- 47, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(41, "MDIO", 6,
- 48, UNIPHIER_PIN_DRV_4_8,
- 48, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(42, "MDIO_INTL", 6,
- 49, UNIPHIER_PIN_DRV_4_8,
- 49, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(43, "PHYRSTL", 6,
- 50, UNIPHIER_PIN_DRV_4_8,
- 50, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(44, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
- 40, UNIPHIER_PIN_DRV_8_12_16_20,
- 156, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(45, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
- 44, UNIPHIER_PIN_DRV_8_12_16_20,
- 157, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(46, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
- 48, UNIPHIER_PIN_DRV_8_12_16_20,
- 158, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(47, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
- 52, UNIPHIER_PIN_DRV_8_12_16_20,
- 159, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(48, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
- 56, UNIPHIER_PIN_DRV_8_12_16_20,
- 160, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(49, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
- 60, UNIPHIER_PIN_DRV_8_12_16_20,
- 161, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(50, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
- 51, UNIPHIER_PIN_DRV_4_8,
- 51, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(51, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
- 52, UNIPHIER_PIN_DRV_4_8,
- 52, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(52, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
- 53, UNIPHIER_PIN_DRV_4_8,
- 53, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(53, "USB0VBUS", 0,
- 54, UNIPHIER_PIN_DRV_4_8,
- 54, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(54, "USB0OD", 0,
- 55, UNIPHIER_PIN_DRV_4_8,
- 55, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(55, "USB1VBUS", 0,
- 56, UNIPHIER_PIN_DRV_4_8,
- 56, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(56, "USB1OD", 0,
- 57, UNIPHIER_PIN_DRV_4_8,
- 57, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(57, "PCRESET", 0,
- 58, UNIPHIER_PIN_DRV_4_8,
- 58, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(58, "PCREG", 0,
- 59, UNIPHIER_PIN_DRV_4_8,
- 59, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(59, "PCCE2", 0,
- 60, UNIPHIER_PIN_DRV_4_8,
- 60, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(60, "PCVS1", 0,
- 61, UNIPHIER_PIN_DRV_4_8,
- 61, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(61, "PCCD2", 0,
- 62, UNIPHIER_PIN_DRV_4_8,
- 62, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(62, "PCCD1", 0,
- 63, UNIPHIER_PIN_DRV_4_8,
- 63, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(63, "PCREADY", 0,
- 64, UNIPHIER_PIN_DRV_4_8,
- 64, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(64, "PCDOE", 0,
- 65, UNIPHIER_PIN_DRV_4_8,
- 65, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(65, "PCCE1", 0,
- 66, UNIPHIER_PIN_DRV_4_8,
- 66, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(66, "PCWE", 0,
- 67, UNIPHIER_PIN_DRV_4_8,
- 67, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(67, "PCOE", 0,
- 68, UNIPHIER_PIN_DRV_4_8,
- 68, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(68, "PCWAIT", 0,
- 69, UNIPHIER_PIN_DRV_4_8,
- 69, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(69, "PCIOWR", 0,
- 70, UNIPHIER_PIN_DRV_4_8,
- 70, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(70, "PCIORD", 0,
- 71, UNIPHIER_PIN_DRV_4_8,
- 71, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(71, "HS0DIN0", 0,
- 72, UNIPHIER_PIN_DRV_4_8,
- 72, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(72, "HS0DIN1", 0,
- 73, UNIPHIER_PIN_DRV_4_8,
- 73, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(73, "HS0DIN2", 0,
- 74, UNIPHIER_PIN_DRV_4_8,
- 74, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(74, "HS0DIN3", 0,
- 75, UNIPHIER_PIN_DRV_4_8,
- 75, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(75, "HS0DIN4", 0,
- 76, UNIPHIER_PIN_DRV_4_8,
- 76, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(76, "HS0DIN5", 0,
- 77, UNIPHIER_PIN_DRV_4_8,
- 77, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(77, "HS0DIN6", 0,
- 78, UNIPHIER_PIN_DRV_4_8,
- 78, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(78, "HS0DIN7", 0,
- 79, UNIPHIER_PIN_DRV_4_8,
- 79, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(79, "HS0BCLKIN", 0,
- 80, UNIPHIER_PIN_DRV_4_8,
- 80, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(80, "HS0VALIN", 0,
- 81, UNIPHIER_PIN_DRV_4_8,
- 81, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(81, "HS0SYNCIN", 0,
- 82, UNIPHIER_PIN_DRV_4_8,
- 82, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(82, "HSDOUT0", 0,
- 83, UNIPHIER_PIN_DRV_4_8,
- 83, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(83, "HSDOUT1", 0,
- 84, UNIPHIER_PIN_DRV_4_8,
- 84, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(84, "HSDOUT2", 0,
- 85, UNIPHIER_PIN_DRV_4_8,
- 85, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(85, "HSDOUT3", 0,
- 86, UNIPHIER_PIN_DRV_4_8,
- 86, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(86, "HSDOUT4", 0,
- 87, UNIPHIER_PIN_DRV_4_8,
- 87, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(87, "HSDOUT5", 0,
- 88, UNIPHIER_PIN_DRV_4_8,
- 88, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(88, "HSDOUT6", 0,
- 89, UNIPHIER_PIN_DRV_4_8,
- 89, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(89, "HSDOUT7", 0,
- 90, UNIPHIER_PIN_DRV_4_8,
- 90, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(90, "HSBCLKOUT", 0,
- 91, UNIPHIER_PIN_DRV_4_8,
- 91, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(91, "HSVALOUT", 0,
- 92, UNIPHIER_PIN_DRV_4_8,
- 92, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(92, "HSSYNCOUT", 0,
- 93, UNIPHIER_PIN_DRV_4_8,
- 93, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(93, "AGCI", 3,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 162, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(94, "AGCR", 4,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 163, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(95, "AGCBS", 5,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 164, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(96, "IECOUT", 0,
- 94, UNIPHIER_PIN_DRV_4_8,
- 94, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(97, "ASMCK", 0,
- 95, UNIPHIER_PIN_DRV_4_8,
- 95, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(98, "ABCKO", UNIPHIER_PIN_IECTRL_NONE,
- 96, UNIPHIER_PIN_DRV_4_8,
- 96, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(99, "ALRCKO", UNIPHIER_PIN_IECTRL_NONE,
- 97, UNIPHIER_PIN_DRV_4_8,
- 97, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(100, "ASDOUT0", UNIPHIER_PIN_IECTRL_NONE,
- 98, UNIPHIER_PIN_DRV_4_8,
- 98, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(101, "ARCOUT", 0,
- 99, UNIPHIER_PIN_DRV_4_8,
- 99, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(102, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(103, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(104, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(105, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(106, "DMDSDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(107, "DMDSCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(108, "DMDSDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(109, "DMDSCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(110, "SBO0", UNIPHIER_PIN_IECTRL_NONE,
- 100, UNIPHIER_PIN_DRV_4_8,
- 100, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(111, "SBI0", UNIPHIER_PIN_IECTRL_NONE,
- 101, UNIPHIER_PIN_DRV_4_8,
- 101, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(112, "HIN", 1,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(113, "VIN", 2,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(114, "TCON0", UNIPHIER_PIN_IECTRL_NONE,
- 102, UNIPHIER_PIN_DRV_4_8,
- 102, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(115, "TCON1", UNIPHIER_PIN_IECTRL_NONE,
- 103, UNIPHIER_PIN_DRV_4_8,
- 103, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(116, "TCON2", UNIPHIER_PIN_IECTRL_NONE,
- 104, UNIPHIER_PIN_DRV_4_8,
- 104, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(117, "TCON3", UNIPHIER_PIN_IECTRL_NONE,
- 105, UNIPHIER_PIN_DRV_4_8,
- 105, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(118, "TCON4", UNIPHIER_PIN_IECTRL_NONE,
- 106, UNIPHIER_PIN_DRV_4_8,
- 106, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(119, "TCON5", UNIPHIER_PIN_IECTRL_NONE,
- 107, UNIPHIER_PIN_DRV_4_8,
- 107, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(120, "TCON6", 0,
- 108, UNIPHIER_PIN_DRV_4_8,
- 108, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(121, "TCON7", 0,
- 109, UNIPHIER_PIN_DRV_4_8,
- 109, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(122, "PWMA", 0,
- 110, UNIPHIER_PIN_DRV_4_8,
- 110, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(123, "XIRQ1", 0,
- 111, UNIPHIER_PIN_DRV_4_8,
- 111, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(124, "XIRQ2", 0,
- 112, UNIPHIER_PIN_DRV_4_8,
- 112, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(125, "XIRQ3", 0,
- 113, UNIPHIER_PIN_DRV_4_8,
- 113, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(126, "XIRQ4", 0,
- 114, UNIPHIER_PIN_DRV_4_8,
- 114, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(127, "XIRQ5", 0,
- 115, UNIPHIER_PIN_DRV_4_8,
- 115, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(128, "XIRQ6", 0,
- 116, UNIPHIER_PIN_DRV_4_8,
- 116, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(129, "XIRQ7", 0,
- 117, UNIPHIER_PIN_DRV_4_8,
- 117, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(130, "XIRQ8", 0,
- 118, UNIPHIER_PIN_DRV_4_8,
- 118, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(131, "XIRQ9", 0,
- 119, UNIPHIER_PIN_DRV_4_8,
- 119, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(132, "XIRQ10", 0,
- 120, UNIPHIER_PIN_DRV_4_8,
- 120, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(133, "XIRQ11", 0,
- 121, UNIPHIER_PIN_DRV_4_8,
- 121, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(134, "XIRQ14", 0,
- 122, UNIPHIER_PIN_DRV_4_8,
- 122, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(135, "PORT00", 0,
- 123, UNIPHIER_PIN_DRV_4_8,
- 123, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(136, "PORT01", 0,
- 124, UNIPHIER_PIN_DRV_4_8,
- 124, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(137, "PORT02", 0,
- 125, UNIPHIER_PIN_DRV_4_8,
- 125, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(138, "PORT03", 0,
- 126, UNIPHIER_PIN_DRV_4_8,
- 126, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(139, "PORT04", 0,
- 127, UNIPHIER_PIN_DRV_4_8,
- 127, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(140, "PORT05", 0,
- 128, UNIPHIER_PIN_DRV_4_8,
- 128, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(141, "PORT06", 0,
- 129, UNIPHIER_PIN_DRV_4_8,
- 129, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(142, "PORT07", 0,
- 130, UNIPHIER_PIN_DRV_4_8,
- 130, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(143, "PORT10", 0,
- 131, UNIPHIER_PIN_DRV_4_8,
- 131, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(144, "PORT11", 0,
- 132, UNIPHIER_PIN_DRV_4_8,
- 132, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(145, "PORT12", 0,
- 133, UNIPHIER_PIN_DRV_4_8,
- 133, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(146, "PORT13", 0,
- 134, UNIPHIER_PIN_DRV_4_8,
- 134, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(147, "PORT14", 0,
- 135, UNIPHIER_PIN_DRV_4_8,
- 135, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(148, "PORT15", 0,
- 136, UNIPHIER_PIN_DRV_4_8,
- 136, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(149, "PORT16", 0,
- 137, UNIPHIER_PIN_DRV_4_8,
- 137, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(150, "PORT17", UNIPHIER_PIN_IECTRL_NONE,
- 138, UNIPHIER_PIN_DRV_4_8,
- 138, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(151, "PORT20", 0,
- 139, UNIPHIER_PIN_DRV_4_8,
- 139, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(152, "PORT21", 0,
- 140, UNIPHIER_PIN_DRV_4_8,
- 140, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(153, "PORT22", 0,
- 141, UNIPHIER_PIN_DRV_4_8,
- 141, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(154, "PORT23", 0,
- 142, UNIPHIER_PIN_DRV_4_8,
- 142, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(155, "PORT24", UNIPHIER_PIN_IECTRL_NONE,
- 143, UNIPHIER_PIN_DRV_4_8,
- 143, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(156, "PORT25", 0,
- 144, UNIPHIER_PIN_DRV_4_8,
- 144, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(157, "PORT26", 0,
- 145, UNIPHIER_PIN_DRV_4_8,
- 145, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(158, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
- 31, UNIPHIER_PIN_DRV_4_8,
- 31, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(159, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_4_8,
- 32, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(160, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
- 33, UNIPHIER_PIN_DRV_4_8,
- 33, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(161, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
- 34, UNIPHIER_PIN_DRV_4_8,
- 34, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(162, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
- 35, UNIPHIER_PIN_DRV_4_8,
- 35, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(163, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_4_8,
- 36, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(164, "NANDRYBY0", UNIPHIER_PIN_IECTRL_NONE,
- 37, UNIPHIER_PIN_DRV_4_8,
- 37, UNIPHIER_PIN_PULL_UP),
-};
-
-static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
-static const unsigned emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
-static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
-static const unsigned i2c0_pins[] = {102, 103};
-static const unsigned i2c0_muxvals[] = {0, 0};
-static const unsigned i2c1_pins[] = {104, 105};
-static const unsigned i2c1_muxvals[] = {0, 0};
-static const unsigned i2c2_pins[] = {108, 109};
-static const unsigned i2c2_muxvals[] = {2, 2};
-static const unsigned i2c3_pins[] = {108, 109};
-static const unsigned i2c3_muxvals[] = {3, 3};
-static const unsigned nand_pins[] = {24, 25, 26, 27, 28, 29, 30, 31, 158, 159,
- 160, 161, 162, 163, 164};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
-static const unsigned nand_cs1_pins[] = {22, 23};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
-static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
-static const unsigned uart0_pins[] = {85, 88};
-static const unsigned uart0_muxvals[] = {1, 1};
-static const unsigned uart1_pins[] = {155, 156};
-static const unsigned uart1_muxvals[] = {13, 13};
-static const unsigned uart1b_pins[] = {69, 70};
-static const unsigned uart1b_muxvals[] = {23, 23};
-static const unsigned uart2_pins[] = {128, 129};
-static const unsigned uart2_muxvals[] = {13, 13};
-static const unsigned uart3_pins[] = {110, 111};
-static const unsigned uart3_muxvals[] = {1, 1};
-static const unsigned usb0_pins[] = {53, 54};
-static const unsigned usb0_muxvals[] = {0, 0};
-static const unsigned usb1_pins[] = {55, 56};
-static const unsigned usb1_muxvals[] = {0, 0};
-static const unsigned usb2_pins[] = {155, 156};
-static const unsigned usb2_muxvals[] = {4, 4};
-static const unsigned usb2b_pins[] = {67, 68};
-static const unsigned usb2b_muxvals[] = {23, 23};
-static const unsigned port_range0_pins[] = {
- 135, 136, 137, 138, 139, 140, 141, 142, /* PORT0x */
- 143, 144, 145, 146, 147, 148, 149, 150, /* PORT1x */
- 151, 152, 153, 154, 155, 156, 157, 0, /* PORT2x */
- 1, 2, 3, 4, 5, 120, 121, 122, /* PORT3x */
- 24, 25, 26, 27, 28, 29, 30, 31, /* PORT4x */
- 40, 41, 42, 43, 44, 45, 46, 47, /* PORT5x */
- 48, 49, 50, 51, 52, 53, 54, 55, /* PORT6x */
- 56, 85, 84, 59, 82, 61, 64, 65, /* PORT7x */
- 8, 9, 10, 11, 12, 13, 14, 15, /* PORT8x */
- 66, 67, 68, 69, 70, 71, 72, 73, /* PORT9x */
- 74, 75, 89, 86, 78, 79, 80, 81, /* PORT10x */
- 60, 83, 58, 57, 88, 87, 77, 76, /* PORT11x */
- 90, 91, 92, 93, 94, 95, 96, 97, /* PORT12x */
- 98, 99, 100, 6, 101, 114, 115, 116, /* PORT13x */
- 103, 108, 21, 22, 23, 117, 118, 119, /* PORT14x */
-};
-static const unsigned port_range0_muxvals[] = {
- 0, 0, 0, 0, 0, 0, 0, 0, /* PORT0x */
- 0, 0, 0, 0, 0, 0, 0, 0, /* PORT1x */
- 0, 0, 0, 0, 0, 0, 0, 15, /* PORT2x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
-};
-static const unsigned port_range1_pins[] = {
- 7, /* PORT166 */
-};
-static const unsigned port_range1_muxvals[] = {
- 15, /* PORT166 */
-};
-static const unsigned xirq_range0_pins[] = {
- 151, 123, 124, 125, 126, 127, 128, 129, /* XIRQ0-7 */
- 130, 131, 132, 133, 62, /* XIRQ8-12 */
-};
-static const unsigned xirq_range0_muxvals[] = {
- 14, 0, 0, 0, 0, 0, 0, 0, /* XIRQ0-7 */
- 0, 0, 0, 0, 14, /* XIRQ8-12 */
-};
-static const unsigned xirq_range1_pins[] = {
- 134, 63, /* XIRQ14-15 */
-};
-static const unsigned xirq_range1_muxvals[] = {
- 0, 14, /* XIRQ14-15 */
-};
-
-static const struct uniphier_pinctrl_group ph1_ld4_groups[] = {
- UNIPHIER_PINCTRL_GROUP(emmc),
- UNIPHIER_PINCTRL_GROUP(emmc_dat8),
- UNIPHIER_PINCTRL_GROUP(i2c0),
- UNIPHIER_PINCTRL_GROUP(i2c1),
- UNIPHIER_PINCTRL_GROUP(i2c2),
- UNIPHIER_PINCTRL_GROUP(i2c3),
- UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
- UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart1b),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart3),
- UNIPHIER_PINCTRL_GROUP(usb0),
- UNIPHIER_PINCTRL_GROUP(usb1),
- UNIPHIER_PINCTRL_GROUP(usb2),
- UNIPHIER_PINCTRL_GROUP(usb2b),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range0),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq_range0, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq_range0, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq_range0, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq_range0, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq_range0, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq_range0, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq_range0, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq_range0, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq_range0, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq_range0, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq_range0, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq_range0, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq_range0, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq_range1, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq_range1, 1),
-};
-
-static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
-static const char * const i2c0_groups[] = {"i2c0"};
-static const char * const i2c1_groups[] = {"i2c1"};
-static const char * const i2c2_groups[] = {"i2c2"};
-static const char * const i2c3_groups[] = {"i2c3"};
-static const char * const nand_groups[] = {"nand", "nand_cs1"};
-static const char * const sd_groups[] = {"sd"};
-static const char * const uart0_groups[] = {"uart0"};
-static const char * const uart1_groups[] = {"uart1", "uart1b"};
-static const char * const uart2_groups[] = {"uart2"};
-static const char * const uart3_groups[] = {"uart3"};
-static const char * const usb0_groups[] = {"usb0"};
-static const char * const usb1_groups[] = {"usb1"};
-static const char * const usb2_groups[] = {"usb2", "usb2b"};
-static const char * const port_groups[] = {
- "port00", "port01", "port02", "port03",
- "port04", "port05", "port06", "port07",
- "port10", "port11", "port12", "port13",
- "port14", "port15", "port16", "port17",
- "port20", "port21", "port22", "port23",
- "port24", "port25", "port26", "port27",
- "port30", "port31", "port32", "port33",
- "port34", "port35", "port36", "port37",
- "port40", "port41", "port42", "port43",
- "port44", "port45", "port46", "port47",
- "port50", "port51", "port52", "port53",
- "port54", "port55", "port56", "port57",
- "port60", "port61", "port62", "port63",
- "port64", "port65", "port66", "port67",
- "port70", "port71", "port72", "port73",
- "port74", "port75", "port76", "port77",
- "port80", "port81", "port82", "port83",
- "port84", "port85", "port86", "port87",
- "port90", "port91", "port92", "port93",
- "port94", "port95", "port96", "port97",
- "port100", "port101", "port102", "port103",
- "port104", "port105", "port106", "port107",
- "port110", "port111", "port112", "port113",
- "port114", "port115", "port116", "port117",
- "port120", "port121", "port122", "port123",
- "port124", "port125", "port126", "port127",
- "port130", "port131", "port132", "port133",
- "port134", "port135", "port136", "port137",
- "port140", "port141", "port142", "port143",
- "port144", "port145", "port146", "port147",
- /* port150-164 missing */
- /* none */ "port165",
-};
-static const char * const xirq_groups[] = {
- "xirq0", "xirq1", "xirq2", "xirq3",
- "xirq4", "xirq5", "xirq6", "xirq7",
- "xirq8", "xirq9", "xirq10", "xirq11",
- "xirq12", /* none*/ "xirq14", "xirq15",
-};
-
-static const struct uniphier_pinmux_function ph1_ld4_functions[] = {
- UNIPHIER_PINMUX_FUNCTION(emmc),
- UNIPHIER_PINMUX_FUNCTION(i2c0),
- UNIPHIER_PINMUX_FUNCTION(i2c1),
- UNIPHIER_PINMUX_FUNCTION(i2c2),
- UNIPHIER_PINMUX_FUNCTION(i2c3),
- UNIPHIER_PINMUX_FUNCTION(nand),
- UNIPHIER_PINMUX_FUNCTION(sd),
- UNIPHIER_PINMUX_FUNCTION(uart0),
- UNIPHIER_PINMUX_FUNCTION(uart1),
- UNIPHIER_PINMUX_FUNCTION(uart2),
- UNIPHIER_PINMUX_FUNCTION(uart3),
- UNIPHIER_PINMUX_FUNCTION(usb0),
- UNIPHIER_PINMUX_FUNCTION(usb1),
- UNIPHIER_PINMUX_FUNCTION(usb2),
- UNIPHIER_PINMUX_FUNCTION(port),
- UNIPHIER_PINMUX_FUNCTION(xirq),
-};
-
-static struct uniphier_pinctrl_socdata ph1_ld4_pindata = {
- .groups = ph1_ld4_groups,
- .groups_count = ARRAY_SIZE(ph1_ld4_groups),
- .functions = ph1_ld4_functions,
- .functions_count = ARRAY_SIZE(ph1_ld4_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
-};
-
-static struct pinctrl_desc ph1_ld4_pinctrl_desc = {
- .name = DRIVER_NAME,
- .pins = ph1_ld4_pins,
- .npins = ARRAY_SIZE(ph1_ld4_pins),
- .owner = THIS_MODULE,
-};
-
-static int ph1_ld4_pinctrl_probe(struct platform_device *pdev)
-{
- return uniphier_pinctrl_probe(pdev, &ph1_ld4_pinctrl_desc,
- &ph1_ld4_pindata);
-}
-
-static const struct of_device_id ph1_ld4_pinctrl_match[] = {
- { .compatible = "socionext,ph1-ld4-pinctrl" },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, ph1_ld4_pinctrl_match);
-
-static struct platform_driver ph1_ld4_pinctrl_driver = {
- .probe = ph1_ld4_pinctrl_probe,
- .remove = uniphier_pinctrl_remove,
- .driver = {
- .name = DRIVER_NAME,
- .of_match_table = ph1_ld4_pinctrl_match,
- },
-};
-module_platform_driver(ph1_ld4_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier PH1-LD4 pinctrl driver");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-
-#include "pinctrl-uniphier.h"
-
-#define DRIVER_NAME "ph1-ld6b-pinctrl"
-
-static const struct pinctrl_pin_desc ph1_ld6b_pins[] = {
- UNIPHIER_PINCTRL_PIN(0, "ED0", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_4_8,
- 0, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(1, "ED1", UNIPHIER_PIN_IECTRL_NONE,
- 1, UNIPHIER_PIN_DRV_4_8,
- 1, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(2, "ED2", UNIPHIER_PIN_IECTRL_NONE,
- 2, UNIPHIER_PIN_DRV_4_8,
- 2, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(3, "ED3", UNIPHIER_PIN_IECTRL_NONE,
- 3, UNIPHIER_PIN_DRV_4_8,
- 3, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(4, "ED4", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_4_8,
- 4, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(5, "ED5", UNIPHIER_PIN_IECTRL_NONE,
- 5, UNIPHIER_PIN_DRV_4_8,
- 5, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(6, "ED6", UNIPHIER_PIN_IECTRL_NONE,
- 6, UNIPHIER_PIN_DRV_4_8,
- 6, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(7, "ED7", UNIPHIER_PIN_IECTRL_NONE,
- 7, UNIPHIER_PIN_DRV_4_8,
- 7, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(8, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_4_8,
- 8, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(9, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
- 9, UNIPHIER_PIN_DRV_4_8,
- 9, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(10, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
- 10, UNIPHIER_PIN_DRV_4_8,
- 10, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(11, "ES0", UNIPHIER_PIN_IECTRL_NONE,
- 11, UNIPHIER_PIN_DRV_4_8,
- 11, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(12, "ES1", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_4_8,
- 12, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(13, "ES2", UNIPHIER_PIN_IECTRL_NONE,
- 13, UNIPHIER_PIN_DRV_4_8,
- 13, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(14, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
- 14, UNIPHIER_PIN_DRV_4_8,
- 14, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(15, "PCA00", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 15, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(16, "PCA01", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 16, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(17, "PCA02", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 17, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(18, "PCA03", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 18, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(19, "PCA04", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 19, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(20, "PCA05", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 20, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(21, "PCA06", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 21, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(22, "PCA07", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 22, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(23, "PCA08", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 23, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(24, "PCA09", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 24, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(25, "PCA10", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 25, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(26, "PCA11", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 26, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(27, "PCA12", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 27, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(28, "PCA13", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 28, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(29, "PCA14", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 29, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(30, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
- 30, UNIPHIER_PIN_DRV_4_8,
- 30, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(31, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
- 31, UNIPHIER_PIN_DRV_4_8,
- 31, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(32, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_4_8,
- 32, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(33, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
- 33, UNIPHIER_PIN_DRV_4_8,
- 33, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(34, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
- 34, UNIPHIER_PIN_DRV_4_8,
- 34, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(35, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
- 35, UNIPHIER_PIN_DRV_4_8,
- 35, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(36, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_4_8,
- 36, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(37, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE,
- 37, UNIPHIER_PIN_DRV_4_8,
- 37, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(38, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE,
- 38, UNIPHIER_PIN_DRV_4_8,
- 38, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(39, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
- 39, UNIPHIER_PIN_DRV_4_8,
- 39, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(40, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
- 40, UNIPHIER_PIN_DRV_4_8,
- 40, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(41, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
- 41, UNIPHIER_PIN_DRV_4_8,
- 41, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(42, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
- 42, UNIPHIER_PIN_DRV_4_8,
- 42, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(43, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
- 43, UNIPHIER_PIN_DRV_4_8,
- 43, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(44, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
- 44, UNIPHIER_PIN_DRV_4_8,
- 44, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(45, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
- 45, UNIPHIER_PIN_DRV_4_8,
- 45, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(46, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
- 46, UNIPHIER_PIN_DRV_4_8,
- 46, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(48, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(49, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(50, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(51, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
- 16, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(52, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
- 20, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(53, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 53, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(54, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 54, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(55, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 55, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(56, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 56, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(57, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 57, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(58, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 58, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(59, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 59, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(60, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 60, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(61, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 61, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(62, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 62, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(63, "USB3OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 63, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(64, "HS0BCLKOUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 64, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(65, "HS0SYNCOUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 65, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(66, "HS0VALOUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 66, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(67, "HS0DOUT0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 67, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(68, "HS0DOUT1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 68, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(69, "HS0DOUT2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 69, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(70, "HS0DOUT3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 70, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(71, "HS0DOUT4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 71, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(72, "HS0DOUT5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 72, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(73, "HS0DOUT6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 73, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(74, "HS0DOUT7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 74, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(75, "HS1BCLKIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 75, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(76, "HS1SYNCIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 76, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(77, "HS1VALIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 77, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(78, "HS1DIN0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 78, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(79, "HS1DIN1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 79, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(80, "HS1DIN2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 80, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(81, "HS1DIN3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 81, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(82, "HS1DIN4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 82, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(83, "HS1DIN5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 83, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(84, "HS1DIN6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 84, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(85, "HS1DIN7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 85, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(86, "HS2BCLKIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 86, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(87, "HS2SYNCIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 87, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(88, "HS2VALIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 88, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(89, "HS2DIN0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 89, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(90, "HS2DIN1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 90, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(91, "HS2DIN2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 91, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(92, "HS2DIN3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 92, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(93, "HS2DIN4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 93, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(94, "HS2DIN5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 94, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(95, "HS2DIN6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 95, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(96, "HS2DIN7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 96, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(97, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 97, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(98, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 98, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(99, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 99, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(100, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 100, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(101, "AO1D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 101, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(102, "AO1D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 102, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(103, "AO1D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 103, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(104, "AO1D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 104, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(105, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 105, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(106, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 106, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(107, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 107, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(108, "AO2D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 108, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(109, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 109, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(110, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 110, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(111, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 111, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(112, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 112, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(113, "SBO0", 0,
- 113, UNIPHIER_PIN_DRV_4_8,
- 113, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(114, "SBI0", 0,
- 114, UNIPHIER_PIN_DRV_4_8,
- 114, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(115, "TXD1", 0,
- 115, UNIPHIER_PIN_DRV_4_8,
- 115, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(116, "RXD1", 0,
- 116, UNIPHIER_PIN_DRV_4_8,
- 116, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(117, "PWSRA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 117, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(118, "XIRQ0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 118, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(119, "XIRQ1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 119, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(120, "XIRQ2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 120, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(121, "XIRQ3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 121, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(122, "XIRQ4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 122, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(123, "XIRQ5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 123, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(124, "XIRQ6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 124, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(125, "XIRQ7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 125, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(126, "XIRQ8", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 126, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(127, "PORT00", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 127, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(128, "PORT01", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 128, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(129, "PORT02", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 129, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(130, "PORT03", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 130, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(131, "PORT04", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 131, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(132, "PORT05", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 132, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(133, "PORT06", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 133, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(134, "PORT07", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 134, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(135, "PORT10", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 135, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(136, "PORT11", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 136, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(137, "PORT12", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 137, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(138, "PORT13", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 138, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(139, "PORT14", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 139, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(140, "PORT15", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 140, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(141, "PORT16", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 141, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(142, "LPST", UNIPHIER_PIN_IECTRL_NONE,
- 142, UNIPHIER_PIN_DRV_4_8,
- 142, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(143, "MDC", 0,
- 143, UNIPHIER_PIN_DRV_4_8,
- 143, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(144, "MDIO", 0,
- 144, UNIPHIER_PIN_DRV_4_8,
- 144, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(145, "MDIO_INTL", 0,
- 145, UNIPHIER_PIN_DRV_4_8,
- 145, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(146, "PHYRSTL", 0,
- 146, UNIPHIER_PIN_DRV_4_8,
- 146, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(147, "RGMII_RXCLK", 0,
- 147, UNIPHIER_PIN_DRV_4_8,
- 147, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(148, "RGMII_RXD0", 0,
- 148, UNIPHIER_PIN_DRV_4_8,
- 148, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(149, "RGMII_RXD1", 0,
- 149, UNIPHIER_PIN_DRV_4_8,
- 149, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(150, "RGMII_RXD2", 0,
- 150, UNIPHIER_PIN_DRV_4_8,
- 150, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(151, "RGMII_RXD3", 0,
- 151, UNIPHIER_PIN_DRV_4_8,
- 151, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(152, "RGMII_RXCTL", 0,
- 152, UNIPHIER_PIN_DRV_4_8,
- 152, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(153, "RGMII_TXCLK", 0,
- 153, UNIPHIER_PIN_DRV_4_8,
- 153, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(154, "RGMII_TXD0", 0,
- 154, UNIPHIER_PIN_DRV_4_8,
- 154, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(155, "RGMII_TXD1", 0,
- 155, UNIPHIER_PIN_DRV_4_8,
- 155, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(156, "RGMII_TXD2", 0,
- 156, UNIPHIER_PIN_DRV_4_8,
- 156, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(157, "RGMII_TXD3", 0,
- 157, UNIPHIER_PIN_DRV_4_8,
- 157, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(158, "RGMII_TXCTL", 0,
- 158, UNIPHIER_PIN_DRV_4_8,
- 158, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(159, "A_D_PCD00OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 159, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(160, "A_D_PCD01OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 160, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(161, "A_D_PCD02OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 161, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(162, "A_D_PCD03OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 162, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(163, "A_D_PCD04OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 163, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(164, "A_D_PCD05OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 164, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(165, "A_D_PCD06OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 165, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(166, "A_D_PCD07OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 166, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(167, "A_D_PCD00IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 167, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(168, "A_D_PCD01IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 168, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(169, "A_D_PCD02IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 169, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(170, "A_D_PCD03IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 170, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(171, "A_D_PCD04IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 171, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(172, "A_D_PCD05IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 172, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(173, "A_D_PCD06IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 173, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(174, "A_D_PCD07IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 174, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(175, "A_D_PCDNOE", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 175, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(176, "A_D_PC0READY", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 176, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(177, "A_D_PC0CD1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 177, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(178, "A_D_PC0CD2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 178, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(179, "A_D_PC0WAIT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 179, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(180, "A_D_PC0RESET", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 180, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(181, "A_D_PC0CE1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 181, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(182, "A_D_PC0WE", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 182, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(183, "A_D_PC0OE", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 183, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(184, "A_D_PC0IOWR", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 184, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(185, "A_D_PC0IORD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 185, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(186, "A_D_PC0NOE", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 186, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(187, "A_D_HS0BCLKIN", 0,
- 187, UNIPHIER_PIN_DRV_4_8,
- 187, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(188, "A_D_HS0SYNCIN", 0,
- 188, UNIPHIER_PIN_DRV_4_8,
- 188, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(189, "A_D_HS0VALIN", 0,
- 189, UNIPHIER_PIN_DRV_4_8,
- 189, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(190, "A_D_HS0DIN0", 0,
- 190, UNIPHIER_PIN_DRV_4_8,
- 190, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(191, "A_D_HS0DIN1", 0,
- 191, UNIPHIER_PIN_DRV_4_8,
- 191, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(192, "A_D_HS0DIN2", 0,
- 192, UNIPHIER_PIN_DRV_4_8,
- 192, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(193, "A_D_HS0DIN3", 0,
- 193, UNIPHIER_PIN_DRV_4_8,
- 193, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(194, "A_D_HS0DIN4", 0,
- 194, UNIPHIER_PIN_DRV_4_8,
- 194, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(195, "A_D_HS0DIN5", 0,
- 195, UNIPHIER_PIN_DRV_4_8,
- 195, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(196, "A_D_HS0DIN6", 0,
- 196, UNIPHIER_PIN_DRV_4_8,
- 196, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(197, "A_D_HS0DIN7", 0,
- 197, UNIPHIER_PIN_DRV_4_8,
- 197, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(198, "A_D_AO1ARC", 0,
- 198, UNIPHIER_PIN_DRV_4_8,
- 198, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(199, "A_D_SPIXRST", UNIPHIER_PIN_IECTRL_NONE,
- 199, UNIPHIER_PIN_DRV_4_8,
- 199, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(200, "A_D_SPISCLK0", UNIPHIER_PIN_IECTRL_NONE,
- 200, UNIPHIER_PIN_DRV_4_8,
- 200, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(201, "A_D_SPITXD0", UNIPHIER_PIN_IECTRL_NONE,
- 201, UNIPHIER_PIN_DRV_4_8,
- 201, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(202, "A_D_SPIRXD0", UNIPHIER_PIN_IECTRL_NONE,
- 202, UNIPHIER_PIN_DRV_4_8,
- 202, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(203, "A_D_DMDCLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 203, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(204, "A_D_DMDPSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 204, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(205, "A_D_DMDVAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 205, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(206, "A_D_DMDDATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 206, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(207, "A_D_HDMIRXXIRQ", 0,
- 207, UNIPHIER_PIN_DRV_4_8,
- 207, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(208, "A_D_VBIXIRQ", 0,
- 208, UNIPHIER_PIN_DRV_4_8,
- 208, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(209, "A_D_HDMITXXIRQ", 0,
- 209, UNIPHIER_PIN_DRV_4_8,
- 209, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(210, "A_D_DMDIRQ", UNIPHIER_PIN_IECTRL_NONE,
- 210, UNIPHIER_PIN_DRV_4_8,
- 210, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(211, "A_D_SPICIRQ", UNIPHIER_PIN_IECTRL_NONE,
- 211, UNIPHIER_PIN_DRV_4_8,
- 211, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(212, "A_D_SPIBIRQ", UNIPHIER_PIN_IECTRL_NONE,
- 212, UNIPHIER_PIN_DRV_4_8,
- 212, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(213, "A_D_BESDAOUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 213, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(214, "A_D_BESDAIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 214, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(215, "A_D_BESCLOUT", UNIPHIER_PIN_IECTRL_NONE,
- 215, UNIPHIER_PIN_DRV_4_8,
- 215, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(216, "A_D_VDACCLKOUT", 0,
- 216, UNIPHIER_PIN_DRV_4_8,
- 216, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(217, "A_D_VDACDOUT5", 0,
- 217, UNIPHIER_PIN_DRV_4_8,
- 217, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(218, "A_D_VDACDOUT6", 0,
- 218, UNIPHIER_PIN_DRV_4_8,
- 218, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(219, "A_D_VDACDOUT7", 0,
- 219, UNIPHIER_PIN_DRV_4_8,
- 219, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(220, "A_D_VDACDOUT8", 0,
- 220, UNIPHIER_PIN_DRV_4_8,
- 220, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(221, "A_D_VDACDOUT9", 0,
- 221, UNIPHIER_PIN_DRV_4_8,
- 221, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(222, "A_D_SIFBCKIN", 0,
- 222, UNIPHIER_PIN_DRV_4_8,
- 222, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(223, "A_D_SIFLRCKIN", 0,
- 223, UNIPHIER_PIN_DRV_4_8,
- 223, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(224, "A_D_SIFDIN", 0,
- 224, UNIPHIER_PIN_DRV_4_8,
- 224, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(225, "A_D_LIBCKOUT", 0,
- 225, UNIPHIER_PIN_DRV_4_8,
- 225, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(226, "A_D_LILRCKOUT", 0,
- 226, UNIPHIER_PIN_DRV_4_8,
- 226, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(227, "A_D_LIDIN", 0,
- 227, UNIPHIER_PIN_DRV_4_8,
- 227, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(228, "A_D_LODOUT", 0,
- 228, UNIPHIER_PIN_DRV_4_8,
- 228, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(229, "A_D_HPDOUT", 0,
- 229, UNIPHIER_PIN_DRV_4_8,
- 229, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(230, "A_D_MCLK", 0,
- 230, UNIPHIER_PIN_DRV_4_8,
- 230, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(231, "A_D_A2PLLREFOUT", 0,
- 231, UNIPHIER_PIN_DRV_4_8,
- 231, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(232, "A_D_HDMI3DSDAOUT", 0,
- 232, UNIPHIER_PIN_DRV_4_8,
- 232, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(233, "A_D_HDMI3DSDAIN", 0,
- 233, UNIPHIER_PIN_DRV_4_8,
- 233, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(234, "A_D_HDMI3DSCLIN", 0,
- 234, UNIPHIER_PIN_DRV_4_8,
- 234, UNIPHIER_PIN_PULL_DOWN),
-};
-
-static const unsigned adinter_pins[] = {
- 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172,
- 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186,
- 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200,
- 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
- 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
- 229, 230, 231, 232, 233, 234,
-};
-static const unsigned adinter_muxvals[] = {
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0,
-};
-static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
-static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
-static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
-static const unsigned i2c0_pins[] = {109, 110};
-static const unsigned i2c0_muxvals[] = {0, 0};
-static const unsigned i2c1_pins[] = {111, 112};
-static const unsigned i2c1_muxvals[] = {0, 0};
-static const unsigned i2c2_pins[] = {115, 116};
-static const unsigned i2c2_muxvals[] = {1, 1};
-static const unsigned i2c3_pins[] = {118, 119};
-static const unsigned i2c3_muxvals[] = {1, 1};
-static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
- 42, 43, 44, 45, 46};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
-static const unsigned nand_cs1_pins[] = {37, 38};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
-static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
-static const unsigned uart0_pins[] = {135, 136};
-static const unsigned uart0_muxvals[] = {3, 3};
-static const unsigned uart0b_pins[] = {11, 12};
-static const unsigned uart0b_muxvals[] = {2, 2};
-static const unsigned uart1_pins[] = {115, 116};
-static const unsigned uart1_muxvals[] = {0, 0};
-static const unsigned uart1b_pins[] = {113, 114};
-static const unsigned uart1b_muxvals[] = {1, 1};
-static const unsigned uart2_pins[] = {113, 114};
-static const unsigned uart2_muxvals[] = {2, 2};
-static const unsigned uart2b_pins[] = {86, 87};
-static const unsigned uart2b_muxvals[] = {1, 1};
-static const unsigned usb0_pins[] = {56, 57};
-static const unsigned usb0_muxvals[] = {0, 0};
-static const unsigned usb1_pins[] = {58, 59};
-static const unsigned usb1_muxvals[] = {0, 0};
-static const unsigned usb2_pins[] = {60, 61};
-static const unsigned usb2_muxvals[] = {0, 0};
-static const unsigned usb3_pins[] = {62, 63};
-static const unsigned usb3_muxvals[] = {0, 0};
-static const unsigned port_range0_pins[] = {
- 127, 128, 129, 130, 131, 132, 133, 134, /* PORT0x */
- 135, 136, 137, 138, 139, 140, 141, 142, /* PORT1x */
- 0, 1, 2, 3, 4, 5, 6, 7, /* PORT2x */
- 8, 9, 10, 11, 12, 13, 14, 15, /* PORT3x */
- 16, 17, 18, 19, 21, 22, 23, 24, /* PORT4x */
- 25, 30, 31, 32, 33, 34, 35, 36, /* PORT5x */
- 37, 38, 39, 40, 41, 42, 43, 44, /* PORT6x */
- 45, 46, 47, 48, 49, 50, 51, 52, /* PORT7x */
- 53, 54, 55, 56, 57, 58, 59, 60, /* PORT8x */
- 61, 62, 63, 64, 65, 66, 67, 68, /* PORT9x */
- 69, 70, 71, 76, 77, 78, 79, 80, /* PORT10x */
-};
-static const unsigned port_range0_muxvals[] = {
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
-};
-static const unsigned port_range1_pins[] = {
- 81, 82, 83, 84, 85, 86, 87, 88, /* PORT12x */
- 89, 90, 95, 96, 97, 98, 99, 100, /* PORT13x */
- 101, 102, 103, 104, 105, 106, 107, 108, /* PORT14x */
- 118, 119, 120, 121, 122, 123, 124, 125, /* PORT15x */
- 126, 72, 73, 92, 177, 93, 94, 176, /* PORT16x */
- 74, 91, 27, 28, 29, 75, 20, 26, /* PORT17x */
- 109, 110, 111, 112, 113, 114, 115, 116, /* PORT18x */
- 117, 143, 144, 145, 146, 147, 148, 149, /* PORT19x */
- 150, 151, 152, 153, 154, 155, 156, 157, /* PORT20x */
- 158, 159, 160, 161, 162, 163, 164, 165, /* PORT21x */
- 166, 178, 179, 180, 181, 182, 183, 184, /* PORT22x */
- 185, 187, 188, 189, 190, 191, 192, 193, /* PORT23x */
- 194, 195, 196, 197, 198, 199, 200, 201, /* PORT24x */
- 202, 203, 204, 205, 206, 207, 208, 209, /* PORT25x */
- 210, 211, 212, 213, 214, 215, 216, 217, /* PORT26x */
- 218, 219, 220, 221, 223, 224, 225, 226, /* PORT27x */
- 227, 228, 229, 230, 231, 232, 233, 234, /* PORT28x */
-};
-static const unsigned port_range1_muxvals[] = {
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT15x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT16x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT17x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */
-};
-static const unsigned xirq_pins[] = {
- 118, 119, 120, 121, 122, 123, 124, 125, /* XIRQ0-7 */
- 126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */
- 74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */
-};
-static const unsigned xirq_muxvals[] = {
- 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
- 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */
- 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */
-};
-
-static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = {
- UNIPHIER_PINCTRL_GROUP(adinter),
- UNIPHIER_PINCTRL_GROUP(emmc),
- UNIPHIER_PINCTRL_GROUP(emmc_dat8),
- UNIPHIER_PINCTRL_GROUP(i2c0),
- UNIPHIER_PINCTRL_GROUP(i2c1),
- UNIPHIER_PINCTRL_GROUP(i2c2),
- UNIPHIER_PINCTRL_GROUP(i2c3),
- UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
- UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart0b),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart1b),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart2b),
- UNIPHIER_PINCTRL_GROUP(usb0),
- UNIPHIER_PINCTRL_GROUP(usb1),
- UNIPHIER_PINCTRL_GROUP(usb2),
- UNIPHIER_PINCTRL_GROUP(usb3),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range1, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range1, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range1, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range1, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range1, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range1, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range1, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range1, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range1, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range1, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range1, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range1, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range1, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range1, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range1, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range1, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range1, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range1, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range1, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range1, 21),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range1, 22),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range1, 23),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port150, port_range1, 24),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port151, port_range1, 25),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port152, port_range1, 26),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port153, port_range1, 27),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port154, port_range1, 28),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port155, port_range1, 29),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port156, port_range1, 30),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port157, port_range1, 31),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port160, port_range1, 32),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port161, port_range1, 33),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port162, port_range1, 34),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port163, port_range1, 35),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port164, port_range1, 36),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 37),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range1, 38),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port167, port_range1, 39),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port170, port_range1, 40),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port171, port_range1, 41),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port172, port_range1, 42),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port173, port_range1, 43),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port174, port_range1, 44),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 45),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 46),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 47),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 48),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 49),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 50),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 51),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 52),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 53),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 54),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 55),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 56),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 57),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 58),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 59),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 60),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 61),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 62),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 63),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 64),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 65),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 66),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 67),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 68),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 69),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 70),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 71),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 72),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 73),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 74),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 75),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 76),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 77),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 78),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 79),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 80),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 81),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 82),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 83),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 84),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 85),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 86),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 87),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 88),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 89),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 90),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 91),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 92),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 93),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 94),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 95),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 96),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 97),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 98),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 99),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 100),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 101),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 102),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 103),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 104),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 105),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 106),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 107),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 108),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 109),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 110),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 111),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 112),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 113),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 114),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 115),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 116),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 117),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 118),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 119),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 120),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 121),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 122),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 123),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 124),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 125),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 126),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 127),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 128),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 129),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 130),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 131),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 132),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 133),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 134),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 135),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23),
-};
-
-static const char * const adinter_groups[] = {"adinter"};
-static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
-static const char * const i2c0_groups[] = {"i2c0"};
-static const char * const i2c1_groups[] = {"i2c1"};
-static const char * const i2c2_groups[] = {"i2c2"};
-static const char * const i2c3_groups[] = {"i2c3"};
-static const char * const nand_groups[] = {"nand", "nand_cs1"};
-static const char * const sd_groups[] = {"sd"};
-static const char * const uart0_groups[] = {"uart0", "uart0b"};
-static const char * const uart1_groups[] = {"uart1", "uart1b"};
-static const char * const uart2_groups[] = {"uart2", "uart2b"};
-static const char * const usb0_groups[] = {"usb0"};
-static const char * const usb1_groups[] = {"usb1"};
-static const char * const usb2_groups[] = {"usb2"};
-static const char * const usb3_groups[] = {"usb3"};
-static const char * const port_groups[] = {
- "port00", "port01", "port02", "port03",
- "port04", "port05", "port06", "port07",
- "port10", "port11", "port12", "port13",
- "port14", "port15", "port16", "port17",
- "port20", "port21", "port22", "port23",
- "port24", "port25", "port26", "port27",
- "port30", "port31", "port32", "port33",
- "port34", "port35", "port36", "port37",
- "port40", "port41", "port42", "port43",
- "port44", "port45", "port46", "port47",
- "port50", "port51", "port52", "port53",
- "port54", "port55", "port56", "port57",
- "port60", "port61", "port62", "port63",
- "port64", "port65", "port66", "port67",
- "port70", "port71", "port72", "port73",
- "port74", "port75", "port76", "port77",
- "port80", "port81", "port82", "port83",
- "port84", "port85", "port86", "port87",
- "port90", "port91", "port92", "port93",
- "port94", "port95", "port96", "port97",
- "port100", "port101", "port102", "port103",
- "port104", "port105", "port106", "port107",
- /* port110-117 missing */
- "port120", "port121", "port122", "port123",
- "port124", "port125", "port126", "port127",
- "port130", "port131", "port132", "port133",
- "port134", "port135", "port136", "port137",
- "port140", "port141", "port142", "port143",
- "port144", "port145", "port146", "port147",
- "port150", "port151", "port152", "port153",
- "port154", "port155", "port156", "port157",
- "port160", "port161", "port162", "port163",
- "port164", "port165", "port166", "port167",
- "port170", "port171", "port172", "port173",
- "port174", "port175", "port176", "port177",
- "port180", "port181", "port182", "port183",
- "port184", "port185", "port186", "port187",
- "port190", "port191", "port192", "port193",
- "port194", "port195", "port196", "port197",
- "port200", "port201", "port202", "port203",
- "port204", "port205", "port206", "port207",
- "port210", "port211", "port212", "port213",
- "port214", "port215", "port216", "port217",
- "port220", "port221", "port222", "port223",
- "port224", "port225", "port226", "port227",
- "port230", "port231", "port232", "port233",
- "port234", "port235", "port236", "port237",
- "port240", "port241", "port242", "port243",
- "port244", "port245", "port246", "port247",
- "port250", "port251", "port252", "port253",
- "port254", "port255", "port256", "port257",
- "port260", "port261", "port262", "port263",
- "port264", "port265", "port266", "port267",
- "port270", "port271", "port272", "port273",
- "port274", "port275", "port276", "port277",
- "port280", "port281", "port282", "port283",
- "port284", "port285", "port286", "port287",
-};
-static const char * const xirq_groups[] = {
- "xirq0", "xirq1", "xirq2", "xirq3",
- "xirq4", "xirq5", "xirq6", "xirq7",
- "xirq8", "xirq9", "xirq10", "xirq11",
- "xirq12", "xirq13", "xirq14", "xirq15",
- "xirq16", "xirq17", "xirq18", "xirq19",
- "xirq20", "xirq21", "xirq22", "xirq23",
-};
-
-static const struct uniphier_pinmux_function ph1_ld6b_functions[] = {
- UNIPHIER_PINMUX_FUNCTION(adinter), /* Achip-Dchip interconnect */
- UNIPHIER_PINMUX_FUNCTION(emmc),
- UNIPHIER_PINMUX_FUNCTION(i2c0),
- UNIPHIER_PINMUX_FUNCTION(i2c1),
- UNIPHIER_PINMUX_FUNCTION(i2c2),
- UNIPHIER_PINMUX_FUNCTION(i2c3),
- UNIPHIER_PINMUX_FUNCTION(nand),
- UNIPHIER_PINMUX_FUNCTION(sd),
- UNIPHIER_PINMUX_FUNCTION(uart0),
- UNIPHIER_PINMUX_FUNCTION(uart1),
- UNIPHIER_PINMUX_FUNCTION(uart2),
- UNIPHIER_PINMUX_FUNCTION(usb0),
- UNIPHIER_PINMUX_FUNCTION(usb1),
- UNIPHIER_PINMUX_FUNCTION(usb2),
- UNIPHIER_PINMUX_FUNCTION(usb3),
- UNIPHIER_PINMUX_FUNCTION(port),
- UNIPHIER_PINMUX_FUNCTION(xirq),
-};
-
-static struct uniphier_pinctrl_socdata ph1_ld6b_pindata = {
- .groups = ph1_ld6b_groups,
- .groups_count = ARRAY_SIZE(ph1_ld6b_groups),
- .functions = ph1_ld6b_functions,
- .functions_count = ARRAY_SIZE(ph1_ld6b_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
-};
-
-static struct pinctrl_desc ph1_ld6b_pinctrl_desc = {
- .name = DRIVER_NAME,
- .pins = ph1_ld6b_pins,
- .npins = ARRAY_SIZE(ph1_ld6b_pins),
- .owner = THIS_MODULE,
-};
-
-static int ph1_ld6b_pinctrl_probe(struct platform_device *pdev)
-{
- return uniphier_pinctrl_probe(pdev, &ph1_ld6b_pinctrl_desc,
- &ph1_ld6b_pindata);
-}
-
-static const struct of_device_id ph1_ld6b_pinctrl_match[] = {
- { .compatible = "socionext,ph1-ld6b-pinctrl" },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, ph1_ld6b_pinctrl_match);
-
-static struct platform_driver ph1_ld6b_pinctrl_driver = {
- .probe = ph1_ld6b_pinctrl_probe,
- .remove = uniphier_pinctrl_remove,
- .driver = {
- .name = DRIVER_NAME,
- .of_match_table = ph1_ld6b_pinctrl_match,
- },
-};
-module_platform_driver(ph1_ld6b_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier PH1-LD6b pinctrl driver");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program5 is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-
-#include "pinctrl-uniphier.h"
-
-#define DRIVER_NAME "ph1-pro4-pinctrl"
-
-static const struct pinctrl_pin_desc ph1_pro4_pins[] = {
- UNIPHIER_PINCTRL_PIN(0, "CK24O", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_4_8,
- 0, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(1, "VC27A", UNIPHIER_PIN_IECTRL_NONE,
- 1, UNIPHIER_PIN_DRV_4_8,
- 1, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(2, "CK27AI", UNIPHIER_PIN_IECTRL_NONE,
- 2, UNIPHIER_PIN_DRV_4_8,
- 2, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(3, "CK27AO", UNIPHIER_PIN_IECTRL_NONE,
- 3, UNIPHIER_PIN_DRV_4_8,
- 3, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(4, "CKSEL", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_4_8,
- 4, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(5, "CK27AV", UNIPHIER_PIN_IECTRL_NONE,
- 5, UNIPHIER_PIN_DRV_4_8,
- 5, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(6, "AEXCKA", UNIPHIER_PIN_IECTRL_NONE,
- 6, UNIPHIER_PIN_DRV_4_8,
- 6, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(7, "ASEL", UNIPHIER_PIN_IECTRL_NONE,
- 7, UNIPHIER_PIN_DRV_4_8,
- 7, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(8, "ARCRESET", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_4_8,
- 8, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(9, "ARCUNLOCK", UNIPHIER_PIN_IECTRL_NONE,
- 9, UNIPHIER_PIN_DRV_4_8,
- 9, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(10, "XSRST", UNIPHIER_PIN_IECTRL_NONE,
- 10, UNIPHIER_PIN_DRV_4_8,
- 10, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(11, "XNMIRQ", UNIPHIER_PIN_IECTRL_NONE,
- 11, UNIPHIER_PIN_DRV_4_8,
- 11, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(12, "XSCIRQ", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_4_8,
- 12, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(13, "EXTRG", UNIPHIER_PIN_IECTRL_NONE,
- 13, UNIPHIER_PIN_DRV_4_8,
- 13, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(14, "TRCCLK", UNIPHIER_PIN_IECTRL_NONE,
- 14, UNIPHIER_PIN_DRV_4_8,
- 14, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(15, "TRCCTL", UNIPHIER_PIN_IECTRL_NONE,
- 15, UNIPHIER_PIN_DRV_4_8,
- 15, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(16, "TRCD0", UNIPHIER_PIN_IECTRL_NONE,
- 16, UNIPHIER_PIN_DRV_4_8,
- 16, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(17, "TRCD1", UNIPHIER_PIN_IECTRL_NONE,
- 17, UNIPHIER_PIN_DRV_4_8,
- 17, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(18, "TRCD2", UNIPHIER_PIN_IECTRL_NONE,
- 18, UNIPHIER_PIN_DRV_4_8,
- 18, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(19, "TRCD3", UNIPHIER_PIN_IECTRL_NONE,
- 19, UNIPHIER_PIN_DRV_4_8,
- 19, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(20, "TRCD4", UNIPHIER_PIN_IECTRL_NONE,
- 20, UNIPHIER_PIN_DRV_4_8,
- 20, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(21, "TRCD5", UNIPHIER_PIN_IECTRL_NONE,
- 21, UNIPHIER_PIN_DRV_4_8,
- 21, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(22, "TRCD6", UNIPHIER_PIN_IECTRL_NONE,
- 22, UNIPHIER_PIN_DRV_4_8,
- 22, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(23, "TRCD7", UNIPHIER_PIN_IECTRL_NONE,
- 23, UNIPHIER_PIN_DRV_4_8,
- 23, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(24, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
- 24, UNIPHIER_PIN_DRV_4_8,
- 24, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(25, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
- 25, UNIPHIER_PIN_DRV_4_8,
- 25, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(26, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
- 26, UNIPHIER_PIN_DRV_4_8,
- 26, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(27, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
- 27, UNIPHIER_PIN_DRV_4_8,
- 27, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(28, "ES0", UNIPHIER_PIN_IECTRL_NONE,
- 28, UNIPHIER_PIN_DRV_4_8,
- 28, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(29, "ES1", UNIPHIER_PIN_IECTRL_NONE,
- 29, UNIPHIER_PIN_DRV_4_8,
- 29, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(30, "ES2", UNIPHIER_PIN_IECTRL_NONE,
- 30, UNIPHIER_PIN_DRV_4_8,
- 30, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(31, "ED0", UNIPHIER_PIN_IECTRL_NONE,
- 31, UNIPHIER_PIN_DRV_4_8,
- 31, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(32, "ED1", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_4_8,
- 32, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(33, "ED2", UNIPHIER_PIN_IECTRL_NONE,
- 33, UNIPHIER_PIN_DRV_4_8,
- 33, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(34, "ED3", UNIPHIER_PIN_IECTRL_NONE,
- 34, UNIPHIER_PIN_DRV_4_8,
- 34, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(35, "ED4", UNIPHIER_PIN_IECTRL_NONE,
- 35, UNIPHIER_PIN_DRV_4_8,
- 35, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(36, "ED5", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_4_8,
- 36, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(37, "ED6", UNIPHIER_PIN_IECTRL_NONE,
- 37, UNIPHIER_PIN_DRV_4_8,
- 37, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(38, "ED7", UNIPHIER_PIN_IECTRL_NONE,
- 38, UNIPHIER_PIN_DRV_4_8,
- 38, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(39, "BOOTSWAP", UNIPHIER_PIN_IECTRL_NONE,
- 39, UNIPHIER_PIN_DRV_NONE,
- 39, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(40, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
- 2, UNIPHIER_PIN_DRV_8_12_16_20,
- 40, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(41, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
- 3, UNIPHIER_PIN_DRV_8_12_16_20,
- 41, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(42, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_8_12_16_20,
- 42, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(43, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
- 5, UNIPHIER_PIN_DRV_8_12_16_20,
- 43, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(44, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
- 6, UNIPHIER_PIN_DRV_8_12_16_20,
- 44, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(45, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
- 7, UNIPHIER_PIN_DRV_8_12_16_20,
- 45, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(46, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_8_12_16_20,
- 46, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(47, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
- 9, UNIPHIER_PIN_DRV_8_12_16_20,
- 47, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(48, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
- 48, UNIPHIER_PIN_DRV_4_8,
- 48, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(49, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
- 49, UNIPHIER_PIN_DRV_4_8,
- 49, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(50, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
- 50, UNIPHIER_PIN_DRV_4_8,
- 50, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(51, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_8_12_16_20,
- 51, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(52, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
- 52, UNIPHIER_PIN_DRV_4_8,
- 52, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(53, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
- 1, UNIPHIER_PIN_DRV_8_12_16_20,
- 53, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(54, "NRYBY0", UNIPHIER_PIN_IECTRL_NONE,
- 54, UNIPHIER_PIN_DRV_4_8,
- 54, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(55, "DMDSCLTST", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_NONE,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(56, "DMDSDATST", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(57, "AGCI0", 3,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 55, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(58, "DMDSCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(59, "DMDSDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(60, "AGCBS0", 5,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 56, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(61, "DMDSCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(62, "DMDSDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(63, "ANTSHORT", UNIPHIER_PIN_IECTRL_NONE,
- 57, UNIPHIER_PIN_DRV_4_8,
- 57, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(64, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE,
- 58, UNIPHIER_PIN_DRV_4_8,
- 58, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(65, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE,
- 59, UNIPHIER_PIN_DRV_4_8,
- 59, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(66, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 60, UNIPHIER_PIN_DRV_4_8,
- 60, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(67, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE,
- 61, UNIPHIER_PIN_DRV_4_8,
- 61, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(68, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE,
- 62, UNIPHIER_PIN_DRV_4_8,
- 62, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(69, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE,
- 63, UNIPHIER_PIN_DRV_4_8,
- 63, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(70, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 64, UNIPHIER_PIN_DRV_4_8,
- 64, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(71, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE,
- 65, UNIPHIER_PIN_DRV_4_8,
- 65, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(72, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE,
- 66, UNIPHIER_PIN_DRV_4_8,
- 66, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(73, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE,
- 67, UNIPHIER_PIN_DRV_4_8,
- 67, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(74, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 68, UNIPHIER_PIN_DRV_4_8,
- 68, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(75, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE,
- 69, UNIPHIER_PIN_DRV_4_8,
- 69, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(76, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE,
- 70, UNIPHIER_PIN_DRV_4_8,
- 70, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(77, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE,
- 71, UNIPHIER_PIN_DRV_4_8,
- 71, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(78, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 72, UNIPHIER_PIN_DRV_4_8,
- 72, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(79, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE,
- 73, UNIPHIER_PIN_DRV_4_8,
- 73, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(80, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE,
- 74, UNIPHIER_PIN_DRV_4_8,
- 74, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(81, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE,
- 75, UNIPHIER_PIN_DRV_4_8,
- 75, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(82, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 76, UNIPHIER_PIN_DRV_4_8,
- 76, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(83, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE,
- 77, UNIPHIER_PIN_DRV_4_8,
- 77, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(84, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE,
- 78, UNIPHIER_PIN_DRV_4_8,
- 78, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(85, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE,
- 79, UNIPHIER_PIN_DRV_4_8,
- 79, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(86, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 80, UNIPHIER_PIN_DRV_4_8,
- 80, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(87, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE,
- 81, UNIPHIER_PIN_DRV_4_8,
- 81, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(88, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE,
- 82, UNIPHIER_PIN_DRV_4_8,
- 82, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(89, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE,
- 83, UNIPHIER_PIN_DRV_4_8,
- 83, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(90, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 84, UNIPHIER_PIN_DRV_4_8,
- 84, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(91, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE,
- 85, UNIPHIER_PIN_DRV_4_8,
- 85, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(92, "CKFEO", UNIPHIER_PIN_IECTRL_NONE,
- 86, UNIPHIER_PIN_DRV_4_8,
- 86, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(93, "XFERST", UNIPHIER_PIN_IECTRL_NONE,
- 87, UNIPHIER_PIN_DRV_4_8,
- 87, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(94, "P_FE_ON", UNIPHIER_PIN_IECTRL_NONE,
- 88, UNIPHIER_PIN_DRV_4_8,
- 88, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(95, "P_TU0_ON", UNIPHIER_PIN_IECTRL_NONE,
- 89, UNIPHIER_PIN_DRV_4_8,
- 89, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(96, "XFEIRQ0", UNIPHIER_PIN_IECTRL_NONE,
- 90, UNIPHIER_PIN_DRV_4_8,
- 90, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(97, "XFEIRQ1", UNIPHIER_PIN_IECTRL_NONE,
- 91, UNIPHIER_PIN_DRV_4_8,
- 91, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(98, "XFEIRQ2", UNIPHIER_PIN_IECTRL_NONE,
- 92, UNIPHIER_PIN_DRV_4_8,
- 92, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(99, "XFEIRQ3", UNIPHIER_PIN_IECTRL_NONE,
- 93, UNIPHIER_PIN_DRV_4_8,
- 93, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(100, "XFEIRQ4", UNIPHIER_PIN_IECTRL_NONE,
- 94, UNIPHIER_PIN_DRV_4_8,
- 94, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(101, "XFEIRQ5", UNIPHIER_PIN_IECTRL_NONE,
- 95, UNIPHIER_PIN_DRV_4_8,
- 95, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(102, "XFEIRQ6", UNIPHIER_PIN_IECTRL_NONE,
- 96, UNIPHIER_PIN_DRV_4_8,
- 96, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(103, "SMTCLK0", UNIPHIER_PIN_IECTRL_NONE,
- 97, UNIPHIER_PIN_DRV_4_8,
- 97, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(104, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE,
- 98, UNIPHIER_PIN_DRV_4_8,
- 98, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(105, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE,
- 99, UNIPHIER_PIN_DRV_4_8,
- 99, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(106, "SMTD0", UNIPHIER_PIN_IECTRL_NONE,
- 100, UNIPHIER_PIN_DRV_4_8,
- 100, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(107, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE,
- 101, UNIPHIER_PIN_DRV_4_8,
- 101, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(108, "SMTDET0", UNIPHIER_PIN_IECTRL_NONE,
- 102, UNIPHIER_PIN_DRV_4_8,
- 102, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(109, "SMTCLK1", UNIPHIER_PIN_IECTRL_NONE,
- 103, UNIPHIER_PIN_DRV_4_8,
- 103, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(110, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE,
- 104, UNIPHIER_PIN_DRV_4_8,
- 104, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(111, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE,
- 105, UNIPHIER_PIN_DRV_4_8,
- 105, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(112, "SMTD1", UNIPHIER_PIN_IECTRL_NONE,
- 106, UNIPHIER_PIN_DRV_4_8,
- 106, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(113, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE,
- 107, UNIPHIER_PIN_DRV_4_8,
- 107, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(114, "SMTDET1", UNIPHIER_PIN_IECTRL_NONE,
- 108, UNIPHIER_PIN_DRV_4_8,
- 108, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(115, "XINTM", UNIPHIER_PIN_IECTRL_NONE,
- 109, UNIPHIER_PIN_DRV_4_8,
- 109, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(116, "SCLKM", UNIPHIER_PIN_IECTRL_NONE,
- 110, UNIPHIER_PIN_DRV_4_8,
- 110, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(117, "SBMTP", UNIPHIER_PIN_IECTRL_NONE,
- 111, UNIPHIER_PIN_DRV_4_8,
- 111, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(118, "SBPTM", UNIPHIER_PIN_IECTRL_NONE,
- 112, UNIPHIER_PIN_DRV_4_8,
- 112, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(119, "XMPREQ", UNIPHIER_PIN_IECTRL_NONE,
- 113, UNIPHIER_PIN_DRV_4_8,
- 113, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(120, "XINTP", UNIPHIER_PIN_IECTRL_NONE,
- 114, UNIPHIER_PIN_DRV_4_8,
- 114, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(121, "LPST", UNIPHIER_PIN_IECTRL_NONE,
- 115, UNIPHIER_PIN_DRV_4_8,
- 115, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(122, "SDBOOT", UNIPHIER_PIN_IECTRL_NONE,
- 116, UNIPHIER_PIN_DRV_4_8,
- 116, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(123, "BFAIL", UNIPHIER_PIN_IECTRL_NONE,
- 117, UNIPHIER_PIN_DRV_4_8,
- 117, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(124, "XFWE", UNIPHIER_PIN_IECTRL_NONE,
- 118, UNIPHIER_PIN_DRV_4_8,
- 118, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(125, "RF_COM_RDY", UNIPHIER_PIN_IECTRL_NONE,
- 119, UNIPHIER_PIN_DRV_4_8,
- 119, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(126, "XDIAG0", UNIPHIER_PIN_IECTRL_NONE,
- 120, UNIPHIER_PIN_DRV_4_8,
- 120, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(127, "RXD0", UNIPHIER_PIN_IECTRL_NONE,
- 121, UNIPHIER_PIN_DRV_4_8,
- 121, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(128, "TXD0", UNIPHIER_PIN_IECTRL_NONE,
- 122, UNIPHIER_PIN_DRV_4_8,
- 122, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(129, "RXD1", UNIPHIER_PIN_IECTRL_NONE,
- 123, UNIPHIER_PIN_DRV_4_8,
- 123, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(130, "TXD1", UNIPHIER_PIN_IECTRL_NONE,
- 124, UNIPHIER_PIN_DRV_4_8,
- 124, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(131, "RXD2", UNIPHIER_PIN_IECTRL_NONE,
- 125, UNIPHIER_PIN_DRV_4_8,
- 125, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(132, "TXD2", UNIPHIER_PIN_IECTRL_NONE,
- 126, UNIPHIER_PIN_DRV_4_8,
- 126, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(133, "SS0CS", UNIPHIER_PIN_IECTRL_NONE,
- 127, UNIPHIER_PIN_DRV_4_8,
- 127, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(134, "SS0CLK", UNIPHIER_PIN_IECTRL_NONE,
- 128, UNIPHIER_PIN_DRV_4_8,
- 128, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(135, "SS0DO", UNIPHIER_PIN_IECTRL_NONE,
- 129, UNIPHIER_PIN_DRV_4_8,
- 129, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(136, "SS0DI", UNIPHIER_PIN_IECTRL_NONE,
- 130, UNIPHIER_PIN_DRV_4_8,
- 130, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(137, "MS0CS0", UNIPHIER_PIN_IECTRL_NONE,
- 131, UNIPHIER_PIN_DRV_4_8,
- 131, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(138, "MS0CLK", UNIPHIER_PIN_IECTRL_NONE,
- 132, UNIPHIER_PIN_DRV_4_8,
- 132, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(139, "MS0DI", UNIPHIER_PIN_IECTRL_NONE,
- 133, UNIPHIER_PIN_DRV_4_8,
- 133, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(140, "MS0DO", UNIPHIER_PIN_IECTRL_NONE,
- 134, UNIPHIER_PIN_DRV_4_8,
- 134, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(141, "XMDMRST", UNIPHIER_PIN_IECTRL_NONE,
- 135, UNIPHIER_PIN_DRV_4_8,
- 135, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(142, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(143, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(144, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(145, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(146, "SCL2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(147, "SDA2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(148, "SCL3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(149, "SDA3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(150, "SD0DAT0", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_8_12_16_20,
- 136, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(151, "SD0DAT1", UNIPHIER_PIN_IECTRL_NONE,
- 13, UNIPHIER_PIN_DRV_8_12_16_20,
- 137, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(152, "SD0DAT2", UNIPHIER_PIN_IECTRL_NONE,
- 14, UNIPHIER_PIN_DRV_8_12_16_20,
- 138, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(153, "SD0DAT3", UNIPHIER_PIN_IECTRL_NONE,
- 15, UNIPHIER_PIN_DRV_8_12_16_20,
- 139, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(154, "SD0CMD", UNIPHIER_PIN_IECTRL_NONE,
- 11, UNIPHIER_PIN_DRV_8_12_16_20,
- 141, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(155, "SD0CLK", UNIPHIER_PIN_IECTRL_NONE,
- 10, UNIPHIER_PIN_DRV_8_12_16_20,
- 140, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(156, "SD0CD", UNIPHIER_PIN_IECTRL_NONE,
- 142, UNIPHIER_PIN_DRV_4_8,
- 142, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(157, "SD0WP", UNIPHIER_PIN_IECTRL_NONE,
- 143, UNIPHIER_PIN_DRV_4_8,
- 143, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(158, "SD0VTCG", UNIPHIER_PIN_IECTRL_NONE,
- 144, UNIPHIER_PIN_DRV_4_8,
- 144, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(159, "CK25O", UNIPHIER_PIN_IECTRL_NONE,
- 145, UNIPHIER_PIN_DRV_4_8,
- 145, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(160, "RGMII_TXCLK", 6,
- 146, UNIPHIER_PIN_DRV_4_8,
- 146, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(161, "RGMII_TXD0", 6,
- 147, UNIPHIER_PIN_DRV_4_8,
- 147, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(162, "RGMII_TXD1", 6,
- 148, UNIPHIER_PIN_DRV_4_8,
- 148, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(163, "RGMII_TXD2", 6,
- 149, UNIPHIER_PIN_DRV_4_8,
- 149, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(164, "RGMII_TXD3", 6,
- 150, UNIPHIER_PIN_DRV_4_8,
- 150, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(165, "RGMII_TXCTL", 6,
- 151, UNIPHIER_PIN_DRV_4_8,
- 151, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(166, "MII_TXER", UNIPHIER_PIN_IECTRL_NONE,
- 152, UNIPHIER_PIN_DRV_4_8,
- 152, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(167, "RGMII_RXCLK", 6,
- 153, UNIPHIER_PIN_DRV_4_8,
- 153, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(168, "RGMII_RXD0", 6,
- 154, UNIPHIER_PIN_DRV_4_8,
- 154, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(169, "RGMII_RXD1", 6,
- 155, UNIPHIER_PIN_DRV_4_8,
- 155, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(170, "RGMII_RXD2", 6,
- 156, UNIPHIER_PIN_DRV_4_8,
- 156, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(171, "RGMII_RXD3", 6,
- 157, UNIPHIER_PIN_DRV_4_8,
- 157, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(172, "RGMII_RXCTL", 6,
- 158, UNIPHIER_PIN_DRV_4_8,
- 158, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(173, "MII_RXER", 6,
- 159, UNIPHIER_PIN_DRV_4_8,
- 159, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(174, "MII_CRS", 6,
- 160, UNIPHIER_PIN_DRV_4_8,
- 160, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(175, "MII_COL", 6,
- 161, UNIPHIER_PIN_DRV_4_8,
- 161, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(176, "MDC", 6,
- 162, UNIPHIER_PIN_DRV_4_8,
- 162, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(177, "MDIO", 6,
- 163, UNIPHIER_PIN_DRV_4_8,
- 163, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(178, "MDIO_INTL", 6,
- 164, UNIPHIER_PIN_DRV_4_8,
- 164, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(179, "XETH_RST", 6,
- 165, UNIPHIER_PIN_DRV_4_8,
- 165, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(180, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
- 166, UNIPHIER_PIN_DRV_4_8,
- 166, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(181, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
- 167, UNIPHIER_PIN_DRV_4_8,
- 167, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(182, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
- 168, UNIPHIER_PIN_DRV_4_8,
- 168, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(183, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
- 169, UNIPHIER_PIN_DRV_4_8,
- 169, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(184, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
- 170, UNIPHIER_PIN_DRV_4_8,
- 170, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(185, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
- 171, UNIPHIER_PIN_DRV_4_8,
- 171, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(186, "USB2ID", UNIPHIER_PIN_IECTRL_NONE,
- 172, UNIPHIER_PIN_DRV_4_8,
- 172, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(187, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE,
- 173, UNIPHIER_PIN_DRV_4_8,
- 173, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(188, "USB3OD", UNIPHIER_PIN_IECTRL_NONE,
- 174, UNIPHIER_PIN_DRV_4_8,
- 174, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(189, "LINKCLK", UNIPHIER_PIN_IECTRL_NONE,
- 175, UNIPHIER_PIN_DRV_4_8,
- 175, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(190, "LINKREQ", UNIPHIER_PIN_IECTRL_NONE,
- 176, UNIPHIER_PIN_DRV_4_8,
- 176, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(191, "LINKCTL0", UNIPHIER_PIN_IECTRL_NONE,
- 177, UNIPHIER_PIN_DRV_4_8,
- 177, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(192, "LINKCTL1", UNIPHIER_PIN_IECTRL_NONE,
- 178, UNIPHIER_PIN_DRV_4_8,
- 178, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(193, "LINKDT0", UNIPHIER_PIN_IECTRL_NONE,
- 179, UNIPHIER_PIN_DRV_4_8,
- 179, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(194, "LINKDT1", UNIPHIER_PIN_IECTRL_NONE,
- 180, UNIPHIER_PIN_DRV_4_8,
- 180, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(195, "LINKDT2", UNIPHIER_PIN_IECTRL_NONE,
- 181, UNIPHIER_PIN_DRV_4_8,
- 181, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(196, "LINKDT3", UNIPHIER_PIN_IECTRL_NONE,
- 182, UNIPHIER_PIN_DRV_4_8,
- 182, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(197, "LINKDT4", UNIPHIER_PIN_IECTRL_NONE,
- 183, UNIPHIER_PIN_DRV_4_8,
- 183, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(198, "LINKDT5", UNIPHIER_PIN_IECTRL_NONE,
- 184, UNIPHIER_PIN_DRV_4_8,
- 184, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(199, "LINKDT6", UNIPHIER_PIN_IECTRL_NONE,
- 185, UNIPHIER_PIN_DRV_4_8,
- 185, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(200, "LINKDT7", UNIPHIER_PIN_IECTRL_NONE,
- 186, UNIPHIER_PIN_DRV_4_8,
- 186, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(201, "CKDVO", UNIPHIER_PIN_IECTRL_NONE,
- 187, UNIPHIER_PIN_DRV_4_8,
- 187, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(202, "PHY_PD", UNIPHIER_PIN_IECTRL_NONE,
- 188, UNIPHIER_PIN_DRV_4_8,
- 188, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(203, "X1394_RST", UNIPHIER_PIN_IECTRL_NONE,
- 189, UNIPHIER_PIN_DRV_4_8,
- 189, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(204, "VOUT_MUTE_L", UNIPHIER_PIN_IECTRL_NONE,
- 190, UNIPHIER_PIN_DRV_4_8,
- 190, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(205, "CLK54O", UNIPHIER_PIN_IECTRL_NONE,
- 191, UNIPHIER_PIN_DRV_4_8,
- 191, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(206, "CLK54I", UNIPHIER_PIN_IECTRL_NONE,
- 192, UNIPHIER_PIN_DRV_NONE,
- 192, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(207, "YIN0", UNIPHIER_PIN_IECTRL_NONE,
- 193, UNIPHIER_PIN_DRV_4_8,
- 193, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(208, "YIN1", UNIPHIER_PIN_IECTRL_NONE,
- 194, UNIPHIER_PIN_DRV_4_8,
- 194, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(209, "YIN2", UNIPHIER_PIN_IECTRL_NONE,
- 195, UNIPHIER_PIN_DRV_4_8,
- 195, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(210, "YIN3", UNIPHIER_PIN_IECTRL_NONE,
- 196, UNIPHIER_PIN_DRV_4_8,
- 196, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(211, "YIN4", UNIPHIER_PIN_IECTRL_NONE,
- 197, UNIPHIER_PIN_DRV_4_8,
- 197, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(212, "YIN5", UNIPHIER_PIN_IECTRL_NONE,
- 198, UNIPHIER_PIN_DRV_4_8,
- 198, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(213, "CIN0", UNIPHIER_PIN_IECTRL_NONE,
- 199, UNIPHIER_PIN_DRV_4_8,
- 199, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(214, "CIN1", UNIPHIER_PIN_IECTRL_NONE,
- 200, UNIPHIER_PIN_DRV_4_8,
- 200, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(215, "CIN2", UNIPHIER_PIN_IECTRL_NONE,
- 201, UNIPHIER_PIN_DRV_4_8,
- 201, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(216, "CIN3", UNIPHIER_PIN_IECTRL_NONE,
- 202, UNIPHIER_PIN_DRV_4_8,
- 202, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(217, "CIN4", UNIPHIER_PIN_IECTRL_NONE,
- 203, UNIPHIER_PIN_DRV_4_8,
- 203, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(218, "CIN5", UNIPHIER_PIN_IECTRL_NONE,
- 204, UNIPHIER_PIN_DRV_4_8,
- 204, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(219, "GCP", UNIPHIER_PIN_IECTRL_NONE,
- 205, UNIPHIER_PIN_DRV_4_8,
- 205, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(220, "ADFLG", UNIPHIER_PIN_IECTRL_NONE,
- 206, UNIPHIER_PIN_DRV_4_8,
- 206, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(221, "CK27AIOF", UNIPHIER_PIN_IECTRL_NONE,
- 207, UNIPHIER_PIN_DRV_4_8,
- 207, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(222, "DACOUT", UNIPHIER_PIN_IECTRL_NONE,
- 208, UNIPHIER_PIN_DRV_4_8,
- 208, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(223, "DAFLG", UNIPHIER_PIN_IECTRL_NONE,
- 209, UNIPHIER_PIN_DRV_4_8,
- 209, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(224, "VBIH", UNIPHIER_PIN_IECTRL_NONE,
- 210, UNIPHIER_PIN_DRV_4_8,
- 210, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(225, "VBIL", UNIPHIER_PIN_IECTRL_NONE,
- 211, UNIPHIER_PIN_DRV_4_8,
- 211, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(226, "XSUB_RST", UNIPHIER_PIN_IECTRL_NONE,
- 212, UNIPHIER_PIN_DRV_4_8,
- 212, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(227, "XADC_PD", UNIPHIER_PIN_IECTRL_NONE,
- 213, UNIPHIER_PIN_DRV_4_8,
- 213, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(228, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE,
- 214, UNIPHIER_PIN_DRV_4_8,
- 214, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(229, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE,
- 215, UNIPHIER_PIN_DRV_4_8,
- 215, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(230, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE,
- 216, UNIPHIER_PIN_DRV_4_8,
- 216, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(231, "AI1DMIX", UNIPHIER_PIN_IECTRL_NONE,
- 217, UNIPHIER_PIN_DRV_4_8,
- 217, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(232, "CK27HD", UNIPHIER_PIN_IECTRL_NONE,
- 218, UNIPHIER_PIN_DRV_4_8,
- 218, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(233, "XHD_RST", UNIPHIER_PIN_IECTRL_NONE,
- 219, UNIPHIER_PIN_DRV_4_8,
- 219, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(234, "INTHD", UNIPHIER_PIN_IECTRL_NONE,
- 220, UNIPHIER_PIN_DRV_4_8,
- 220, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(235, "VO1HDCK", UNIPHIER_PIN_IECTRL_NONE,
- 221, UNIPHIER_PIN_DRV_4_8,
- 221, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(236, "VO1HSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 222, UNIPHIER_PIN_DRV_4_8,
- 222, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(237, "VO1VSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 223, UNIPHIER_PIN_DRV_4_8,
- 223, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(238, "VO1DE", UNIPHIER_PIN_IECTRL_NONE,
- 224, UNIPHIER_PIN_DRV_4_8,
- 224, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(239, "VO1Y0", UNIPHIER_PIN_IECTRL_NONE,
- 225, UNIPHIER_PIN_DRV_4_8,
- 225, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(240, "VO1Y1", UNIPHIER_PIN_IECTRL_NONE,
- 226, UNIPHIER_PIN_DRV_4_8,
- 226, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(241, "VO1Y2", UNIPHIER_PIN_IECTRL_NONE,
- 227, UNIPHIER_PIN_DRV_4_8,
- 227, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(242, "VO1Y3", UNIPHIER_PIN_IECTRL_NONE,
- 228, UNIPHIER_PIN_DRV_4_8,
- 228, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(243, "VO1Y4", UNIPHIER_PIN_IECTRL_NONE,
- 229, UNIPHIER_PIN_DRV_4_8,
- 229, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(244, "VO1Y5", UNIPHIER_PIN_IECTRL_NONE,
- 230, UNIPHIER_PIN_DRV_4_8,
- 230, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(245, "VO1Y6", UNIPHIER_PIN_IECTRL_NONE,
- 231, UNIPHIER_PIN_DRV_4_8,
- 231, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(246, "VO1Y7", UNIPHIER_PIN_IECTRL_NONE,
- 232, UNIPHIER_PIN_DRV_4_8,
- 232, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(247, "VO1Y8", UNIPHIER_PIN_IECTRL_NONE,
- 233, UNIPHIER_PIN_DRV_4_8,
- 233, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(248, "VO1Y9", UNIPHIER_PIN_IECTRL_NONE,
- 234, UNIPHIER_PIN_DRV_4_8,
- 234, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(249, "VO1Y10", UNIPHIER_PIN_IECTRL_NONE,
- 235, UNIPHIER_PIN_DRV_4_8,
- 235, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(250, "VO1Y11", UNIPHIER_PIN_IECTRL_NONE,
- 236, UNIPHIER_PIN_DRV_4_8,
- 236, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(251, "VO1CB0", UNIPHIER_PIN_IECTRL_NONE,
- 237, UNIPHIER_PIN_DRV_4_8,
- 237, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(252, "VO1CB1", UNIPHIER_PIN_IECTRL_NONE,
- 238, UNIPHIER_PIN_DRV_4_8,
- 238, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(253, "VO1CB2", UNIPHIER_PIN_IECTRL_NONE,
- 239, UNIPHIER_PIN_DRV_4_8,
- 239, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(254, "VO1CB3", UNIPHIER_PIN_IECTRL_NONE,
- 240, UNIPHIER_PIN_DRV_4_8,
- 240, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(255, "VO1CB4", UNIPHIER_PIN_IECTRL_NONE,
- 241, UNIPHIER_PIN_DRV_4_8,
- 241, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(256, "VO1CB5", UNIPHIER_PIN_IECTRL_NONE,
- 242, UNIPHIER_PIN_DRV_4_8,
- 242, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(257, "VO1CB6", UNIPHIER_PIN_IECTRL_NONE,
- 243, UNIPHIER_PIN_DRV_4_8,
- 243, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(258, "VO1CB7", UNIPHIER_PIN_IECTRL_NONE,
- 244, UNIPHIER_PIN_DRV_4_8,
- 244, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(259, "VO1CB8", UNIPHIER_PIN_IECTRL_NONE,
- 245, UNIPHIER_PIN_DRV_4_8,
- 245, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(260, "VO1CB9", UNIPHIER_PIN_IECTRL_NONE,
- 246, UNIPHIER_PIN_DRV_4_8,
- 246, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(261, "VO1CB10", UNIPHIER_PIN_IECTRL_NONE,
- 247, UNIPHIER_PIN_DRV_4_8,
- 247, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(262, "VO1CB11", UNIPHIER_PIN_IECTRL_NONE,
- 248, UNIPHIER_PIN_DRV_4_8,
- 248, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(263, "VO1CR0", UNIPHIER_PIN_IECTRL_NONE,
- 249, UNIPHIER_PIN_DRV_4_8,
- 249, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(264, "VO1CR1", UNIPHIER_PIN_IECTRL_NONE,
- 250, UNIPHIER_PIN_DRV_4_8,
- 250, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(265, "VO1CR2", UNIPHIER_PIN_IECTRL_NONE,
- 251, UNIPHIER_PIN_DRV_4_8,
- 251, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(266, "VO1CR3", UNIPHIER_PIN_IECTRL_NONE,
- 252, UNIPHIER_PIN_DRV_4_8,
- 252, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(267, "VO1CR4", UNIPHIER_PIN_IECTRL_NONE,
- 253, UNIPHIER_PIN_DRV_4_8,
- 253, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(268, "VO1CR5", UNIPHIER_PIN_IECTRL_NONE,
- 254, UNIPHIER_PIN_DRV_4_8,
- 254, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(269, "VO1CR6", UNIPHIER_PIN_IECTRL_NONE,
- 255, UNIPHIER_PIN_DRV_4_8,
- 255, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(270, "VO1CR7", UNIPHIER_PIN_IECTRL_NONE,
- 256, UNIPHIER_PIN_DRV_4_8,
- 256, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(271, "VO1CR8", UNIPHIER_PIN_IECTRL_NONE,
- 257, UNIPHIER_PIN_DRV_4_8,
- 257, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(272, "VO1CR9", UNIPHIER_PIN_IECTRL_NONE,
- 258, UNIPHIER_PIN_DRV_4_8,
- 258, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(273, "VO1CR10", UNIPHIER_PIN_IECTRL_NONE,
- 259, UNIPHIER_PIN_DRV_4_8,
- 259, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(274, "VO1CR11", UNIPHIER_PIN_IECTRL_NONE,
- 260, UNIPHIER_PIN_DRV_4_8,
- 260, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(275, "VO1EX0", UNIPHIER_PIN_IECTRL_NONE,
- 261, UNIPHIER_PIN_DRV_4_8,
- 261, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(276, "VO1EX1", UNIPHIER_PIN_IECTRL_NONE,
- 262, UNIPHIER_PIN_DRV_4_8,
- 262, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(277, "VO1EX2", UNIPHIER_PIN_IECTRL_NONE,
- 263, UNIPHIER_PIN_DRV_4_8,
- 263, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(278, "VO1EX3", UNIPHIER_PIN_IECTRL_NONE,
- 264, UNIPHIER_PIN_DRV_4_8,
- 264, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(279, "VEXCKA", UNIPHIER_PIN_IECTRL_NONE,
- 265, UNIPHIER_PIN_DRV_4_8,
- 265, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(280, "VSEL0", UNIPHIER_PIN_IECTRL_NONE,
- 266, UNIPHIER_PIN_DRV_4_8,
- 266, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(281, "VSEL1", UNIPHIER_PIN_IECTRL_NONE,
- 267, UNIPHIER_PIN_DRV_4_8,
- 267, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(282, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE,
- 268, UNIPHIER_PIN_DRV_4_8,
- 268, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(283, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE,
- 269, UNIPHIER_PIN_DRV_4_8,
- 269, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(284, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE,
- 270, UNIPHIER_PIN_DRV_4_8,
- 270, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(285, "AO1D0", UNIPHIER_PIN_IECTRL_NONE,
- 271, UNIPHIER_PIN_DRV_4_8,
- 271, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(286, "AO1D1", UNIPHIER_PIN_IECTRL_NONE,
- 272, UNIPHIER_PIN_DRV_4_8,
- 272, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(287, "AO1D2", UNIPHIER_PIN_IECTRL_NONE,
- 273, UNIPHIER_PIN_DRV_4_8,
- 273, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(288, "AO1D3", UNIPHIER_PIN_IECTRL_NONE,
- 274, UNIPHIER_PIN_DRV_4_8,
- 274, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(289, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE,
- 275, UNIPHIER_PIN_DRV_4_8,
- 275, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(290, "XDAC_PD", UNIPHIER_PIN_IECTRL_NONE,
- 276, UNIPHIER_PIN_DRV_4_8,
- 276, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(291, "EX_A_MUTE", UNIPHIER_PIN_IECTRL_NONE,
- 277, UNIPHIER_PIN_DRV_4_8,
- 277, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(292, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
- 278, UNIPHIER_PIN_DRV_4_8,
- 278, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(293, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
- 279, UNIPHIER_PIN_DRV_4_8,
- 279, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(294, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
- 280, UNIPHIER_PIN_DRV_4_8,
- 280, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(295, "AO2DMIX", UNIPHIER_PIN_IECTRL_NONE,
- 281, UNIPHIER_PIN_DRV_4_8,
- 281, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(296, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE,
- 282, UNIPHIER_PIN_DRV_4_8,
- 282, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(297, "HTHPD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(298, "HTSCL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(299, "HTSDA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(300, "PORT00", UNIPHIER_PIN_IECTRL_NONE,
- 284, UNIPHIER_PIN_DRV_4_8,
- 284, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(301, "PORT01", UNIPHIER_PIN_IECTRL_NONE,
- 285, UNIPHIER_PIN_DRV_4_8,
- 285, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(302, "PORT02", UNIPHIER_PIN_IECTRL_NONE,
- 286, UNIPHIER_PIN_DRV_4_8,
- 286, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(303, "PORT03", UNIPHIER_PIN_IECTRL_NONE,
- 287, UNIPHIER_PIN_DRV_4_8,
- 287, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(304, "PORT04", UNIPHIER_PIN_IECTRL_NONE,
- 288, UNIPHIER_PIN_DRV_4_8,
- 288, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(305, "PORT05", UNIPHIER_PIN_IECTRL_NONE,
- 289, UNIPHIER_PIN_DRV_4_8,
- 289, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(306, "PORT06", UNIPHIER_PIN_IECTRL_NONE,
- 290, UNIPHIER_PIN_DRV_4_8,
- 290, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(307, "PORT07", UNIPHIER_PIN_IECTRL_NONE,
- 291, UNIPHIER_PIN_DRV_4_8,
- 291, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(308, "PORT10", UNIPHIER_PIN_IECTRL_NONE,
- 292, UNIPHIER_PIN_DRV_4_8,
- 292, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(309, "PORT11", UNIPHIER_PIN_IECTRL_NONE,
- 293, UNIPHIER_PIN_DRV_4_8,
- 293, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(310, "PORT12", UNIPHIER_PIN_IECTRL_NONE,
- 294, UNIPHIER_PIN_DRV_4_8,
- 294, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(311, "PORT13", UNIPHIER_PIN_IECTRL_NONE,
- 295, UNIPHIER_PIN_DRV_4_8,
- 295, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(312, "PORT14", UNIPHIER_PIN_IECTRL_NONE,
- 296, UNIPHIER_PIN_DRV_4_8,
- 296, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(313, "PORT15", UNIPHIER_PIN_IECTRL_NONE,
- 297, UNIPHIER_PIN_DRV_4_8,
- 297, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(314, "PORT16", UNIPHIER_PIN_IECTRL_NONE,
- 298, UNIPHIER_PIN_DRV_4_8,
- 298, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(315, "PORT17", UNIPHIER_PIN_IECTRL_NONE,
- 299, UNIPHIER_PIN_DRV_4_8,
- 299, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(316, "PORT20", UNIPHIER_PIN_IECTRL_NONE,
- 300, UNIPHIER_PIN_DRV_4_8,
- 300, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(317, "PORT21", UNIPHIER_PIN_IECTRL_NONE,
- 301, UNIPHIER_PIN_DRV_4_8,
- 301, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(318, "PORT22", UNIPHIER_PIN_IECTRL_NONE,
- 302, UNIPHIER_PIN_DRV_4_8,
- 302, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(319, "SD1DAT0", UNIPHIER_PIN_IECTRL_NONE,
- 303, UNIPHIER_PIN_DRV_4_8,
- 303, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(320, "SD1DAT1", UNIPHIER_PIN_IECTRL_NONE,
- 304, UNIPHIER_PIN_DRV_4_8,
- 304, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(321, "SD1DAT2", UNIPHIER_PIN_IECTRL_NONE,
- 305, UNIPHIER_PIN_DRV_4_8,
- 305, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(322, "SD1DAT3", UNIPHIER_PIN_IECTRL_NONE,
- 306, UNIPHIER_PIN_DRV_4_8,
- 306, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(323, "SD1CMD", UNIPHIER_PIN_IECTRL_NONE,
- 307, UNIPHIER_PIN_DRV_4_8,
- 307, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(324, "SD1CLK", UNIPHIER_PIN_IECTRL_NONE,
- 308, UNIPHIER_PIN_DRV_4_8,
- 308, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(325, "SD1CD", UNIPHIER_PIN_IECTRL_NONE,
- 309, UNIPHIER_PIN_DRV_4_8,
- 309, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(326, "SD1WP", UNIPHIER_PIN_IECTRL_NONE,
- 310, UNIPHIER_PIN_DRV_4_8,
- 310, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(327, "SD1VTCG", UNIPHIER_PIN_IECTRL_NONE,
- 311, UNIPHIER_PIN_DRV_4_8,
- 311, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(328, "DMDISO", UNIPHIER_PIN_IECTRL_NONE,
- 312, UNIPHIER_PIN_DRV_NONE,
- 312, UNIPHIER_PIN_PULL_DOWN),
-};
-
-static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53};
-static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
-static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
-static const unsigned i2c0_pins[] = {142, 143};
-static const unsigned i2c0_muxvals[] = {0, 0};
-static const unsigned i2c1_pins[] = {144, 145};
-static const unsigned i2c1_muxvals[] = {0, 0};
-static const unsigned i2c2_pins[] = {146, 147};
-static const unsigned i2c2_muxvals[] = {0, 0};
-static const unsigned i2c3_pins[] = {148, 149};
-static const unsigned i2c3_muxvals[] = {0, 0};
-static const unsigned i2c6_pins[] = {308, 309};
-static const unsigned i2c6_muxvals[] = {6, 6};
-static const unsigned nand_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
- 50, 51, 52, 53, 54};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
-static const unsigned nand_cs1_pins[] = {131, 132};
-static const unsigned nand_cs1_muxvals[] = {1, 1};
-static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 158};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
-static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326,
- 327};
-static const unsigned sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
-static const unsigned uart0_pins[] = {127, 128};
-static const unsigned uart0_muxvals[] = {0, 0};
-static const unsigned uart1_pins[] = {129, 130};
-static const unsigned uart1_muxvals[] = {0, 0};
-static const unsigned uart2_pins[] = {131, 132};
-static const unsigned uart2_muxvals[] = {0, 0};
-static const unsigned uart3_pins[] = {88, 89};
-static const unsigned uart3_muxvals[] = {2, 2};
-static const unsigned usb0_pins[] = {180, 181};
-static const unsigned usb0_muxvals[] = {0, 0};
-static const unsigned usb1_pins[] = {182, 183};
-static const unsigned usb1_muxvals[] = {0, 0};
-static const unsigned usb2_pins[] = {184, 185};
-static const unsigned usb2_muxvals[] = {0, 0};
-static const unsigned usb3_pins[] = {186, 187};
-static const unsigned usb3_muxvals[] = {0, 0};
-static const unsigned port_range0_pins[] = {
- 300, 301, 302, 303, 304, 305, 306, 307, /* PORT0x */
- 308, 309, 310, 311, 312, 313, 314, 315, /* PORT1x */
- 316, 317, 318, 16, 17, 18, 19, 20, /* PORT2x */
- 21, 22, 23, 4, 93, 94, 95, 63, /* PORT3x */
- 123, 122, 124, 125, 126, 141, 202, 203, /* PORT4x */
- 204, 226, 227, 290, 291, 233, 280, 281, /* PORT5x */
- 8, 7, 10, 29, 30, 48, 49, 50, /* PORT6x */
- 40, 41, 42, 43, 44, 45, 46, 47, /* PORT7x */
- 54, 51, 52, 53, 127, 128, 129, 130, /* PORT8x */
- 131, 132, 57, 60, 134, 133, 135, 136, /* PORT9x */
- 138, 137, 140, 139, 64, 65, 66, 67, /* PORT10x */
- 107, 106, 105, 104, 113, 112, 111, 110, /* PORT11x */
- 68, 69, 70, 71, 72, 73, 74, 75, /* PORT12x */
- 76, 77, 78, 79, 80, 81, 82, 83, /* PORT13x */
- 84, 85, 86, 87, 88, 89, 90, 91, /* PORT14x */
-};
-static const unsigned port_range0_muxvals[] = {
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT0x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT1x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT2x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT3x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT4x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT5x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT6x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT7x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT8x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT9x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT10x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT11x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT12x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT13x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT14x */
-};
-static const unsigned port_range1_pins[] = {
- 13, 14, 15, /* PORT175-177 */
- 157, 158, 156, 154, 150, 151, 152, 153, /* PORT18x */
- 326, 327, 325, 323, 319, 320, 321, 322, /* PORT19x */
- 160, 161, 162, 163, 164, 165, 166, 167, /* PORT20x */
- 168, 169, 170, 171, 172, 173, 174, 175, /* PORT21x */
- 180, 181, 182, 183, 184, 185, 187, 188, /* PORT22x */
- 193, 194, 195, 196, 197, 198, 199, 200, /* PORT23x */
- 191, 192, 215, 216, 217, 218, 219, 220, /* PORT24x */
- 222, 223, 224, 225, 228, 229, 230, 231, /* PORT25x */
- 282, 283, 284, 285, 286, 287, 288, 289, /* PORT26x */
- 292, 293, 294, 295, 296, 236, 237, 238, /* PORT27x */
- 275, 276, 277, 278, 239, 240, 249, 250, /* PORT28x */
- 251, 252, 261, 262, 263, 264, 273, 274, /* PORT29x */
- 31, 32, 33, 34, 35, 36, 37, 38, /* PORT30x */
-};
-static const unsigned port_range1_muxvals[] = {
- 7, 7, 7, /* PORT175-177 */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT18x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT19x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT20x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT21x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT22x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT23x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT24x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT25x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT26x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT27x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT28x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT29x */
- 7, 7, 7, 7, 7, 7, 7, 7, /* PORT30x */
-};
-static const unsigned xirq_pins[] = {
- 11, 9, 12, 96, 97, 98, 108, 114, /* XIRQ0-7 */
- 234, 186, 99, 100, 101, 102, 184, 301, /* XIRQ8-15 */
- 302, 303, 304, 305, 306, /* XIRQ16-20 */
-};
-static const unsigned xirq_muxvals[] = {
- 7, 7, 7, 7, 7, 7, 7, 7, /* XIRQ0-7 */
- 7, 7, 7, 7, 7, 7, 2, 2, /* XIRQ8-15 */
- 2, 2, 2, 2, 2, /* XIRQ16-20 */
-};
-static const unsigned xirq_alternatives_pins[] = {
- 184, 310, 316,
-};
-static const unsigned xirq_alternatives_muxvals[] = {
- 2, 2, 2,
-};
-
-static const struct uniphier_pinctrl_group ph1_pro4_groups[] = {
- UNIPHIER_PINCTRL_GROUP(emmc),
- UNIPHIER_PINCTRL_GROUP(emmc_dat8),
- UNIPHIER_PINCTRL_GROUP(i2c0),
- UNIPHIER_PINCTRL_GROUP(i2c1),
- UNIPHIER_PINCTRL_GROUP(i2c2),
- UNIPHIER_PINCTRL_GROUP(i2c3),
- UNIPHIER_PINCTRL_GROUP(i2c6),
- UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
- UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(sd1),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart3),
- UNIPHIER_PINCTRL_GROUP(usb0),
- UNIPHIER_PINCTRL_GROUP(usb1),
- UNIPHIER_PINCTRL_GROUP(usb2),
- UNIPHIER_PINCTRL_GROUP(usb3),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 21),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 22),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 23),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 24),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 25),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 26),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 27),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 28),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 29),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 30),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 31),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 32),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 33),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 34),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 35),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 36),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 37),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 38),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 39),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 40),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 41),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 42),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 43),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 44),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 45),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 46),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 47),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 48),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 49),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 50),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 51),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 52),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 53),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 54),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 55),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 56),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 57),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 58),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 59),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 60),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 61),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 62),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 63),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 64),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 65),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 66),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 67),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 68),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 69),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 70),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 71),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 72),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 73),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 74),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 75),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 76),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 77),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 78),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 79),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 80),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 81),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 82),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 83),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 84),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 85),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 86),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 87),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 88),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 89),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 90),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port290, port_range1, 91),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port291, port_range1, 92),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port292, port_range1, 93),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port293, port_range1, 94),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port294, port_range1, 95),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port295, port_range1, 96),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port296, port_range1, 97),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port297, port_range1, 98),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port300, port_range1, 99),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port301, port_range1, 100),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port302, port_range1, 101),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port303, port_range1, 102),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port304, port_range1, 103),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port305, port_range1, 104),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port306, port_range1, 105),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port307, port_range1, 106),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14b, xirq_alternatives, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 2),
-};
-
-static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
-static const char * const i2c0_groups[] = {"i2c0"};
-static const char * const i2c1_groups[] = {"i2c1"};
-static const char * const i2c2_groups[] = {"i2c2"};
-static const char * const i2c3_groups[] = {"i2c3"};
-static const char * const i2c6_groups[] = {"i2c6"};
-static const char * const nand_groups[] = {"nand", "nand_cs1"};
-static const char * const sd_groups[] = {"sd"};
-static const char * const sd1_groups[] = {"sd1"};
-static const char * const uart0_groups[] = {"uart0"};
-static const char * const uart1_groups[] = {"uart1"};
-static const char * const uart2_groups[] = {"uart2"};
-static const char * const uart3_groups[] = {"uart3"};
-static const char * const usb0_groups[] = {"usb0"};
-static const char * const usb1_groups[] = {"usb1"};
-static const char * const usb2_groups[] = {"usb2"};
-static const char * const usb3_groups[] = {"usb3"};
-static const char * const port_groups[] = {
- "port00", "port01", "port02", "port03",
- "port04", "port05", "port06", "port07",
- "port10", "port11", "port12", "port13",
- "port14", "port15", "port16", "port17",
- "port20", "port21", "port22", "port23",
- "port24", "port25", "port26", "port27",
- "port30", "port31", "port32", "port33",
- "port34", "port35", "port36", "port37",
- "port40", "port41", "port42", "port43",
- "port44", "port45", "port46", "port47",
- "port50", "port51", "port52", "port53",
- "port54", "port55", "port56", "port57",
- "port60", "port61", "port62", "port63",
- "port64", "port65", "port66", "port67",
- "port70", "port71", "port72", "port73",
- "port74", "port75", "port76", "port77",
- "port80", "port81", "port82", "port83",
- "port84", "port85", "port86", "port87",
- "port90", "port91", "port92", "port93",
- "port94", "port95", "port96", "port97",
- "port100", "port101", "port102", "port103",
- "port104", "port105", "port106", "port107",
- "port110", "port111", "port112", "port113",
- "port114", "port115", "port116", "port117",
- "port120", "port121", "port122", "port123",
- "port124", "port125", "port126", "port127",
- "port130", "port131", "port132", "port133",
- "port134", "port135", "port136", "port137",
- "port140", "port141", "port142", "port143",
- "port144", "port145", "port146", "port147",
- /* port150-174 missing */
- /* none */ "port175", "port176", "port177",
- "port180", "port181", "port182", "port183",
- "port184", "port185", "port186", "port187",
- "port190", "port191", "port192", "port193",
- "port194", "port195", "port196", "port197",
- "port200", "port201", "port202", "port203",
- "port204", "port205", "port206", "port207",
- "port210", "port211", "port212", "port213",
- "port214", "port215", "port216", "port217",
- "port220", "port221", "port222", "port223",
- "port224", "port225", "port226", "port227",
- "port230", "port231", "port232", "port233",
- "port234", "port235", "port236", "port237",
- "port240", "port241", "port242", "port243",
- "port244", "port245", "port246", "port247",
- "port250", "port251", "port252", "port253",
- "port254", "port255", "port256", "port257",
- "port260", "port261", "port262", "port263",
- "port264", "port265", "port266", "port267",
- "port270", "port271", "port272", "port273",
- "port274", "port275", "port276", "port277",
- "port280", "port281", "port282", "port283",
- "port284", "port285", "port286", "port287",
- "port290", "port291", "port292", "port293",
- "port294", "port295", "port296", "port297",
- "port300", "port301", "port302", "port303",
- "port304", "port305", "port306", "port307",
-};
-static const char * const xirq_groups[] = {
- "xirq0", "xirq1", "xirq2", "xirq3",
- "xirq4", "xirq5", "xirq6", "xirq7",
- "xirq8", "xirq9", "xirq10", "xirq11",
- "xirq12", "xirq13", "xirq14", "xirq15",
- "xirq16", "xirq17", "xirq18", "xirq19",
- "xirq20",
- "xirq14b", "xirq17b", "xirq18b",
-};
-
-static const struct uniphier_pinmux_function ph1_pro4_functions[] = {
- UNIPHIER_PINMUX_FUNCTION(emmc),
- UNIPHIER_PINMUX_FUNCTION(i2c0),
- UNIPHIER_PINMUX_FUNCTION(i2c1),
- UNIPHIER_PINMUX_FUNCTION(i2c2),
- UNIPHIER_PINMUX_FUNCTION(i2c3),
- UNIPHIER_PINMUX_FUNCTION(i2c6),
- UNIPHIER_PINMUX_FUNCTION(nand),
- UNIPHIER_PINMUX_FUNCTION(sd),
- UNIPHIER_PINMUX_FUNCTION(sd1),
- UNIPHIER_PINMUX_FUNCTION(uart0),
- UNIPHIER_PINMUX_FUNCTION(uart1),
- UNIPHIER_PINMUX_FUNCTION(uart2),
- UNIPHIER_PINMUX_FUNCTION(uart3),
- UNIPHIER_PINMUX_FUNCTION(usb0),
- UNIPHIER_PINMUX_FUNCTION(usb1),
- UNIPHIER_PINMUX_FUNCTION(usb2),
- UNIPHIER_PINMUX_FUNCTION(usb3),
- UNIPHIER_PINMUX_FUNCTION(port),
- UNIPHIER_PINMUX_FUNCTION(xirq),
-};
-
-static struct uniphier_pinctrl_socdata ph1_pro4_pindata = {
- .groups = ph1_pro4_groups,
- .groups_count = ARRAY_SIZE(ph1_pro4_groups),
- .functions = ph1_pro4_functions,
- .functions_count = ARRAY_SIZE(ph1_pro4_functions),
- .mux_bits = 4,
- .reg_stride = 8,
- .load_pinctrl = true,
-};
-
-static struct pinctrl_desc ph1_pro4_pinctrl_desc = {
- .name = DRIVER_NAME,
- .pins = ph1_pro4_pins,
- .npins = ARRAY_SIZE(ph1_pro4_pins),
- .owner = THIS_MODULE,
-};
-
-static int ph1_pro4_pinctrl_probe(struct platform_device *pdev)
-{
- return uniphier_pinctrl_probe(pdev, &ph1_pro4_pinctrl_desc,
- &ph1_pro4_pindata);
-}
-
-static const struct of_device_id ph1_pro4_pinctrl_match[] = {
- { .compatible = "socionext,ph1-pro4-pinctrl" },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, ph1_pro4_pinctrl_match);
-
-static struct platform_driver ph1_pro4_pinctrl_driver = {
- .probe = ph1_pro4_pinctrl_probe,
- .remove = uniphier_pinctrl_remove,
- .driver = {
- .name = DRIVER_NAME,
- .of_match_table = ph1_pro4_pinctrl_match,
- },
-};
-module_platform_driver(ph1_pro4_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier PH1-Pro4 pinctrl driver");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program5 is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-
-#include "pinctrl-uniphier.h"
-
-#define DRIVER_NAME "ph1-pro5-pinctrl"
-
-static const struct pinctrl_pin_desc ph1_pro5_pins[] = {
- UNIPHIER_PINCTRL_PIN(0, "AEXCKA1", 0,
- 0, UNIPHIER_PIN_DRV_4_8,
- 0, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(1, "AEXCKA2", 0,
- 1, UNIPHIER_PIN_DRV_4_8,
- 1, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(2, "CK27EXI", 0,
- 2, UNIPHIER_PIN_DRV_4_8,
- 2, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(3, "CK54EXI", 0,
- 3, UNIPHIER_PIN_DRV_4_8,
- 3, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(4, "ED0", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_4_8,
- 4, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(5, "ED1", UNIPHIER_PIN_IECTRL_NONE,
- 5, UNIPHIER_PIN_DRV_4_8,
- 5, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(6, "ED2", UNIPHIER_PIN_IECTRL_NONE,
- 6, UNIPHIER_PIN_DRV_4_8,
- 6, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(7, "ED3", UNIPHIER_PIN_IECTRL_NONE,
- 7, UNIPHIER_PIN_DRV_4_8,
- 7, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(8, "ED4", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_4_8,
- 8, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(9, "ED5", UNIPHIER_PIN_IECTRL_NONE,
- 9, UNIPHIER_PIN_DRV_4_8,
- 9, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(10, "ED6", UNIPHIER_PIN_IECTRL_NONE,
- 10, UNIPHIER_PIN_DRV_4_8,
- 10, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(11, "ED7", UNIPHIER_PIN_IECTRL_NONE,
- 11, UNIPHIER_PIN_DRV_4_8,
- 11, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(12, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_4_8,
- 12, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(13, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
- 13, UNIPHIER_PIN_DRV_4_8,
- 13, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(14, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
- 14, UNIPHIER_PIN_DRV_4_8,
- 14, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(15, "ES0", UNIPHIER_PIN_IECTRL_NONE,
- 15, UNIPHIER_PIN_DRV_4_8,
- 15, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(16, "ES1", UNIPHIER_PIN_IECTRL_NONE,
- 16, UNIPHIER_PIN_DRV_4_8,
- 16, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(17, "ES2", UNIPHIER_PIN_IECTRL_NONE,
- 17, UNIPHIER_PIN_DRV_4_8,
- 17, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(18, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
- 18, UNIPHIER_PIN_DRV_4_8,
- 18, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(19, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
- 19, UNIPHIER_PIN_DRV_4_8,
- 19, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(20, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
- 20, UNIPHIER_PIN_DRV_4_8,
- 20, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(21, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
- 21, UNIPHIER_PIN_DRV_4_8,
- 21, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(22, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
- 22, UNIPHIER_PIN_DRV_4_8,
- 22, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(23, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
- 23, UNIPHIER_PIN_DRV_4_8,
- 23, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(24, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
- 24, UNIPHIER_PIN_DRV_4_8,
- 24, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(25, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE,
- 25, UNIPHIER_PIN_DRV_4_8,
- 25, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(26, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE,
- 26, UNIPHIER_PIN_DRV_4_8,
- 26, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(27, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE,
- 27, UNIPHIER_PIN_DRV_4_8,
- 27, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(28, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
- 28, UNIPHIER_PIN_DRV_4_8,
- 28, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(29, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
- 29, UNIPHIER_PIN_DRV_4_8,
- 29, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(30, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
- 30, UNIPHIER_PIN_DRV_4_8,
- 30, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(31, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
- 31, UNIPHIER_PIN_DRV_4_8,
- 31, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(32, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_4_8,
- 32, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(33, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
- 33, UNIPHIER_PIN_DRV_4_8,
- 33, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(34, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
- 34, UNIPHIER_PIN_DRV_4_8,
- 34, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(35, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
- 35, UNIPHIER_PIN_DRV_4_8,
- 35, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(36, "XERST", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_4_8,
- 36, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(37, "MMCCLK", UNIPHIER_PIN_IECTRL_NONE,
- 37, UNIPHIER_PIN_DRV_4_8,
- 37, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(38, "MMCCMD", UNIPHIER_PIN_IECTRL_NONE,
- 38, UNIPHIER_PIN_DRV_4_8,
- 38, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(39, "MMCDAT0", UNIPHIER_PIN_IECTRL_NONE,
- 39, UNIPHIER_PIN_DRV_4_8,
- 39, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(40, "MMCDAT1", UNIPHIER_PIN_IECTRL_NONE,
- 40, UNIPHIER_PIN_DRV_4_8,
- 40, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(41, "MMCDAT2", UNIPHIER_PIN_IECTRL_NONE,
- 41, UNIPHIER_PIN_DRV_4_8,
- 41, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(42, "MMCDAT3", UNIPHIER_PIN_IECTRL_NONE,
- 42, UNIPHIER_PIN_DRV_4_8,
- 42, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(43, "MMCDAT4", UNIPHIER_PIN_IECTRL_NONE,
- 43, UNIPHIER_PIN_DRV_4_8,
- 43, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(44, "MMCDAT5", UNIPHIER_PIN_IECTRL_NONE,
- 44, UNIPHIER_PIN_DRV_4_8,
- 44, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(45, "MMCDAT6", UNIPHIER_PIN_IECTRL_NONE,
- 45, UNIPHIER_PIN_DRV_4_8,
- 45, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(46, "MMCDAT7", UNIPHIER_PIN_IECTRL_NONE,
- 46, UNIPHIER_PIN_DRV_4_8,
- 46, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(47, "TXD0", 0,
- 47, UNIPHIER_PIN_DRV_4_8,
- 47, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(48, "RXD0", 0,
- 48, UNIPHIER_PIN_DRV_4_8,
- 48, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(49, "TXD1", 0,
- 49, UNIPHIER_PIN_DRV_4_8,
- 49, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(50, "RXD1", 0,
- 50, UNIPHIER_PIN_DRV_4_8,
- 50, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(51, "TXD2", UNIPHIER_PIN_IECTRL_NONE,
- 51, UNIPHIER_PIN_DRV_4_8,
- 51, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(52, "RXD2", UNIPHIER_PIN_IECTRL_NONE,
- 52, UNIPHIER_PIN_DRV_4_8,
- 52, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(53, "TXD3", 0,
- 53, UNIPHIER_PIN_DRV_4_8,
- 53, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(54, "RXD3", 0,
- 54, UNIPHIER_PIN_DRV_4_8,
- 54, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(55, "MS0CS0", 0,
- 55, UNIPHIER_PIN_DRV_4_8,
- 55, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(56, "MS0DO", 0,
- 56, UNIPHIER_PIN_DRV_4_8,
- 56, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(57, "MS0DI", 0,
- 57, UNIPHIER_PIN_DRV_4_8,
- 57, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(58, "MS0CLK", 0,
- 58, UNIPHIER_PIN_DRV_4_8,
- 58, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(59, "CSCLK", 0,
- 59, UNIPHIER_PIN_DRV_4_8,
- 59, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(60, "CSBPTM", 0,
- 60, UNIPHIER_PIN_DRV_4_8,
- 60, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(61, "CSBMTP", 0,
- 61, UNIPHIER_PIN_DRV_4_8,
- 61, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(62, "XCINTP", 0,
- 62, UNIPHIER_PIN_DRV_4_8,
- 62, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(63, "XCINTM", 0,
- 63, UNIPHIER_PIN_DRV_4_8,
- 63, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(64, "XCMPREQ", 0,
- 64, UNIPHIER_PIN_DRV_4_8,
- 64, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(65, "XSRST", 0,
- 65, UNIPHIER_PIN_DRV_4_8,
- 65, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(66, "LPST", UNIPHIER_PIN_IECTRL_NONE,
- 66, UNIPHIER_PIN_DRV_4_8,
- 66, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(67, "PWMA", 0,
- 67, UNIPHIER_PIN_DRV_4_8,
- 67, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(68, "XIRQ0", 0,
- 68, UNIPHIER_PIN_DRV_4_8,
- 68, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(69, "XIRQ1", 0,
- 69, UNIPHIER_PIN_DRV_4_8,
- 69, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(70, "XIRQ2", 0,
- 70, UNIPHIER_PIN_DRV_4_8,
- 70, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(71, "XIRQ3", 0,
- 71, UNIPHIER_PIN_DRV_4_8,
- 71, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(72, "XIRQ4", 0,
- 72, UNIPHIER_PIN_DRV_4_8,
- 72, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(73, "XIRQ5", 0,
- 73, UNIPHIER_PIN_DRV_4_8,
- 73, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(74, "XIRQ6", 0,
- 74, UNIPHIER_PIN_DRV_4_8,
- 74, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(75, "XIRQ7", 0,
- 75, UNIPHIER_PIN_DRV_4_8,
- 75, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(76, "XIRQ8", 0,
- 76, UNIPHIER_PIN_DRV_4_8,
- 76, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(77, "XIRQ9", 0,
- 77, UNIPHIER_PIN_DRV_4_8,
- 77, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(78, "XIRQ10", 0,
- 78, UNIPHIER_PIN_DRV_4_8,
- 78, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(79, "XIRQ11", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 79, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(80, "XIRQ12", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 80, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(81, "XIRQ13", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 81, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(82, "XIRQ14", 0,
- 82, UNIPHIER_PIN_DRV_4_8,
- 82, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(83, "XIRQ15", 0,
- 83, UNIPHIER_PIN_DRV_4_8,
- 83, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(84, "XIRQ16", 0,
- 84, UNIPHIER_PIN_DRV_4_8,
- 84, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(85, "XIRQ17", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 85, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(86, "XIRQ18", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 86, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(87, "XIRQ19", 0,
- 87, UNIPHIER_PIN_DRV_4_8,
- 87, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(88, "XIRQ20", 0,
- 88, UNIPHIER_PIN_DRV_4_8,
- 88, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(89, "PORT00", 0,
- 89, UNIPHIER_PIN_DRV_4_8,
- 89, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(90, "PORT01", 0,
- 90, UNIPHIER_PIN_DRV_4_8,
- 90, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(91, "PORT02", 0,
- 91, UNIPHIER_PIN_DRV_4_8,
- 91, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(92, "PORT03", 0,
- 92, UNIPHIER_PIN_DRV_4_8,
- 92, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(93, "PORT04", 0,
- 93, UNIPHIER_PIN_DRV_4_8,
- 93, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(94, "PORT05", 0,
- 94, UNIPHIER_PIN_DRV_4_8,
- 94, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(95, "PORT06", 0,
- 95, UNIPHIER_PIN_DRV_4_8,
- 95, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(96, "PORT07", 0,
- 96, UNIPHIER_PIN_DRV_4_8,
- 96, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(97, "PORT10", 0,
- 97, UNIPHIER_PIN_DRV_4_8,
- 97, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(98, "PORT11", 0,
- 98, UNIPHIER_PIN_DRV_4_8,
- 98, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(99, "PORT12", 0,
- 99, UNIPHIER_PIN_DRV_4_8,
- 99, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(100, "PORT13", 0,
- 100, UNIPHIER_PIN_DRV_4_8,
- 100, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(101, "PORT14", 0,
- 101, UNIPHIER_PIN_DRV_4_8,
- 101, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(102, "PORT15", 0,
- 102, UNIPHIER_PIN_DRV_4_8,
- 102, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(103, "PORT16", 0,
- 103, UNIPHIER_PIN_DRV_4_8,
- 103, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(104, "PORT17", 0,
- 104, UNIPHIER_PIN_DRV_4_8,
- 104, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(105, "T0HPD", 0,
- 105, UNIPHIER_PIN_DRV_4_8,
- 105, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(106, "T1HPD", 0,
- 106, UNIPHIER_PIN_DRV_4_8,
- 106, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(107, "R0HPD", 0,
- 107, UNIPHIER_PIN_DRV_4_8,
- 107, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(108, "R1HPD", 0,
- 108, UNIPHIER_PIN_DRV_4_8,
- 108, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(109, "XPERST", 0,
- 109, UNIPHIER_PIN_DRV_4_8,
- 109, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(110, "XPEWAKE", 0,
- 110, UNIPHIER_PIN_DRV_4_8,
- 110, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(111, "XPECLKRQ", 0,
- 111, UNIPHIER_PIN_DRV_4_8,
- 111, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(112, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 112, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(113, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 113, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(114, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 114, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(115, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 115, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(116, "SDA2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 116, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(117, "SCL2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 117, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(118, "SDA3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 118, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(119, "SCL3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 119, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(120, "SPISYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 120, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(121, "SPISCLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 121, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(122, "SPITXD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 122, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(123, "SPIRXD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 123, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(124, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 124, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(125, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 125, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(126, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 126, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(127, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 127, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(128, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 128, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(129, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 129, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(130, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 130, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(131, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 131, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(132, "SMTD0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 132, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(133, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 133, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(134, "SMTCLK0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 134, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(135, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 135, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(136, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 136, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(137, "SMTD1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 137, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(138, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 138, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(139, "SMTCLK1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 139, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(140, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 140, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(141, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 141, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(142, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 142, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(143, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 143, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(144, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 144, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(145, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 145, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(146, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 146, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(147, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 147, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(148, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 148, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(149, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 149, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(150, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 150, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(151, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 151, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(152, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 152, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(153, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 153, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(154, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 154, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(155, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 155, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(156, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 156, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(157, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 157, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(158, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 158, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(159, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 159, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(160, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 160, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(161, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 161, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(162, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 162, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(163, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 163, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(164, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 164, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(165, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 165, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(166, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 166, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(167, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 167, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(168, "CH7CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 168, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(169, "CH7PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 169, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(170, "CH7VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 170, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(171, "CH7DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 171, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(172, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 172, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(173, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 173, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(174, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 174, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(175, "AI1D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 175, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(176, "AI1D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 176, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(177, "AI1D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 177, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(178, "AI1D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 178, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(179, "AI2ADCCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 179, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(180, "AI2BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 180, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(181, "AI2LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 181, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(182, "AI2D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 182, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(183, "AI2D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 183, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(184, "AI2D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 184, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(185, "AI2D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 185, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(186, "AI3ADCCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 186, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(187, "AI3BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 187, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(188, "AI3LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 188, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(189, "AI3D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 189, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(190, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 190, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(191, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 191, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(192, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 192, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(193, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 193, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(194, "AO1D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 194, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(195, "AO1D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 195, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(196, "AO1D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 196, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(197, "AO1D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 197, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(198, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 198, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(199, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 199, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(200, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 200, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(201, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 201, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(202, "AO2D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 202, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(203, "AO2D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 203, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(204, "AO2D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 204, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(205, "AO2D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 205, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(206, "AO3DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 206, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(207, "AO3BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 207, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(208, "AO3LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 208, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(209, "AO3DMIX", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 209, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(210, "AO4DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 210, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(211, "AO4BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 211, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(212, "AO4LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 212, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(213, "AO4DMIX", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 213, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(214, "VI1CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 214, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(215, "VI1C0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 215, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(216, "VI1C1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 216, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(217, "VI1C2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 217, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(218, "VI1C3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 218, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(219, "VI1C4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 219, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(220, "VI1C5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 220, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(221, "VI1C6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 221, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(222, "VI1C7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 222, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(223, "VI1C8", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 223, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(224, "VI1C9", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 224, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(225, "VI1Y0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 225, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(226, "VI1Y1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 226, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(227, "VI1Y2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 227, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(228, "VI1Y3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 228, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(229, "VI1Y4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 229, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(230, "VI1Y5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 230, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(231, "VI1Y6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 231, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(232, "VI1Y7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 232, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(233, "VI1Y8", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 233, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(234, "VI1Y9", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 234, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(235, "VI1DE", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 235, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(236, "VI1HSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 236, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(237, "VI1VSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 237, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(238, "VO1CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 238, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(239, "VO1D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 239, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(240, "VO1D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 240, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(241, "VO1D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 241, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(242, "VO1D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 242, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(243, "VO1D4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 243, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(244, "VO1D5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 244, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(245, "VO1D6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 245, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(246, "VO1D7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 246, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(247, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 247, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(248, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 248, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(249, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 249, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(250, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
- 40, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(251, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
- 44, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(252, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
- 48, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(253, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
- 52, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(254, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
- 56, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(255, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
- 60, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
-};
-
-static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
-static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
-static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
-static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
-static const unsigned i2c0_pins[] = {112, 113};
-static const unsigned i2c0_muxvals[] = {0, 0};
-static const unsigned i2c1_pins[] = {114, 115};
-static const unsigned i2c1_muxvals[] = {0, 0};
-static const unsigned i2c2_pins[] = {116, 117};
-static const unsigned i2c2_muxvals[] = {0, 0};
-static const unsigned i2c3_pins[] = {118, 119};
-static const unsigned i2c3_muxvals[] = {0, 0};
-static const unsigned i2c5_pins[] = {87, 88};
-static const unsigned i2c5_muxvals[] = {2, 2};
-static const unsigned i2c5b_pins[] = {196, 197};
-static const unsigned i2c5b_muxvals[] = {2, 2};
-static const unsigned i2c5c_pins[] = {215, 216};
-static const unsigned i2c5c_muxvals[] = {2, 2};
-static const unsigned i2c6_pins[] = {101, 102};
-static const unsigned i2c6_muxvals[] = {2, 2};
-static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
- 31, 32, 33, 34, 35};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
-static const unsigned nand_cs1_pins[] = {26, 27};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
-static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
-static const unsigned uart0_pins[] = {47, 48};
-static const unsigned uart0_muxvals[] = {0, 0};
-static const unsigned uart0b_pins[] = {227, 228};
-static const unsigned uart0b_muxvals[] = {3, 3};
-static const unsigned uart1_pins[] = {49, 50};
-static const unsigned uart1_muxvals[] = {0, 0};
-static const unsigned uart2_pins[] = {51, 52};
-static const unsigned uart2_muxvals[] = {0, 0};
-static const unsigned uart3_pins[] = {53, 54};
-static const unsigned uart3_muxvals[] = {0, 0};
-static const unsigned usb0_pins[] = {124, 125};
-static const unsigned usb0_muxvals[] = {0, 0};
-static const unsigned usb1_pins[] = {126, 127};
-static const unsigned usb1_muxvals[] = {0, 0};
-static const unsigned usb2_pins[] = {128, 129};
-static const unsigned usb2_muxvals[] = {0, 0};
-static const unsigned port_range0_pins[] = {
- 89, 90, 91, 92, 93, 94, 95, 96, /* PORT0x */
- 97, 98, 99, 100, 101, 102, 103, 104, /* PORT1x */
- 251, 252, 253, 254, 255, 247, 248, 249, /* PORT2x */
- 39, 40, 41, 42, 43, 44, 45, 46, /* PORT3x */
- 156, 157, 158, 159, 160, 161, 162, 163, /* PORT4x */
- 164, 165, 166, 167, 168, 169, 170, 171, /* PORT5x */
- 190, 191, 192, 193, 194, 195, 196, 197, /* PORT6x */
- 198, 199, 200, 201, 202, 203, 204, 205, /* PORT7x */
- 120, 121, 122, 123, 55, 56, 57, 58, /* PORT8x */
- 124, 125, 126, 127, 49, 50, 53, 54, /* PORT9x */
- 148, 149, 150, 151, 152, 153, 154, 155, /* PORT10x */
- 133, 134, 131, 130, 138, 139, 136, 135, /* PORT11x */
- 28, 29, 30, 31, 32, 33, 34, 35, /* PORT12x */
- 179, 180, 181, 182, 186, 187, 188, 189, /* PORT13x */
- 4, 5, 6, 7, 8, 9, 10, 11, /* PORT14x */
-};
-static const unsigned port_range0_muxvals[] = {
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
-};
-static const unsigned port_range1_pins[] = {
- 109, 110, 111, /* PORT175-177 */
- 206, 207, 208, 209, 210, 211, 212, 213, /* PORT18x */
- 12, 13, 14, 15, 16, 17, 107, 108, /* PORT19x */
- 140, 141, 142, 143, 144, 145, 146, 147, /* PORT20x */
- 59, 60, 61, 62, 63, 64, 65, 66, /* PORT21x */
- 214, 215, 216, 217, 218, 219, 220, 221, /* PORT22x */
- 222, 223, 224, 225, 226, 227, 228, 229, /* PORT23x */
- 19, 20, 21, 22, 23, 24, 25, 26, /* PORT24x */
- 230, 231, 232, 233, 234, 235, 236, 237, /* PORT25x */
- 239, 240, 241, 242, 243, 244, 245, 246, /* PORT26x */
- 172, 173, 174, 175, 176, 177, 178, 129, /* PORT27x */
- 0, 1, 2, 67, 85, 86, 87, 88, /* PORT28x */
- 105, 106, 18, 27, 36, 128, 132, 137, /* PORT29x */
- 183, 184, 185, 84, 47, 48, 51, 52, /* PORT30x */
-};
-static const unsigned port_range1_muxvals[] = {
- 15, 15, 15, /* PORT175-177 */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT29x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT30x */
-};
-static const unsigned xirq_pins[] = {
- 68, 69, 70, 71, 72, 73, 74, 75, /* XIRQ0-7 */
- 76, 77, 78, 79, 80, 81, 82, 83, /* XIRQ8-15 */
- 84, 85, 86, 87, 88, /* XIRQ16-20 */
-};
-static const unsigned xirq_muxvals[] = {
- 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
- 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */
- 14, 14, 14, 14, 14, /* XIRQ16-20 */
-};
-static const unsigned xirq_alternatives_pins[] = {
- 91, 92, 239, 144, 240, 156, 241, 106, 128,
-};
-static const unsigned xirq_alternatives_muxvals[] = {
- 14, 14, 14, 14, 14, 14, 14, 14, 14,
-};
-
-static const struct uniphier_pinctrl_group ph1_pro5_groups[] = {
- UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
- UNIPHIER_PINCTRL_GROUP(emmc),
- UNIPHIER_PINCTRL_GROUP(emmc_dat8),
- UNIPHIER_PINCTRL_GROUP(i2c0),
- UNIPHIER_PINCTRL_GROUP(i2c1),
- UNIPHIER_PINCTRL_GROUP(i2c2),
- UNIPHIER_PINCTRL_GROUP(i2c3),
- UNIPHIER_PINCTRL_GROUP(i2c5),
- UNIPHIER_PINCTRL_GROUP(i2c5b),
- UNIPHIER_PINCTRL_GROUP(i2c5c),
- UNIPHIER_PINCTRL_GROUP(i2c6),
- UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart0b),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart3),
- UNIPHIER_PINCTRL_GROUP(usb0),
- UNIPHIER_PINCTRL_GROUP(usb1),
- UNIPHIER_PINCTRL_GROUP(usb2),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 21),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 22),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 23),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 24),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 25),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 26),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 27),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 28),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 29),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 30),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 31),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 32),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 33),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 34),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 35),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 36),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 37),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 38),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 39),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 40),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 41),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 42),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 43),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 44),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 45),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 46),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 47),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 48),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 49),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 50),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 51),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 52),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 53),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 54),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 55),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 56),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 57),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 58),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 59),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 60),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 61),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 62),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 63),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 64),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 65),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 66),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 67),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 68),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 69),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 70),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 71),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 72),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 73),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 74),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 75),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 76),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 77),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 78),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 79),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 80),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 81),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 82),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 83),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 84),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 85),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 86),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 87),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 88),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 89),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 90),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port290, port_range1, 91),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port291, port_range1, 92),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port292, port_range1, 93),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port293, port_range1, 94),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port294, port_range1, 95),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port295, port_range1, 96),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port296, port_range1, 97),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port297, port_range1, 98),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port300, port_range1, 99),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port301, port_range1, 100),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port302, port_range1, 101),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port303, port_range1, 102),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port304, port_range1, 103),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port305, port_range1, 104),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port306, port_range1, 105),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port307, port_range1, 106),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3b, xirq_alternatives, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4b, xirq_alternatives, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16b, xirq_alternatives, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17c, xirq_alternatives, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18c, xirq_alternatives, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19b, xirq_alternatives, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20b, xirq_alternatives, 8),
-};
-
-static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
-static const char * const i2c0_groups[] = {"i2c0"};
-static const char * const i2c1_groups[] = {"i2c1"};
-static const char * const i2c2_groups[] = {"i2c2"};
-static const char * const i2c3_groups[] = {"i2c3"};
-static const char * const i2c5_groups[] = {"i2c5", "i2c5b", "i2c5c"};
-static const char * const i2c6_groups[] = {"i2c6"};
-static const char * const nand_groups[] = {"nand", "nand_cs1"};
-static const char * const sd_groups[] = {"sd"};
-static const char * const uart0_groups[] = {"uart0", "uart0b"};
-static const char * const uart1_groups[] = {"uart1"};
-static const char * const uart2_groups[] = {"uart2"};
-static const char * const uart3_groups[] = {"uart3"};
-static const char * const usb0_groups[] = {"usb0"};
-static const char * const usb1_groups[] = {"usb1"};
-static const char * const usb2_groups[] = {"usb2"};
-static const char * const port_groups[] = {
- "port00", "port01", "port02", "port03",
- "port04", "port05", "port06", "port07",
- "port10", "port11", "port12", "port13",
- "port14", "port15", "port16", "port17",
- "port20", "port21", "port22", "port23",
- "port24", "port25", "port26", "port27",
- "port30", "port31", "port32", "port33",
- "port34", "port35", "port36", "port37",
- "port40", "port41", "port42", "port43",
- "port44", "port45", "port46", "port47",
- "port50", "port51", "port52", "port53",
- "port54", "port55", "port56", "port57",
- "port60", "port61", "port62", "port63",
- "port64", "port65", "port66", "port67",
- "port70", "port71", "port72", "port73",
- "port74", "port75", "port76", "port77",
- "port80", "port81", "port82", "port83",
- "port84", "port85", "port86", "port87",
- "port90", "port91", "port92", "port93",
- "port94", "port95", "port96", "port97",
- "port100", "port101", "port102", "port103",
- "port104", "port105", "port106", "port107",
- "port110", "port111", "port112", "port113",
- "port114", "port115", "port116", "port117",
- "port120", "port121", "port122", "port123",
- "port124", "port125", "port126", "port127",
- "port130", "port131", "port132", "port133",
- "port134", "port135", "port136", "port137",
- "port140", "port141", "port142", "port143",
- "port144", "port145", "port146", "port147",
- /* port150-174 missing */
- /* none */ "port175", "port176", "port177",
- "port180", "port181", "port182", "port183",
- "port184", "port185", "port186", "port187",
- "port190", "port191", "port192", "port193",
- "port194", "port195", "port196", "port197",
- "port200", "port201", "port202", "port203",
- "port204", "port205", "port206", "port207",
- "port210", "port211", "port212", "port213",
- "port214", "port215", "port216", "port217",
- "port220", "port221", "port222", "port223",
- "port224", "port225", "port226", "port227",
- "port230", "port231", "port232", "port233",
- "port234", "port235", "port236", "port237",
- "port240", "port241", "port242", "port243",
- "port244", "port245", "port246", "port247",
- "port250", "port251", "port252", "port253",
- "port254", "port255", "port256", "port257",
- "port260", "port261", "port262", "port263",
- "port264", "port265", "port266", "port267",
- "port270", "port271", "port272", "port273",
- "port274", "port275", "port276", "port277",
- "port280", "port281", "port282", "port283",
- "port284", "port285", "port286", "port287",
- "port290", "port291", "port292", "port293",
- "port294", "port295", "port296", "port297",
- "port300", "port301", "port302", "port303",
- "port304", "port305", "port306", "port307",
-};
-static const char * const xirq_groups[] = {
- "xirq0", "xirq1", "xirq2", "xirq3",
- "xirq4", "xirq5", "xirq6", "xirq7",
- "xirq8", "xirq9", "xirq10", "xirq11",
- "xirq12", "xirq13", "xirq14", "xirq15",
- "xirq16", "xirq17", "xirq18", "xirq19",
- "xirq20",
- "xirq3b", "xirq4b", "xirq16b", "xirq17b", "xirq17c",
- "xirq18b", "xirq18c", "xirq19b", "xirq20b",
-};
-
-static const struct uniphier_pinmux_function ph1_pro5_functions[] = {
- UNIPHIER_PINMUX_FUNCTION(emmc),
- UNIPHIER_PINMUX_FUNCTION(i2c0),
- UNIPHIER_PINMUX_FUNCTION(i2c1),
- UNIPHIER_PINMUX_FUNCTION(i2c2),
- UNIPHIER_PINMUX_FUNCTION(i2c3),
- UNIPHIER_PINMUX_FUNCTION(i2c5),
- UNIPHIER_PINMUX_FUNCTION(i2c6),
- UNIPHIER_PINMUX_FUNCTION(nand),
- UNIPHIER_PINMUX_FUNCTION(sd),
- UNIPHIER_PINMUX_FUNCTION(uart0),
- UNIPHIER_PINMUX_FUNCTION(uart1),
- UNIPHIER_PINMUX_FUNCTION(uart2),
- UNIPHIER_PINMUX_FUNCTION(uart3),
- UNIPHIER_PINMUX_FUNCTION(usb0),
- UNIPHIER_PINMUX_FUNCTION(usb1),
- UNIPHIER_PINMUX_FUNCTION(usb2),
- UNIPHIER_PINMUX_FUNCTION(port),
- UNIPHIER_PINMUX_FUNCTION(xirq),
-};
-
-static struct uniphier_pinctrl_socdata ph1_pro5_pindata = {
- .groups = ph1_pro5_groups,
- .groups_count = ARRAY_SIZE(ph1_pro5_groups),
- .functions = ph1_pro5_functions,
- .functions_count = ARRAY_SIZE(ph1_pro5_functions),
- .mux_bits = 4,
- .reg_stride = 8,
- .load_pinctrl = true,
-};
-
-static struct pinctrl_desc ph1_pro5_pinctrl_desc = {
- .name = DRIVER_NAME,
- .pins = ph1_pro5_pins,
- .npins = ARRAY_SIZE(ph1_pro5_pins),
- .owner = THIS_MODULE,
-};
-
-static int ph1_pro5_pinctrl_probe(struct platform_device *pdev)
-{
- return uniphier_pinctrl_probe(pdev, &ph1_pro5_pinctrl_desc,
- &ph1_pro5_pindata);
-}
-
-static const struct of_device_id ph1_pro5_pinctrl_match[] = {
- { .compatible = "socionext,ph1-pro5-pinctrl" },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, ph1_pro5_pinctrl_match);
-
-static struct platform_driver ph1_pro5_pinctrl_driver = {
- .probe = ph1_pro5_pinctrl_probe,
- .remove = uniphier_pinctrl_remove,
- .driver = {
- .name = DRIVER_NAME,
- .of_match_table = ph1_pro5_pinctrl_match,
- },
-};
-module_platform_driver(ph1_pro5_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier PH1-Pro5 pinctrl driver");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-
-#include "pinctrl-uniphier.h"
-
-#define DRIVER_NAME "ph1-sld8-pinctrl"
-
-static const struct pinctrl_pin_desc ph1_sld8_pins[] = {
- UNIPHIER_PINCTRL_PIN(0, "PCA00", 0,
- 15, UNIPHIER_PIN_DRV_4_8,
- 15, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(1, "PCA01", 0,
- 16, UNIPHIER_PIN_DRV_4_8,
- 16, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(2, "PCA02", 0,
- 17, UNIPHIER_PIN_DRV_4_8,
- 17, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(3, "PCA03", 0,
- 18, UNIPHIER_PIN_DRV_4_8,
- 18, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(4, "PCA04", 0,
- 19, UNIPHIER_PIN_DRV_4_8,
- 19, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(5, "PCA05", 0,
- 20, UNIPHIER_PIN_DRV_4_8,
- 20, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(6, "PCA06", 0,
- 21, UNIPHIER_PIN_DRV_4_8,
- 21, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(7, "PCA07", 0,
- 22, UNIPHIER_PIN_DRV_4_8,
- 22, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(8, "PCA08", 0,
- 23, UNIPHIER_PIN_DRV_4_8,
- 23, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(9, "PCA09", 0,
- 24, UNIPHIER_PIN_DRV_4_8,
- 24, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(10, "PCA10", 0,
- 25, UNIPHIER_PIN_DRV_4_8,
- 25, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(11, "PCA11", 0,
- 26, UNIPHIER_PIN_DRV_4_8,
- 26, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(12, "PCA12", 0,
- 27, UNIPHIER_PIN_DRV_4_8,
- 27, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(13, "PCA13", 0,
- 28, UNIPHIER_PIN_DRV_4_8,
- 28, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(14, "PCA14", 0,
- 29, UNIPHIER_PIN_DRV_4_8,
- 29, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(15, "XNFRE_GB", UNIPHIER_PIN_IECTRL_NONE,
- 30, UNIPHIER_PIN_DRV_4_8,
- 30, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(16, "XNFWE_GB", UNIPHIER_PIN_IECTRL_NONE,
- 31, UNIPHIER_PIN_DRV_4_8,
- 31, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(17, "NFALE_GB", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_4_8,
- 32, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(18, "NFCLE_GB", UNIPHIER_PIN_IECTRL_NONE,
- 33, UNIPHIER_PIN_DRV_4_8,
- 33, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(19, "XNFWP_GB", UNIPHIER_PIN_IECTRL_NONE,
- 34, UNIPHIER_PIN_DRV_4_8,
- 34, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(20, "XNFCE0_GB", UNIPHIER_PIN_IECTRL_NONE,
- 35, UNIPHIER_PIN_DRV_4_8,
- 35, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(21, "NANDRYBY0_GB", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_4_8,
- 36, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(22, "XNFCE1_GB", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_8_12_16_20,
- 119, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(23, "NANDRYBY1_GB", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_8_12_16_20,
- 120, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(24, "NFD0_GB", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_8_12_16_20,
- 121, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(25, "NFD1_GB", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_8_12_16_20,
- 122, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(26, "NFD2_GB", UNIPHIER_PIN_IECTRL_NONE,
- 16, UNIPHIER_PIN_DRV_8_12_16_20,
- 123, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(27, "NFD3_GB", UNIPHIER_PIN_IECTRL_NONE,
- 20, UNIPHIER_PIN_DRV_8_12_16_20,
- 124, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(28, "NFD4_GB", UNIPHIER_PIN_IECTRL_NONE,
- 24, UNIPHIER_PIN_DRV_8_12_16_20,
- 125, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(29, "NFD5_GB", UNIPHIER_PIN_IECTRL_NONE,
- 28, UNIPHIER_PIN_DRV_8_12_16_20,
- 126, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(30, "NFD6_GB", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_8_12_16_20,
- 127, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(31, "NFD7_GB", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_8_12_16_20,
- 128, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(32, "SDCLK", 8,
- 40, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(33, "SDCMD", 8,
- 44, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(34, "SDDAT0", 8,
- 48, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(35, "SDDAT1", 8,
- 52, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(36, "SDDAT2", 8,
- 56, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(37, "SDDAT3", 8,
- 60, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(38, "SDCD", 8,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 129, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(39, "SDWP", 8,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 130, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(40, "SDVOLC", 9,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 131, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(41, "USB0VBUS", 0,
- 37, UNIPHIER_PIN_DRV_4_8,
- 37, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(42, "USB0OD", 0,
- 38, UNIPHIER_PIN_DRV_4_8,
- 38, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(43, "USB1VBUS", 0,
- 39, UNIPHIER_PIN_DRV_4_8,
- 39, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(44, "USB1OD", 0,
- 40, UNIPHIER_PIN_DRV_4_8,
- 40, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(45, "PCRESET", 0,
- 41, UNIPHIER_PIN_DRV_4_8,
- 41, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(46, "PCREG", 0,
- 42, UNIPHIER_PIN_DRV_4_8,
- 42, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(47, "PCCE2", 0,
- 43, UNIPHIER_PIN_DRV_4_8,
- 43, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(48, "PCVS1", 0,
- 44, UNIPHIER_PIN_DRV_4_8,
- 44, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(49, "PCCD2", 0,
- 45, UNIPHIER_PIN_DRV_4_8,
- 45, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(50, "PCCD1", 0,
- 46, UNIPHIER_PIN_DRV_4_8,
- 46, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(51, "PCREADY", 0,
- 47, UNIPHIER_PIN_DRV_4_8,
- 47, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(52, "PCDOE", 0,
- 48, UNIPHIER_PIN_DRV_4_8,
- 48, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(53, "PCCE1", 0,
- 49, UNIPHIER_PIN_DRV_4_8,
- 49, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(54, "PCWE", 0,
- 50, UNIPHIER_PIN_DRV_4_8,
- 50, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(55, "PCOE", 0,
- 51, UNIPHIER_PIN_DRV_4_8,
- 51, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(56, "PCWAIT", 0,
- 52, UNIPHIER_PIN_DRV_4_8,
- 52, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(57, "PCIOWR", 0,
- 53, UNIPHIER_PIN_DRV_4_8,
- 53, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(58, "PCIORD", 0,
- 54, UNIPHIER_PIN_DRV_4_8,
- 54, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(59, "HS0DIN0", 0,
- 55, UNIPHIER_PIN_DRV_4_8,
- 55, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(60, "HS0DIN1", 0,
- 56, UNIPHIER_PIN_DRV_4_8,
- 56, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(61, "HS0DIN2", 0,
- 57, UNIPHIER_PIN_DRV_4_8,
- 57, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(62, "HS0DIN3", 0,
- 58, UNIPHIER_PIN_DRV_4_8,
- 58, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(63, "HS0DIN4", 0,
- 59, UNIPHIER_PIN_DRV_4_8,
- 59, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(64, "HS0DIN5", 0,
- 60, UNIPHIER_PIN_DRV_4_8,
- 60, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(65, "HS0DIN6", 0,
- 61, UNIPHIER_PIN_DRV_4_8,
- 61, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(66, "HS0DIN7", 0,
- 62, UNIPHIER_PIN_DRV_4_8,
- 62, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(67, "HS0BCLKIN", 0,
- 63, UNIPHIER_PIN_DRV_4_8,
- 63, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(68, "HS0VALIN", 0,
- 64, UNIPHIER_PIN_DRV_4_8,
- 64, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(69, "HS0SYNCIN", 0,
- 65, UNIPHIER_PIN_DRV_4_8,
- 65, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(70, "HSDOUT0", 0,
- 66, UNIPHIER_PIN_DRV_4_8,
- 66, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(71, "HSDOUT1", 0,
- 67, UNIPHIER_PIN_DRV_4_8,
- 67, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(72, "HSDOUT2", 0,
- 68, UNIPHIER_PIN_DRV_4_8,
- 68, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(73, "HSDOUT3", 0,
- 69, UNIPHIER_PIN_DRV_4_8,
- 69, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(74, "HSDOUT4", 0,
- 70, UNIPHIER_PIN_DRV_4_8,
- 70, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(75, "HSDOUT5", 0,
- 71, UNIPHIER_PIN_DRV_4_8,
- 71, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(76, "HSDOUT6", 0,
- 72, UNIPHIER_PIN_DRV_4_8,
- 72, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(77, "HSDOUT7", 0,
- 73, UNIPHIER_PIN_DRV_4_8,
- 73, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(78, "HSBCLKOUT", 0,
- 74, UNIPHIER_PIN_DRV_4_8,
- 74, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(79, "HSVALOUT", 0,
- 75, UNIPHIER_PIN_DRV_4_8,
- 75, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(80, "HSSYNCOUT", 0,
- 76, UNIPHIER_PIN_DRV_4_8,
- 76, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(81, "HS1DIN0", 0,
- 77, UNIPHIER_PIN_DRV_4_8,
- 77, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(82, "HS1DIN1", 0,
- 78, UNIPHIER_PIN_DRV_4_8,
- 78, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(83, "HS1DIN2", 0,
- 79, UNIPHIER_PIN_DRV_4_8,
- 79, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(84, "HS1DIN3", 0,
- 80, UNIPHIER_PIN_DRV_4_8,
- 80, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(85, "HS1DIN4", 0,
- 81, UNIPHIER_PIN_DRV_4_8,
- 81, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(86, "HS1DIN5", 0,
- 82, UNIPHIER_PIN_DRV_4_8,
- 82, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(87, "HS1DIN6", 0,
- 83, UNIPHIER_PIN_DRV_4_8,
- 83, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(88, "HS1DIN7", 0,
- 84, UNIPHIER_PIN_DRV_4_8,
- 84, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(89, "HS1BCLKIN", 0,
- 85, UNIPHIER_PIN_DRV_4_8,
- 85, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(90, "HS1VALIN", 0,
- 86, UNIPHIER_PIN_DRV_4_8,
- 86, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(91, "HS1SYNCIN", 0,
- 87, UNIPHIER_PIN_DRV_4_8,
- 87, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(92, "AGCI", 3,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 132, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(93, "AGCR", 4,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 133, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(94, "AGCBS", 5,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 134, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(95, "IECOUT", 0,
- 88, UNIPHIER_PIN_DRV_4_8,
- 88, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(96, "ASMCK", 0,
- 89, UNIPHIER_PIN_DRV_4_8,
- 89, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(97, "ABCKO", UNIPHIER_PIN_IECTRL_NONE,
- 90, UNIPHIER_PIN_DRV_4_8,
- 90, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(98, "ALRCKO", UNIPHIER_PIN_IECTRL_NONE,
- 91, UNIPHIER_PIN_DRV_4_8,
- 91, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(99, "ASDOUT0", UNIPHIER_PIN_IECTRL_NONE,
- 92, UNIPHIER_PIN_DRV_4_8,
- 92, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(100, "ASDOUT1", UNIPHIER_PIN_IECTRL_NONE,
- 93, UNIPHIER_PIN_DRV_4_8,
- 93, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(101, "ARCOUT", 0,
- 94, UNIPHIER_PIN_DRV_4_8,
- 94, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(102, "SDA0", 10,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(103, "SCL0", 10,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(104, "SDA1", 11,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(105, "SCL1", 11,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(106, "DMDSDA0", 12,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(107, "DMDSCL0", 12,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(108, "DMDSDA1", 13,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(109, "DMDSCL1", 13,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(110, "SBO0", UNIPHIER_PIN_IECTRL_NONE,
- 95, UNIPHIER_PIN_DRV_4_8,
- 95, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(111, "SBI0", UNIPHIER_PIN_IECTRL_NONE,
- 96, UNIPHIER_PIN_DRV_4_8,
- 96, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(112, "SBO1", 0,
- 97, UNIPHIER_PIN_DRV_4_8,
- 97, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(113, "SBI1", 0,
- 98, UNIPHIER_PIN_DRV_4_8,
- 98, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(114, "TXD1", 0,
- 99, UNIPHIER_PIN_DRV_4_8,
- 99, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(115, "RXD1", 0,
- 100, UNIPHIER_PIN_DRV_4_8,
- 100, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(116, "HIN", 1,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(117, "VIN", 2,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
- -1, UNIPHIER_PIN_PULL_NONE),
- UNIPHIER_PINCTRL_PIN(118, "TCON0", 0,
- 101, UNIPHIER_PIN_DRV_4_8,
- 101, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(119, "TCON1", 0,
- 102, UNIPHIER_PIN_DRV_4_8,
- 102, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(120, "TCON2", 0,
- 103, UNIPHIER_PIN_DRV_4_8,
- 103, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(121, "TCON3", 0,
- 104, UNIPHIER_PIN_DRV_4_8,
- 104, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(122, "TCON4", 0,
- 105, UNIPHIER_PIN_DRV_4_8,
- 105, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(123, "TCON5", 0,
- 106, UNIPHIER_PIN_DRV_4_8,
- 106, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(124, "TCON6", 0,
- 107, UNIPHIER_PIN_DRV_4_8,
- 107, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(125, "TCON7", 0,
- 108, UNIPHIER_PIN_DRV_4_8,
- 108, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(126, "TCON8", 0,
- 109, UNIPHIER_PIN_DRV_4_8,
- 109, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(127, "PWMA", 0,
- 110, UNIPHIER_PIN_DRV_4_8,
- 110, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(128, "XIRQ0", 0,
- 111, UNIPHIER_PIN_DRV_4_8,
- 111, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(129, "XIRQ1", 0,
- 112, UNIPHIER_PIN_DRV_4_8,
- 112, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(130, "XIRQ2", 0,
- 113, UNIPHIER_PIN_DRV_4_8,
- 113, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(131, "XIRQ3", 0,
- 114, UNIPHIER_PIN_DRV_4_8,
- 114, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(132, "XIRQ4", 0,
- 115, UNIPHIER_PIN_DRV_4_8,
- 115, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(133, "XIRQ5", 0,
- 116, UNIPHIER_PIN_DRV_4_8,
- 116, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(134, "XIRQ6", 0,
- 117, UNIPHIER_PIN_DRV_4_8,
- 117, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(135, "XIRQ7", 0,
- 118, UNIPHIER_PIN_DRV_4_8,
- 118, UNIPHIER_PIN_PULL_DOWN),
-};
-
-static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
-static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
-static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
-static const unsigned i2c0_pins[] = {102, 103};
-static const unsigned i2c0_muxvals[] = {0, 0};
-static const unsigned i2c1_pins[] = {104, 105};
-static const unsigned i2c1_muxvals[] = {0, 0};
-static const unsigned i2c2_pins[] = {108, 109};
-static const unsigned i2c2_muxvals[] = {2, 2};
-static const unsigned i2c3_pins[] = {108, 109};
-static const unsigned i2c3_muxvals[] = {3, 3};
-static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26,
- 27, 28, 29, 30, 31};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
-static const unsigned nand_cs1_pins[] = {22, 23};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
-static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
-static const unsigned uart0_pins[] = {70, 71};
-static const unsigned uart0_muxvals[] = {3, 3};
-static const unsigned uart1_pins[] = {114, 115};
-static const unsigned uart1_muxvals[] = {0, 0};
-static const unsigned uart2_pins[] = {112, 113};
-static const unsigned uart2_muxvals[] = {1, 1};
-static const unsigned uart3_pins[] = {110, 111};
-static const unsigned uart3_muxvals[] = {1, 1};
-static const unsigned usb0_pins[] = {41, 42};
-static const unsigned usb0_muxvals[] = {0, 0};
-static const unsigned usb1_pins[] = {43, 44};
-static const unsigned usb1_muxvals[] = {0, 0};
-static const unsigned usb2_pins[] = {114, 115};
-static const unsigned usb2_muxvals[] = {1, 1};
-static const unsigned port_range0_pins[] = {
- 0, 1, 2, 3, 4, 5, 6, 7, /* PORT0x */
- 8, 9, 10, 11, 12, 13, 14, 15, /* PORT1x */
- 32, 33, 34, 35, 36, 37, 38, 39, /* PORT2x */
- 59, 60, 61, 62, 63, 64, 65, 66, /* PORT3x */
- 95, 96, 97, 98, 99, 100, 101, 57, /* PORT4x */
- 70, 71, 72, 73, 74, 75, 76, 77, /* PORT5x */
- 81, 83, 84, 85, 86, 89, 90, 91, /* PORT6x */
- 118, 119, 120, 121, 122, 53, 54, 55, /* PORT7x */
- 41, 42, 43, 44, 79, 80, 18, 19, /* PORT8x */
- 110, 111, 112, 113, 114, 115, 16, 17, /* PORT9x */
- 40, 67, 68, 69, 78, 92, 93, 94, /* PORT10x */
- 48, 49, 46, 45, 123, 124, 125, 126, /* PORT11x */
- 47, 127, 20, 56, 22, /* PORT120-124 */
-};
-static const unsigned port_range0_muxvals[] = {
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */
- 15, 15, 15, 15, 15, /* PORT120-124 */
-};
-static const unsigned port_range1_pins[] = {
- 116, 117, /* PORT130-131 */
-};
-static const unsigned port_range1_muxvals[] = {
- 15, 15, /* PORT130-131 */
-};
-static const unsigned port_range2_pins[] = {
- 102, 103, 104, 105, 106, 107, 108, 109, /* PORT14x */
-};
-static const unsigned port_range2_muxvals[] = {
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
-};
-static const unsigned port_range3_pins[] = {
- 23, /* PORT166 */
-};
-static const unsigned port_range3_muxvals[] = {
- 15, /* PORT166 */
-};
-static const unsigned xirq_range0_pins[] = {
- 128, 129, 130, 131, 132, 133, 134, 135, /* XIRQ0-7 */
- 82, 87, 88, 50, 51, /* XIRQ8-12 */
-};
-static const unsigned xirq_range0_muxvals[] = {
- 0, 0, 0, 0, 0, 0, 0, 0, /* XIRQ0-7 */
- 14, 14, 14, 14, 14, /* XIRQ8-12 */
-};
-static const unsigned xirq_range1_pins[] = {
- 52, 58, /* XIRQ14-15 */
-};
-static const unsigned xirq_range1_muxvals[] = {
- 14, 14, /* XIRQ14-15 */
-};
-
-static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
- UNIPHIER_PINCTRL_GROUP(emmc),
- UNIPHIER_PINCTRL_GROUP(emmc_dat8),
- UNIPHIER_PINCTRL_GROUP(i2c0),
- UNIPHIER_PINCTRL_GROUP(i2c1),
- UNIPHIER_PINCTRL_GROUP(i2c2),
- UNIPHIER_PINCTRL_GROUP(i2c3),
- UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
- UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart3),
- UNIPHIER_PINCTRL_GROUP(usb0),
- UNIPHIER_PINCTRL_GROUP(usb1),
- UNIPHIER_PINCTRL_GROUP(usb2),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range2),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range3),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range0),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range2, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range2, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range2, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range2, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range2, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range2, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range2, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range2, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range3, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq_range0, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq_range0, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq_range0, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq_range0, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq_range0, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq_range0, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq_range0, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq_range0, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq_range0, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq_range0, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq_range0, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq_range0, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq_range0, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq_range1, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq_range1, 1),
-};
-
-static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
-static const char * const i2c0_groups[] = {"i2c0"};
-static const char * const i2c1_groups[] = {"i2c1"};
-static const char * const i2c2_groups[] = {"i2c2"};
-static const char * const i2c3_groups[] = {"i2c3"};
-static const char * const nand_groups[] = {"nand", "nand_cs1"};
-static const char * const sd_groups[] = {"sd"};
-static const char * const uart0_groups[] = {"uart0"};
-static const char * const uart1_groups[] = {"uart1"};
-static const char * const uart2_groups[] = {"uart2"};
-static const char * const uart3_groups[] = {"uart3"};
-static const char * const usb0_groups[] = {"usb0"};
-static const char * const usb1_groups[] = {"usb1"};
-static const char * const usb2_groups[] = {"usb2"};
-static const char * const port_groups[] = {
- "port00", "port01", "port02", "port03",
- "port04", "port05", "port06", "port07",
- "port10", "port11", "port12", "port13",
- "port14", "port15", "port16", "port17",
- "port20", "port21", "port22", "port23",
- "port24", "port25", "port26", "port27",
- "port30", "port31", "port32", "port33",
- "port34", "port35", "port36", "port37",
- "port40", "port41", "port42", "port43",
- "port44", "port45", "port46", "port47",
- "port50", "port51", "port52", "port53",
- "port54", "port55", "port56", "port57",
- "port60", "port61", "port62", "port63",
- "port64", "port65", "port66", "port67",
- "port70", "port71", "port72", "port73",
- "port74", "port75", "port76", "port77",
- "port80", "port81", "port82", "port83",
- "port84", "port85", "port86", "port87",
- "port90", "port91", "port92", "port93",
- "port94", "port95", "port96", "port97",
- "port100", "port101", "port102", "port103",
- "port104", "port105", "port106", "port107",
- "port110", "port111", "port112", "port113",
- "port114", "port115", "port116", "port117",
- "port120", "port121", "port122", "port123",
- "port124", "port125", "port126", "port127",
- "port130", "port131", "port132", "port133",
- "port134", "port135", "port136", "port137",
- "port140", "port141", "port142", "port143",
- "port144", "port145", "port146", "port147",
- /* port150-164 missing */
- /* none */ "port165",
-};
-static const char * const xirq_groups[] = {
- "xirq0", "xirq1", "xirq2", "xirq3",
- "xirq4", "xirq5", "xirq6", "xirq7",
- "xirq8", "xirq9", "xirq10", "xirq11",
- "xirq12", /* none*/ "xirq14", "xirq15",
-};
-
-static const struct uniphier_pinmux_function ph1_sld8_functions[] = {
- UNIPHIER_PINMUX_FUNCTION(emmc),
- UNIPHIER_PINMUX_FUNCTION(i2c0),
- UNIPHIER_PINMUX_FUNCTION(i2c1),
- UNIPHIER_PINMUX_FUNCTION(i2c2),
- UNIPHIER_PINMUX_FUNCTION(i2c3),
- UNIPHIER_PINMUX_FUNCTION(nand),
- UNIPHIER_PINMUX_FUNCTION(sd),
- UNIPHIER_PINMUX_FUNCTION(uart0),
- UNIPHIER_PINMUX_FUNCTION(uart1),
- UNIPHIER_PINMUX_FUNCTION(uart2),
- UNIPHIER_PINMUX_FUNCTION(uart3),
- UNIPHIER_PINMUX_FUNCTION(usb0),
- UNIPHIER_PINMUX_FUNCTION(usb1),
- UNIPHIER_PINMUX_FUNCTION(usb2),
- UNIPHIER_PINMUX_FUNCTION(port),
- UNIPHIER_PINMUX_FUNCTION(xirq),
-};
-
-static struct uniphier_pinctrl_socdata ph1_sld8_pindata = {
- .groups = ph1_sld8_groups,
- .groups_count = ARRAY_SIZE(ph1_sld8_groups),
- .functions = ph1_sld8_functions,
- .functions_count = ARRAY_SIZE(ph1_sld8_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
-};
-
-static struct pinctrl_desc ph1_sld8_pinctrl_desc = {
- .name = DRIVER_NAME,
- .pins = ph1_sld8_pins,
- .npins = ARRAY_SIZE(ph1_sld8_pins),
- .owner = THIS_MODULE,
-};
-
-static int ph1_sld8_pinctrl_probe(struct platform_device *pdev)
-{
- return uniphier_pinctrl_probe(pdev, &ph1_sld8_pinctrl_desc,
- &ph1_sld8_pindata);
-}
-
-static const struct of_device_id ph1_sld8_pinctrl_match[] = {
- { .compatible = "socionext,ph1-sld8-pinctrl" },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, ph1_sld8_pinctrl_match);
-
-static struct platform_driver ph1_sld8_pinctrl_driver = {
- .probe = ph1_sld8_pinctrl_probe,
- .remove = uniphier_pinctrl_remove,
- .driver = {
- .name = DRIVER_NAME,
- .of_match_table = ph1_sld8_pinctrl_match,
- },
-};
-module_platform_driver(ph1_sld8_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier PH1-sLD8 pinctrl driver");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-
-#include "pinctrl-uniphier.h"
-
-#define DRIVER_NAME "proxstream2-pinctrl"
-
-static const struct pinctrl_pin_desc proxstream2_pins[] = {
- UNIPHIER_PINCTRL_PIN(0, "ED0", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_4_8,
- 0, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(1, "ED1", UNIPHIER_PIN_IECTRL_NONE,
- 1, UNIPHIER_PIN_DRV_4_8,
- 1, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(2, "ED2", UNIPHIER_PIN_IECTRL_NONE,
- 2, UNIPHIER_PIN_DRV_4_8,
- 2, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(3, "ED3", UNIPHIER_PIN_IECTRL_NONE,
- 3, UNIPHIER_PIN_DRV_4_8,
- 3, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(4, "ED4", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_4_8,
- 4, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(5, "ED5", UNIPHIER_PIN_IECTRL_NONE,
- 5, UNIPHIER_PIN_DRV_4_8,
- 5, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(6, "ED6", UNIPHIER_PIN_IECTRL_NONE,
- 6, UNIPHIER_PIN_DRV_4_8,
- 6, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(7, "ED7", UNIPHIER_PIN_IECTRL_NONE,
- 7, UNIPHIER_PIN_DRV_4_8,
- 7, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(8, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_4_8,
- 8, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(9, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
- 9, UNIPHIER_PIN_DRV_4_8,
- 9, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(10, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
- 10, UNIPHIER_PIN_DRV_4_8,
- 10, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(11, "ES0", UNIPHIER_PIN_IECTRL_NONE,
- 11, UNIPHIER_PIN_DRV_4_8,
- 11, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(12, "ES1", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_4_8,
- 12, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(13, "ES2", UNIPHIER_PIN_IECTRL_NONE,
- 13, UNIPHIER_PIN_DRV_4_8,
- 13, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(14, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
- 14, UNIPHIER_PIN_DRV_4_8,
- 14, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(15, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 15, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(16, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 16, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(17, "SMTD0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 17, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(18, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 18, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(19, "SMTCLK0CG", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 19, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(20, "SMTDET0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 20, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(21, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 21, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(22, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 22, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(23, "SMTD1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 23, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(24, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 24, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(25, "SMTCLK1CG", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 25, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(26, "SMTDET1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 26, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(27, "XIRQ18", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 27, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(28, "XIRQ19", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 28, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(29, "XIRQ20", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 29, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(30, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
- 30, UNIPHIER_PIN_DRV_4_8,
- 30, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(31, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
- 31, UNIPHIER_PIN_DRV_4_8,
- 31, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(32, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_4_8,
- 32, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(33, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
- 33, UNIPHIER_PIN_DRV_4_8,
- 33, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(34, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
- 34, UNIPHIER_PIN_DRV_4_8,
- 34, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(35, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
- 35, UNIPHIER_PIN_DRV_4_8,
- 35, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(36, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_4_8,
- 36, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(37, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE,
- 37, UNIPHIER_PIN_DRV_4_8,
- 37, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(38, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE,
- 38, UNIPHIER_PIN_DRV_4_8,
- 38, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(39, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
- 39, UNIPHIER_PIN_DRV_4_8,
- 39, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(40, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
- 40, UNIPHIER_PIN_DRV_4_8,
- 40, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(41, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
- 41, UNIPHIER_PIN_DRV_4_8,
- 41, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(42, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
- 42, UNIPHIER_PIN_DRV_4_8,
- 42, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(43, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
- 43, UNIPHIER_PIN_DRV_4_8,
- 43, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(44, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
- 44, UNIPHIER_PIN_DRV_4_8,
- 44, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(45, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
- 45, UNIPHIER_PIN_DRV_4_8,
- 45, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(46, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
- 46, UNIPHIER_PIN_DRV_4_8,
- 46, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(48, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(49, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(50, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(51, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
- 16, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(52, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
- 20, UNIPHIER_PIN_DRV_8_12_16_20,
- -1, UNIPHIER_PIN_PULL_UP_FIXED),
- UNIPHIER_PINCTRL_PIN(53, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 53, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(54, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 54, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(55, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 55, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(56, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 56, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(57, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 57, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(58, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 58, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(59, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 59, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(60, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 60, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(61, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 61, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(62, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 62, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(63, "USB3OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 63, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(64, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 64, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(65, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 65, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(66, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 66, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(67, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 67, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(68, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 68, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(69, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 69, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(70, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 70, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(71, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 71, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(72, "XIRQ9", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 72, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(73, "XIRQ10", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 73, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(74, "XIRQ16", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 74, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(75, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 75, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(76, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 76, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(77, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 77, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(78, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 78, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(79, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 79, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(80, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 80, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(81, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 81, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(82, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 82, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(83, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 83, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(84, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 84, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(85, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 85, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(86, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 86, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(87, "STS0CLKO", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 87, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(88, "STS0SYNCO", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 88, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(89, "STS0VALO", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 89, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(90, "STS0DATAO", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 90, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(91, "XIRQ17", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 91, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(92, "PORT163", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 92, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(93, "PORT165", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 93, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(94, "PORT166", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 94, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(95, "PORT132", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 95, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(96, "PORT133", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 96, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(97, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 97, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(98, "AI2ADCCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 98, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(99, "AI2BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 99, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(100, "AI2LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 100, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(101, "AI2D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 101, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(102, "AI2D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 102, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(103, "AI2D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 103, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(104, "AI2D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 104, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(105, "AO3DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 105, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(106, "AO3BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 106, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(107, "AO3LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 107, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(108, "AO3DMIX", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 108, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(109, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 109, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(110, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 110, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(111, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 111, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(112, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 112, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(113, "TXD2", 0,
- 113, UNIPHIER_PIN_DRV_4_8,
- 113, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(114, "RXD2", 0,
- 114, UNIPHIER_PIN_DRV_4_8,
- 114, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(115, "TXD1", 0,
- 115, UNIPHIER_PIN_DRV_4_8,
- 115, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(116, "RXD1", 0,
- 116, UNIPHIER_PIN_DRV_4_8,
- 116, UNIPHIER_PIN_PULL_UP),
- UNIPHIER_PINCTRL_PIN(117, "PORT190", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 117, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(118, "VI1HSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 118, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(119, "VI1VSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 119, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(120, "VI1DE", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 120, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(121, "XIRQ3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 121, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(122, "XIRQ4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 122, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(123, "VI1G2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 123, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(124, "VI1G3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 124, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(125, "VI1G4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 125, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(126, "VI1G5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 126, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(127, "VI1G6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 127, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(128, "VI1G7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 128, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(129, "VI1G8", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 129, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(130, "VI1G9", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 130, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(131, "VI1CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 131, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(132, "PORT05", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 132, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(133, "PORT06", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 133, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(134, "VI1R2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 134, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(135, "VI1R3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 135, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(136, "VI1R4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 136, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(137, "VI1R5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 137, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(138, "VI1R6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 138, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(139, "VI1R7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 139, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(140, "VI1R8", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 140, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(141, "VI1R9", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 141, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(142, "LPST", UNIPHIER_PIN_IECTRL_NONE,
- 142, UNIPHIER_PIN_DRV_4_8,
- 142, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(143, "MDC", 0,
- 143, UNIPHIER_PIN_DRV_4_8,
- 143, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(144, "MDIO", 0,
- 144, UNIPHIER_PIN_DRV_4_8,
- 144, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(145, "MDIO_INTL", 0,
- 145, UNIPHIER_PIN_DRV_4_8,
- 145, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(146, "PHYRSTL", 0,
- 146, UNIPHIER_PIN_DRV_4_8,
- 146, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(147, "RGMII_RXCLK", 0,
- 147, UNIPHIER_PIN_DRV_4_8,
- 147, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(148, "RGMII_RXD0", 0,
- 148, UNIPHIER_PIN_DRV_4_8,
- 148, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(149, "RGMII_RXD1", 0,
- 149, UNIPHIER_PIN_DRV_4_8,
- 149, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(150, "RGMII_RXD2", 0,
- 150, UNIPHIER_PIN_DRV_4_8,
- 150, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(151, "RGMII_RXD3", 0,
- 151, UNIPHIER_PIN_DRV_4_8,
- 151, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(152, "RGMII_RXCTL", 0,
- 152, UNIPHIER_PIN_DRV_4_8,
- 152, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(153, "RGMII_TXCLK", 0,
- 153, UNIPHIER_PIN_DRV_4_8,
- 153, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(154, "RGMII_TXD0", 0,
- 154, UNIPHIER_PIN_DRV_4_8,
- 154, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(155, "RGMII_TXD1", 0,
- 155, UNIPHIER_PIN_DRV_4_8,
- 155, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(156, "RGMII_TXD2", 0,
- 156, UNIPHIER_PIN_DRV_4_8,
- 156, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(157, "RGMII_TXD3", 0,
- 157, UNIPHIER_PIN_DRV_4_8,
- 157, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(158, "RGMII_TXCTL", 0,
- 158, UNIPHIER_PIN_DRV_4_8,
- 158, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(159, "SDA3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 159, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(160, "SCL3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 160, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(161, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 161, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(162, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 162, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(163, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 163, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(164, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 164, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(165, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 165, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(166, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 166, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(167, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 167, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(168, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 168, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(169, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 169, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(170, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 170, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(171, "SDA2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 171, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(172, "SCL2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 172, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(173, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 173, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(174, "AI1D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 174, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(175, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 175, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(176, "AO2D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 176, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(177, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 177, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(178, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 178, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(179, "PORT222", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 179, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(180, "PORT223", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 180, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(181, "PORT224", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 181, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(182, "PORT225", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 182, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(183, "PORT226", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 183, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(184, "PORT227", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 184, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(185, "PORT230", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 185, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(186, "FANPWM", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 186, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(187, "HRDDCSDA0", 0,
- 187, UNIPHIER_PIN_DRV_4_8,
- 187, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(188, "HRDDCSCL0", 0,
- 188, UNIPHIER_PIN_DRV_4_8,
- 188, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(189, "HRDDCSDA1", 0,
- 189, UNIPHIER_PIN_DRV_4_8,
- 189, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(190, "HRDDCSCL1", 0,
- 190, UNIPHIER_PIN_DRV_4_8,
- 190, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(191, "HTDDCSDA0", 0,
- 191, UNIPHIER_PIN_DRV_4_8,
- 191, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(192, "HTDDCSCL0", 0,
- 192, UNIPHIER_PIN_DRV_4_8,
- 192, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(193, "HTDDCSDA1", 0,
- 193, UNIPHIER_PIN_DRV_4_8,
- 193, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(194, "HTDDCSCL1", 0,
- 194, UNIPHIER_PIN_DRV_4_8,
- 194, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(195, "PORT241", 0,
- 195, UNIPHIER_PIN_DRV_4_8,
- 195, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(196, "PORT242", 0,
- 196, UNIPHIER_PIN_DRV_4_8,
- 196, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(197, "PORT243", 0,
- 197, UNIPHIER_PIN_DRV_4_8,
- 197, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(198, "MVSYNC", 0,
- 198, UNIPHIER_PIN_DRV_4_8,
- 198, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(199, "SPISYNC0", UNIPHIER_PIN_IECTRL_NONE,
- 199, UNIPHIER_PIN_DRV_4_8,
- 199, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(200, "SPISCLK0", UNIPHIER_PIN_IECTRL_NONE,
- 200, UNIPHIER_PIN_DRV_4_8,
- 200, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(201, "SPITXD0", UNIPHIER_PIN_IECTRL_NONE,
- 201, UNIPHIER_PIN_DRV_4_8,
- 201, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(202, "SPIRXD0", UNIPHIER_PIN_IECTRL_NONE,
- 202, UNIPHIER_PIN_DRV_4_8,
- 202, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(203, "CK54EXI", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 203, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(204, "AEXCKA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 204, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(205, "AEXCKA2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 205, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(206, "CK27EXI", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
- 206, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(207, "STCDIN", 0,
- 207, UNIPHIER_PIN_DRV_4_8,
- 207, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(208, "PHSYNI", 0,
- 208, UNIPHIER_PIN_DRV_4_8,
- 208, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(209, "PVSYNI", 0,
- 209, UNIPHIER_PIN_DRV_4_8,
- 209, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(210, "MVSYN", UNIPHIER_PIN_IECTRL_NONE,
- 210, UNIPHIER_PIN_DRV_4_8,
- 210, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(211, "STCV", UNIPHIER_PIN_IECTRL_NONE,
- 211, UNIPHIER_PIN_DRV_4_8,
- 211, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(212, "PORT262", UNIPHIER_PIN_IECTRL_NONE,
- 212, UNIPHIER_PIN_DRV_4_8,
- 212, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(213, "USB0VBUS_IRQ", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 213, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(214, "USB1VBUS_IRQ", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
- 214, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(215, "PORT265", UNIPHIER_PIN_IECTRL_NONE,
- 215, UNIPHIER_PIN_DRV_4_8,
- 215, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(216, "CK25O", 0,
- 216, UNIPHIER_PIN_DRV_4_8,
- 216, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(217, "TXD0", 0,
- 217, UNIPHIER_PIN_DRV_4_8,
- 217, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(218, "RXD0", 0,
- 218, UNIPHIER_PIN_DRV_4_8,
- 218, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(219, "TXD3", 0,
- 219, UNIPHIER_PIN_DRV_4_8,
- 219, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(220, "RXD3", 0,
- 220, UNIPHIER_PIN_DRV_4_8,
- 220, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(221, "PORT273", 0,
- 221, UNIPHIER_PIN_DRV_4_8,
- 221, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(222, "STCDOUTC", 0,
- 222, UNIPHIER_PIN_DRV_4_8,
- 222, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(223, "PORT274", 0,
- 223, UNIPHIER_PIN_DRV_4_8,
- 223, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(224, "PORT275", 0,
- 224, UNIPHIER_PIN_DRV_4_8,
- 224, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(225, "PORT276", 0,
- 225, UNIPHIER_PIN_DRV_4_8,
- 225, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(226, "PORT277", 0,
- 226, UNIPHIER_PIN_DRV_4_8,
- 226, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(227, "PORT280", 0,
- 227, UNIPHIER_PIN_DRV_4_8,
- 227, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(228, "PORT281", 0,
- 228, UNIPHIER_PIN_DRV_4_8,
- 228, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(229, "PORT282", 0,
- 229, UNIPHIER_PIN_DRV_4_8,
- 229, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(230, "PORT283", 0,
- 230, UNIPHIER_PIN_DRV_4_8,
- 230, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(231, "PORT284", 0,
- 231, UNIPHIER_PIN_DRV_4_8,
- 231, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(232, "PORT285", 0,
- 232, UNIPHIER_PIN_DRV_4_8,
- 232, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(233, "T0HPD", 0,
- 233, UNIPHIER_PIN_DRV_4_8,
- 233, UNIPHIER_PIN_PULL_DOWN),
- UNIPHIER_PINCTRL_PIN(234, "T1HPD", 0,
- 234, UNIPHIER_PIN_DRV_4_8,
- 234, UNIPHIER_PIN_PULL_DOWN),
-};
-
-static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
-static const unsigned emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
-static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
-static const unsigned emmc_dat8_muxvals[] = {9, 9, 9, 9};
-static const unsigned i2c0_pins[] = {109, 110};
-static const unsigned i2c0_muxvals[] = {8, 8};
-static const unsigned i2c1_pins[] = {111, 112};
-static const unsigned i2c1_muxvals[] = {8, 8};
-static const unsigned i2c2_pins[] = {171, 172};
-static const unsigned i2c2_muxvals[] = {8, 8};
-static const unsigned i2c3_pins[] = {159, 160};
-static const unsigned i2c3_muxvals[] = {8, 8};
-static const unsigned i2c5_pins[] = {183, 184};
-static const unsigned i2c5_muxvals[] = {11, 11};
-static const unsigned i2c6_pins[] = {185, 186};
-static const unsigned i2c6_muxvals[] = {11, 11};
-static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
- 42, 43, 44, 45, 46};
-static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
- 8, 8};
-static const unsigned nand_cs1_pins[] = {37, 38};
-static const unsigned nand_cs1_muxvals[] = {8, 8};
-static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
-static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
-static const unsigned uart0_pins[] = {217, 218};
-static const unsigned uart0_muxvals[] = {8, 8};
-static const unsigned uart0b_pins[] = {179, 180};
-static const unsigned uart0b_muxvals[] = {10, 10};
-static const unsigned uart1_pins[] = {115, 116};
-static const unsigned uart1_muxvals[] = {8, 8};
-static const unsigned uart2_pins[] = {113, 114};
-static const unsigned uart2_muxvals[] = {8, 8};
-static const unsigned uart3_pins[] = {219, 220};
-static const unsigned uart3_muxvals[] = {8, 8};
-static const unsigned uart3b_pins[] = {181, 182};
-static const unsigned uart3b_muxvals[] = {10, 10};
-static const unsigned usb0_pins[] = {56, 57};
-static const unsigned usb0_muxvals[] = {8, 8};
-static const unsigned usb1_pins[] = {58, 59};
-static const unsigned usb1_muxvals[] = {8, 8};
-static const unsigned usb2_pins[] = {60, 61};
-static const unsigned usb2_muxvals[] = {8, 8};
-static const unsigned usb3_pins[] = {62, 63};
-static const unsigned usb3_muxvals[] = {8, 8};
-static const unsigned port_range0_pins[] = {
- 127, 128, 129, 130, 131, 132, 133, 134, /* PORT0x */
- 135, 136, 137, 138, 139, 140, 141, 142, /* PORT1x */
- 0, 1, 2, 3, 4, 5, 6, 7, /* PORT2x */
- 8, 9, 10, 11, 12, 13, 14, 15, /* PORT3x */
- 16, 17, 18, 19, 21, 22, 23, 24, /* PORT4x */
- 25, 30, 31, 32, 33, 34, 35, 36, /* PORT5x */
- 37, 38, 39, 40, 41, 42, 43, 44, /* PORT6x */
- 45, 46, 47, 48, 49, 50, 51, 52, /* PORT7x */
- 53, 54, 55, 56, 57, 58, 59, 60, /* PORT8x */
- 61, 62, 63, 64, 65, 66, 67, 68, /* PORT9x */
- 69, 70, 71, 76, 77, 78, 79, 80, /* PORT10x */
-};
-static const unsigned port_range0_muxvals[] = {
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
-};
-static const unsigned port_range1_pins[] = {
- 81, 82, 83, 84, 85, 86, 87, 88, /* PORT12x */
- 89, 90, 95, 96, 97, 98, 99, 100, /* PORT13x */
- 101, 102, 103, 104, 105, 106, 107, 108, /* PORT14x */
- 118, 119, 120, 121, 122, 123, 124, 125, /* PORT15x */
- 126, 72, 73, 92, 177, 93, 94, 176, /* PORT16x */
- 74, 91, 27, 28, 29, 75, 20, 26, /* PORT17x */
- 109, 110, 111, 112, 113, 114, 115, 116, /* PORT18x */
- 117, 143, 144, 145, 146, 147, 148, 149, /* PORT19x */
- 150, 151, 152, 153, 154, 155, 156, 157, /* PORT20x */
- 158, 159, 160, 161, 162, 163, 164, 165, /* PORT21x */
- 166, 178, 179, 180, 181, 182, 183, 184, /* PORT22x */
- 185, 187, 188, 189, 190, 191, 192, 193, /* PORT23x */
- 194, 195, 196, 197, 198, 199, 200, 201, /* PORT24x */
- 202, 203, 204, 205, 206, 207, 208, 209, /* PORT25x */
- 210, 211, 212, 213, 214, 215, 216, 217, /* PORT26x */
- 218, 219, 220, 221, 223, 224, 225, 226, /* PORT27x */
- 227, 228, 229, 230, 231, 232, 233, 234, /* PORT28x */
-};
-static const unsigned port_range1_muxvals[] = {
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT15x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT16x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT17x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */
-};
-static const unsigned xirq_pins[] = {
- 118, 119, 120, 121, 122, 123, 124, 125, /* XIRQ0-7 */
- 126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */
- 74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */
-};
-static const unsigned xirq_muxvals[] = {
- 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
- 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */
- 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */
-};
-
-static const struct uniphier_pinctrl_group proxstream2_groups[] = {
- UNIPHIER_PINCTRL_GROUP(emmc),
- UNIPHIER_PINCTRL_GROUP(emmc_dat8),
- UNIPHIER_PINCTRL_GROUP(i2c0),
- UNIPHIER_PINCTRL_GROUP(i2c1),
- UNIPHIER_PINCTRL_GROUP(i2c2),
- UNIPHIER_PINCTRL_GROUP(i2c3),
- UNIPHIER_PINCTRL_GROUP(i2c5),
- UNIPHIER_PINCTRL_GROUP(i2c6),
- UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
- UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(uart0),
- UNIPHIER_PINCTRL_GROUP(uart0b),
- UNIPHIER_PINCTRL_GROUP(uart1),
- UNIPHIER_PINCTRL_GROUP(uart2),
- UNIPHIER_PINCTRL_GROUP(uart3),
- UNIPHIER_PINCTRL_GROUP(uart3b),
- UNIPHIER_PINCTRL_GROUP(usb0),
- UNIPHIER_PINCTRL_GROUP(usb1),
- UNIPHIER_PINCTRL_GROUP(usb2),
- UNIPHIER_PINCTRL_GROUP(usb3),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range1, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range1, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range1, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range1, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range1, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range1, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range1, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range1, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range1, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range1, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range1, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range1, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range1, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range1, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range1, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range1, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range1, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range1, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range1, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range1, 21),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range1, 22),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range1, 23),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port150, port_range1, 24),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port151, port_range1, 25),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port152, port_range1, 26),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port153, port_range1, 27),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port154, port_range1, 28),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port155, port_range1, 29),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port156, port_range1, 30),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port157, port_range1, 31),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port160, port_range1, 32),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port161, port_range1, 33),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port162, port_range1, 34),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port163, port_range1, 35),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port164, port_range1, 36),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 37),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range1, 38),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port167, port_range1, 39),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port170, port_range1, 40),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port171, port_range1, 41),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port172, port_range1, 42),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port173, port_range1, 43),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port174, port_range1, 44),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 45),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 46),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 47),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 48),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 49),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 50),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 51),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 52),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 53),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 54),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 55),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 56),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 57),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 58),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 59),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 60),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 61),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 62),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 63),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 64),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 65),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 66),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 67),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 68),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 69),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 70),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 71),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 72),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 73),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 74),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 75),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 76),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 77),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 78),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 79),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 80),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 81),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 82),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 83),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 84),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 85),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 86),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 87),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 88),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 89),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 90),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 91),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 92),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 93),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 94),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 95),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 96),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 97),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 98),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 99),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 100),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 101),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 102),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 103),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 104),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 105),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 106),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 107),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 108),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 109),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 110),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 111),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 112),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 113),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 114),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 115),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 116),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 117),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 118),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 119),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 120),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 121),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 122),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 123),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 124),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 125),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 126),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 127),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 128),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 129),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 130),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 131),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 132),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 133),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 134),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 135),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23),
-};
-
-static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
-static const char * const i2c0_groups[] = {"i2c0"};
-static const char * const i2c1_groups[] = {"i2c1"};
-static const char * const i2c2_groups[] = {"i2c2"};
-static const char * const i2c3_groups[] = {"i2c3"};
-static const char * const i2c5_groups[] = {"i2c5"};
-static const char * const i2c6_groups[] = {"i2c6"};
-static const char * const nand_groups[] = {"nand", "nand_cs1"};
-static const char * const sd_groups[] = {"sd"};
-static const char * const uart0_groups[] = {"uart0", "uart0b"};
-static const char * const uart1_groups[] = {"uart1"};
-static const char * const uart2_groups[] = {"uart2"};
-static const char * const uart3_groups[] = {"uart3", "uart3b"};
-static const char * const usb0_groups[] = {"usb0"};
-static const char * const usb1_groups[] = {"usb1"};
-static const char * const usb2_groups[] = {"usb2"};
-static const char * const usb3_groups[] = {"usb3"};
-static const char * const port_groups[] = {
- "port00", "port01", "port02", "port03",
- "port04", "port05", "port06", "port07",
- "port10", "port11", "port12", "port13",
- "port14", "port15", "port16", "port17",
- "port20", "port21", "port22", "port23",
- "port24", "port25", "port26", "port27",
- "port30", "port31", "port32", "port33",
- "port34", "port35", "port36", "port37",
- "port40", "port41", "port42", "port43",
- "port44", "port45", "port46", "port47",
- "port50", "port51", "port52", "port53",
- "port54", "port55", "port56", "port57",
- "port60", "port61", "port62", "port63",
- "port64", "port65", "port66", "port67",
- "port70", "port71", "port72", "port73",
- "port74", "port75", "port76", "port77",
- "port80", "port81", "port82", "port83",
- "port84", "port85", "port86", "port87",
- "port90", "port91", "port92", "port93",
- "port94", "port95", "port96", "port97",
- "port100", "port101", "port102", "port103",
- "port104", "port105", "port106", "port107",
- /* port110-117 missing */
- "port120", "port121", "port122", "port123",
- "port124", "port125", "port126", "port127",
- "port130", "port131", "port132", "port133",
- "port134", "port135", "port136", "port137",
- "port140", "port141", "port142", "port143",
- "port144", "port145", "port146", "port147",
- "port150", "port151", "port152", "port153",
- "port154", "port155", "port156", "port157",
- "port160", "port161", "port162", "port163",
- "port164", "port165", "port166", "port167",
- "port170", "port171", "port172", "port173",
- "port174", "port175", "port176", "port177",
- "port180", "port181", "port182", "port183",
- "port184", "port185", "port186", "port187",
- "port190", "port191", "port192", "port193",
- "port194", "port195", "port196", "port197",
- "port200", "port201", "port202", "port203",
- "port204", "port205", "port206", "port207",
- "port210", "port211", "port212", "port213",
- "port214", "port215", "port216", "port217",
- "port220", "port221", "port222", "port223",
- "port224", "port225", "port226", "port227",
- "port230", "port231", "port232", "port233",
- "port234", "port235", "port236", "port237",
- "port240", "port241", "port242", "port243",
- "port244", "port245", "port246", "port247",
- "port250", "port251", "port252", "port253",
- "port254", "port255", "port256", "port257",
- "port260", "port261", "port262", "port263",
- "port264", "port265", "port266", "port267",
- "port270", "port271", "port272", "port273",
- "port274", "port275", "port276", "port277",
- "port280", "port281", "port282", "port283",
- "port284", "port285", "port286", "port287",
-};
-static const char * const xirq_groups[] = {
- "xirq0", "xirq1", "xirq2", "xirq3",
- "xirq4", "xirq5", "xirq6", "xirq7",
- "xirq8", "xirq9", "xirq10", "xirq11",
- "xirq12", "xirq13", "xirq14", "xirq15",
- "xirq16", "xirq17", "xirq18", "xirq19",
- "xirq20", "xirq21", "xirq22", "xirq23",
-};
-
-static const struct uniphier_pinmux_function proxstream2_functions[] = {
- UNIPHIER_PINMUX_FUNCTION(emmc),
- UNIPHIER_PINMUX_FUNCTION(i2c0),
- UNIPHIER_PINMUX_FUNCTION(i2c1),
- UNIPHIER_PINMUX_FUNCTION(i2c2),
- UNIPHIER_PINMUX_FUNCTION(i2c3),
- UNIPHIER_PINMUX_FUNCTION(i2c5),
- UNIPHIER_PINMUX_FUNCTION(i2c6),
- UNIPHIER_PINMUX_FUNCTION(nand),
- UNIPHIER_PINMUX_FUNCTION(sd),
- UNIPHIER_PINMUX_FUNCTION(uart0),
- UNIPHIER_PINMUX_FUNCTION(uart1),
- UNIPHIER_PINMUX_FUNCTION(uart2),
- UNIPHIER_PINMUX_FUNCTION(uart3),
- UNIPHIER_PINMUX_FUNCTION(usb0),
- UNIPHIER_PINMUX_FUNCTION(usb1),
- UNIPHIER_PINMUX_FUNCTION(usb2),
- UNIPHIER_PINMUX_FUNCTION(usb3),
- UNIPHIER_PINMUX_FUNCTION(port),
- UNIPHIER_PINMUX_FUNCTION(xirq),
-};
-
-static struct uniphier_pinctrl_socdata proxstream2_pindata = {
- .groups = proxstream2_groups,
- .groups_count = ARRAY_SIZE(proxstream2_groups),
- .functions = proxstream2_functions,
- .functions_count = ARRAY_SIZE(proxstream2_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
-};
-
-static struct pinctrl_desc proxstream2_pinctrl_desc = {
- .name = DRIVER_NAME,
- .pins = proxstream2_pins,
- .npins = ARRAY_SIZE(proxstream2_pins),
- .owner = THIS_MODULE,
-};
-
-static int proxstream2_pinctrl_probe(struct platform_device *pdev)
-{
- return uniphier_pinctrl_probe(pdev, &proxstream2_pinctrl_desc,
- &proxstream2_pindata);
-}
-
-static const struct of_device_id proxstream2_pinctrl_match[] = {
- { .compatible = "socionext,proxstream2-pinctrl" },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, proxstream2_pinctrl_match);
-
-static struct platform_driver proxstream2_pinctrl_driver = {
- .probe = proxstream2_pinctrl_probe,
- .remove = uniphier_pinctrl_remove,
- .driver = {
- .name = DRIVER_NAME,
- .of_match_table = proxstream2_pinctrl_match,
- },
-};
-module_platform_driver(proxstream2_pinctrl_driver);
-
-MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
-MODULE_DESCRIPTION("UniPhier ProXstream2 pinctrl driver");
-MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-uniphier.h"
+
+#define DRIVER_NAME "ph1-ld4-pinctrl"
+
+static const struct pinctrl_pin_desc ph1_ld4_pins[] = {
+ UNIPHIER_PINCTRL_PIN(0, "EA1", UNIPHIER_PIN_IECTRL_NONE,
+ 8, UNIPHIER_PIN_DRV_4_8,
+ 8, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(1, "EA2", UNIPHIER_PIN_IECTRL_NONE,
+ 9, UNIPHIER_PIN_DRV_4_8,
+ 9, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(2, "EA3", UNIPHIER_PIN_IECTRL_NONE,
+ 10, UNIPHIER_PIN_DRV_4_8,
+ 10, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(3, "EA4", UNIPHIER_PIN_IECTRL_NONE,
+ 11, UNIPHIER_PIN_DRV_4_8,
+ 11, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(4, "EA5", UNIPHIER_PIN_IECTRL_NONE,
+ 12, UNIPHIER_PIN_DRV_4_8,
+ 12, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(5, "EA6", UNIPHIER_PIN_IECTRL_NONE,
+ 13, UNIPHIER_PIN_DRV_4_8,
+ 13, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(6, "EA7", UNIPHIER_PIN_IECTRL_NONE,
+ 14, UNIPHIER_PIN_DRV_4_8,
+ 14, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(7, "EA8", 0,
+ 15, UNIPHIER_PIN_DRV_4_8,
+ 15, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(8, "EA9", 0,
+ 16, UNIPHIER_PIN_DRV_4_8,
+ 16, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(9, "EA10", 0,
+ 17, UNIPHIER_PIN_DRV_4_8,
+ 17, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(10, "EA11", 0,
+ 18, UNIPHIER_PIN_DRV_4_8,
+ 18, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(11, "EA12", 0,
+ 19, UNIPHIER_PIN_DRV_4_8,
+ 19, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(12, "EA13", 0,
+ 20, UNIPHIER_PIN_DRV_4_8,
+ 20, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(13, "EA14", 0,
+ 21, UNIPHIER_PIN_DRV_4_8,
+ 21, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(14, "EA15", 0,
+ 22, UNIPHIER_PIN_DRV_4_8,
+ 22, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(15, "ECLK", UNIPHIER_PIN_IECTRL_NONE,
+ 23, UNIPHIER_PIN_DRV_4_8,
+ 23, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(16, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
+ 24, UNIPHIER_PIN_DRV_4_8,
+ 24, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(17, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
+ 25, UNIPHIER_PIN_DRV_4_8,
+ 25, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(18, "ES0", UNIPHIER_PIN_IECTRL_NONE,
+ 27, UNIPHIER_PIN_DRV_4_8,
+ 27, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(19, "ES1", UNIPHIER_PIN_IECTRL_NONE,
+ 28, UNIPHIER_PIN_DRV_4_8,
+ 28, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(20, "ES2", UNIPHIER_PIN_IECTRL_NONE,
+ 29, UNIPHIER_PIN_DRV_4_8,
+ 29, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(21, "XERST", UNIPHIER_PIN_IECTRL_NONE,
+ 38, UNIPHIER_PIN_DRV_4_8,
+ 38, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(22, "MMCCLK", UNIPHIER_PIN_IECTRL_NONE,
+ 0, UNIPHIER_PIN_DRV_8_12_16_20,
+ 146, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(23, "MMCCMD", UNIPHIER_PIN_IECTRL_NONE,
+ 4, UNIPHIER_PIN_DRV_8_12_16_20,
+ 147, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(24, "MMCDAT0", UNIPHIER_PIN_IECTRL_NONE,
+ 8, UNIPHIER_PIN_DRV_8_12_16_20,
+ 148, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(25, "MMCDAT1", UNIPHIER_PIN_IECTRL_NONE,
+ 12, UNIPHIER_PIN_DRV_8_12_16_20,
+ 149, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(26, "MMCDAT2", UNIPHIER_PIN_IECTRL_NONE,
+ 16, UNIPHIER_PIN_DRV_8_12_16_20,
+ 150, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(27, "MMCDAT3", UNIPHIER_PIN_IECTRL_NONE,
+ 20, UNIPHIER_PIN_DRV_8_12_16_20,
+ 151, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(28, "MMCDAT4", UNIPHIER_PIN_IECTRL_NONE,
+ 24, UNIPHIER_PIN_DRV_8_12_16_20,
+ 152, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(29, "MMCDAT5", UNIPHIER_PIN_IECTRL_NONE,
+ 28, UNIPHIER_PIN_DRV_8_12_16_20,
+ 153, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(30, "MMCDAT6", UNIPHIER_PIN_IECTRL_NONE,
+ 32, UNIPHIER_PIN_DRV_8_12_16_20,
+ 154, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(31, "MMCDAT7", UNIPHIER_PIN_IECTRL_NONE,
+ 36, UNIPHIER_PIN_DRV_8_12_16_20,
+ 155, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(32, "RMII_RXD0", 6,
+ 39, UNIPHIER_PIN_DRV_4_8,
+ 39, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(33, "RMII_RXD1", 6,
+ 40, UNIPHIER_PIN_DRV_4_8,
+ 40, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(34, "RMII_CRS_DV", 6,
+ 41, UNIPHIER_PIN_DRV_4_8,
+ 41, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(35, "RMII_RXER", 6,
+ 42, UNIPHIER_PIN_DRV_4_8,
+ 42, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(36, "RMII_REFCLK", 6,
+ 43, UNIPHIER_PIN_DRV_4_8,
+ 43, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(37, "RMII_TXD0", 6,
+ 44, UNIPHIER_PIN_DRV_4_8,
+ 44, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(38, "RMII_TXD1", 6,
+ 45, UNIPHIER_PIN_DRV_4_8,
+ 45, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(39, "RMII_TXEN", 6,
+ 46, UNIPHIER_PIN_DRV_4_8,
+ 46, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(40, "MDC", 6,
+ 47, UNIPHIER_PIN_DRV_4_8,
+ 47, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(41, "MDIO", 6,
+ 48, UNIPHIER_PIN_DRV_4_8,
+ 48, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(42, "MDIO_INTL", 6,
+ 49, UNIPHIER_PIN_DRV_4_8,
+ 49, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(43, "PHYRSTL", 6,
+ 50, UNIPHIER_PIN_DRV_4_8,
+ 50, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(44, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
+ 40, UNIPHIER_PIN_DRV_8_12_16_20,
+ 156, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(45, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
+ 44, UNIPHIER_PIN_DRV_8_12_16_20,
+ 157, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(46, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
+ 48, UNIPHIER_PIN_DRV_8_12_16_20,
+ 158, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(47, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
+ 52, UNIPHIER_PIN_DRV_8_12_16_20,
+ 159, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(48, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
+ 56, UNIPHIER_PIN_DRV_8_12_16_20,
+ 160, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(49, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
+ 60, UNIPHIER_PIN_DRV_8_12_16_20,
+ 161, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(50, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
+ 51, UNIPHIER_PIN_DRV_4_8,
+ 51, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(51, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
+ 52, UNIPHIER_PIN_DRV_4_8,
+ 52, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(52, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
+ 53, UNIPHIER_PIN_DRV_4_8,
+ 53, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(53, "USB0VBUS", 0,
+ 54, UNIPHIER_PIN_DRV_4_8,
+ 54, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(54, "USB0OD", 0,
+ 55, UNIPHIER_PIN_DRV_4_8,
+ 55, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(55, "USB1VBUS", 0,
+ 56, UNIPHIER_PIN_DRV_4_8,
+ 56, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(56, "USB1OD", 0,
+ 57, UNIPHIER_PIN_DRV_4_8,
+ 57, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(57, "PCRESET", 0,
+ 58, UNIPHIER_PIN_DRV_4_8,
+ 58, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(58, "PCREG", 0,
+ 59, UNIPHIER_PIN_DRV_4_8,
+ 59, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(59, "PCCE2", 0,
+ 60, UNIPHIER_PIN_DRV_4_8,
+ 60, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(60, "PCVS1", 0,
+ 61, UNIPHIER_PIN_DRV_4_8,
+ 61, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(61, "PCCD2", 0,
+ 62, UNIPHIER_PIN_DRV_4_8,
+ 62, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(62, "PCCD1", 0,
+ 63, UNIPHIER_PIN_DRV_4_8,
+ 63, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(63, "PCREADY", 0,
+ 64, UNIPHIER_PIN_DRV_4_8,
+ 64, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(64, "PCDOE", 0,
+ 65, UNIPHIER_PIN_DRV_4_8,
+ 65, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(65, "PCCE1", 0,
+ 66, UNIPHIER_PIN_DRV_4_8,
+ 66, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(66, "PCWE", 0,
+ 67, UNIPHIER_PIN_DRV_4_8,
+ 67, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(67, "PCOE", 0,
+ 68, UNIPHIER_PIN_DRV_4_8,
+ 68, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(68, "PCWAIT", 0,
+ 69, UNIPHIER_PIN_DRV_4_8,
+ 69, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(69, "PCIOWR", 0,
+ 70, UNIPHIER_PIN_DRV_4_8,
+ 70, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(70, "PCIORD", 0,
+ 71, UNIPHIER_PIN_DRV_4_8,
+ 71, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(71, "HS0DIN0", 0,
+ 72, UNIPHIER_PIN_DRV_4_8,
+ 72, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(72, "HS0DIN1", 0,
+ 73, UNIPHIER_PIN_DRV_4_8,
+ 73, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(73, "HS0DIN2", 0,
+ 74, UNIPHIER_PIN_DRV_4_8,
+ 74, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(74, "HS0DIN3", 0,
+ 75, UNIPHIER_PIN_DRV_4_8,
+ 75, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(75, "HS0DIN4", 0,
+ 76, UNIPHIER_PIN_DRV_4_8,
+ 76, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(76, "HS0DIN5", 0,
+ 77, UNIPHIER_PIN_DRV_4_8,
+ 77, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(77, "HS0DIN6", 0,
+ 78, UNIPHIER_PIN_DRV_4_8,
+ 78, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(78, "HS0DIN7", 0,
+ 79, UNIPHIER_PIN_DRV_4_8,
+ 79, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(79, "HS0BCLKIN", 0,
+ 80, UNIPHIER_PIN_DRV_4_8,
+ 80, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(80, "HS0VALIN", 0,
+ 81, UNIPHIER_PIN_DRV_4_8,
+ 81, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(81, "HS0SYNCIN", 0,
+ 82, UNIPHIER_PIN_DRV_4_8,
+ 82, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(82, "HSDOUT0", 0,
+ 83, UNIPHIER_PIN_DRV_4_8,
+ 83, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(83, "HSDOUT1", 0,
+ 84, UNIPHIER_PIN_DRV_4_8,
+ 84, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(84, "HSDOUT2", 0,
+ 85, UNIPHIER_PIN_DRV_4_8,
+ 85, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(85, "HSDOUT3", 0,
+ 86, UNIPHIER_PIN_DRV_4_8,
+ 86, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(86, "HSDOUT4", 0,
+ 87, UNIPHIER_PIN_DRV_4_8,
+ 87, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(87, "HSDOUT5", 0,
+ 88, UNIPHIER_PIN_DRV_4_8,
+ 88, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(88, "HSDOUT6", 0,
+ 89, UNIPHIER_PIN_DRV_4_8,
+ 89, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(89, "HSDOUT7", 0,
+ 90, UNIPHIER_PIN_DRV_4_8,
+ 90, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(90, "HSBCLKOUT", 0,
+ 91, UNIPHIER_PIN_DRV_4_8,
+ 91, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(91, "HSVALOUT", 0,
+ 92, UNIPHIER_PIN_DRV_4_8,
+ 92, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(92, "HSSYNCOUT", 0,
+ 93, UNIPHIER_PIN_DRV_4_8,
+ 93, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(93, "AGCI", 3,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 162, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(94, "AGCR", 4,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 163, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(95, "AGCBS", 5,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 164, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(96, "IECOUT", 0,
+ 94, UNIPHIER_PIN_DRV_4_8,
+ 94, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(97, "ASMCK", 0,
+ 95, UNIPHIER_PIN_DRV_4_8,
+ 95, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(98, "ABCKO", UNIPHIER_PIN_IECTRL_NONE,
+ 96, UNIPHIER_PIN_DRV_4_8,
+ 96, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(99, "ALRCKO", UNIPHIER_PIN_IECTRL_NONE,
+ 97, UNIPHIER_PIN_DRV_4_8,
+ 97, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(100, "ASDOUT0", UNIPHIER_PIN_IECTRL_NONE,
+ 98, UNIPHIER_PIN_DRV_4_8,
+ 98, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(101, "ARCOUT", 0,
+ 99, UNIPHIER_PIN_DRV_4_8,
+ 99, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(102, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(103, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(104, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(105, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(106, "DMDSDA0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(107, "DMDSCL0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(108, "DMDSDA1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(109, "DMDSCL1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(110, "SBO0", UNIPHIER_PIN_IECTRL_NONE,
+ 100, UNIPHIER_PIN_DRV_4_8,
+ 100, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(111, "SBI0", UNIPHIER_PIN_IECTRL_NONE,
+ 101, UNIPHIER_PIN_DRV_4_8,
+ 101, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(112, "HIN", 1,
+ -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(113, "VIN", 2,
+ -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(114, "TCON0", UNIPHIER_PIN_IECTRL_NONE,
+ 102, UNIPHIER_PIN_DRV_4_8,
+ 102, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(115, "TCON1", UNIPHIER_PIN_IECTRL_NONE,
+ 103, UNIPHIER_PIN_DRV_4_8,
+ 103, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(116, "TCON2", UNIPHIER_PIN_IECTRL_NONE,
+ 104, UNIPHIER_PIN_DRV_4_8,
+ 104, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(117, "TCON3", UNIPHIER_PIN_IECTRL_NONE,
+ 105, UNIPHIER_PIN_DRV_4_8,
+ 105, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(118, "TCON4", UNIPHIER_PIN_IECTRL_NONE,
+ 106, UNIPHIER_PIN_DRV_4_8,
+ 106, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(119, "TCON5", UNIPHIER_PIN_IECTRL_NONE,
+ 107, UNIPHIER_PIN_DRV_4_8,
+ 107, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(120, "TCON6", 0,
+ 108, UNIPHIER_PIN_DRV_4_8,
+ 108, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(121, "TCON7", 0,
+ 109, UNIPHIER_PIN_DRV_4_8,
+ 109, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(122, "PWMA", 0,
+ 110, UNIPHIER_PIN_DRV_4_8,
+ 110, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(123, "XIRQ1", 0,
+ 111, UNIPHIER_PIN_DRV_4_8,
+ 111, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(124, "XIRQ2", 0,
+ 112, UNIPHIER_PIN_DRV_4_8,
+ 112, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(125, "XIRQ3", 0,
+ 113, UNIPHIER_PIN_DRV_4_8,
+ 113, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(126, "XIRQ4", 0,
+ 114, UNIPHIER_PIN_DRV_4_8,
+ 114, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(127, "XIRQ5", 0,
+ 115, UNIPHIER_PIN_DRV_4_8,
+ 115, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(128, "XIRQ6", 0,
+ 116, UNIPHIER_PIN_DRV_4_8,
+ 116, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(129, "XIRQ7", 0,
+ 117, UNIPHIER_PIN_DRV_4_8,
+ 117, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(130, "XIRQ8", 0,
+ 118, UNIPHIER_PIN_DRV_4_8,
+ 118, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(131, "XIRQ9", 0,
+ 119, UNIPHIER_PIN_DRV_4_8,
+ 119, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(132, "XIRQ10", 0,
+ 120, UNIPHIER_PIN_DRV_4_8,
+ 120, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(133, "XIRQ11", 0,
+ 121, UNIPHIER_PIN_DRV_4_8,
+ 121, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(134, "XIRQ14", 0,
+ 122, UNIPHIER_PIN_DRV_4_8,
+ 122, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(135, "PORT00", 0,
+ 123, UNIPHIER_PIN_DRV_4_8,
+ 123, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(136, "PORT01", 0,
+ 124, UNIPHIER_PIN_DRV_4_8,
+ 124, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(137, "PORT02", 0,
+ 125, UNIPHIER_PIN_DRV_4_8,
+ 125, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(138, "PORT03", 0,
+ 126, UNIPHIER_PIN_DRV_4_8,
+ 126, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(139, "PORT04", 0,
+ 127, UNIPHIER_PIN_DRV_4_8,
+ 127, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(140, "PORT05", 0,
+ 128, UNIPHIER_PIN_DRV_4_8,
+ 128, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(141, "PORT06", 0,
+ 129, UNIPHIER_PIN_DRV_4_8,
+ 129, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(142, "PORT07", 0,
+ 130, UNIPHIER_PIN_DRV_4_8,
+ 130, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(143, "PORT10", 0,
+ 131, UNIPHIER_PIN_DRV_4_8,
+ 131, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(144, "PORT11", 0,
+ 132, UNIPHIER_PIN_DRV_4_8,
+ 132, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(145, "PORT12", 0,
+ 133, UNIPHIER_PIN_DRV_4_8,
+ 133, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(146, "PORT13", 0,
+ 134, UNIPHIER_PIN_DRV_4_8,
+ 134, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(147, "PORT14", 0,
+ 135, UNIPHIER_PIN_DRV_4_8,
+ 135, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(148, "PORT15", 0,
+ 136, UNIPHIER_PIN_DRV_4_8,
+ 136, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(149, "PORT16", 0,
+ 137, UNIPHIER_PIN_DRV_4_8,
+ 137, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(150, "PORT17", UNIPHIER_PIN_IECTRL_NONE,
+ 138, UNIPHIER_PIN_DRV_4_8,
+ 138, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(151, "PORT20", 0,
+ 139, UNIPHIER_PIN_DRV_4_8,
+ 139, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(152, "PORT21", 0,
+ 140, UNIPHIER_PIN_DRV_4_8,
+ 140, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(153, "PORT22", 0,
+ 141, UNIPHIER_PIN_DRV_4_8,
+ 141, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(154, "PORT23", 0,
+ 142, UNIPHIER_PIN_DRV_4_8,
+ 142, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(155, "PORT24", UNIPHIER_PIN_IECTRL_NONE,
+ 143, UNIPHIER_PIN_DRV_4_8,
+ 143, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(156, "PORT25", 0,
+ 144, UNIPHIER_PIN_DRV_4_8,
+ 144, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(157, "PORT26", 0,
+ 145, UNIPHIER_PIN_DRV_4_8,
+ 145, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(158, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
+ 31, UNIPHIER_PIN_DRV_4_8,
+ 31, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(159, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
+ 32, UNIPHIER_PIN_DRV_4_8,
+ 32, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(160, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
+ 33, UNIPHIER_PIN_DRV_4_8,
+ 33, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(161, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
+ 34, UNIPHIER_PIN_DRV_4_8,
+ 34, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(162, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
+ 35, UNIPHIER_PIN_DRV_4_8,
+ 35, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(163, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
+ 36, UNIPHIER_PIN_DRV_4_8,
+ 36, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(164, "NANDRYBY0", UNIPHIER_PIN_IECTRL_NONE,
+ 37, UNIPHIER_PIN_DRV_4_8,
+ 37, UNIPHIER_PIN_PULL_UP),
+};
+
+static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
+static const unsigned emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {102, 103};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {104, 105};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {108, 109};
+static const unsigned i2c2_muxvals[] = {2, 2};
+static const unsigned i2c3_pins[] = {108, 109};
+static const unsigned i2c3_muxvals[] = {3, 3};
+static const unsigned nand_pins[] = {24, 25, 26, 27, 28, 29, 30, 31, 158, 159,
+ 160, 161, 162, 163, 164};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {22, 23};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {85, 88};
+static const unsigned uart0_muxvals[] = {1, 1};
+static const unsigned uart1_pins[] = {155, 156};
+static const unsigned uart1_muxvals[] = {13, 13};
+static const unsigned uart1b_pins[] = {69, 70};
+static const unsigned uart1b_muxvals[] = {23, 23};
+static const unsigned uart2_pins[] = {128, 129};
+static const unsigned uart2_muxvals[] = {13, 13};
+static const unsigned uart3_pins[] = {110, 111};
+static const unsigned uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {53, 54};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {55, 56};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {155, 156};
+static const unsigned usb2_muxvals[] = {4, 4};
+static const unsigned usb2b_pins[] = {67, 68};
+static const unsigned usb2b_muxvals[] = {23, 23};
+static const unsigned port_range0_pins[] = {
+ 135, 136, 137, 138, 139, 140, 141, 142, /* PORT0x */
+ 143, 144, 145, 146, 147, 148, 149, 150, /* PORT1x */
+ 151, 152, 153, 154, 155, 156, 157, 0, /* PORT2x */
+ 1, 2, 3, 4, 5, 120, 121, 122, /* PORT3x */
+ 24, 25, 26, 27, 28, 29, 30, 31, /* PORT4x */
+ 40, 41, 42, 43, 44, 45, 46, 47, /* PORT5x */
+ 48, 49, 50, 51, 52, 53, 54, 55, /* PORT6x */
+ 56, 85, 84, 59, 82, 61, 64, 65, /* PORT7x */
+ 8, 9, 10, 11, 12, 13, 14, 15, /* PORT8x */
+ 66, 67, 68, 69, 70, 71, 72, 73, /* PORT9x */
+ 74, 75, 89, 86, 78, 79, 80, 81, /* PORT10x */
+ 60, 83, 58, 57, 88, 87, 77, 76, /* PORT11x */
+ 90, 91, 92, 93, 94, 95, 96, 97, /* PORT12x */
+ 98, 99, 100, 6, 101, 114, 115, 116, /* PORT13x */
+ 103, 108, 21, 22, 23, 117, 118, 119, /* PORT14x */
+};
+static const unsigned port_range0_muxvals[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, /* PORT0x */
+ 0, 0, 0, 0, 0, 0, 0, 0, /* PORT1x */
+ 0, 0, 0, 0, 0, 0, 0, 15, /* PORT2x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
+};
+static const unsigned port_range1_pins[] = {
+ 7, /* PORT166 */
+};
+static const unsigned port_range1_muxvals[] = {
+ 15, /* PORT166 */
+};
+static const unsigned xirq_range0_pins[] = {
+ 151, 123, 124, 125, 126, 127, 128, 129, /* XIRQ0-7 */
+ 130, 131, 132, 133, 62, /* XIRQ8-12 */
+};
+static const unsigned xirq_range0_muxvals[] = {
+ 14, 0, 0, 0, 0, 0, 0, 0, /* XIRQ0-7 */
+ 0, 0, 0, 0, 14, /* XIRQ8-12 */
+};
+static const unsigned xirq_range1_pins[] = {
+ 134, 63, /* XIRQ14-15 */
+};
+static const unsigned xirq_range1_muxvals[] = {
+ 0, 14, /* XIRQ14-15 */
+};
+
+static const struct uniphier_pinctrl_group ph1_ld4_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart1b),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb2b),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range0),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq_range0, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq_range0, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq_range0, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq_range0, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq_range0, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq_range0, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq_range0, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq_range0, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq_range0, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq_range0, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq_range0, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq_range0, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq_range0, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq_range1, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq_range1, 1),
+};
+
+static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const i2c0_groups[] = {"i2c0"};
+static const char * const i2c1_groups[] = {"i2c1"};
+static const char * const i2c2_groups[] = {"i2c2"};
+static const char * const i2c3_groups[] = {"i2c3"};
+static const char * const nand_groups[] = {"nand", "nand_cs1"};
+static const char * const sd_groups[] = {"sd"};
+static const char * const uart0_groups[] = {"uart0"};
+static const char * const uart1_groups[] = {"uart1", "uart1b"};
+static const char * const uart2_groups[] = {"uart2"};
+static const char * const uart3_groups[] = {"uart3"};
+static const char * const usb0_groups[] = {"usb0"};
+static const char * const usb1_groups[] = {"usb1"};
+static const char * const usb2_groups[] = {"usb2", "usb2b"};
+static const char * const port_groups[] = {
+ "port00", "port01", "port02", "port03",
+ "port04", "port05", "port06", "port07",
+ "port10", "port11", "port12", "port13",
+ "port14", "port15", "port16", "port17",
+ "port20", "port21", "port22", "port23",
+ "port24", "port25", "port26", "port27",
+ "port30", "port31", "port32", "port33",
+ "port34", "port35", "port36", "port37",
+ "port40", "port41", "port42", "port43",
+ "port44", "port45", "port46", "port47",
+ "port50", "port51", "port52", "port53",
+ "port54", "port55", "port56", "port57",
+ "port60", "port61", "port62", "port63",
+ "port64", "port65", "port66", "port67",
+ "port70", "port71", "port72", "port73",
+ "port74", "port75", "port76", "port77",
+ "port80", "port81", "port82", "port83",
+ "port84", "port85", "port86", "port87",
+ "port90", "port91", "port92", "port93",
+ "port94", "port95", "port96", "port97",
+ "port100", "port101", "port102", "port103",
+ "port104", "port105", "port106", "port107",
+ "port110", "port111", "port112", "port113",
+ "port114", "port115", "port116", "port117",
+ "port120", "port121", "port122", "port123",
+ "port124", "port125", "port126", "port127",
+ "port130", "port131", "port132", "port133",
+ "port134", "port135", "port136", "port137",
+ "port140", "port141", "port142", "port143",
+ "port144", "port145", "port146", "port147",
+ /* port150-164 missing */
+ /* none */ "port165",
+};
+static const char * const xirq_groups[] = {
+ "xirq0", "xirq1", "xirq2", "xirq3",
+ "xirq4", "xirq5", "xirq6", "xirq7",
+ "xirq8", "xirq9", "xirq10", "xirq11",
+ "xirq12", /* none*/ "xirq14", "xirq15",
+};
+
+static const struct uniphier_pinmux_function ph1_ld4_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(i2c0),
+ UNIPHIER_PINMUX_FUNCTION(i2c1),
+ UNIPHIER_PINMUX_FUNCTION(i2c2),
+ UNIPHIER_PINMUX_FUNCTION(i2c3),
+ UNIPHIER_PINMUX_FUNCTION(nand),
+ UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(uart0),
+ UNIPHIER_PINMUX_FUNCTION(uart1),
+ UNIPHIER_PINMUX_FUNCTION(uart2),
+ UNIPHIER_PINMUX_FUNCTION(uart3),
+ UNIPHIER_PINMUX_FUNCTION(usb0),
+ UNIPHIER_PINMUX_FUNCTION(usb1),
+ UNIPHIER_PINMUX_FUNCTION(usb2),
+ UNIPHIER_PINMUX_FUNCTION(port),
+ UNIPHIER_PINMUX_FUNCTION(xirq),
+};
+
+static struct uniphier_pinctrl_socdata ph1_ld4_pindata = {
+ .groups = ph1_ld4_groups,
+ .groups_count = ARRAY_SIZE(ph1_ld4_groups),
+ .functions = ph1_ld4_functions,
+ .functions_count = ARRAY_SIZE(ph1_ld4_functions),
+ .mux_bits = 8,
+ .reg_stride = 4,
+ .load_pinctrl = false,
+};
+
+static struct pinctrl_desc ph1_ld4_pinctrl_desc = {
+ .name = DRIVER_NAME,
+ .pins = ph1_ld4_pins,
+ .npins = ARRAY_SIZE(ph1_ld4_pins),
+ .owner = THIS_MODULE,
+};
+
+static int ph1_ld4_pinctrl_probe(struct platform_device *pdev)
+{
+ return uniphier_pinctrl_probe(pdev, &ph1_ld4_pinctrl_desc,
+ &ph1_ld4_pindata);
+}
+
+static const struct of_device_id ph1_ld4_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-ld4-pinctrl" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ph1_ld4_pinctrl_match);
+
+static struct platform_driver ph1_ld4_pinctrl_driver = {
+ .probe = ph1_ld4_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = ph1_ld4_pinctrl_match,
+ },
+};
+module_platform_driver(ph1_ld4_pinctrl_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-LD4 pinctrl driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-uniphier.h"
+
+#define DRIVER_NAME "ph1-ld6b-pinctrl"
+
+static const struct pinctrl_pin_desc ph1_ld6b_pins[] = {
+ UNIPHIER_PINCTRL_PIN(0, "ED0", UNIPHIER_PIN_IECTRL_NONE,
+ 0, UNIPHIER_PIN_DRV_4_8,
+ 0, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(1, "ED1", UNIPHIER_PIN_IECTRL_NONE,
+ 1, UNIPHIER_PIN_DRV_4_8,
+ 1, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(2, "ED2", UNIPHIER_PIN_IECTRL_NONE,
+ 2, UNIPHIER_PIN_DRV_4_8,
+ 2, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(3, "ED3", UNIPHIER_PIN_IECTRL_NONE,
+ 3, UNIPHIER_PIN_DRV_4_8,
+ 3, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(4, "ED4", UNIPHIER_PIN_IECTRL_NONE,
+ 4, UNIPHIER_PIN_DRV_4_8,
+ 4, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(5, "ED5", UNIPHIER_PIN_IECTRL_NONE,
+ 5, UNIPHIER_PIN_DRV_4_8,
+ 5, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(6, "ED6", UNIPHIER_PIN_IECTRL_NONE,
+ 6, UNIPHIER_PIN_DRV_4_8,
+ 6, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(7, "ED7", UNIPHIER_PIN_IECTRL_NONE,
+ 7, UNIPHIER_PIN_DRV_4_8,
+ 7, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(8, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
+ 8, UNIPHIER_PIN_DRV_4_8,
+ 8, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(9, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
+ 9, UNIPHIER_PIN_DRV_4_8,
+ 9, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(10, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
+ 10, UNIPHIER_PIN_DRV_4_8,
+ 10, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(11, "ES0", UNIPHIER_PIN_IECTRL_NONE,
+ 11, UNIPHIER_PIN_DRV_4_8,
+ 11, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(12, "ES1", UNIPHIER_PIN_IECTRL_NONE,
+ 12, UNIPHIER_PIN_DRV_4_8,
+ 12, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(13, "ES2", UNIPHIER_PIN_IECTRL_NONE,
+ 13, UNIPHIER_PIN_DRV_4_8,
+ 13, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(14, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
+ 14, UNIPHIER_PIN_DRV_4_8,
+ 14, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(15, "PCA00", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 15, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(16, "PCA01", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 16, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(17, "PCA02", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 17, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(18, "PCA03", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 18, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(19, "PCA04", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 19, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(20, "PCA05", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 20, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(21, "PCA06", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 21, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(22, "PCA07", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 22, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(23, "PCA08", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 23, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(24, "PCA09", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 24, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(25, "PCA10", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 25, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(26, "PCA11", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 26, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(27, "PCA12", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 27, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(28, "PCA13", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 28, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(29, "PCA14", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 29, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(30, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
+ 30, UNIPHIER_PIN_DRV_4_8,
+ 30, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(31, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
+ 31, UNIPHIER_PIN_DRV_4_8,
+ 31, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(32, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
+ 32, UNIPHIER_PIN_DRV_4_8,
+ 32, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(33, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
+ 33, UNIPHIER_PIN_DRV_4_8,
+ 33, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(34, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
+ 34, UNIPHIER_PIN_DRV_4_8,
+ 34, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(35, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
+ 35, UNIPHIER_PIN_DRV_4_8,
+ 35, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(36, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE,
+ 36, UNIPHIER_PIN_DRV_4_8,
+ 36, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(37, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE,
+ 37, UNIPHIER_PIN_DRV_4_8,
+ 37, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(38, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE,
+ 38, UNIPHIER_PIN_DRV_4_8,
+ 38, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(39, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
+ 39, UNIPHIER_PIN_DRV_4_8,
+ 39, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(40, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
+ 40, UNIPHIER_PIN_DRV_4_8,
+ 40, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(41, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
+ 41, UNIPHIER_PIN_DRV_4_8,
+ 41, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(42, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
+ 42, UNIPHIER_PIN_DRV_4_8,
+ 42, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(43, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
+ 43, UNIPHIER_PIN_DRV_4_8,
+ 43, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(44, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
+ 44, UNIPHIER_PIN_DRV_4_8,
+ 44, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(45, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
+ 45, UNIPHIER_PIN_DRV_4_8,
+ 45, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(46, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
+ 46, UNIPHIER_PIN_DRV_4_8,
+ 46, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
+ 0, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(48, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
+ 4, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(49, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
+ 8, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(50, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
+ 12, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(51, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
+ 16, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(52, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
+ 20, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(53, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 53, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(54, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 54, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(55, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 55, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(56, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 56, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(57, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 57, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(58, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 58, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(59, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 59, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(60, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 60, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(61, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 61, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(62, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 62, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(63, "USB3OD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 63, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(64, "HS0BCLKOUT", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 64, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(65, "HS0SYNCOUT", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 65, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(66, "HS0VALOUT", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 66, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(67, "HS0DOUT0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 67, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(68, "HS0DOUT1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 68, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(69, "HS0DOUT2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 69, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(70, "HS0DOUT3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 70, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(71, "HS0DOUT4", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 71, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(72, "HS0DOUT5", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 72, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(73, "HS0DOUT6", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 73, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(74, "HS0DOUT7", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 74, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(75, "HS1BCLKIN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 75, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(76, "HS1SYNCIN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 76, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(77, "HS1VALIN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 77, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(78, "HS1DIN0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 78, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(79, "HS1DIN1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 79, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(80, "HS1DIN2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 80, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(81, "HS1DIN3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 81, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(82, "HS1DIN4", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 82, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(83, "HS1DIN5", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 83, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(84, "HS1DIN6", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 84, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(85, "HS1DIN7", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 85, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(86, "HS2BCLKIN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 86, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(87, "HS2SYNCIN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 87, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(88, "HS2VALIN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 88, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(89, "HS2DIN0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 89, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(90, "HS2DIN1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 90, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(91, "HS2DIN2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 91, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(92, "HS2DIN3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 92, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(93, "HS2DIN4", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 93, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(94, "HS2DIN5", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 94, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(95, "HS2DIN6", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 95, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(96, "HS2DIN7", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 96, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(97, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 97, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(98, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 98, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(99, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 99, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(100, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 100, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(101, "AO1D0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 101, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(102, "AO1D1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 102, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(103, "AO1D2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 103, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(104, "AO1D3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 104, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(105, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 105, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(106, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 106, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(107, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 107, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(108, "AO2D0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 108, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(109, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 109, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(110, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 110, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(111, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 111, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(112, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 112, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(113, "SBO0", 0,
+ 113, UNIPHIER_PIN_DRV_4_8,
+ 113, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(114, "SBI0", 0,
+ 114, UNIPHIER_PIN_DRV_4_8,
+ 114, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(115, "TXD1", 0,
+ 115, UNIPHIER_PIN_DRV_4_8,
+ 115, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(116, "RXD1", 0,
+ 116, UNIPHIER_PIN_DRV_4_8,
+ 116, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(117, "PWSRA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 117, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(118, "XIRQ0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 118, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(119, "XIRQ1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 119, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(120, "XIRQ2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 120, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(121, "XIRQ3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 121, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(122, "XIRQ4", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 122, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(123, "XIRQ5", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 123, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(124, "XIRQ6", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 124, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(125, "XIRQ7", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 125, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(126, "XIRQ8", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 126, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(127, "PORT00", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 127, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(128, "PORT01", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 128, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(129, "PORT02", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 129, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(130, "PORT03", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 130, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(131, "PORT04", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 131, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(132, "PORT05", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 132, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(133, "PORT06", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 133, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(134, "PORT07", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 134, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(135, "PORT10", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 135, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(136, "PORT11", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 136, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(137, "PORT12", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 137, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(138, "PORT13", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 138, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(139, "PORT14", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 139, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(140, "PORT15", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 140, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(141, "PORT16", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 141, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(142, "LPST", UNIPHIER_PIN_IECTRL_NONE,
+ 142, UNIPHIER_PIN_DRV_4_8,
+ 142, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(143, "MDC", 0,
+ 143, UNIPHIER_PIN_DRV_4_8,
+ 143, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(144, "MDIO", 0,
+ 144, UNIPHIER_PIN_DRV_4_8,
+ 144, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(145, "MDIO_INTL", 0,
+ 145, UNIPHIER_PIN_DRV_4_8,
+ 145, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(146, "PHYRSTL", 0,
+ 146, UNIPHIER_PIN_DRV_4_8,
+ 146, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(147, "RGMII_RXCLK", 0,
+ 147, UNIPHIER_PIN_DRV_4_8,
+ 147, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(148, "RGMII_RXD0", 0,
+ 148, UNIPHIER_PIN_DRV_4_8,
+ 148, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(149, "RGMII_RXD1", 0,
+ 149, UNIPHIER_PIN_DRV_4_8,
+ 149, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(150, "RGMII_RXD2", 0,
+ 150, UNIPHIER_PIN_DRV_4_8,
+ 150, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(151, "RGMII_RXD3", 0,
+ 151, UNIPHIER_PIN_DRV_4_8,
+ 151, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(152, "RGMII_RXCTL", 0,
+ 152, UNIPHIER_PIN_DRV_4_8,
+ 152, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(153, "RGMII_TXCLK", 0,
+ 153, UNIPHIER_PIN_DRV_4_8,
+ 153, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(154, "RGMII_TXD0", 0,
+ 154, UNIPHIER_PIN_DRV_4_8,
+ 154, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(155, "RGMII_TXD1", 0,
+ 155, UNIPHIER_PIN_DRV_4_8,
+ 155, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(156, "RGMII_TXD2", 0,
+ 156, UNIPHIER_PIN_DRV_4_8,
+ 156, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(157, "RGMII_TXD3", 0,
+ 157, UNIPHIER_PIN_DRV_4_8,
+ 157, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(158, "RGMII_TXCTL", 0,
+ 158, UNIPHIER_PIN_DRV_4_8,
+ 158, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(159, "A_D_PCD00OUT", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 159, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(160, "A_D_PCD01OUT", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 160, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(161, "A_D_PCD02OUT", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 161, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(162, "A_D_PCD03OUT", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 162, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(163, "A_D_PCD04OUT", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 163, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(164, "A_D_PCD05OUT", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 164, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(165, "A_D_PCD06OUT", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 165, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(166, "A_D_PCD07OUT", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 166, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(167, "A_D_PCD00IN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 167, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(168, "A_D_PCD01IN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 168, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(169, "A_D_PCD02IN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 169, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(170, "A_D_PCD03IN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 170, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(171, "A_D_PCD04IN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 171, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(172, "A_D_PCD05IN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 172, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(173, "A_D_PCD06IN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 173, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(174, "A_D_PCD07IN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 174, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(175, "A_D_PCDNOE", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 175, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(176, "A_D_PC0READY", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 176, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(177, "A_D_PC0CD1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 177, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(178, "A_D_PC0CD2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 178, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(179, "A_D_PC0WAIT", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 179, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(180, "A_D_PC0RESET", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 180, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(181, "A_D_PC0CE1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 181, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(182, "A_D_PC0WE", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 182, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(183, "A_D_PC0OE", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 183, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(184, "A_D_PC0IOWR", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 184, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(185, "A_D_PC0IORD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 185, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(186, "A_D_PC0NOE", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 186, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(187, "A_D_HS0BCLKIN", 0,
+ 187, UNIPHIER_PIN_DRV_4_8,
+ 187, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(188, "A_D_HS0SYNCIN", 0,
+ 188, UNIPHIER_PIN_DRV_4_8,
+ 188, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(189, "A_D_HS0VALIN", 0,
+ 189, UNIPHIER_PIN_DRV_4_8,
+ 189, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(190, "A_D_HS0DIN0", 0,
+ 190, UNIPHIER_PIN_DRV_4_8,
+ 190, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(191, "A_D_HS0DIN1", 0,
+ 191, UNIPHIER_PIN_DRV_4_8,
+ 191, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(192, "A_D_HS0DIN2", 0,
+ 192, UNIPHIER_PIN_DRV_4_8,
+ 192, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(193, "A_D_HS0DIN3", 0,
+ 193, UNIPHIER_PIN_DRV_4_8,
+ 193, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(194, "A_D_HS0DIN4", 0,
+ 194, UNIPHIER_PIN_DRV_4_8,
+ 194, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(195, "A_D_HS0DIN5", 0,
+ 195, UNIPHIER_PIN_DRV_4_8,
+ 195, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(196, "A_D_HS0DIN6", 0,
+ 196, UNIPHIER_PIN_DRV_4_8,
+ 196, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(197, "A_D_HS0DIN7", 0,
+ 197, UNIPHIER_PIN_DRV_4_8,
+ 197, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(198, "A_D_AO1ARC", 0,
+ 198, UNIPHIER_PIN_DRV_4_8,
+ 198, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(199, "A_D_SPIXRST", UNIPHIER_PIN_IECTRL_NONE,
+ 199, UNIPHIER_PIN_DRV_4_8,
+ 199, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(200, "A_D_SPISCLK0", UNIPHIER_PIN_IECTRL_NONE,
+ 200, UNIPHIER_PIN_DRV_4_8,
+ 200, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(201, "A_D_SPITXD0", UNIPHIER_PIN_IECTRL_NONE,
+ 201, UNIPHIER_PIN_DRV_4_8,
+ 201, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(202, "A_D_SPIRXD0", UNIPHIER_PIN_IECTRL_NONE,
+ 202, UNIPHIER_PIN_DRV_4_8,
+ 202, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(203, "A_D_DMDCLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 203, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(204, "A_D_DMDPSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 204, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(205, "A_D_DMDVAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 205, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(206, "A_D_DMDDATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 206, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(207, "A_D_HDMIRXXIRQ", 0,
+ 207, UNIPHIER_PIN_DRV_4_8,
+ 207, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(208, "A_D_VBIXIRQ", 0,
+ 208, UNIPHIER_PIN_DRV_4_8,
+ 208, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(209, "A_D_HDMITXXIRQ", 0,
+ 209, UNIPHIER_PIN_DRV_4_8,
+ 209, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(210, "A_D_DMDIRQ", UNIPHIER_PIN_IECTRL_NONE,
+ 210, UNIPHIER_PIN_DRV_4_8,
+ 210, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(211, "A_D_SPICIRQ", UNIPHIER_PIN_IECTRL_NONE,
+ 211, UNIPHIER_PIN_DRV_4_8,
+ 211, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(212, "A_D_SPIBIRQ", UNIPHIER_PIN_IECTRL_NONE,
+ 212, UNIPHIER_PIN_DRV_4_8,
+ 212, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(213, "A_D_BESDAOUT", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 213, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(214, "A_D_BESDAIN", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 214, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(215, "A_D_BESCLOUT", UNIPHIER_PIN_IECTRL_NONE,
+ 215, UNIPHIER_PIN_DRV_4_8,
+ 215, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(216, "A_D_VDACCLKOUT", 0,
+ 216, UNIPHIER_PIN_DRV_4_8,
+ 216, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(217, "A_D_VDACDOUT5", 0,
+ 217, UNIPHIER_PIN_DRV_4_8,
+ 217, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(218, "A_D_VDACDOUT6", 0,
+ 218, UNIPHIER_PIN_DRV_4_8,
+ 218, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(219, "A_D_VDACDOUT7", 0,
+ 219, UNIPHIER_PIN_DRV_4_8,
+ 219, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(220, "A_D_VDACDOUT8", 0,
+ 220, UNIPHIER_PIN_DRV_4_8,
+ 220, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(221, "A_D_VDACDOUT9", 0,
+ 221, UNIPHIER_PIN_DRV_4_8,
+ 221, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(222, "A_D_SIFBCKIN", 0,
+ 222, UNIPHIER_PIN_DRV_4_8,
+ 222, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(223, "A_D_SIFLRCKIN", 0,
+ 223, UNIPHIER_PIN_DRV_4_8,
+ 223, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(224, "A_D_SIFDIN", 0,
+ 224, UNIPHIER_PIN_DRV_4_8,
+ 224, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(225, "A_D_LIBCKOUT", 0,
+ 225, UNIPHIER_PIN_DRV_4_8,
+ 225, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(226, "A_D_LILRCKOUT", 0,
+ 226, UNIPHIER_PIN_DRV_4_8,
+ 226, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(227, "A_D_LIDIN", 0,
+ 227, UNIPHIER_PIN_DRV_4_8,
+ 227, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(228, "A_D_LODOUT", 0,
+ 228, UNIPHIER_PIN_DRV_4_8,
+ 228, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(229, "A_D_HPDOUT", 0,
+ 229, UNIPHIER_PIN_DRV_4_8,
+ 229, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(230, "A_D_MCLK", 0,
+ 230, UNIPHIER_PIN_DRV_4_8,
+ 230, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(231, "A_D_A2PLLREFOUT", 0,
+ 231, UNIPHIER_PIN_DRV_4_8,
+ 231, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(232, "A_D_HDMI3DSDAOUT", 0,
+ 232, UNIPHIER_PIN_DRV_4_8,
+ 232, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(233, "A_D_HDMI3DSDAIN", 0,
+ 233, UNIPHIER_PIN_DRV_4_8,
+ 233, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(234, "A_D_HDMI3DSCLIN", 0,
+ 234, UNIPHIER_PIN_DRV_4_8,
+ 234, UNIPHIER_PIN_PULL_DOWN),
+};
+
+static const unsigned adinter_pins[] = {
+ 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172,
+ 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186,
+ 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200,
+ 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
+ 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
+ 229, 230, 231, 232, 233, 234,
+};
+static const unsigned adinter_muxvals[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0,
+};
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {109, 110};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {111, 112};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {115, 116};
+static const unsigned i2c2_muxvals[] = {1, 1};
+static const unsigned i2c3_pins[] = {118, 119};
+static const unsigned i2c3_muxvals[] = {1, 1};
+static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
+ 42, 43, 44, 45, 46};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {37, 38};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {135, 136};
+static const unsigned uart0_muxvals[] = {3, 3};
+static const unsigned uart0b_pins[] = {11, 12};
+static const unsigned uart0b_muxvals[] = {2, 2};
+static const unsigned uart1_pins[] = {115, 116};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart1b_pins[] = {113, 114};
+static const unsigned uart1b_muxvals[] = {1, 1};
+static const unsigned uart2_pins[] = {113, 114};
+static const unsigned uart2_muxvals[] = {2, 2};
+static const unsigned uart2b_pins[] = {86, 87};
+static const unsigned uart2b_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {56, 57};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {58, 59};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {60, 61};
+static const unsigned usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {62, 63};
+static const unsigned usb3_muxvals[] = {0, 0};
+static const unsigned port_range0_pins[] = {
+ 127, 128, 129, 130, 131, 132, 133, 134, /* PORT0x */
+ 135, 136, 137, 138, 139, 140, 141, 142, /* PORT1x */
+ 0, 1, 2, 3, 4, 5, 6, 7, /* PORT2x */
+ 8, 9, 10, 11, 12, 13, 14, 15, /* PORT3x */
+ 16, 17, 18, 19, 21, 22, 23, 24, /* PORT4x */
+ 25, 30, 31, 32, 33, 34, 35, 36, /* PORT5x */
+ 37, 38, 39, 40, 41, 42, 43, 44, /* PORT6x */
+ 45, 46, 47, 48, 49, 50, 51, 52, /* PORT7x */
+ 53, 54, 55, 56, 57, 58, 59, 60, /* PORT8x */
+ 61, 62, 63, 64, 65, 66, 67, 68, /* PORT9x */
+ 69, 70, 71, 76, 77, 78, 79, 80, /* PORT10x */
+};
+static const unsigned port_range0_muxvals[] = {
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
+};
+static const unsigned port_range1_pins[] = {
+ 81, 82, 83, 84, 85, 86, 87, 88, /* PORT12x */
+ 89, 90, 95, 96, 97, 98, 99, 100, /* PORT13x */
+ 101, 102, 103, 104, 105, 106, 107, 108, /* PORT14x */
+ 118, 119, 120, 121, 122, 123, 124, 125, /* PORT15x */
+ 126, 72, 73, 92, 177, 93, 94, 176, /* PORT16x */
+ 74, 91, 27, 28, 29, 75, 20, 26, /* PORT17x */
+ 109, 110, 111, 112, 113, 114, 115, 116, /* PORT18x */
+ 117, 143, 144, 145, 146, 147, 148, 149, /* PORT19x */
+ 150, 151, 152, 153, 154, 155, 156, 157, /* PORT20x */
+ 158, 159, 160, 161, 162, 163, 164, 165, /* PORT21x */
+ 166, 178, 179, 180, 181, 182, 183, 184, /* PORT22x */
+ 185, 187, 188, 189, 190, 191, 192, 193, /* PORT23x */
+ 194, 195, 196, 197, 198, 199, 200, 201, /* PORT24x */
+ 202, 203, 204, 205, 206, 207, 208, 209, /* PORT25x */
+ 210, 211, 212, 213, 214, 215, 216, 217, /* PORT26x */
+ 218, 219, 220, 221, 223, 224, 225, 226, /* PORT27x */
+ 227, 228, 229, 230, 231, 232, 233, 234, /* PORT28x */
+};
+static const unsigned port_range1_muxvals[] = {
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT15x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT16x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT17x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */
+};
+static const unsigned xirq_pins[] = {
+ 118, 119, 120, 121, 122, 123, 124, 125, /* XIRQ0-7 */
+ 126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */
+ 74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */
+};
+static const unsigned xirq_muxvals[] = {
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */
+};
+
+static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(adinter),
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart0b),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart1b),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart2b),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb3),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range1, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range1, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range1, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range1, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range1, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range1, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range1, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range1, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range1, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range1, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range1, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range1, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range1, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range1, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range1, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range1, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range1, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range1, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range1, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range1, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range1, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range1, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port150, port_range1, 24),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port151, port_range1, 25),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port152, port_range1, 26),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port153, port_range1, 27),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port154, port_range1, 28),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port155, port_range1, 29),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port156, port_range1, 30),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port157, port_range1, 31),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port160, port_range1, 32),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port161, port_range1, 33),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port162, port_range1, 34),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port163, port_range1, 35),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port164, port_range1, 36),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 37),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range1, 38),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port167, port_range1, 39),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port170, port_range1, 40),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port171, port_range1, 41),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port172, port_range1, 42),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port173, port_range1, 43),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port174, port_range1, 44),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 45),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 46),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 47),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 48),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 49),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 50),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 51),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 52),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 53),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 54),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 55),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 56),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 57),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 58),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 59),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 60),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 61),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 62),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 63),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 64),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 65),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 66),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 67),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 68),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 69),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 70),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 71),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 72),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 73),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 74),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 75),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 76),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 77),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 78),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 79),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 80),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 81),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 82),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 83),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 84),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 85),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 86),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 87),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 88),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 89),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 90),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 91),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 92),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 93),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 94),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 95),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 96),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 97),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 98),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 99),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 100),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 101),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 102),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 103),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 104),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 105),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 106),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 107),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 108),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 109),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 110),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 111),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 112),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 113),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 114),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 115),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 116),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 117),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 118),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 119),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 120),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 121),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 122),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 123),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 124),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 125),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 126),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 127),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 128),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 129),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 130),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 131),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 132),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 133),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 134),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 135),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23),
+};
+
+static const char * const adinter_groups[] = {"adinter"};
+static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const i2c0_groups[] = {"i2c0"};
+static const char * const i2c1_groups[] = {"i2c1"};
+static const char * const i2c2_groups[] = {"i2c2"};
+static const char * const i2c3_groups[] = {"i2c3"};
+static const char * const nand_groups[] = {"nand", "nand_cs1"};
+static const char * const sd_groups[] = {"sd"};
+static const char * const uart0_groups[] = {"uart0", "uart0b"};
+static const char * const uart1_groups[] = {"uart1", "uart1b"};
+static const char * const uart2_groups[] = {"uart2", "uart2b"};
+static const char * const usb0_groups[] = {"usb0"};
+static const char * const usb1_groups[] = {"usb1"};
+static const char * const usb2_groups[] = {"usb2"};
+static const char * const usb3_groups[] = {"usb3"};
+static const char * const port_groups[] = {
+ "port00", "port01", "port02", "port03",
+ "port04", "port05", "port06", "port07",
+ "port10", "port11", "port12", "port13",
+ "port14", "port15", "port16", "port17",
+ "port20", "port21", "port22", "port23",
+ "port24", "port25", "port26", "port27",
+ "port30", "port31", "port32", "port33",
+ "port34", "port35", "port36", "port37",
+ "port40", "port41", "port42", "port43",
+ "port44", "port45", "port46", "port47",
+ "port50", "port51", "port52", "port53",
+ "port54", "port55", "port56", "port57",
+ "port60", "port61", "port62", "port63",
+ "port64", "port65", "port66", "port67",
+ "port70", "port71", "port72", "port73",
+ "port74", "port75", "port76", "port77",
+ "port80", "port81", "port82", "port83",
+ "port84", "port85", "port86", "port87",
+ "port90", "port91", "port92", "port93",
+ "port94", "port95", "port96", "port97",
+ "port100", "port101", "port102", "port103",
+ "port104", "port105", "port106", "port107",
+ /* port110-117 missing */
+ "port120", "port121", "port122", "port123",
+ "port124", "port125", "port126", "port127",
+ "port130", "port131", "port132", "port133",
+ "port134", "port135", "port136", "port137",
+ "port140", "port141", "port142", "port143",
+ "port144", "port145", "port146", "port147",
+ "port150", "port151", "port152", "port153",
+ "port154", "port155", "port156", "port157",
+ "port160", "port161", "port162", "port163",
+ "port164", "port165", "port166", "port167",
+ "port170", "port171", "port172", "port173",
+ "port174", "port175", "port176", "port177",
+ "port180", "port181", "port182", "port183",
+ "port184", "port185", "port186", "port187",
+ "port190", "port191", "port192", "port193",
+ "port194", "port195", "port196", "port197",
+ "port200", "port201", "port202", "port203",
+ "port204", "port205", "port206", "port207",
+ "port210", "port211", "port212", "port213",
+ "port214", "port215", "port216", "port217",
+ "port220", "port221", "port222", "port223",
+ "port224", "port225", "port226", "port227",
+ "port230", "port231", "port232", "port233",
+ "port234", "port235", "port236", "port237",
+ "port240", "port241", "port242", "port243",
+ "port244", "port245", "port246", "port247",
+ "port250", "port251", "port252", "port253",
+ "port254", "port255", "port256", "port257",
+ "port260", "port261", "port262", "port263",
+ "port264", "port265", "port266", "port267",
+ "port270", "port271", "port272", "port273",
+ "port274", "port275", "port276", "port277",
+ "port280", "port281", "port282", "port283",
+ "port284", "port285", "port286", "port287",
+};
+static const char * const xirq_groups[] = {
+ "xirq0", "xirq1", "xirq2", "xirq3",
+ "xirq4", "xirq5", "xirq6", "xirq7",
+ "xirq8", "xirq9", "xirq10", "xirq11",
+ "xirq12", "xirq13", "xirq14", "xirq15",
+ "xirq16", "xirq17", "xirq18", "xirq19",
+ "xirq20", "xirq21", "xirq22", "xirq23",
+};
+
+static const struct uniphier_pinmux_function ph1_ld6b_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(adinter), /* Achip-Dchip interconnect */
+ UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(i2c0),
+ UNIPHIER_PINMUX_FUNCTION(i2c1),
+ UNIPHIER_PINMUX_FUNCTION(i2c2),
+ UNIPHIER_PINMUX_FUNCTION(i2c3),
+ UNIPHIER_PINMUX_FUNCTION(nand),
+ UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(uart0),
+ UNIPHIER_PINMUX_FUNCTION(uart1),
+ UNIPHIER_PINMUX_FUNCTION(uart2),
+ UNIPHIER_PINMUX_FUNCTION(usb0),
+ UNIPHIER_PINMUX_FUNCTION(usb1),
+ UNIPHIER_PINMUX_FUNCTION(usb2),
+ UNIPHIER_PINMUX_FUNCTION(usb3),
+ UNIPHIER_PINMUX_FUNCTION(port),
+ UNIPHIER_PINMUX_FUNCTION(xirq),
+};
+
+static struct uniphier_pinctrl_socdata ph1_ld6b_pindata = {
+ .groups = ph1_ld6b_groups,
+ .groups_count = ARRAY_SIZE(ph1_ld6b_groups),
+ .functions = ph1_ld6b_functions,
+ .functions_count = ARRAY_SIZE(ph1_ld6b_functions),
+ .mux_bits = 8,
+ .reg_stride = 4,
+ .load_pinctrl = false,
+};
+
+static struct pinctrl_desc ph1_ld6b_pinctrl_desc = {
+ .name = DRIVER_NAME,
+ .pins = ph1_ld6b_pins,
+ .npins = ARRAY_SIZE(ph1_ld6b_pins),
+ .owner = THIS_MODULE,
+};
+
+static int ph1_ld6b_pinctrl_probe(struct platform_device *pdev)
+{
+ return uniphier_pinctrl_probe(pdev, &ph1_ld6b_pinctrl_desc,
+ &ph1_ld6b_pindata);
+}
+
+static const struct of_device_id ph1_ld6b_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-ld6b-pinctrl" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ph1_ld6b_pinctrl_match);
+
+static struct platform_driver ph1_ld6b_pinctrl_driver = {
+ .probe = ph1_ld6b_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = ph1_ld6b_pinctrl_match,
+ },
+};
+module_platform_driver(ph1_ld6b_pinctrl_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-LD6b pinctrl driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program5 is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-uniphier.h"
+
+#define DRIVER_NAME "ph1-pro4-pinctrl"
+
+static const struct pinctrl_pin_desc ph1_pro4_pins[] = {
+ UNIPHIER_PINCTRL_PIN(0, "CK24O", UNIPHIER_PIN_IECTRL_NONE,
+ 0, UNIPHIER_PIN_DRV_4_8,
+ 0, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(1, "VC27A", UNIPHIER_PIN_IECTRL_NONE,
+ 1, UNIPHIER_PIN_DRV_4_8,
+ 1, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(2, "CK27AI", UNIPHIER_PIN_IECTRL_NONE,
+ 2, UNIPHIER_PIN_DRV_4_8,
+ 2, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(3, "CK27AO", UNIPHIER_PIN_IECTRL_NONE,
+ 3, UNIPHIER_PIN_DRV_4_8,
+ 3, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(4, "CKSEL", UNIPHIER_PIN_IECTRL_NONE,
+ 4, UNIPHIER_PIN_DRV_4_8,
+ 4, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(5, "CK27AV", UNIPHIER_PIN_IECTRL_NONE,
+ 5, UNIPHIER_PIN_DRV_4_8,
+ 5, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(6, "AEXCKA", UNIPHIER_PIN_IECTRL_NONE,
+ 6, UNIPHIER_PIN_DRV_4_8,
+ 6, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(7, "ASEL", UNIPHIER_PIN_IECTRL_NONE,
+ 7, UNIPHIER_PIN_DRV_4_8,
+ 7, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(8, "ARCRESET", UNIPHIER_PIN_IECTRL_NONE,
+ 8, UNIPHIER_PIN_DRV_4_8,
+ 8, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(9, "ARCUNLOCK", UNIPHIER_PIN_IECTRL_NONE,
+ 9, UNIPHIER_PIN_DRV_4_8,
+ 9, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(10, "XSRST", UNIPHIER_PIN_IECTRL_NONE,
+ 10, UNIPHIER_PIN_DRV_4_8,
+ 10, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(11, "XNMIRQ", UNIPHIER_PIN_IECTRL_NONE,
+ 11, UNIPHIER_PIN_DRV_4_8,
+ 11, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(12, "XSCIRQ", UNIPHIER_PIN_IECTRL_NONE,
+ 12, UNIPHIER_PIN_DRV_4_8,
+ 12, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(13, "EXTRG", UNIPHIER_PIN_IECTRL_NONE,
+ 13, UNIPHIER_PIN_DRV_4_8,
+ 13, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(14, "TRCCLK", UNIPHIER_PIN_IECTRL_NONE,
+ 14, UNIPHIER_PIN_DRV_4_8,
+ 14, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(15, "TRCCTL", UNIPHIER_PIN_IECTRL_NONE,
+ 15, UNIPHIER_PIN_DRV_4_8,
+ 15, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(16, "TRCD0", UNIPHIER_PIN_IECTRL_NONE,
+ 16, UNIPHIER_PIN_DRV_4_8,
+ 16, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(17, "TRCD1", UNIPHIER_PIN_IECTRL_NONE,
+ 17, UNIPHIER_PIN_DRV_4_8,
+ 17, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(18, "TRCD2", UNIPHIER_PIN_IECTRL_NONE,
+ 18, UNIPHIER_PIN_DRV_4_8,
+ 18, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(19, "TRCD3", UNIPHIER_PIN_IECTRL_NONE,
+ 19, UNIPHIER_PIN_DRV_4_8,
+ 19, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(20, "TRCD4", UNIPHIER_PIN_IECTRL_NONE,
+ 20, UNIPHIER_PIN_DRV_4_8,
+ 20, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(21, "TRCD5", UNIPHIER_PIN_IECTRL_NONE,
+ 21, UNIPHIER_PIN_DRV_4_8,
+ 21, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(22, "TRCD6", UNIPHIER_PIN_IECTRL_NONE,
+ 22, UNIPHIER_PIN_DRV_4_8,
+ 22, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(23, "TRCD7", UNIPHIER_PIN_IECTRL_NONE,
+ 23, UNIPHIER_PIN_DRV_4_8,
+ 23, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(24, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
+ 24, UNIPHIER_PIN_DRV_4_8,
+ 24, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(25, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
+ 25, UNIPHIER_PIN_DRV_4_8,
+ 25, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(26, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
+ 26, UNIPHIER_PIN_DRV_4_8,
+ 26, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(27, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
+ 27, UNIPHIER_PIN_DRV_4_8,
+ 27, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(28, "ES0", UNIPHIER_PIN_IECTRL_NONE,
+ 28, UNIPHIER_PIN_DRV_4_8,
+ 28, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(29, "ES1", UNIPHIER_PIN_IECTRL_NONE,
+ 29, UNIPHIER_PIN_DRV_4_8,
+ 29, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(30, "ES2", UNIPHIER_PIN_IECTRL_NONE,
+ 30, UNIPHIER_PIN_DRV_4_8,
+ 30, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(31, "ED0", UNIPHIER_PIN_IECTRL_NONE,
+ 31, UNIPHIER_PIN_DRV_4_8,
+ 31, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(32, "ED1", UNIPHIER_PIN_IECTRL_NONE,
+ 32, UNIPHIER_PIN_DRV_4_8,
+ 32, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(33, "ED2", UNIPHIER_PIN_IECTRL_NONE,
+ 33, UNIPHIER_PIN_DRV_4_8,
+ 33, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(34, "ED3", UNIPHIER_PIN_IECTRL_NONE,
+ 34, UNIPHIER_PIN_DRV_4_8,
+ 34, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(35, "ED4", UNIPHIER_PIN_IECTRL_NONE,
+ 35, UNIPHIER_PIN_DRV_4_8,
+ 35, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(36, "ED5", UNIPHIER_PIN_IECTRL_NONE,
+ 36, UNIPHIER_PIN_DRV_4_8,
+ 36, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(37, "ED6", UNIPHIER_PIN_IECTRL_NONE,
+ 37, UNIPHIER_PIN_DRV_4_8,
+ 37, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(38, "ED7", UNIPHIER_PIN_IECTRL_NONE,
+ 38, UNIPHIER_PIN_DRV_4_8,
+ 38, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(39, "BOOTSWAP", UNIPHIER_PIN_IECTRL_NONE,
+ 39, UNIPHIER_PIN_DRV_NONE,
+ 39, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(40, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
+ 2, UNIPHIER_PIN_DRV_8_12_16_20,
+ 40, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(41, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
+ 3, UNIPHIER_PIN_DRV_8_12_16_20,
+ 41, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(42, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
+ 4, UNIPHIER_PIN_DRV_8_12_16_20,
+ 42, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(43, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
+ 5, UNIPHIER_PIN_DRV_8_12_16_20,
+ 43, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(44, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
+ 6, UNIPHIER_PIN_DRV_8_12_16_20,
+ 44, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(45, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
+ 7, UNIPHIER_PIN_DRV_8_12_16_20,
+ 45, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(46, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
+ 8, UNIPHIER_PIN_DRV_8_12_16_20,
+ 46, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(47, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
+ 9, UNIPHIER_PIN_DRV_8_12_16_20,
+ 47, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(48, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
+ 48, UNIPHIER_PIN_DRV_4_8,
+ 48, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(49, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
+ 49, UNIPHIER_PIN_DRV_4_8,
+ 49, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(50, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
+ 50, UNIPHIER_PIN_DRV_4_8,
+ 50, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(51, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
+ 0, UNIPHIER_PIN_DRV_8_12_16_20,
+ 51, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(52, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
+ 52, UNIPHIER_PIN_DRV_4_8,
+ 52, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(53, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
+ 1, UNIPHIER_PIN_DRV_8_12_16_20,
+ 53, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(54, "NRYBY0", UNIPHIER_PIN_IECTRL_NONE,
+ 54, UNIPHIER_PIN_DRV_4_8,
+ 54, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(55, "DMDSCLTST", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_NONE,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(56, "DMDSDATST", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(57, "AGCI0", 3,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 55, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(58, "DMDSCL0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(59, "DMDSDA0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(60, "AGCBS0", 5,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 56, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(61, "DMDSCL1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(62, "DMDSDA1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(63, "ANTSHORT", UNIPHIER_PIN_IECTRL_NONE,
+ 57, UNIPHIER_PIN_DRV_4_8,
+ 57, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(64, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE,
+ 58, UNIPHIER_PIN_DRV_4_8,
+ 58, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(65, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE,
+ 59, UNIPHIER_PIN_DRV_4_8,
+ 59, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(66, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ 60, UNIPHIER_PIN_DRV_4_8,
+ 60, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(67, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE,
+ 61, UNIPHIER_PIN_DRV_4_8,
+ 61, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(68, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE,
+ 62, UNIPHIER_PIN_DRV_4_8,
+ 62, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(69, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE,
+ 63, UNIPHIER_PIN_DRV_4_8,
+ 63, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(70, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ 64, UNIPHIER_PIN_DRV_4_8,
+ 64, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(71, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE,
+ 65, UNIPHIER_PIN_DRV_4_8,
+ 65, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(72, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE,
+ 66, UNIPHIER_PIN_DRV_4_8,
+ 66, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(73, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE,
+ 67, UNIPHIER_PIN_DRV_4_8,
+ 67, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(74, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ 68, UNIPHIER_PIN_DRV_4_8,
+ 68, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(75, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE,
+ 69, UNIPHIER_PIN_DRV_4_8,
+ 69, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(76, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE,
+ 70, UNIPHIER_PIN_DRV_4_8,
+ 70, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(77, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE,
+ 71, UNIPHIER_PIN_DRV_4_8,
+ 71, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(78, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ 72, UNIPHIER_PIN_DRV_4_8,
+ 72, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(79, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE,
+ 73, UNIPHIER_PIN_DRV_4_8,
+ 73, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(80, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE,
+ 74, UNIPHIER_PIN_DRV_4_8,
+ 74, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(81, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE,
+ 75, UNIPHIER_PIN_DRV_4_8,
+ 75, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(82, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ 76, UNIPHIER_PIN_DRV_4_8,
+ 76, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(83, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE,
+ 77, UNIPHIER_PIN_DRV_4_8,
+ 77, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(84, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE,
+ 78, UNIPHIER_PIN_DRV_4_8,
+ 78, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(85, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE,
+ 79, UNIPHIER_PIN_DRV_4_8,
+ 79, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(86, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ 80, UNIPHIER_PIN_DRV_4_8,
+ 80, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(87, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE,
+ 81, UNIPHIER_PIN_DRV_4_8,
+ 81, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(88, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE,
+ 82, UNIPHIER_PIN_DRV_4_8,
+ 82, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(89, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE,
+ 83, UNIPHIER_PIN_DRV_4_8,
+ 83, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(90, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ 84, UNIPHIER_PIN_DRV_4_8,
+ 84, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(91, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE,
+ 85, UNIPHIER_PIN_DRV_4_8,
+ 85, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(92, "CKFEO", UNIPHIER_PIN_IECTRL_NONE,
+ 86, UNIPHIER_PIN_DRV_4_8,
+ 86, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(93, "XFERST", UNIPHIER_PIN_IECTRL_NONE,
+ 87, UNIPHIER_PIN_DRV_4_8,
+ 87, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(94, "P_FE_ON", UNIPHIER_PIN_IECTRL_NONE,
+ 88, UNIPHIER_PIN_DRV_4_8,
+ 88, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(95, "P_TU0_ON", UNIPHIER_PIN_IECTRL_NONE,
+ 89, UNIPHIER_PIN_DRV_4_8,
+ 89, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(96, "XFEIRQ0", UNIPHIER_PIN_IECTRL_NONE,
+ 90, UNIPHIER_PIN_DRV_4_8,
+ 90, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(97, "XFEIRQ1", UNIPHIER_PIN_IECTRL_NONE,
+ 91, UNIPHIER_PIN_DRV_4_8,
+ 91, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(98, "XFEIRQ2", UNIPHIER_PIN_IECTRL_NONE,
+ 92, UNIPHIER_PIN_DRV_4_8,
+ 92, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(99, "XFEIRQ3", UNIPHIER_PIN_IECTRL_NONE,
+ 93, UNIPHIER_PIN_DRV_4_8,
+ 93, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(100, "XFEIRQ4", UNIPHIER_PIN_IECTRL_NONE,
+ 94, UNIPHIER_PIN_DRV_4_8,
+ 94, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(101, "XFEIRQ5", UNIPHIER_PIN_IECTRL_NONE,
+ 95, UNIPHIER_PIN_DRV_4_8,
+ 95, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(102, "XFEIRQ6", UNIPHIER_PIN_IECTRL_NONE,
+ 96, UNIPHIER_PIN_DRV_4_8,
+ 96, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(103, "SMTCLK0", UNIPHIER_PIN_IECTRL_NONE,
+ 97, UNIPHIER_PIN_DRV_4_8,
+ 97, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(104, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE,
+ 98, UNIPHIER_PIN_DRV_4_8,
+ 98, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(105, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE,
+ 99, UNIPHIER_PIN_DRV_4_8,
+ 99, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(106, "SMTD0", UNIPHIER_PIN_IECTRL_NONE,
+ 100, UNIPHIER_PIN_DRV_4_8,
+ 100, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(107, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE,
+ 101, UNIPHIER_PIN_DRV_4_8,
+ 101, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(108, "SMTDET0", UNIPHIER_PIN_IECTRL_NONE,
+ 102, UNIPHIER_PIN_DRV_4_8,
+ 102, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(109, "SMTCLK1", UNIPHIER_PIN_IECTRL_NONE,
+ 103, UNIPHIER_PIN_DRV_4_8,
+ 103, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(110, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE,
+ 104, UNIPHIER_PIN_DRV_4_8,
+ 104, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(111, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE,
+ 105, UNIPHIER_PIN_DRV_4_8,
+ 105, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(112, "SMTD1", UNIPHIER_PIN_IECTRL_NONE,
+ 106, UNIPHIER_PIN_DRV_4_8,
+ 106, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(113, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE,
+ 107, UNIPHIER_PIN_DRV_4_8,
+ 107, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(114, "SMTDET1", UNIPHIER_PIN_IECTRL_NONE,
+ 108, UNIPHIER_PIN_DRV_4_8,
+ 108, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(115, "XINTM", UNIPHIER_PIN_IECTRL_NONE,
+ 109, UNIPHIER_PIN_DRV_4_8,
+ 109, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(116, "SCLKM", UNIPHIER_PIN_IECTRL_NONE,
+ 110, UNIPHIER_PIN_DRV_4_8,
+ 110, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(117, "SBMTP", UNIPHIER_PIN_IECTRL_NONE,
+ 111, UNIPHIER_PIN_DRV_4_8,
+ 111, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(118, "SBPTM", UNIPHIER_PIN_IECTRL_NONE,
+ 112, UNIPHIER_PIN_DRV_4_8,
+ 112, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(119, "XMPREQ", UNIPHIER_PIN_IECTRL_NONE,
+ 113, UNIPHIER_PIN_DRV_4_8,
+ 113, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(120, "XINTP", UNIPHIER_PIN_IECTRL_NONE,
+ 114, UNIPHIER_PIN_DRV_4_8,
+ 114, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(121, "LPST", UNIPHIER_PIN_IECTRL_NONE,
+ 115, UNIPHIER_PIN_DRV_4_8,
+ 115, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(122, "SDBOOT", UNIPHIER_PIN_IECTRL_NONE,
+ 116, UNIPHIER_PIN_DRV_4_8,
+ 116, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(123, "BFAIL", UNIPHIER_PIN_IECTRL_NONE,
+ 117, UNIPHIER_PIN_DRV_4_8,
+ 117, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(124, "XFWE", UNIPHIER_PIN_IECTRL_NONE,
+ 118, UNIPHIER_PIN_DRV_4_8,
+ 118, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(125, "RF_COM_RDY", UNIPHIER_PIN_IECTRL_NONE,
+ 119, UNIPHIER_PIN_DRV_4_8,
+ 119, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(126, "XDIAG0", UNIPHIER_PIN_IECTRL_NONE,
+ 120, UNIPHIER_PIN_DRV_4_8,
+ 120, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(127, "RXD0", UNIPHIER_PIN_IECTRL_NONE,
+ 121, UNIPHIER_PIN_DRV_4_8,
+ 121, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(128, "TXD0", UNIPHIER_PIN_IECTRL_NONE,
+ 122, UNIPHIER_PIN_DRV_4_8,
+ 122, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(129, "RXD1", UNIPHIER_PIN_IECTRL_NONE,
+ 123, UNIPHIER_PIN_DRV_4_8,
+ 123, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(130, "TXD1", UNIPHIER_PIN_IECTRL_NONE,
+ 124, UNIPHIER_PIN_DRV_4_8,
+ 124, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(131, "RXD2", UNIPHIER_PIN_IECTRL_NONE,
+ 125, UNIPHIER_PIN_DRV_4_8,
+ 125, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(132, "TXD2", UNIPHIER_PIN_IECTRL_NONE,
+ 126, UNIPHIER_PIN_DRV_4_8,
+ 126, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(133, "SS0CS", UNIPHIER_PIN_IECTRL_NONE,
+ 127, UNIPHIER_PIN_DRV_4_8,
+ 127, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(134, "SS0CLK", UNIPHIER_PIN_IECTRL_NONE,
+ 128, UNIPHIER_PIN_DRV_4_8,
+ 128, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(135, "SS0DO", UNIPHIER_PIN_IECTRL_NONE,
+ 129, UNIPHIER_PIN_DRV_4_8,
+ 129, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(136, "SS0DI", UNIPHIER_PIN_IECTRL_NONE,
+ 130, UNIPHIER_PIN_DRV_4_8,
+ 130, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(137, "MS0CS0", UNIPHIER_PIN_IECTRL_NONE,
+ 131, UNIPHIER_PIN_DRV_4_8,
+ 131, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(138, "MS0CLK", UNIPHIER_PIN_IECTRL_NONE,
+ 132, UNIPHIER_PIN_DRV_4_8,
+ 132, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(139, "MS0DI", UNIPHIER_PIN_IECTRL_NONE,
+ 133, UNIPHIER_PIN_DRV_4_8,
+ 133, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(140, "MS0DO", UNIPHIER_PIN_IECTRL_NONE,
+ 134, UNIPHIER_PIN_DRV_4_8,
+ 134, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(141, "XMDMRST", UNIPHIER_PIN_IECTRL_NONE,
+ 135, UNIPHIER_PIN_DRV_4_8,
+ 135, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(142, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(143, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(144, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(145, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(146, "SCL2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(147, "SDA2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(148, "SCL3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(149, "SDA3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(150, "SD0DAT0", UNIPHIER_PIN_IECTRL_NONE,
+ 12, UNIPHIER_PIN_DRV_8_12_16_20,
+ 136, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(151, "SD0DAT1", UNIPHIER_PIN_IECTRL_NONE,
+ 13, UNIPHIER_PIN_DRV_8_12_16_20,
+ 137, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(152, "SD0DAT2", UNIPHIER_PIN_IECTRL_NONE,
+ 14, UNIPHIER_PIN_DRV_8_12_16_20,
+ 138, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(153, "SD0DAT3", UNIPHIER_PIN_IECTRL_NONE,
+ 15, UNIPHIER_PIN_DRV_8_12_16_20,
+ 139, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(154, "SD0CMD", UNIPHIER_PIN_IECTRL_NONE,
+ 11, UNIPHIER_PIN_DRV_8_12_16_20,
+ 141, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(155, "SD0CLK", UNIPHIER_PIN_IECTRL_NONE,
+ 10, UNIPHIER_PIN_DRV_8_12_16_20,
+ 140, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(156, "SD0CD", UNIPHIER_PIN_IECTRL_NONE,
+ 142, UNIPHIER_PIN_DRV_4_8,
+ 142, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(157, "SD0WP", UNIPHIER_PIN_IECTRL_NONE,
+ 143, UNIPHIER_PIN_DRV_4_8,
+ 143, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(158, "SD0VTCG", UNIPHIER_PIN_IECTRL_NONE,
+ 144, UNIPHIER_PIN_DRV_4_8,
+ 144, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(159, "CK25O", UNIPHIER_PIN_IECTRL_NONE,
+ 145, UNIPHIER_PIN_DRV_4_8,
+ 145, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(160, "RGMII_TXCLK", 6,
+ 146, UNIPHIER_PIN_DRV_4_8,
+ 146, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(161, "RGMII_TXD0", 6,
+ 147, UNIPHIER_PIN_DRV_4_8,
+ 147, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(162, "RGMII_TXD1", 6,
+ 148, UNIPHIER_PIN_DRV_4_8,
+ 148, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(163, "RGMII_TXD2", 6,
+ 149, UNIPHIER_PIN_DRV_4_8,
+ 149, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(164, "RGMII_TXD3", 6,
+ 150, UNIPHIER_PIN_DRV_4_8,
+ 150, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(165, "RGMII_TXCTL", 6,
+ 151, UNIPHIER_PIN_DRV_4_8,
+ 151, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(166, "MII_TXER", UNIPHIER_PIN_IECTRL_NONE,
+ 152, UNIPHIER_PIN_DRV_4_8,
+ 152, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(167, "RGMII_RXCLK", 6,
+ 153, UNIPHIER_PIN_DRV_4_8,
+ 153, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(168, "RGMII_RXD0", 6,
+ 154, UNIPHIER_PIN_DRV_4_8,
+ 154, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(169, "RGMII_RXD1", 6,
+ 155, UNIPHIER_PIN_DRV_4_8,
+ 155, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(170, "RGMII_RXD2", 6,
+ 156, UNIPHIER_PIN_DRV_4_8,
+ 156, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(171, "RGMII_RXD3", 6,
+ 157, UNIPHIER_PIN_DRV_4_8,
+ 157, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(172, "RGMII_RXCTL", 6,
+ 158, UNIPHIER_PIN_DRV_4_8,
+ 158, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(173, "MII_RXER", 6,
+ 159, UNIPHIER_PIN_DRV_4_8,
+ 159, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(174, "MII_CRS", 6,
+ 160, UNIPHIER_PIN_DRV_4_8,
+ 160, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(175, "MII_COL", 6,
+ 161, UNIPHIER_PIN_DRV_4_8,
+ 161, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(176, "MDC", 6,
+ 162, UNIPHIER_PIN_DRV_4_8,
+ 162, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(177, "MDIO", 6,
+ 163, UNIPHIER_PIN_DRV_4_8,
+ 163, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(178, "MDIO_INTL", 6,
+ 164, UNIPHIER_PIN_DRV_4_8,
+ 164, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(179, "XETH_RST", 6,
+ 165, UNIPHIER_PIN_DRV_4_8,
+ 165, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(180, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ 166, UNIPHIER_PIN_DRV_4_8,
+ 166, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(181, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
+ 167, UNIPHIER_PIN_DRV_4_8,
+ 167, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(182, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ 168, UNIPHIER_PIN_DRV_4_8,
+ 168, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(183, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
+ 169, UNIPHIER_PIN_DRV_4_8,
+ 169, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(184, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ 170, UNIPHIER_PIN_DRV_4_8,
+ 170, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(185, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
+ 171, UNIPHIER_PIN_DRV_4_8,
+ 171, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(186, "USB2ID", UNIPHIER_PIN_IECTRL_NONE,
+ 172, UNIPHIER_PIN_DRV_4_8,
+ 172, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(187, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ 173, UNIPHIER_PIN_DRV_4_8,
+ 173, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(188, "USB3OD", UNIPHIER_PIN_IECTRL_NONE,
+ 174, UNIPHIER_PIN_DRV_4_8,
+ 174, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(189, "LINKCLK", UNIPHIER_PIN_IECTRL_NONE,
+ 175, UNIPHIER_PIN_DRV_4_8,
+ 175, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(190, "LINKREQ", UNIPHIER_PIN_IECTRL_NONE,
+ 176, UNIPHIER_PIN_DRV_4_8,
+ 176, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(191, "LINKCTL0", UNIPHIER_PIN_IECTRL_NONE,
+ 177, UNIPHIER_PIN_DRV_4_8,
+ 177, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(192, "LINKCTL1", UNIPHIER_PIN_IECTRL_NONE,
+ 178, UNIPHIER_PIN_DRV_4_8,
+ 178, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(193, "LINKDT0", UNIPHIER_PIN_IECTRL_NONE,
+ 179, UNIPHIER_PIN_DRV_4_8,
+ 179, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(194, "LINKDT1", UNIPHIER_PIN_IECTRL_NONE,
+ 180, UNIPHIER_PIN_DRV_4_8,
+ 180, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(195, "LINKDT2", UNIPHIER_PIN_IECTRL_NONE,
+ 181, UNIPHIER_PIN_DRV_4_8,
+ 181, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(196, "LINKDT3", UNIPHIER_PIN_IECTRL_NONE,
+ 182, UNIPHIER_PIN_DRV_4_8,
+ 182, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(197, "LINKDT4", UNIPHIER_PIN_IECTRL_NONE,
+ 183, UNIPHIER_PIN_DRV_4_8,
+ 183, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(198, "LINKDT5", UNIPHIER_PIN_IECTRL_NONE,
+ 184, UNIPHIER_PIN_DRV_4_8,
+ 184, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(199, "LINKDT6", UNIPHIER_PIN_IECTRL_NONE,
+ 185, UNIPHIER_PIN_DRV_4_8,
+ 185, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(200, "LINKDT7", UNIPHIER_PIN_IECTRL_NONE,
+ 186, UNIPHIER_PIN_DRV_4_8,
+ 186, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(201, "CKDVO", UNIPHIER_PIN_IECTRL_NONE,
+ 187, UNIPHIER_PIN_DRV_4_8,
+ 187, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(202, "PHY_PD", UNIPHIER_PIN_IECTRL_NONE,
+ 188, UNIPHIER_PIN_DRV_4_8,
+ 188, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(203, "X1394_RST", UNIPHIER_PIN_IECTRL_NONE,
+ 189, UNIPHIER_PIN_DRV_4_8,
+ 189, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(204, "VOUT_MUTE_L", UNIPHIER_PIN_IECTRL_NONE,
+ 190, UNIPHIER_PIN_DRV_4_8,
+ 190, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(205, "CLK54O", UNIPHIER_PIN_IECTRL_NONE,
+ 191, UNIPHIER_PIN_DRV_4_8,
+ 191, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(206, "CLK54I", UNIPHIER_PIN_IECTRL_NONE,
+ 192, UNIPHIER_PIN_DRV_NONE,
+ 192, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(207, "YIN0", UNIPHIER_PIN_IECTRL_NONE,
+ 193, UNIPHIER_PIN_DRV_4_8,
+ 193, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(208, "YIN1", UNIPHIER_PIN_IECTRL_NONE,
+ 194, UNIPHIER_PIN_DRV_4_8,
+ 194, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(209, "YIN2", UNIPHIER_PIN_IECTRL_NONE,
+ 195, UNIPHIER_PIN_DRV_4_8,
+ 195, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(210, "YIN3", UNIPHIER_PIN_IECTRL_NONE,
+ 196, UNIPHIER_PIN_DRV_4_8,
+ 196, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(211, "YIN4", UNIPHIER_PIN_IECTRL_NONE,
+ 197, UNIPHIER_PIN_DRV_4_8,
+ 197, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(212, "YIN5", UNIPHIER_PIN_IECTRL_NONE,
+ 198, UNIPHIER_PIN_DRV_4_8,
+ 198, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(213, "CIN0", UNIPHIER_PIN_IECTRL_NONE,
+ 199, UNIPHIER_PIN_DRV_4_8,
+ 199, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(214, "CIN1", UNIPHIER_PIN_IECTRL_NONE,
+ 200, UNIPHIER_PIN_DRV_4_8,
+ 200, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(215, "CIN2", UNIPHIER_PIN_IECTRL_NONE,
+ 201, UNIPHIER_PIN_DRV_4_8,
+ 201, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(216, "CIN3", UNIPHIER_PIN_IECTRL_NONE,
+ 202, UNIPHIER_PIN_DRV_4_8,
+ 202, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(217, "CIN4", UNIPHIER_PIN_IECTRL_NONE,
+ 203, UNIPHIER_PIN_DRV_4_8,
+ 203, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(218, "CIN5", UNIPHIER_PIN_IECTRL_NONE,
+ 204, UNIPHIER_PIN_DRV_4_8,
+ 204, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(219, "GCP", UNIPHIER_PIN_IECTRL_NONE,
+ 205, UNIPHIER_PIN_DRV_4_8,
+ 205, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(220, "ADFLG", UNIPHIER_PIN_IECTRL_NONE,
+ 206, UNIPHIER_PIN_DRV_4_8,
+ 206, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(221, "CK27AIOF", UNIPHIER_PIN_IECTRL_NONE,
+ 207, UNIPHIER_PIN_DRV_4_8,
+ 207, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(222, "DACOUT", UNIPHIER_PIN_IECTRL_NONE,
+ 208, UNIPHIER_PIN_DRV_4_8,
+ 208, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(223, "DAFLG", UNIPHIER_PIN_IECTRL_NONE,
+ 209, UNIPHIER_PIN_DRV_4_8,
+ 209, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(224, "VBIH", UNIPHIER_PIN_IECTRL_NONE,
+ 210, UNIPHIER_PIN_DRV_4_8,
+ 210, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(225, "VBIL", UNIPHIER_PIN_IECTRL_NONE,
+ 211, UNIPHIER_PIN_DRV_4_8,
+ 211, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(226, "XSUB_RST", UNIPHIER_PIN_IECTRL_NONE,
+ 212, UNIPHIER_PIN_DRV_4_8,
+ 212, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(227, "XADC_PD", UNIPHIER_PIN_IECTRL_NONE,
+ 213, UNIPHIER_PIN_DRV_4_8,
+ 213, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(228, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE,
+ 214, UNIPHIER_PIN_DRV_4_8,
+ 214, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(229, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE,
+ 215, UNIPHIER_PIN_DRV_4_8,
+ 215, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(230, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ 216, UNIPHIER_PIN_DRV_4_8,
+ 216, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(231, "AI1DMIX", UNIPHIER_PIN_IECTRL_NONE,
+ 217, UNIPHIER_PIN_DRV_4_8,
+ 217, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(232, "CK27HD", UNIPHIER_PIN_IECTRL_NONE,
+ 218, UNIPHIER_PIN_DRV_4_8,
+ 218, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(233, "XHD_RST", UNIPHIER_PIN_IECTRL_NONE,
+ 219, UNIPHIER_PIN_DRV_4_8,
+ 219, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(234, "INTHD", UNIPHIER_PIN_IECTRL_NONE,
+ 220, UNIPHIER_PIN_DRV_4_8,
+ 220, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(235, "VO1HDCK", UNIPHIER_PIN_IECTRL_NONE,
+ 221, UNIPHIER_PIN_DRV_4_8,
+ 221, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(236, "VO1HSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ 222, UNIPHIER_PIN_DRV_4_8,
+ 222, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(237, "VO1VSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ 223, UNIPHIER_PIN_DRV_4_8,
+ 223, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(238, "VO1DE", UNIPHIER_PIN_IECTRL_NONE,
+ 224, UNIPHIER_PIN_DRV_4_8,
+ 224, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(239, "VO1Y0", UNIPHIER_PIN_IECTRL_NONE,
+ 225, UNIPHIER_PIN_DRV_4_8,
+ 225, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(240, "VO1Y1", UNIPHIER_PIN_IECTRL_NONE,
+ 226, UNIPHIER_PIN_DRV_4_8,
+ 226, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(241, "VO1Y2", UNIPHIER_PIN_IECTRL_NONE,
+ 227, UNIPHIER_PIN_DRV_4_8,
+ 227, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(242, "VO1Y3", UNIPHIER_PIN_IECTRL_NONE,
+ 228, UNIPHIER_PIN_DRV_4_8,
+ 228, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(243, "VO1Y4", UNIPHIER_PIN_IECTRL_NONE,
+ 229, UNIPHIER_PIN_DRV_4_8,
+ 229, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(244, "VO1Y5", UNIPHIER_PIN_IECTRL_NONE,
+ 230, UNIPHIER_PIN_DRV_4_8,
+ 230, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(245, "VO1Y6", UNIPHIER_PIN_IECTRL_NONE,
+ 231, UNIPHIER_PIN_DRV_4_8,
+ 231, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(246, "VO1Y7", UNIPHIER_PIN_IECTRL_NONE,
+ 232, UNIPHIER_PIN_DRV_4_8,
+ 232, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(247, "VO1Y8", UNIPHIER_PIN_IECTRL_NONE,
+ 233, UNIPHIER_PIN_DRV_4_8,
+ 233, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(248, "VO1Y9", UNIPHIER_PIN_IECTRL_NONE,
+ 234, UNIPHIER_PIN_DRV_4_8,
+ 234, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(249, "VO1Y10", UNIPHIER_PIN_IECTRL_NONE,
+ 235, UNIPHIER_PIN_DRV_4_8,
+ 235, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(250, "VO1Y11", UNIPHIER_PIN_IECTRL_NONE,
+ 236, UNIPHIER_PIN_DRV_4_8,
+ 236, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(251, "VO1CB0", UNIPHIER_PIN_IECTRL_NONE,
+ 237, UNIPHIER_PIN_DRV_4_8,
+ 237, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(252, "VO1CB1", UNIPHIER_PIN_IECTRL_NONE,
+ 238, UNIPHIER_PIN_DRV_4_8,
+ 238, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(253, "VO1CB2", UNIPHIER_PIN_IECTRL_NONE,
+ 239, UNIPHIER_PIN_DRV_4_8,
+ 239, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(254, "VO1CB3", UNIPHIER_PIN_IECTRL_NONE,
+ 240, UNIPHIER_PIN_DRV_4_8,
+ 240, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(255, "VO1CB4", UNIPHIER_PIN_IECTRL_NONE,
+ 241, UNIPHIER_PIN_DRV_4_8,
+ 241, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(256, "VO1CB5", UNIPHIER_PIN_IECTRL_NONE,
+ 242, UNIPHIER_PIN_DRV_4_8,
+ 242, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(257, "VO1CB6", UNIPHIER_PIN_IECTRL_NONE,
+ 243, UNIPHIER_PIN_DRV_4_8,
+ 243, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(258, "VO1CB7", UNIPHIER_PIN_IECTRL_NONE,
+ 244, UNIPHIER_PIN_DRV_4_8,
+ 244, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(259, "VO1CB8", UNIPHIER_PIN_IECTRL_NONE,
+ 245, UNIPHIER_PIN_DRV_4_8,
+ 245, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(260, "VO1CB9", UNIPHIER_PIN_IECTRL_NONE,
+ 246, UNIPHIER_PIN_DRV_4_8,
+ 246, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(261, "VO1CB10", UNIPHIER_PIN_IECTRL_NONE,
+ 247, UNIPHIER_PIN_DRV_4_8,
+ 247, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(262, "VO1CB11", UNIPHIER_PIN_IECTRL_NONE,
+ 248, UNIPHIER_PIN_DRV_4_8,
+ 248, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(263, "VO1CR0", UNIPHIER_PIN_IECTRL_NONE,
+ 249, UNIPHIER_PIN_DRV_4_8,
+ 249, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(264, "VO1CR1", UNIPHIER_PIN_IECTRL_NONE,
+ 250, UNIPHIER_PIN_DRV_4_8,
+ 250, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(265, "VO1CR2", UNIPHIER_PIN_IECTRL_NONE,
+ 251, UNIPHIER_PIN_DRV_4_8,
+ 251, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(266, "VO1CR3", UNIPHIER_PIN_IECTRL_NONE,
+ 252, UNIPHIER_PIN_DRV_4_8,
+ 252, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(267, "VO1CR4", UNIPHIER_PIN_IECTRL_NONE,
+ 253, UNIPHIER_PIN_DRV_4_8,
+ 253, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(268, "VO1CR5", UNIPHIER_PIN_IECTRL_NONE,
+ 254, UNIPHIER_PIN_DRV_4_8,
+ 254, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(269, "VO1CR6", UNIPHIER_PIN_IECTRL_NONE,
+ 255, UNIPHIER_PIN_DRV_4_8,
+ 255, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(270, "VO1CR7", UNIPHIER_PIN_IECTRL_NONE,
+ 256, UNIPHIER_PIN_DRV_4_8,
+ 256, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(271, "VO1CR8", UNIPHIER_PIN_IECTRL_NONE,
+ 257, UNIPHIER_PIN_DRV_4_8,
+ 257, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(272, "VO1CR9", UNIPHIER_PIN_IECTRL_NONE,
+ 258, UNIPHIER_PIN_DRV_4_8,
+ 258, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(273, "VO1CR10", UNIPHIER_PIN_IECTRL_NONE,
+ 259, UNIPHIER_PIN_DRV_4_8,
+ 259, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(274, "VO1CR11", UNIPHIER_PIN_IECTRL_NONE,
+ 260, UNIPHIER_PIN_DRV_4_8,
+ 260, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(275, "VO1EX0", UNIPHIER_PIN_IECTRL_NONE,
+ 261, UNIPHIER_PIN_DRV_4_8,
+ 261, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(276, "VO1EX1", UNIPHIER_PIN_IECTRL_NONE,
+ 262, UNIPHIER_PIN_DRV_4_8,
+ 262, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(277, "VO1EX2", UNIPHIER_PIN_IECTRL_NONE,
+ 263, UNIPHIER_PIN_DRV_4_8,
+ 263, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(278, "VO1EX3", UNIPHIER_PIN_IECTRL_NONE,
+ 264, UNIPHIER_PIN_DRV_4_8,
+ 264, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(279, "VEXCKA", UNIPHIER_PIN_IECTRL_NONE,
+ 265, UNIPHIER_PIN_DRV_4_8,
+ 265, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(280, "VSEL0", UNIPHIER_PIN_IECTRL_NONE,
+ 266, UNIPHIER_PIN_DRV_4_8,
+ 266, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(281, "VSEL1", UNIPHIER_PIN_IECTRL_NONE,
+ 267, UNIPHIER_PIN_DRV_4_8,
+ 267, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(282, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE,
+ 268, UNIPHIER_PIN_DRV_4_8,
+ 268, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(283, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE,
+ 269, UNIPHIER_PIN_DRV_4_8,
+ 269, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(284, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ 270, UNIPHIER_PIN_DRV_4_8,
+ 270, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(285, "AO1D0", UNIPHIER_PIN_IECTRL_NONE,
+ 271, UNIPHIER_PIN_DRV_4_8,
+ 271, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(286, "AO1D1", UNIPHIER_PIN_IECTRL_NONE,
+ 272, UNIPHIER_PIN_DRV_4_8,
+ 272, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(287, "AO1D2", UNIPHIER_PIN_IECTRL_NONE,
+ 273, UNIPHIER_PIN_DRV_4_8,
+ 273, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(288, "AO1D3", UNIPHIER_PIN_IECTRL_NONE,
+ 274, UNIPHIER_PIN_DRV_4_8,
+ 274, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(289, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE,
+ 275, UNIPHIER_PIN_DRV_4_8,
+ 275, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(290, "XDAC_PD", UNIPHIER_PIN_IECTRL_NONE,
+ 276, UNIPHIER_PIN_DRV_4_8,
+ 276, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(291, "EX_A_MUTE", UNIPHIER_PIN_IECTRL_NONE,
+ 277, UNIPHIER_PIN_DRV_4_8,
+ 277, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(292, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
+ 278, UNIPHIER_PIN_DRV_4_8,
+ 278, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(293, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
+ 279, UNIPHIER_PIN_DRV_4_8,
+ 279, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(294, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ 280, UNIPHIER_PIN_DRV_4_8,
+ 280, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(295, "AO2DMIX", UNIPHIER_PIN_IECTRL_NONE,
+ 281, UNIPHIER_PIN_DRV_4_8,
+ 281, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(296, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE,
+ 282, UNIPHIER_PIN_DRV_4_8,
+ 282, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(297, "HTHPD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(298, "HTSCL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(299, "HTSDA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(300, "PORT00", UNIPHIER_PIN_IECTRL_NONE,
+ 284, UNIPHIER_PIN_DRV_4_8,
+ 284, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(301, "PORT01", UNIPHIER_PIN_IECTRL_NONE,
+ 285, UNIPHIER_PIN_DRV_4_8,
+ 285, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(302, "PORT02", UNIPHIER_PIN_IECTRL_NONE,
+ 286, UNIPHIER_PIN_DRV_4_8,
+ 286, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(303, "PORT03", UNIPHIER_PIN_IECTRL_NONE,
+ 287, UNIPHIER_PIN_DRV_4_8,
+ 287, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(304, "PORT04", UNIPHIER_PIN_IECTRL_NONE,
+ 288, UNIPHIER_PIN_DRV_4_8,
+ 288, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(305, "PORT05", UNIPHIER_PIN_IECTRL_NONE,
+ 289, UNIPHIER_PIN_DRV_4_8,
+ 289, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(306, "PORT06", UNIPHIER_PIN_IECTRL_NONE,
+ 290, UNIPHIER_PIN_DRV_4_8,
+ 290, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(307, "PORT07", UNIPHIER_PIN_IECTRL_NONE,
+ 291, UNIPHIER_PIN_DRV_4_8,
+ 291, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(308, "PORT10", UNIPHIER_PIN_IECTRL_NONE,
+ 292, UNIPHIER_PIN_DRV_4_8,
+ 292, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(309, "PORT11", UNIPHIER_PIN_IECTRL_NONE,
+ 293, UNIPHIER_PIN_DRV_4_8,
+ 293, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(310, "PORT12", UNIPHIER_PIN_IECTRL_NONE,
+ 294, UNIPHIER_PIN_DRV_4_8,
+ 294, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(311, "PORT13", UNIPHIER_PIN_IECTRL_NONE,
+ 295, UNIPHIER_PIN_DRV_4_8,
+ 295, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(312, "PORT14", UNIPHIER_PIN_IECTRL_NONE,
+ 296, UNIPHIER_PIN_DRV_4_8,
+ 296, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(313, "PORT15", UNIPHIER_PIN_IECTRL_NONE,
+ 297, UNIPHIER_PIN_DRV_4_8,
+ 297, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(314, "PORT16", UNIPHIER_PIN_IECTRL_NONE,
+ 298, UNIPHIER_PIN_DRV_4_8,
+ 298, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(315, "PORT17", UNIPHIER_PIN_IECTRL_NONE,
+ 299, UNIPHIER_PIN_DRV_4_8,
+ 299, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(316, "PORT20", UNIPHIER_PIN_IECTRL_NONE,
+ 300, UNIPHIER_PIN_DRV_4_8,
+ 300, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(317, "PORT21", UNIPHIER_PIN_IECTRL_NONE,
+ 301, UNIPHIER_PIN_DRV_4_8,
+ 301, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(318, "PORT22", UNIPHIER_PIN_IECTRL_NONE,
+ 302, UNIPHIER_PIN_DRV_4_8,
+ 302, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(319, "SD1DAT0", UNIPHIER_PIN_IECTRL_NONE,
+ 303, UNIPHIER_PIN_DRV_4_8,
+ 303, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(320, "SD1DAT1", UNIPHIER_PIN_IECTRL_NONE,
+ 304, UNIPHIER_PIN_DRV_4_8,
+ 304, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(321, "SD1DAT2", UNIPHIER_PIN_IECTRL_NONE,
+ 305, UNIPHIER_PIN_DRV_4_8,
+ 305, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(322, "SD1DAT3", UNIPHIER_PIN_IECTRL_NONE,
+ 306, UNIPHIER_PIN_DRV_4_8,
+ 306, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(323, "SD1CMD", UNIPHIER_PIN_IECTRL_NONE,
+ 307, UNIPHIER_PIN_DRV_4_8,
+ 307, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(324, "SD1CLK", UNIPHIER_PIN_IECTRL_NONE,
+ 308, UNIPHIER_PIN_DRV_4_8,
+ 308, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(325, "SD1CD", UNIPHIER_PIN_IECTRL_NONE,
+ 309, UNIPHIER_PIN_DRV_4_8,
+ 309, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(326, "SD1WP", UNIPHIER_PIN_IECTRL_NONE,
+ 310, UNIPHIER_PIN_DRV_4_8,
+ 310, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(327, "SD1VTCG", UNIPHIER_PIN_IECTRL_NONE,
+ 311, UNIPHIER_PIN_DRV_4_8,
+ 311, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(328, "DMDISO", UNIPHIER_PIN_IECTRL_NONE,
+ 312, UNIPHIER_PIN_DRV_NONE,
+ 312, UNIPHIER_PIN_PULL_DOWN),
+};
+
+static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53};
+static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {142, 143};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {144, 145};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {146, 147};
+static const unsigned i2c2_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {148, 149};
+static const unsigned i2c3_muxvals[] = {0, 0};
+static const unsigned i2c6_pins[] = {308, 309};
+static const unsigned i2c6_muxvals[] = {6, 6};
+static const unsigned nand_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
+ 50, 51, 52, 53, 54};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {131, 132};
+static const unsigned nand_cs1_muxvals[] = {1, 1};
+static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 158};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326,
+ 327};
+static const unsigned sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {127, 128};
+static const unsigned uart0_muxvals[] = {0, 0};
+static const unsigned uart1_pins[] = {129, 130};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {131, 132};
+static const unsigned uart2_muxvals[] = {0, 0};
+static const unsigned uart3_pins[] = {88, 89};
+static const unsigned uart3_muxvals[] = {2, 2};
+static const unsigned usb0_pins[] = {180, 181};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {182, 183};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {184, 185};
+static const unsigned usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {186, 187};
+static const unsigned usb3_muxvals[] = {0, 0};
+static const unsigned port_range0_pins[] = {
+ 300, 301, 302, 303, 304, 305, 306, 307, /* PORT0x */
+ 308, 309, 310, 311, 312, 313, 314, 315, /* PORT1x */
+ 316, 317, 318, 16, 17, 18, 19, 20, /* PORT2x */
+ 21, 22, 23, 4, 93, 94, 95, 63, /* PORT3x */
+ 123, 122, 124, 125, 126, 141, 202, 203, /* PORT4x */
+ 204, 226, 227, 290, 291, 233, 280, 281, /* PORT5x */
+ 8, 7, 10, 29, 30, 48, 49, 50, /* PORT6x */
+ 40, 41, 42, 43, 44, 45, 46, 47, /* PORT7x */
+ 54, 51, 52, 53, 127, 128, 129, 130, /* PORT8x */
+ 131, 132, 57, 60, 134, 133, 135, 136, /* PORT9x */
+ 138, 137, 140, 139, 64, 65, 66, 67, /* PORT10x */
+ 107, 106, 105, 104, 113, 112, 111, 110, /* PORT11x */
+ 68, 69, 70, 71, 72, 73, 74, 75, /* PORT12x */
+ 76, 77, 78, 79, 80, 81, 82, 83, /* PORT13x */
+ 84, 85, 86, 87, 88, 89, 90, 91, /* PORT14x */
+};
+static const unsigned port_range0_muxvals[] = {
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT0x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT1x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT2x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT3x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT4x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT5x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT6x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT7x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT8x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT9x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT10x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT11x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT12x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT13x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT14x */
+};
+static const unsigned port_range1_pins[] = {
+ 13, 14, 15, /* PORT175-177 */
+ 157, 158, 156, 154, 150, 151, 152, 153, /* PORT18x */
+ 326, 327, 325, 323, 319, 320, 321, 322, /* PORT19x */
+ 160, 161, 162, 163, 164, 165, 166, 167, /* PORT20x */
+ 168, 169, 170, 171, 172, 173, 174, 175, /* PORT21x */
+ 180, 181, 182, 183, 184, 185, 187, 188, /* PORT22x */
+ 193, 194, 195, 196, 197, 198, 199, 200, /* PORT23x */
+ 191, 192, 215, 216, 217, 218, 219, 220, /* PORT24x */
+ 222, 223, 224, 225, 228, 229, 230, 231, /* PORT25x */
+ 282, 283, 284, 285, 286, 287, 288, 289, /* PORT26x */
+ 292, 293, 294, 295, 296, 236, 237, 238, /* PORT27x */
+ 275, 276, 277, 278, 239, 240, 249, 250, /* PORT28x */
+ 251, 252, 261, 262, 263, 264, 273, 274, /* PORT29x */
+ 31, 32, 33, 34, 35, 36, 37, 38, /* PORT30x */
+};
+static const unsigned port_range1_muxvals[] = {
+ 7, 7, 7, /* PORT175-177 */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT18x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT19x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT20x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT21x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT22x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT23x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT24x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT25x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT26x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT27x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT28x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT29x */
+ 7, 7, 7, 7, 7, 7, 7, 7, /* PORT30x */
+};
+static const unsigned xirq_pins[] = {
+ 11, 9, 12, 96, 97, 98, 108, 114, /* XIRQ0-7 */
+ 234, 186, 99, 100, 101, 102, 184, 301, /* XIRQ8-15 */
+ 302, 303, 304, 305, 306, /* XIRQ16-20 */
+};
+static const unsigned xirq_muxvals[] = {
+ 7, 7, 7, 7, 7, 7, 7, 7, /* XIRQ0-7 */
+ 7, 7, 7, 7, 7, 7, 2, 2, /* XIRQ8-15 */
+ 2, 2, 2, 2, 2, /* XIRQ16-20 */
+};
+static const unsigned xirq_alternatives_pins[] = {
+ 184, 310, 316,
+};
+static const unsigned xirq_alternatives_muxvals[] = {
+ 2, 2, 2,
+};
+
+static const struct uniphier_pinctrl_group ph1_pro4_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c6),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(sd1),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb3),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 24),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 25),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 26),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 27),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 28),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 29),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 30),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 31),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 32),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 33),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 34),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 35),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 36),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 37),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 38),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 39),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 40),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 41),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 42),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 43),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 44),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 45),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 46),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 47),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 48),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 49),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 50),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 51),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 52),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 53),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 54),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 55),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 56),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 57),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 58),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 59),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 60),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 61),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 62),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 63),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 64),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 65),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 66),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 67),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 68),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 69),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 70),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 71),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 72),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 73),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 74),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 75),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 76),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 77),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 78),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 79),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 80),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 81),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 82),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 83),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 84),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 85),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 86),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 87),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 88),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 89),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 90),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port290, port_range1, 91),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port291, port_range1, 92),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port292, port_range1, 93),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port293, port_range1, 94),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port294, port_range1, 95),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port295, port_range1, 96),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port296, port_range1, 97),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port297, port_range1, 98),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port300, port_range1, 99),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port301, port_range1, 100),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port302, port_range1, 101),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port303, port_range1, 102),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port304, port_range1, 103),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port305, port_range1, 104),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port306, port_range1, 105),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port307, port_range1, 106),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14b, xirq_alternatives, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 2),
+};
+
+static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const i2c0_groups[] = {"i2c0"};
+static const char * const i2c1_groups[] = {"i2c1"};
+static const char * const i2c2_groups[] = {"i2c2"};
+static const char * const i2c3_groups[] = {"i2c3"};
+static const char * const i2c6_groups[] = {"i2c6"};
+static const char * const nand_groups[] = {"nand", "nand_cs1"};
+static const char * const sd_groups[] = {"sd"};
+static const char * const sd1_groups[] = {"sd1"};
+static const char * const uart0_groups[] = {"uart0"};
+static const char * const uart1_groups[] = {"uart1"};
+static const char * const uart2_groups[] = {"uart2"};
+static const char * const uart3_groups[] = {"uart3"};
+static const char * const usb0_groups[] = {"usb0"};
+static const char * const usb1_groups[] = {"usb1"};
+static const char * const usb2_groups[] = {"usb2"};
+static const char * const usb3_groups[] = {"usb3"};
+static const char * const port_groups[] = {
+ "port00", "port01", "port02", "port03",
+ "port04", "port05", "port06", "port07",
+ "port10", "port11", "port12", "port13",
+ "port14", "port15", "port16", "port17",
+ "port20", "port21", "port22", "port23",
+ "port24", "port25", "port26", "port27",
+ "port30", "port31", "port32", "port33",
+ "port34", "port35", "port36", "port37",
+ "port40", "port41", "port42", "port43",
+ "port44", "port45", "port46", "port47",
+ "port50", "port51", "port52", "port53",
+ "port54", "port55", "port56", "port57",
+ "port60", "port61", "port62", "port63",
+ "port64", "port65", "port66", "port67",
+ "port70", "port71", "port72", "port73",
+ "port74", "port75", "port76", "port77",
+ "port80", "port81", "port82", "port83",
+ "port84", "port85", "port86", "port87",
+ "port90", "port91", "port92", "port93",
+ "port94", "port95", "port96", "port97",
+ "port100", "port101", "port102", "port103",
+ "port104", "port105", "port106", "port107",
+ "port110", "port111", "port112", "port113",
+ "port114", "port115", "port116", "port117",
+ "port120", "port121", "port122", "port123",
+ "port124", "port125", "port126", "port127",
+ "port130", "port131", "port132", "port133",
+ "port134", "port135", "port136", "port137",
+ "port140", "port141", "port142", "port143",
+ "port144", "port145", "port146", "port147",
+ /* port150-174 missing */
+ /* none */ "port175", "port176", "port177",
+ "port180", "port181", "port182", "port183",
+ "port184", "port185", "port186", "port187",
+ "port190", "port191", "port192", "port193",
+ "port194", "port195", "port196", "port197",
+ "port200", "port201", "port202", "port203",
+ "port204", "port205", "port206", "port207",
+ "port210", "port211", "port212", "port213",
+ "port214", "port215", "port216", "port217",
+ "port220", "port221", "port222", "port223",
+ "port224", "port225", "port226", "port227",
+ "port230", "port231", "port232", "port233",
+ "port234", "port235", "port236", "port237",
+ "port240", "port241", "port242", "port243",
+ "port244", "port245", "port246", "port247",
+ "port250", "port251", "port252", "port253",
+ "port254", "port255", "port256", "port257",
+ "port260", "port261", "port262", "port263",
+ "port264", "port265", "port266", "port267",
+ "port270", "port271", "port272", "port273",
+ "port274", "port275", "port276", "port277",
+ "port280", "port281", "port282", "port283",
+ "port284", "port285", "port286", "port287",
+ "port290", "port291", "port292", "port293",
+ "port294", "port295", "port296", "port297",
+ "port300", "port301", "port302", "port303",
+ "port304", "port305", "port306", "port307",
+};
+static const char * const xirq_groups[] = {
+ "xirq0", "xirq1", "xirq2", "xirq3",
+ "xirq4", "xirq5", "xirq6", "xirq7",
+ "xirq8", "xirq9", "xirq10", "xirq11",
+ "xirq12", "xirq13", "xirq14", "xirq15",
+ "xirq16", "xirq17", "xirq18", "xirq19",
+ "xirq20",
+ "xirq14b", "xirq17b", "xirq18b",
+};
+
+static const struct uniphier_pinmux_function ph1_pro4_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(i2c0),
+ UNIPHIER_PINMUX_FUNCTION(i2c1),
+ UNIPHIER_PINMUX_FUNCTION(i2c2),
+ UNIPHIER_PINMUX_FUNCTION(i2c3),
+ UNIPHIER_PINMUX_FUNCTION(i2c6),
+ UNIPHIER_PINMUX_FUNCTION(nand),
+ UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(sd1),
+ UNIPHIER_PINMUX_FUNCTION(uart0),
+ UNIPHIER_PINMUX_FUNCTION(uart1),
+ UNIPHIER_PINMUX_FUNCTION(uart2),
+ UNIPHIER_PINMUX_FUNCTION(uart3),
+ UNIPHIER_PINMUX_FUNCTION(usb0),
+ UNIPHIER_PINMUX_FUNCTION(usb1),
+ UNIPHIER_PINMUX_FUNCTION(usb2),
+ UNIPHIER_PINMUX_FUNCTION(usb3),
+ UNIPHIER_PINMUX_FUNCTION(port),
+ UNIPHIER_PINMUX_FUNCTION(xirq),
+};
+
+static struct uniphier_pinctrl_socdata ph1_pro4_pindata = {
+ .groups = ph1_pro4_groups,
+ .groups_count = ARRAY_SIZE(ph1_pro4_groups),
+ .functions = ph1_pro4_functions,
+ .functions_count = ARRAY_SIZE(ph1_pro4_functions),
+ .mux_bits = 4,
+ .reg_stride = 8,
+ .load_pinctrl = true,
+};
+
+static struct pinctrl_desc ph1_pro4_pinctrl_desc = {
+ .name = DRIVER_NAME,
+ .pins = ph1_pro4_pins,
+ .npins = ARRAY_SIZE(ph1_pro4_pins),
+ .owner = THIS_MODULE,
+};
+
+static int ph1_pro4_pinctrl_probe(struct platform_device *pdev)
+{
+ return uniphier_pinctrl_probe(pdev, &ph1_pro4_pinctrl_desc,
+ &ph1_pro4_pindata);
+}
+
+static const struct of_device_id ph1_pro4_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-pro4-pinctrl" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ph1_pro4_pinctrl_match);
+
+static struct platform_driver ph1_pro4_pinctrl_driver = {
+ .probe = ph1_pro4_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = ph1_pro4_pinctrl_match,
+ },
+};
+module_platform_driver(ph1_pro4_pinctrl_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-Pro4 pinctrl driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program5 is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-uniphier.h"
+
+#define DRIVER_NAME "ph1-pro5-pinctrl"
+
+static const struct pinctrl_pin_desc ph1_pro5_pins[] = {
+ UNIPHIER_PINCTRL_PIN(0, "AEXCKA1", 0,
+ 0, UNIPHIER_PIN_DRV_4_8,
+ 0, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(1, "AEXCKA2", 0,
+ 1, UNIPHIER_PIN_DRV_4_8,
+ 1, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(2, "CK27EXI", 0,
+ 2, UNIPHIER_PIN_DRV_4_8,
+ 2, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(3, "CK54EXI", 0,
+ 3, UNIPHIER_PIN_DRV_4_8,
+ 3, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(4, "ED0", UNIPHIER_PIN_IECTRL_NONE,
+ 4, UNIPHIER_PIN_DRV_4_8,
+ 4, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(5, "ED1", UNIPHIER_PIN_IECTRL_NONE,
+ 5, UNIPHIER_PIN_DRV_4_8,
+ 5, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(6, "ED2", UNIPHIER_PIN_IECTRL_NONE,
+ 6, UNIPHIER_PIN_DRV_4_8,
+ 6, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(7, "ED3", UNIPHIER_PIN_IECTRL_NONE,
+ 7, UNIPHIER_PIN_DRV_4_8,
+ 7, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(8, "ED4", UNIPHIER_PIN_IECTRL_NONE,
+ 8, UNIPHIER_PIN_DRV_4_8,
+ 8, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(9, "ED5", UNIPHIER_PIN_IECTRL_NONE,
+ 9, UNIPHIER_PIN_DRV_4_8,
+ 9, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(10, "ED6", UNIPHIER_PIN_IECTRL_NONE,
+ 10, UNIPHIER_PIN_DRV_4_8,
+ 10, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(11, "ED7", UNIPHIER_PIN_IECTRL_NONE,
+ 11, UNIPHIER_PIN_DRV_4_8,
+ 11, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(12, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
+ 12, UNIPHIER_PIN_DRV_4_8,
+ 12, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(13, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
+ 13, UNIPHIER_PIN_DRV_4_8,
+ 13, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(14, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
+ 14, UNIPHIER_PIN_DRV_4_8,
+ 14, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(15, "ES0", UNIPHIER_PIN_IECTRL_NONE,
+ 15, UNIPHIER_PIN_DRV_4_8,
+ 15, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(16, "ES1", UNIPHIER_PIN_IECTRL_NONE,
+ 16, UNIPHIER_PIN_DRV_4_8,
+ 16, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(17, "ES2", UNIPHIER_PIN_IECTRL_NONE,
+ 17, UNIPHIER_PIN_DRV_4_8,
+ 17, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(18, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
+ 18, UNIPHIER_PIN_DRV_4_8,
+ 18, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(19, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
+ 19, UNIPHIER_PIN_DRV_4_8,
+ 19, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(20, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
+ 20, UNIPHIER_PIN_DRV_4_8,
+ 20, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(21, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
+ 21, UNIPHIER_PIN_DRV_4_8,
+ 21, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(22, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
+ 22, UNIPHIER_PIN_DRV_4_8,
+ 22, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(23, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
+ 23, UNIPHIER_PIN_DRV_4_8,
+ 23, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(24, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
+ 24, UNIPHIER_PIN_DRV_4_8,
+ 24, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(25, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE,
+ 25, UNIPHIER_PIN_DRV_4_8,
+ 25, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(26, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE,
+ 26, UNIPHIER_PIN_DRV_4_8,
+ 26, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(27, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE,
+ 27, UNIPHIER_PIN_DRV_4_8,
+ 27, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(28, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
+ 28, UNIPHIER_PIN_DRV_4_8,
+ 28, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(29, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
+ 29, UNIPHIER_PIN_DRV_4_8,
+ 29, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(30, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
+ 30, UNIPHIER_PIN_DRV_4_8,
+ 30, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(31, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
+ 31, UNIPHIER_PIN_DRV_4_8,
+ 31, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(32, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
+ 32, UNIPHIER_PIN_DRV_4_8,
+ 32, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(33, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
+ 33, UNIPHIER_PIN_DRV_4_8,
+ 33, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(34, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
+ 34, UNIPHIER_PIN_DRV_4_8,
+ 34, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(35, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
+ 35, UNIPHIER_PIN_DRV_4_8,
+ 35, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(36, "XERST", UNIPHIER_PIN_IECTRL_NONE,
+ 36, UNIPHIER_PIN_DRV_4_8,
+ 36, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(37, "MMCCLK", UNIPHIER_PIN_IECTRL_NONE,
+ 37, UNIPHIER_PIN_DRV_4_8,
+ 37, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(38, "MMCCMD", UNIPHIER_PIN_IECTRL_NONE,
+ 38, UNIPHIER_PIN_DRV_4_8,
+ 38, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(39, "MMCDAT0", UNIPHIER_PIN_IECTRL_NONE,
+ 39, UNIPHIER_PIN_DRV_4_8,
+ 39, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(40, "MMCDAT1", UNIPHIER_PIN_IECTRL_NONE,
+ 40, UNIPHIER_PIN_DRV_4_8,
+ 40, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(41, "MMCDAT2", UNIPHIER_PIN_IECTRL_NONE,
+ 41, UNIPHIER_PIN_DRV_4_8,
+ 41, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(42, "MMCDAT3", UNIPHIER_PIN_IECTRL_NONE,
+ 42, UNIPHIER_PIN_DRV_4_8,
+ 42, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(43, "MMCDAT4", UNIPHIER_PIN_IECTRL_NONE,
+ 43, UNIPHIER_PIN_DRV_4_8,
+ 43, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(44, "MMCDAT5", UNIPHIER_PIN_IECTRL_NONE,
+ 44, UNIPHIER_PIN_DRV_4_8,
+ 44, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(45, "MMCDAT6", UNIPHIER_PIN_IECTRL_NONE,
+ 45, UNIPHIER_PIN_DRV_4_8,
+ 45, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(46, "MMCDAT7", UNIPHIER_PIN_IECTRL_NONE,
+ 46, UNIPHIER_PIN_DRV_4_8,
+ 46, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(47, "TXD0", 0,
+ 47, UNIPHIER_PIN_DRV_4_8,
+ 47, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(48, "RXD0", 0,
+ 48, UNIPHIER_PIN_DRV_4_8,
+ 48, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(49, "TXD1", 0,
+ 49, UNIPHIER_PIN_DRV_4_8,
+ 49, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(50, "RXD1", 0,
+ 50, UNIPHIER_PIN_DRV_4_8,
+ 50, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(51, "TXD2", UNIPHIER_PIN_IECTRL_NONE,
+ 51, UNIPHIER_PIN_DRV_4_8,
+ 51, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(52, "RXD2", UNIPHIER_PIN_IECTRL_NONE,
+ 52, UNIPHIER_PIN_DRV_4_8,
+ 52, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(53, "TXD3", 0,
+ 53, UNIPHIER_PIN_DRV_4_8,
+ 53, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(54, "RXD3", 0,
+ 54, UNIPHIER_PIN_DRV_4_8,
+ 54, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(55, "MS0CS0", 0,
+ 55, UNIPHIER_PIN_DRV_4_8,
+ 55, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(56, "MS0DO", 0,
+ 56, UNIPHIER_PIN_DRV_4_8,
+ 56, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(57, "MS0DI", 0,
+ 57, UNIPHIER_PIN_DRV_4_8,
+ 57, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(58, "MS0CLK", 0,
+ 58, UNIPHIER_PIN_DRV_4_8,
+ 58, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(59, "CSCLK", 0,
+ 59, UNIPHIER_PIN_DRV_4_8,
+ 59, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(60, "CSBPTM", 0,
+ 60, UNIPHIER_PIN_DRV_4_8,
+ 60, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(61, "CSBMTP", 0,
+ 61, UNIPHIER_PIN_DRV_4_8,
+ 61, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(62, "XCINTP", 0,
+ 62, UNIPHIER_PIN_DRV_4_8,
+ 62, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(63, "XCINTM", 0,
+ 63, UNIPHIER_PIN_DRV_4_8,
+ 63, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(64, "XCMPREQ", 0,
+ 64, UNIPHIER_PIN_DRV_4_8,
+ 64, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(65, "XSRST", 0,
+ 65, UNIPHIER_PIN_DRV_4_8,
+ 65, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(66, "LPST", UNIPHIER_PIN_IECTRL_NONE,
+ 66, UNIPHIER_PIN_DRV_4_8,
+ 66, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(67, "PWMA", 0,
+ 67, UNIPHIER_PIN_DRV_4_8,
+ 67, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(68, "XIRQ0", 0,
+ 68, UNIPHIER_PIN_DRV_4_8,
+ 68, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(69, "XIRQ1", 0,
+ 69, UNIPHIER_PIN_DRV_4_8,
+ 69, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(70, "XIRQ2", 0,
+ 70, UNIPHIER_PIN_DRV_4_8,
+ 70, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(71, "XIRQ3", 0,
+ 71, UNIPHIER_PIN_DRV_4_8,
+ 71, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(72, "XIRQ4", 0,
+ 72, UNIPHIER_PIN_DRV_4_8,
+ 72, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(73, "XIRQ5", 0,
+ 73, UNIPHIER_PIN_DRV_4_8,
+ 73, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(74, "XIRQ6", 0,
+ 74, UNIPHIER_PIN_DRV_4_8,
+ 74, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(75, "XIRQ7", 0,
+ 75, UNIPHIER_PIN_DRV_4_8,
+ 75, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(76, "XIRQ8", 0,
+ 76, UNIPHIER_PIN_DRV_4_8,
+ 76, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(77, "XIRQ9", 0,
+ 77, UNIPHIER_PIN_DRV_4_8,
+ 77, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(78, "XIRQ10", 0,
+ 78, UNIPHIER_PIN_DRV_4_8,
+ 78, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(79, "XIRQ11", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 79, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(80, "XIRQ12", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 80, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(81, "XIRQ13", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 81, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(82, "XIRQ14", 0,
+ 82, UNIPHIER_PIN_DRV_4_8,
+ 82, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(83, "XIRQ15", 0,
+ 83, UNIPHIER_PIN_DRV_4_8,
+ 83, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(84, "XIRQ16", 0,
+ 84, UNIPHIER_PIN_DRV_4_8,
+ 84, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(85, "XIRQ17", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 85, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(86, "XIRQ18", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 86, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(87, "XIRQ19", 0,
+ 87, UNIPHIER_PIN_DRV_4_8,
+ 87, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(88, "XIRQ20", 0,
+ 88, UNIPHIER_PIN_DRV_4_8,
+ 88, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(89, "PORT00", 0,
+ 89, UNIPHIER_PIN_DRV_4_8,
+ 89, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(90, "PORT01", 0,
+ 90, UNIPHIER_PIN_DRV_4_8,
+ 90, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(91, "PORT02", 0,
+ 91, UNIPHIER_PIN_DRV_4_8,
+ 91, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(92, "PORT03", 0,
+ 92, UNIPHIER_PIN_DRV_4_8,
+ 92, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(93, "PORT04", 0,
+ 93, UNIPHIER_PIN_DRV_4_8,
+ 93, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(94, "PORT05", 0,
+ 94, UNIPHIER_PIN_DRV_4_8,
+ 94, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(95, "PORT06", 0,
+ 95, UNIPHIER_PIN_DRV_4_8,
+ 95, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(96, "PORT07", 0,
+ 96, UNIPHIER_PIN_DRV_4_8,
+ 96, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(97, "PORT10", 0,
+ 97, UNIPHIER_PIN_DRV_4_8,
+ 97, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(98, "PORT11", 0,
+ 98, UNIPHIER_PIN_DRV_4_8,
+ 98, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(99, "PORT12", 0,
+ 99, UNIPHIER_PIN_DRV_4_8,
+ 99, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(100, "PORT13", 0,
+ 100, UNIPHIER_PIN_DRV_4_8,
+ 100, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(101, "PORT14", 0,
+ 101, UNIPHIER_PIN_DRV_4_8,
+ 101, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(102, "PORT15", 0,
+ 102, UNIPHIER_PIN_DRV_4_8,
+ 102, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(103, "PORT16", 0,
+ 103, UNIPHIER_PIN_DRV_4_8,
+ 103, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(104, "PORT17", 0,
+ 104, UNIPHIER_PIN_DRV_4_8,
+ 104, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(105, "T0HPD", 0,
+ 105, UNIPHIER_PIN_DRV_4_8,
+ 105, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(106, "T1HPD", 0,
+ 106, UNIPHIER_PIN_DRV_4_8,
+ 106, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(107, "R0HPD", 0,
+ 107, UNIPHIER_PIN_DRV_4_8,
+ 107, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(108, "R1HPD", 0,
+ 108, UNIPHIER_PIN_DRV_4_8,
+ 108, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(109, "XPERST", 0,
+ 109, UNIPHIER_PIN_DRV_4_8,
+ 109, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(110, "XPEWAKE", 0,
+ 110, UNIPHIER_PIN_DRV_4_8,
+ 110, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(111, "XPECLKRQ", 0,
+ 111, UNIPHIER_PIN_DRV_4_8,
+ 111, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(112, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 112, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(113, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 113, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(114, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 114, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(115, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 115, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(116, "SDA2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 116, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(117, "SCL2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 117, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(118, "SDA3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 118, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(119, "SCL3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 119, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(120, "SPISYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 120, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(121, "SPISCLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 121, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(122, "SPITXD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 122, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(123, "SPIRXD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 123, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(124, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 124, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(125, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 125, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(126, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 126, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(127, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 127, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(128, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 128, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(129, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 129, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(130, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 130, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(131, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 131, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(132, "SMTD0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 132, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(133, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 133, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(134, "SMTCLK0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 134, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(135, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 135, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(136, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 136, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(137, "SMTD1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 137, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(138, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 138, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(139, "SMTCLK1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 139, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(140, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 140, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(141, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 141, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(142, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 142, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(143, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 143, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(144, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 144, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(145, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 145, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(146, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 146, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(147, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 147, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(148, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 148, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(149, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 149, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(150, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 150, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(151, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 151, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(152, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 152, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(153, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 153, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(154, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 154, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(155, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 155, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(156, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 156, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(157, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 157, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(158, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 158, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(159, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 159, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(160, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 160, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(161, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 161, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(162, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 162, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(163, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 163, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(164, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 164, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(165, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 165, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(166, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 166, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(167, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 167, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(168, "CH7CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 168, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(169, "CH7PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 169, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(170, "CH7VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 170, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(171, "CH7DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 171, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(172, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 172, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(173, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 173, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(174, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 174, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(175, "AI1D0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 175, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(176, "AI1D1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 176, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(177, "AI1D2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 177, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(178, "AI1D3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 178, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(179, "AI2ADCCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 179, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(180, "AI2BCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 180, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(181, "AI2LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 181, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(182, "AI2D0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 182, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(183, "AI2D1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 183, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(184, "AI2D2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 184, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(185, "AI2D3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 185, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(186, "AI3ADCCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 186, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(187, "AI3BCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 187, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(188, "AI3LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 188, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(189, "AI3D0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 189, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(190, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 190, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(191, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 191, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(192, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 192, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(193, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 193, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(194, "AO1D0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 194, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(195, "AO1D1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 195, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(196, "AO1D2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 196, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(197, "AO1D3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 197, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(198, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 198, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(199, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 199, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(200, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 200, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(201, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 201, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(202, "AO2D0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 202, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(203, "AO2D1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 203, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(204, "AO2D2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 204, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(205, "AO2D3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 205, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(206, "AO3DACCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 206, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(207, "AO3BCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 207, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(208, "AO3LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 208, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(209, "AO3DMIX", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 209, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(210, "AO4DACCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 210, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(211, "AO4BCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 211, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(212, "AO4LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 212, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(213, "AO4DMIX", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 213, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(214, "VI1CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 214, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(215, "VI1C0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 215, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(216, "VI1C1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 216, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(217, "VI1C2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 217, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(218, "VI1C3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 218, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(219, "VI1C4", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 219, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(220, "VI1C5", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 220, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(221, "VI1C6", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 221, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(222, "VI1C7", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 222, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(223, "VI1C8", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 223, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(224, "VI1C9", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 224, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(225, "VI1Y0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 225, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(226, "VI1Y1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 226, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(227, "VI1Y2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 227, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(228, "VI1Y3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 228, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(229, "VI1Y4", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 229, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(230, "VI1Y5", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 230, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(231, "VI1Y6", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 231, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(232, "VI1Y7", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 232, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(233, "VI1Y8", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 233, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(234, "VI1Y9", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 234, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(235, "VI1DE", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 235, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(236, "VI1HSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 236, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(237, "VI1VSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 237, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(238, "VO1CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 238, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(239, "VO1D0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 239, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(240, "VO1D1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 240, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(241, "VO1D2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 241, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(242, "VO1D3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 242, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(243, "VO1D4", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 243, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(244, "VO1D5", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 244, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(245, "VO1D6", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 245, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(246, "VO1D7", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 246, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(247, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 247, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(248, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 248, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(249, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 249, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(250, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
+ 40, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(251, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
+ 44, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(252, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
+ 48, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(253, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
+ 52, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(254, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
+ 56, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(255, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
+ 60, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+};
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned i2c0_pins[] = {112, 113};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {114, 115};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {116, 117};
+static const unsigned i2c2_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {118, 119};
+static const unsigned i2c3_muxvals[] = {0, 0};
+static const unsigned i2c5_pins[] = {87, 88};
+static const unsigned i2c5_muxvals[] = {2, 2};
+static const unsigned i2c5b_pins[] = {196, 197};
+static const unsigned i2c5b_muxvals[] = {2, 2};
+static const unsigned i2c5c_pins[] = {215, 216};
+static const unsigned i2c5c_muxvals[] = {2, 2};
+static const unsigned i2c6_pins[] = {101, 102};
+static const unsigned i2c6_muxvals[] = {2, 2};
+static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
+ 31, 32, 33, 34, 35};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {26, 27};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {47, 48};
+static const unsigned uart0_muxvals[] = {0, 0};
+static const unsigned uart0b_pins[] = {227, 228};
+static const unsigned uart0b_muxvals[] = {3, 3};
+static const unsigned uart1_pins[] = {49, 50};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {51, 52};
+static const unsigned uart2_muxvals[] = {0, 0};
+static const unsigned uart3_pins[] = {53, 54};
+static const unsigned uart3_muxvals[] = {0, 0};
+static const unsigned usb0_pins[] = {124, 125};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {126, 127};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {128, 129};
+static const unsigned usb2_muxvals[] = {0, 0};
+static const unsigned port_range0_pins[] = {
+ 89, 90, 91, 92, 93, 94, 95, 96, /* PORT0x */
+ 97, 98, 99, 100, 101, 102, 103, 104, /* PORT1x */
+ 251, 252, 253, 254, 255, 247, 248, 249, /* PORT2x */
+ 39, 40, 41, 42, 43, 44, 45, 46, /* PORT3x */
+ 156, 157, 158, 159, 160, 161, 162, 163, /* PORT4x */
+ 164, 165, 166, 167, 168, 169, 170, 171, /* PORT5x */
+ 190, 191, 192, 193, 194, 195, 196, 197, /* PORT6x */
+ 198, 199, 200, 201, 202, 203, 204, 205, /* PORT7x */
+ 120, 121, 122, 123, 55, 56, 57, 58, /* PORT8x */
+ 124, 125, 126, 127, 49, 50, 53, 54, /* PORT9x */
+ 148, 149, 150, 151, 152, 153, 154, 155, /* PORT10x */
+ 133, 134, 131, 130, 138, 139, 136, 135, /* PORT11x */
+ 28, 29, 30, 31, 32, 33, 34, 35, /* PORT12x */
+ 179, 180, 181, 182, 186, 187, 188, 189, /* PORT13x */
+ 4, 5, 6, 7, 8, 9, 10, 11, /* PORT14x */
+};
+static const unsigned port_range0_muxvals[] = {
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
+};
+static const unsigned port_range1_pins[] = {
+ 109, 110, 111, /* PORT175-177 */
+ 206, 207, 208, 209, 210, 211, 212, 213, /* PORT18x */
+ 12, 13, 14, 15, 16, 17, 107, 108, /* PORT19x */
+ 140, 141, 142, 143, 144, 145, 146, 147, /* PORT20x */
+ 59, 60, 61, 62, 63, 64, 65, 66, /* PORT21x */
+ 214, 215, 216, 217, 218, 219, 220, 221, /* PORT22x */
+ 222, 223, 224, 225, 226, 227, 228, 229, /* PORT23x */
+ 19, 20, 21, 22, 23, 24, 25, 26, /* PORT24x */
+ 230, 231, 232, 233, 234, 235, 236, 237, /* PORT25x */
+ 239, 240, 241, 242, 243, 244, 245, 246, /* PORT26x */
+ 172, 173, 174, 175, 176, 177, 178, 129, /* PORT27x */
+ 0, 1, 2, 67, 85, 86, 87, 88, /* PORT28x */
+ 105, 106, 18, 27, 36, 128, 132, 137, /* PORT29x */
+ 183, 184, 185, 84, 47, 48, 51, 52, /* PORT30x */
+};
+static const unsigned port_range1_muxvals[] = {
+ 15, 15, 15, /* PORT175-177 */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT29x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT30x */
+};
+static const unsigned xirq_pins[] = {
+ 68, 69, 70, 71, 72, 73, 74, 75, /* XIRQ0-7 */
+ 76, 77, 78, 79, 80, 81, 82, 83, /* XIRQ8-15 */
+ 84, 85, 86, 87, 88, /* XIRQ16-20 */
+};
+static const unsigned xirq_muxvals[] = {
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */
+ 14, 14, 14, 14, 14, /* XIRQ16-20 */
+};
+static const unsigned xirq_alternatives_pins[] = {
+ 91, 92, 239, 144, 240, 156, 241, 106, 128,
+};
+static const unsigned xirq_alternatives_muxvals[] = {
+ 14, 14, 14, 14, 14, 14, 14, 14, 14,
+};
+
+static const struct uniphier_pinctrl_group ph1_pro5_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c5),
+ UNIPHIER_PINCTRL_GROUP(i2c5b),
+ UNIPHIER_PINCTRL_GROUP(i2c5c),
+ UNIPHIER_PINCTRL_GROUP(i2c6),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart0b),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 24),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 25),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 26),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 27),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 28),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 29),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 30),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 31),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 32),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 33),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 34),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 35),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 36),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 37),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 38),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 39),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 40),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 41),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 42),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 43),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 44),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 45),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 46),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 47),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 48),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 49),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 50),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 51),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 52),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 53),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 54),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 55),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 56),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 57),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 58),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 59),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 60),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 61),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 62),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 63),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 64),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 65),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 66),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 67),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 68),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 69),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 70),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 71),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 72),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 73),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 74),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 75),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 76),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 77),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 78),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 79),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 80),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 81),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 82),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 83),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 84),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 85),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 86),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 87),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 88),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 89),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 90),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port290, port_range1, 91),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port291, port_range1, 92),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port292, port_range1, 93),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port293, port_range1, 94),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port294, port_range1, 95),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port295, port_range1, 96),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port296, port_range1, 97),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port297, port_range1, 98),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port300, port_range1, 99),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port301, port_range1, 100),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port302, port_range1, 101),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port303, port_range1, 102),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port304, port_range1, 103),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port305, port_range1, 104),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port306, port_range1, 105),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port307, port_range1, 106),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3b, xirq_alternatives, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4b, xirq_alternatives, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16b, xirq_alternatives, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17c, xirq_alternatives, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18c, xirq_alternatives, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19b, xirq_alternatives, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20b, xirq_alternatives, 8),
+};
+
+static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const i2c0_groups[] = {"i2c0"};
+static const char * const i2c1_groups[] = {"i2c1"};
+static const char * const i2c2_groups[] = {"i2c2"};
+static const char * const i2c3_groups[] = {"i2c3"};
+static const char * const i2c5_groups[] = {"i2c5", "i2c5b", "i2c5c"};
+static const char * const i2c6_groups[] = {"i2c6"};
+static const char * const nand_groups[] = {"nand", "nand_cs1"};
+static const char * const sd_groups[] = {"sd"};
+static const char * const uart0_groups[] = {"uart0", "uart0b"};
+static const char * const uart1_groups[] = {"uart1"};
+static const char * const uart2_groups[] = {"uart2"};
+static const char * const uart3_groups[] = {"uart3"};
+static const char * const usb0_groups[] = {"usb0"};
+static const char * const usb1_groups[] = {"usb1"};
+static const char * const usb2_groups[] = {"usb2"};
+static const char * const port_groups[] = {
+ "port00", "port01", "port02", "port03",
+ "port04", "port05", "port06", "port07",
+ "port10", "port11", "port12", "port13",
+ "port14", "port15", "port16", "port17",
+ "port20", "port21", "port22", "port23",
+ "port24", "port25", "port26", "port27",
+ "port30", "port31", "port32", "port33",
+ "port34", "port35", "port36", "port37",
+ "port40", "port41", "port42", "port43",
+ "port44", "port45", "port46", "port47",
+ "port50", "port51", "port52", "port53",
+ "port54", "port55", "port56", "port57",
+ "port60", "port61", "port62", "port63",
+ "port64", "port65", "port66", "port67",
+ "port70", "port71", "port72", "port73",
+ "port74", "port75", "port76", "port77",
+ "port80", "port81", "port82", "port83",
+ "port84", "port85", "port86", "port87",
+ "port90", "port91", "port92", "port93",
+ "port94", "port95", "port96", "port97",
+ "port100", "port101", "port102", "port103",
+ "port104", "port105", "port106", "port107",
+ "port110", "port111", "port112", "port113",
+ "port114", "port115", "port116", "port117",
+ "port120", "port121", "port122", "port123",
+ "port124", "port125", "port126", "port127",
+ "port130", "port131", "port132", "port133",
+ "port134", "port135", "port136", "port137",
+ "port140", "port141", "port142", "port143",
+ "port144", "port145", "port146", "port147",
+ /* port150-174 missing */
+ /* none */ "port175", "port176", "port177",
+ "port180", "port181", "port182", "port183",
+ "port184", "port185", "port186", "port187",
+ "port190", "port191", "port192", "port193",
+ "port194", "port195", "port196", "port197",
+ "port200", "port201", "port202", "port203",
+ "port204", "port205", "port206", "port207",
+ "port210", "port211", "port212", "port213",
+ "port214", "port215", "port216", "port217",
+ "port220", "port221", "port222", "port223",
+ "port224", "port225", "port226", "port227",
+ "port230", "port231", "port232", "port233",
+ "port234", "port235", "port236", "port237",
+ "port240", "port241", "port242", "port243",
+ "port244", "port245", "port246", "port247",
+ "port250", "port251", "port252", "port253",
+ "port254", "port255", "port256", "port257",
+ "port260", "port261", "port262", "port263",
+ "port264", "port265", "port266", "port267",
+ "port270", "port271", "port272", "port273",
+ "port274", "port275", "port276", "port277",
+ "port280", "port281", "port282", "port283",
+ "port284", "port285", "port286", "port287",
+ "port290", "port291", "port292", "port293",
+ "port294", "port295", "port296", "port297",
+ "port300", "port301", "port302", "port303",
+ "port304", "port305", "port306", "port307",
+};
+static const char * const xirq_groups[] = {
+ "xirq0", "xirq1", "xirq2", "xirq3",
+ "xirq4", "xirq5", "xirq6", "xirq7",
+ "xirq8", "xirq9", "xirq10", "xirq11",
+ "xirq12", "xirq13", "xirq14", "xirq15",
+ "xirq16", "xirq17", "xirq18", "xirq19",
+ "xirq20",
+ "xirq3b", "xirq4b", "xirq16b", "xirq17b", "xirq17c",
+ "xirq18b", "xirq18c", "xirq19b", "xirq20b",
+};
+
+static const struct uniphier_pinmux_function ph1_pro5_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(i2c0),
+ UNIPHIER_PINMUX_FUNCTION(i2c1),
+ UNIPHIER_PINMUX_FUNCTION(i2c2),
+ UNIPHIER_PINMUX_FUNCTION(i2c3),
+ UNIPHIER_PINMUX_FUNCTION(i2c5),
+ UNIPHIER_PINMUX_FUNCTION(i2c6),
+ UNIPHIER_PINMUX_FUNCTION(nand),
+ UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(uart0),
+ UNIPHIER_PINMUX_FUNCTION(uart1),
+ UNIPHIER_PINMUX_FUNCTION(uart2),
+ UNIPHIER_PINMUX_FUNCTION(uart3),
+ UNIPHIER_PINMUX_FUNCTION(usb0),
+ UNIPHIER_PINMUX_FUNCTION(usb1),
+ UNIPHIER_PINMUX_FUNCTION(usb2),
+ UNIPHIER_PINMUX_FUNCTION(port),
+ UNIPHIER_PINMUX_FUNCTION(xirq),
+};
+
+static struct uniphier_pinctrl_socdata ph1_pro5_pindata = {
+ .groups = ph1_pro5_groups,
+ .groups_count = ARRAY_SIZE(ph1_pro5_groups),
+ .functions = ph1_pro5_functions,
+ .functions_count = ARRAY_SIZE(ph1_pro5_functions),
+ .mux_bits = 4,
+ .reg_stride = 8,
+ .load_pinctrl = true,
+};
+
+static struct pinctrl_desc ph1_pro5_pinctrl_desc = {
+ .name = DRIVER_NAME,
+ .pins = ph1_pro5_pins,
+ .npins = ARRAY_SIZE(ph1_pro5_pins),
+ .owner = THIS_MODULE,
+};
+
+static int ph1_pro5_pinctrl_probe(struct platform_device *pdev)
+{
+ return uniphier_pinctrl_probe(pdev, &ph1_pro5_pinctrl_desc,
+ &ph1_pro5_pindata);
+}
+
+static const struct of_device_id ph1_pro5_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-pro5-pinctrl" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ph1_pro5_pinctrl_match);
+
+static struct platform_driver ph1_pro5_pinctrl_driver = {
+ .probe = ph1_pro5_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = ph1_pro5_pinctrl_match,
+ },
+};
+module_platform_driver(ph1_pro5_pinctrl_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-Pro5 pinctrl driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-uniphier.h"
+
+#define DRIVER_NAME "proxstream2-pinctrl"
+
+static const struct pinctrl_pin_desc proxstream2_pins[] = {
+ UNIPHIER_PINCTRL_PIN(0, "ED0", UNIPHIER_PIN_IECTRL_NONE,
+ 0, UNIPHIER_PIN_DRV_4_8,
+ 0, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(1, "ED1", UNIPHIER_PIN_IECTRL_NONE,
+ 1, UNIPHIER_PIN_DRV_4_8,
+ 1, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(2, "ED2", UNIPHIER_PIN_IECTRL_NONE,
+ 2, UNIPHIER_PIN_DRV_4_8,
+ 2, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(3, "ED3", UNIPHIER_PIN_IECTRL_NONE,
+ 3, UNIPHIER_PIN_DRV_4_8,
+ 3, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(4, "ED4", UNIPHIER_PIN_IECTRL_NONE,
+ 4, UNIPHIER_PIN_DRV_4_8,
+ 4, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(5, "ED5", UNIPHIER_PIN_IECTRL_NONE,
+ 5, UNIPHIER_PIN_DRV_4_8,
+ 5, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(6, "ED6", UNIPHIER_PIN_IECTRL_NONE,
+ 6, UNIPHIER_PIN_DRV_4_8,
+ 6, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(7, "ED7", UNIPHIER_PIN_IECTRL_NONE,
+ 7, UNIPHIER_PIN_DRV_4_8,
+ 7, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(8, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
+ 8, UNIPHIER_PIN_DRV_4_8,
+ 8, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(9, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
+ 9, UNIPHIER_PIN_DRV_4_8,
+ 9, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(10, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
+ 10, UNIPHIER_PIN_DRV_4_8,
+ 10, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(11, "ES0", UNIPHIER_PIN_IECTRL_NONE,
+ 11, UNIPHIER_PIN_DRV_4_8,
+ 11, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(12, "ES1", UNIPHIER_PIN_IECTRL_NONE,
+ 12, UNIPHIER_PIN_DRV_4_8,
+ 12, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(13, "ES2", UNIPHIER_PIN_IECTRL_NONE,
+ 13, UNIPHIER_PIN_DRV_4_8,
+ 13, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(14, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
+ 14, UNIPHIER_PIN_DRV_4_8,
+ 14, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(15, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 15, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(16, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 16, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(17, "SMTD0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 17, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(18, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 18, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(19, "SMTCLK0CG", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 19, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(20, "SMTDET0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 20, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(21, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 21, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(22, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 22, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(23, "SMTD1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 23, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(24, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 24, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(25, "SMTCLK1CG", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 25, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(26, "SMTDET1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 26, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(27, "XIRQ18", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 27, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(28, "XIRQ19", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 28, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(29, "XIRQ20", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 29, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(30, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
+ 30, UNIPHIER_PIN_DRV_4_8,
+ 30, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(31, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
+ 31, UNIPHIER_PIN_DRV_4_8,
+ 31, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(32, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
+ 32, UNIPHIER_PIN_DRV_4_8,
+ 32, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(33, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
+ 33, UNIPHIER_PIN_DRV_4_8,
+ 33, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(34, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
+ 34, UNIPHIER_PIN_DRV_4_8,
+ 34, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(35, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
+ 35, UNIPHIER_PIN_DRV_4_8,
+ 35, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(36, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE,
+ 36, UNIPHIER_PIN_DRV_4_8,
+ 36, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(37, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE,
+ 37, UNIPHIER_PIN_DRV_4_8,
+ 37, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(38, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE,
+ 38, UNIPHIER_PIN_DRV_4_8,
+ 38, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(39, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
+ 39, UNIPHIER_PIN_DRV_4_8,
+ 39, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(40, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
+ 40, UNIPHIER_PIN_DRV_4_8,
+ 40, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(41, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
+ 41, UNIPHIER_PIN_DRV_4_8,
+ 41, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(42, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
+ 42, UNIPHIER_PIN_DRV_4_8,
+ 42, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(43, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
+ 43, UNIPHIER_PIN_DRV_4_8,
+ 43, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(44, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
+ 44, UNIPHIER_PIN_DRV_4_8,
+ 44, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(45, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
+ 45, UNIPHIER_PIN_DRV_4_8,
+ 45, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(46, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
+ 46, UNIPHIER_PIN_DRV_4_8,
+ 46, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
+ 0, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(48, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
+ 4, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(49, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
+ 8, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(50, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
+ 12, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(51, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
+ 16, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(52, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
+ 20, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_UP_FIXED),
+ UNIPHIER_PINCTRL_PIN(53, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 53, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(54, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 54, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(55, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 55, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(56, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 56, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(57, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 57, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(58, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 58, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(59, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 59, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(60, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 60, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(61, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 61, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(62, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 62, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(63, "USB3OD", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 63, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(64, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 64, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(65, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 65, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(66, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 66, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(67, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 67, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(68, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 68, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(69, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 69, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(70, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 70, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(71, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 71, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(72, "XIRQ9", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 72, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(73, "XIRQ10", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 73, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(74, "XIRQ16", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 74, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(75, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 75, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(76, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 76, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(77, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 77, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(78, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 78, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(79, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 79, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(80, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 80, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(81, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 81, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(82, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 82, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(83, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 83, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(84, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 84, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(85, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 85, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(86, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 86, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(87, "STS0CLKO", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 87, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(88, "STS0SYNCO", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 88, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(89, "STS0VALO", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 89, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(90, "STS0DATAO", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 90, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(91, "XIRQ17", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 91, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(92, "PORT163", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 92, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(93, "PORT165", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 93, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(94, "PORT166", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 94, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(95, "PORT132", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 95, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(96, "PORT133", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 96, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(97, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 97, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(98, "AI2ADCCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 98, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(99, "AI2BCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 99, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(100, "AI2LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 100, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(101, "AI2D0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 101, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(102, "AI2D1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 102, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(103, "AI2D2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 103, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(104, "AI2D3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 104, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(105, "AO3DACCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 105, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(106, "AO3BCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 106, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(107, "AO3LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 107, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(108, "AO3DMIX", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 108, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(109, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 109, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(110, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 110, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(111, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 111, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(112, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 112, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(113, "TXD2", 0,
+ 113, UNIPHIER_PIN_DRV_4_8,
+ 113, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(114, "RXD2", 0,
+ 114, UNIPHIER_PIN_DRV_4_8,
+ 114, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(115, "TXD1", 0,
+ 115, UNIPHIER_PIN_DRV_4_8,
+ 115, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(116, "RXD1", 0,
+ 116, UNIPHIER_PIN_DRV_4_8,
+ 116, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(117, "PORT190", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 117, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(118, "VI1HSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 118, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(119, "VI1VSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 119, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(120, "VI1DE", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 120, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(121, "XIRQ3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 121, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(122, "XIRQ4", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 122, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(123, "VI1G2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 123, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(124, "VI1G3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 124, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(125, "VI1G4", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 125, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(126, "VI1G5", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 126, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(127, "VI1G6", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 127, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(128, "VI1G7", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 128, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(129, "VI1G8", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 129, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(130, "VI1G9", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 130, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(131, "VI1CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 131, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(132, "PORT05", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 132, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(133, "PORT06", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 133, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(134, "VI1R2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 134, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(135, "VI1R3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 135, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(136, "VI1R4", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 136, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(137, "VI1R5", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 137, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(138, "VI1R6", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 138, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(139, "VI1R7", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 139, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(140, "VI1R8", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 140, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(141, "VI1R9", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 141, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(142, "LPST", UNIPHIER_PIN_IECTRL_NONE,
+ 142, UNIPHIER_PIN_DRV_4_8,
+ 142, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(143, "MDC", 0,
+ 143, UNIPHIER_PIN_DRV_4_8,
+ 143, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(144, "MDIO", 0,
+ 144, UNIPHIER_PIN_DRV_4_8,
+ 144, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(145, "MDIO_INTL", 0,
+ 145, UNIPHIER_PIN_DRV_4_8,
+ 145, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(146, "PHYRSTL", 0,
+ 146, UNIPHIER_PIN_DRV_4_8,
+ 146, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(147, "RGMII_RXCLK", 0,
+ 147, UNIPHIER_PIN_DRV_4_8,
+ 147, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(148, "RGMII_RXD0", 0,
+ 148, UNIPHIER_PIN_DRV_4_8,
+ 148, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(149, "RGMII_RXD1", 0,
+ 149, UNIPHIER_PIN_DRV_4_8,
+ 149, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(150, "RGMII_RXD2", 0,
+ 150, UNIPHIER_PIN_DRV_4_8,
+ 150, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(151, "RGMII_RXD3", 0,
+ 151, UNIPHIER_PIN_DRV_4_8,
+ 151, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(152, "RGMII_RXCTL", 0,
+ 152, UNIPHIER_PIN_DRV_4_8,
+ 152, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(153, "RGMII_TXCLK", 0,
+ 153, UNIPHIER_PIN_DRV_4_8,
+ 153, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(154, "RGMII_TXD0", 0,
+ 154, UNIPHIER_PIN_DRV_4_8,
+ 154, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(155, "RGMII_TXD1", 0,
+ 155, UNIPHIER_PIN_DRV_4_8,
+ 155, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(156, "RGMII_TXD2", 0,
+ 156, UNIPHIER_PIN_DRV_4_8,
+ 156, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(157, "RGMII_TXD3", 0,
+ 157, UNIPHIER_PIN_DRV_4_8,
+ 157, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(158, "RGMII_TXCTL", 0,
+ 158, UNIPHIER_PIN_DRV_4_8,
+ 158, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(159, "SDA3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 159, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(160, "SCL3", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 160, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(161, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 161, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(162, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 162, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(163, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 163, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(164, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 164, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(165, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 165, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(166, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 166, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(167, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 167, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(168, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 168, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(169, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 169, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(170, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 170, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(171, "SDA2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 171, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(172, "SCL2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 172, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(173, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 173, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(174, "AI1D0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 174, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(175, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 175, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(176, "AO2D0", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 176, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(177, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 177, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(178, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 178, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(179, "PORT222", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 179, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(180, "PORT223", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 180, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(181, "PORT224", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 181, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(182, "PORT225", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 182, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(183, "PORT226", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 183, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(184, "PORT227", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 184, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(185, "PORT230", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 185, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(186, "FANPWM", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 186, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(187, "HRDDCSDA0", 0,
+ 187, UNIPHIER_PIN_DRV_4_8,
+ 187, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(188, "HRDDCSCL0", 0,
+ 188, UNIPHIER_PIN_DRV_4_8,
+ 188, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(189, "HRDDCSDA1", 0,
+ 189, UNIPHIER_PIN_DRV_4_8,
+ 189, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(190, "HRDDCSCL1", 0,
+ 190, UNIPHIER_PIN_DRV_4_8,
+ 190, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(191, "HTDDCSDA0", 0,
+ 191, UNIPHIER_PIN_DRV_4_8,
+ 191, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(192, "HTDDCSCL0", 0,
+ 192, UNIPHIER_PIN_DRV_4_8,
+ 192, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(193, "HTDDCSDA1", 0,
+ 193, UNIPHIER_PIN_DRV_4_8,
+ 193, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(194, "HTDDCSCL1", 0,
+ 194, UNIPHIER_PIN_DRV_4_8,
+ 194, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(195, "PORT241", 0,
+ 195, UNIPHIER_PIN_DRV_4_8,
+ 195, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(196, "PORT242", 0,
+ 196, UNIPHIER_PIN_DRV_4_8,
+ 196, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(197, "PORT243", 0,
+ 197, UNIPHIER_PIN_DRV_4_8,
+ 197, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(198, "MVSYNC", 0,
+ 198, UNIPHIER_PIN_DRV_4_8,
+ 198, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(199, "SPISYNC0", UNIPHIER_PIN_IECTRL_NONE,
+ 199, UNIPHIER_PIN_DRV_4_8,
+ 199, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(200, "SPISCLK0", UNIPHIER_PIN_IECTRL_NONE,
+ 200, UNIPHIER_PIN_DRV_4_8,
+ 200, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(201, "SPITXD0", UNIPHIER_PIN_IECTRL_NONE,
+ 201, UNIPHIER_PIN_DRV_4_8,
+ 201, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(202, "SPIRXD0", UNIPHIER_PIN_IECTRL_NONE,
+ 202, UNIPHIER_PIN_DRV_4_8,
+ 202, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(203, "CK54EXI", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 203, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(204, "AEXCKA1", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 204, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(205, "AEXCKA2", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 205, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(206, "CK27EXI", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_8,
+ 206, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(207, "STCDIN", 0,
+ 207, UNIPHIER_PIN_DRV_4_8,
+ 207, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(208, "PHSYNI", 0,
+ 208, UNIPHIER_PIN_DRV_4_8,
+ 208, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(209, "PVSYNI", 0,
+ 209, UNIPHIER_PIN_DRV_4_8,
+ 209, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(210, "MVSYN", UNIPHIER_PIN_IECTRL_NONE,
+ 210, UNIPHIER_PIN_DRV_4_8,
+ 210, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(211, "STCV", UNIPHIER_PIN_IECTRL_NONE,
+ 211, UNIPHIER_PIN_DRV_4_8,
+ 211, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(212, "PORT262", UNIPHIER_PIN_IECTRL_NONE,
+ 212, UNIPHIER_PIN_DRV_4_8,
+ 212, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(213, "USB0VBUS_IRQ", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 213, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(214, "USB1VBUS_IRQ", UNIPHIER_PIN_IECTRL_NONE,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 214, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(215, "PORT265", UNIPHIER_PIN_IECTRL_NONE,
+ 215, UNIPHIER_PIN_DRV_4_8,
+ 215, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(216, "CK25O", 0,
+ 216, UNIPHIER_PIN_DRV_4_8,
+ 216, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(217, "TXD0", 0,
+ 217, UNIPHIER_PIN_DRV_4_8,
+ 217, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(218, "RXD0", 0,
+ 218, UNIPHIER_PIN_DRV_4_8,
+ 218, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(219, "TXD3", 0,
+ 219, UNIPHIER_PIN_DRV_4_8,
+ 219, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(220, "RXD3", 0,
+ 220, UNIPHIER_PIN_DRV_4_8,
+ 220, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(221, "PORT273", 0,
+ 221, UNIPHIER_PIN_DRV_4_8,
+ 221, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(222, "STCDOUTC", 0,
+ 222, UNIPHIER_PIN_DRV_4_8,
+ 222, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(223, "PORT274", 0,
+ 223, UNIPHIER_PIN_DRV_4_8,
+ 223, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(224, "PORT275", 0,
+ 224, UNIPHIER_PIN_DRV_4_8,
+ 224, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(225, "PORT276", 0,
+ 225, UNIPHIER_PIN_DRV_4_8,
+ 225, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(226, "PORT277", 0,
+ 226, UNIPHIER_PIN_DRV_4_8,
+ 226, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(227, "PORT280", 0,
+ 227, UNIPHIER_PIN_DRV_4_8,
+ 227, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(228, "PORT281", 0,
+ 228, UNIPHIER_PIN_DRV_4_8,
+ 228, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(229, "PORT282", 0,
+ 229, UNIPHIER_PIN_DRV_4_8,
+ 229, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(230, "PORT283", 0,
+ 230, UNIPHIER_PIN_DRV_4_8,
+ 230, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(231, "PORT284", 0,
+ 231, UNIPHIER_PIN_DRV_4_8,
+ 231, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(232, "PORT285", 0,
+ 232, UNIPHIER_PIN_DRV_4_8,
+ 232, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(233, "T0HPD", 0,
+ 233, UNIPHIER_PIN_DRV_4_8,
+ 233, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(234, "T1HPD", 0,
+ 234, UNIPHIER_PIN_DRV_4_8,
+ 234, UNIPHIER_PIN_PULL_DOWN),
+};
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const unsigned emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const unsigned emmc_dat8_muxvals[] = {9, 9, 9, 9};
+static const unsigned i2c0_pins[] = {109, 110};
+static const unsigned i2c0_muxvals[] = {8, 8};
+static const unsigned i2c1_pins[] = {111, 112};
+static const unsigned i2c1_muxvals[] = {8, 8};
+static const unsigned i2c2_pins[] = {171, 172};
+static const unsigned i2c2_muxvals[] = {8, 8};
+static const unsigned i2c3_pins[] = {159, 160};
+static const unsigned i2c3_muxvals[] = {8, 8};
+static const unsigned i2c5_pins[] = {183, 184};
+static const unsigned i2c5_muxvals[] = {11, 11};
+static const unsigned i2c6_pins[] = {185, 186};
+static const unsigned i2c6_muxvals[] = {11, 11};
+static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
+ 42, 43, 44, 45, 46};
+static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8};
+static const unsigned nand_cs1_pins[] = {37, 38};
+static const unsigned nand_cs1_muxvals[] = {8, 8};
+static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
+static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
+static const unsigned uart0_pins[] = {217, 218};
+static const unsigned uart0_muxvals[] = {8, 8};
+static const unsigned uart0b_pins[] = {179, 180};
+static const unsigned uart0b_muxvals[] = {10, 10};
+static const unsigned uart1_pins[] = {115, 116};
+static const unsigned uart1_muxvals[] = {8, 8};
+static const unsigned uart2_pins[] = {113, 114};
+static const unsigned uart2_muxvals[] = {8, 8};
+static const unsigned uart3_pins[] = {219, 220};
+static const unsigned uart3_muxvals[] = {8, 8};
+static const unsigned uart3b_pins[] = {181, 182};
+static const unsigned uart3b_muxvals[] = {10, 10};
+static const unsigned usb0_pins[] = {56, 57};
+static const unsigned usb0_muxvals[] = {8, 8};
+static const unsigned usb1_pins[] = {58, 59};
+static const unsigned usb1_muxvals[] = {8, 8};
+static const unsigned usb2_pins[] = {60, 61};
+static const unsigned usb2_muxvals[] = {8, 8};
+static const unsigned usb3_pins[] = {62, 63};
+static const unsigned usb3_muxvals[] = {8, 8};
+static const unsigned port_range0_pins[] = {
+ 127, 128, 129, 130, 131, 132, 133, 134, /* PORT0x */
+ 135, 136, 137, 138, 139, 140, 141, 142, /* PORT1x */
+ 0, 1, 2, 3, 4, 5, 6, 7, /* PORT2x */
+ 8, 9, 10, 11, 12, 13, 14, 15, /* PORT3x */
+ 16, 17, 18, 19, 21, 22, 23, 24, /* PORT4x */
+ 25, 30, 31, 32, 33, 34, 35, 36, /* PORT5x */
+ 37, 38, 39, 40, 41, 42, 43, 44, /* PORT6x */
+ 45, 46, 47, 48, 49, 50, 51, 52, /* PORT7x */
+ 53, 54, 55, 56, 57, 58, 59, 60, /* PORT8x */
+ 61, 62, 63, 64, 65, 66, 67, 68, /* PORT9x */
+ 69, 70, 71, 76, 77, 78, 79, 80, /* PORT10x */
+};
+static const unsigned port_range0_muxvals[] = {
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
+};
+static const unsigned port_range1_pins[] = {
+ 81, 82, 83, 84, 85, 86, 87, 88, /* PORT12x */
+ 89, 90, 95, 96, 97, 98, 99, 100, /* PORT13x */
+ 101, 102, 103, 104, 105, 106, 107, 108, /* PORT14x */
+ 118, 119, 120, 121, 122, 123, 124, 125, /* PORT15x */
+ 126, 72, 73, 92, 177, 93, 94, 176, /* PORT16x */
+ 74, 91, 27, 28, 29, 75, 20, 26, /* PORT17x */
+ 109, 110, 111, 112, 113, 114, 115, 116, /* PORT18x */
+ 117, 143, 144, 145, 146, 147, 148, 149, /* PORT19x */
+ 150, 151, 152, 153, 154, 155, 156, 157, /* PORT20x */
+ 158, 159, 160, 161, 162, 163, 164, 165, /* PORT21x */
+ 166, 178, 179, 180, 181, 182, 183, 184, /* PORT22x */
+ 185, 187, 188, 189, 190, 191, 192, 193, /* PORT23x */
+ 194, 195, 196, 197, 198, 199, 200, 201, /* PORT24x */
+ 202, 203, 204, 205, 206, 207, 208, 209, /* PORT25x */
+ 210, 211, 212, 213, 214, 215, 216, 217, /* PORT26x */
+ 218, 219, 220, 221, 223, 224, 225, 226, /* PORT27x */
+ 227, 228, 229, 230, 231, 232, 233, 234, /* PORT28x */
+};
+static const unsigned port_range1_muxvals[] = {
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT15x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT16x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT17x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */
+};
+static const unsigned xirq_pins[] = {
+ 118, 119, 120, 121, 122, 123, 124, 125, /* XIRQ0-7 */
+ 126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */
+ 74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */
+};
+static const unsigned xirq_muxvals[] = {
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */
+};
+
+static const struct uniphier_pinctrl_group proxstream2_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c5),
+ UNIPHIER_PINCTRL_GROUP(i2c6),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart0b),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(uart3b),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb3),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range1, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range1, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range1, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range1, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range1, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range1, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range1, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range1, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range1, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range1, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range1, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range1, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range1, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range1, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range1, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range1, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range1, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range1, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range1, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range1, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range1, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range1, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port150, port_range1, 24),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port151, port_range1, 25),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port152, port_range1, 26),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port153, port_range1, 27),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port154, port_range1, 28),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port155, port_range1, 29),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port156, port_range1, 30),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port157, port_range1, 31),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port160, port_range1, 32),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port161, port_range1, 33),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port162, port_range1, 34),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port163, port_range1, 35),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port164, port_range1, 36),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 37),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range1, 38),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port167, port_range1, 39),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port170, port_range1, 40),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port171, port_range1, 41),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port172, port_range1, 42),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port173, port_range1, 43),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port174, port_range1, 44),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 45),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 46),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 47),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 48),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 49),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 50),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 51),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 52),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 53),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 54),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 55),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 56),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 57),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 58),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 59),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 60),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 61),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 62),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 63),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 64),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 65),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 66),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 67),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 68),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 69),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 70),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 71),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 72),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 73),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 74),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 75),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 76),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 77),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 78),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 79),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 80),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 81),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 82),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 83),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 84),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 85),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 86),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 87),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 88),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 89),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 90),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 91),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 92),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 93),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 94),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 95),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 96),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 97),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 98),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 99),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 100),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 101),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 102),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 103),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 104),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 105),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 106),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 107),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 108),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 109),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 110),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 111),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 112),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 113),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 114),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 115),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 116),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 117),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 118),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 119),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 120),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 121),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 122),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 123),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 124),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 125),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 126),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 127),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 128),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 129),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 130),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 131),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 132),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 133),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 134),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 135),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23),
+};
+
+static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const i2c0_groups[] = {"i2c0"};
+static const char * const i2c1_groups[] = {"i2c1"};
+static const char * const i2c2_groups[] = {"i2c2"};
+static const char * const i2c3_groups[] = {"i2c3"};
+static const char * const i2c5_groups[] = {"i2c5"};
+static const char * const i2c6_groups[] = {"i2c6"};
+static const char * const nand_groups[] = {"nand", "nand_cs1"};
+static const char * const sd_groups[] = {"sd"};
+static const char * const uart0_groups[] = {"uart0", "uart0b"};
+static const char * const uart1_groups[] = {"uart1"};
+static const char * const uart2_groups[] = {"uart2"};
+static const char * const uart3_groups[] = {"uart3", "uart3b"};
+static const char * const usb0_groups[] = {"usb0"};
+static const char * const usb1_groups[] = {"usb1"};
+static const char * const usb2_groups[] = {"usb2"};
+static const char * const usb3_groups[] = {"usb3"};
+static const char * const port_groups[] = {
+ "port00", "port01", "port02", "port03",
+ "port04", "port05", "port06", "port07",
+ "port10", "port11", "port12", "port13",
+ "port14", "port15", "port16", "port17",
+ "port20", "port21", "port22", "port23",
+ "port24", "port25", "port26", "port27",
+ "port30", "port31", "port32", "port33",
+ "port34", "port35", "port36", "port37",
+ "port40", "port41", "port42", "port43",
+ "port44", "port45", "port46", "port47",
+ "port50", "port51", "port52", "port53",
+ "port54", "port55", "port56", "port57",
+ "port60", "port61", "port62", "port63",
+ "port64", "port65", "port66", "port67",
+ "port70", "port71", "port72", "port73",
+ "port74", "port75", "port76", "port77",
+ "port80", "port81", "port82", "port83",
+ "port84", "port85", "port86", "port87",
+ "port90", "port91", "port92", "port93",
+ "port94", "port95", "port96", "port97",
+ "port100", "port101", "port102", "port103",
+ "port104", "port105", "port106", "port107",
+ /* port110-117 missing */
+ "port120", "port121", "port122", "port123",
+ "port124", "port125", "port126", "port127",
+ "port130", "port131", "port132", "port133",
+ "port134", "port135", "port136", "port137",
+ "port140", "port141", "port142", "port143",
+ "port144", "port145", "port146", "port147",
+ "port150", "port151", "port152", "port153",
+ "port154", "port155", "port156", "port157",
+ "port160", "port161", "port162", "port163",
+ "port164", "port165", "port166", "port167",
+ "port170", "port171", "port172", "port173",
+ "port174", "port175", "port176", "port177",
+ "port180", "port181", "port182", "port183",
+ "port184", "port185", "port186", "port187",
+ "port190", "port191", "port192", "port193",
+ "port194", "port195", "port196", "port197",
+ "port200", "port201", "port202", "port203",
+ "port204", "port205", "port206", "port207",
+ "port210", "port211", "port212", "port213",
+ "port214", "port215", "port216", "port217",
+ "port220", "port221", "port222", "port223",
+ "port224", "port225", "port226", "port227",
+ "port230", "port231", "port232", "port233",
+ "port234", "port235", "port236", "port237",
+ "port240", "port241", "port242", "port243",
+ "port244", "port245", "port246", "port247",
+ "port250", "port251", "port252", "port253",
+ "port254", "port255", "port256", "port257",
+ "port260", "port261", "port262", "port263",
+ "port264", "port265", "port266", "port267",
+ "port270", "port271", "port272", "port273",
+ "port274", "port275", "port276", "port277",
+ "port280", "port281", "port282", "port283",
+ "port284", "port285", "port286", "port287",
+};
+static const char * const xirq_groups[] = {
+ "xirq0", "xirq1", "xirq2", "xirq3",
+ "xirq4", "xirq5", "xirq6", "xirq7",
+ "xirq8", "xirq9", "xirq10", "xirq11",
+ "xirq12", "xirq13", "xirq14", "xirq15",
+ "xirq16", "xirq17", "xirq18", "xirq19",
+ "xirq20", "xirq21", "xirq22", "xirq23",
+};
+
+static const struct uniphier_pinmux_function proxstream2_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(i2c0),
+ UNIPHIER_PINMUX_FUNCTION(i2c1),
+ UNIPHIER_PINMUX_FUNCTION(i2c2),
+ UNIPHIER_PINMUX_FUNCTION(i2c3),
+ UNIPHIER_PINMUX_FUNCTION(i2c5),
+ UNIPHIER_PINMUX_FUNCTION(i2c6),
+ UNIPHIER_PINMUX_FUNCTION(nand),
+ UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(uart0),
+ UNIPHIER_PINMUX_FUNCTION(uart1),
+ UNIPHIER_PINMUX_FUNCTION(uart2),
+ UNIPHIER_PINMUX_FUNCTION(uart3),
+ UNIPHIER_PINMUX_FUNCTION(usb0),
+ UNIPHIER_PINMUX_FUNCTION(usb1),
+ UNIPHIER_PINMUX_FUNCTION(usb2),
+ UNIPHIER_PINMUX_FUNCTION(usb3),
+ UNIPHIER_PINMUX_FUNCTION(port),
+ UNIPHIER_PINMUX_FUNCTION(xirq),
+};
+
+static struct uniphier_pinctrl_socdata proxstream2_pindata = {
+ .groups = proxstream2_groups,
+ .groups_count = ARRAY_SIZE(proxstream2_groups),
+ .functions = proxstream2_functions,
+ .functions_count = ARRAY_SIZE(proxstream2_functions),
+ .mux_bits = 8,
+ .reg_stride = 4,
+ .load_pinctrl = false,
+};
+
+static struct pinctrl_desc proxstream2_pinctrl_desc = {
+ .name = DRIVER_NAME,
+ .pins = proxstream2_pins,
+ .npins = ARRAY_SIZE(proxstream2_pins),
+ .owner = THIS_MODULE,
+};
+
+static int proxstream2_pinctrl_probe(struct platform_device *pdev)
+{
+ return uniphier_pinctrl_probe(pdev, &proxstream2_pinctrl_desc,
+ &proxstream2_pindata);
+}
+
+static const struct of_device_id proxstream2_pinctrl_match[] = {
+ { .compatible = "socionext,proxstream2-pinctrl" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, proxstream2_pinctrl_match);
+
+static struct platform_driver proxstream2_pinctrl_driver = {
+ .probe = proxstream2_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = proxstream2_pinctrl_match,
+ },
+};
+module_platform_driver(proxstream2_pinctrl_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier ProXstream2 pinctrl driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-uniphier.h"
+
+#define DRIVER_NAME "ph1-sld8-pinctrl"
+
+static const struct pinctrl_pin_desc ph1_sld8_pins[] = {
+ UNIPHIER_PINCTRL_PIN(0, "PCA00", 0,
+ 15, UNIPHIER_PIN_DRV_4_8,
+ 15, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(1, "PCA01", 0,
+ 16, UNIPHIER_PIN_DRV_4_8,
+ 16, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(2, "PCA02", 0,
+ 17, UNIPHIER_PIN_DRV_4_8,
+ 17, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(3, "PCA03", 0,
+ 18, UNIPHIER_PIN_DRV_4_8,
+ 18, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(4, "PCA04", 0,
+ 19, UNIPHIER_PIN_DRV_4_8,
+ 19, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(5, "PCA05", 0,
+ 20, UNIPHIER_PIN_DRV_4_8,
+ 20, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(6, "PCA06", 0,
+ 21, UNIPHIER_PIN_DRV_4_8,
+ 21, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(7, "PCA07", 0,
+ 22, UNIPHIER_PIN_DRV_4_8,
+ 22, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(8, "PCA08", 0,
+ 23, UNIPHIER_PIN_DRV_4_8,
+ 23, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(9, "PCA09", 0,
+ 24, UNIPHIER_PIN_DRV_4_8,
+ 24, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(10, "PCA10", 0,
+ 25, UNIPHIER_PIN_DRV_4_8,
+ 25, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(11, "PCA11", 0,
+ 26, UNIPHIER_PIN_DRV_4_8,
+ 26, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(12, "PCA12", 0,
+ 27, UNIPHIER_PIN_DRV_4_8,
+ 27, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(13, "PCA13", 0,
+ 28, UNIPHIER_PIN_DRV_4_8,
+ 28, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(14, "PCA14", 0,
+ 29, UNIPHIER_PIN_DRV_4_8,
+ 29, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(15, "XNFRE_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 30, UNIPHIER_PIN_DRV_4_8,
+ 30, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(16, "XNFWE_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 31, UNIPHIER_PIN_DRV_4_8,
+ 31, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(17, "NFALE_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 32, UNIPHIER_PIN_DRV_4_8,
+ 32, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(18, "NFCLE_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 33, UNIPHIER_PIN_DRV_4_8,
+ 33, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(19, "XNFWP_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 34, UNIPHIER_PIN_DRV_4_8,
+ 34, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(20, "XNFCE0_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 35, UNIPHIER_PIN_DRV_4_8,
+ 35, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(21, "NANDRYBY0_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 36, UNIPHIER_PIN_DRV_4_8,
+ 36, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(22, "XNFCE1_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 0, UNIPHIER_PIN_DRV_8_12_16_20,
+ 119, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(23, "NANDRYBY1_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 4, UNIPHIER_PIN_DRV_8_12_16_20,
+ 120, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(24, "NFD0_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 8, UNIPHIER_PIN_DRV_8_12_16_20,
+ 121, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(25, "NFD1_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 12, UNIPHIER_PIN_DRV_8_12_16_20,
+ 122, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(26, "NFD2_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 16, UNIPHIER_PIN_DRV_8_12_16_20,
+ 123, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(27, "NFD3_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 20, UNIPHIER_PIN_DRV_8_12_16_20,
+ 124, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(28, "NFD4_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 24, UNIPHIER_PIN_DRV_8_12_16_20,
+ 125, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(29, "NFD5_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 28, UNIPHIER_PIN_DRV_8_12_16_20,
+ 126, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(30, "NFD6_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 32, UNIPHIER_PIN_DRV_8_12_16_20,
+ 127, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(31, "NFD7_GB", UNIPHIER_PIN_IECTRL_NONE,
+ 36, UNIPHIER_PIN_DRV_8_12_16_20,
+ 128, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(32, "SDCLK", 8,
+ 40, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(33, "SDCMD", 8,
+ 44, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(34, "SDDAT0", 8,
+ 48, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(35, "SDDAT1", 8,
+ 52, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(36, "SDDAT2", 8,
+ 56, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(37, "SDDAT3", 8,
+ 60, UNIPHIER_PIN_DRV_8_12_16_20,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(38, "SDCD", 8,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 129, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(39, "SDWP", 8,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 130, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(40, "SDVOLC", 9,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 131, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(41, "USB0VBUS", 0,
+ 37, UNIPHIER_PIN_DRV_4_8,
+ 37, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(42, "USB0OD", 0,
+ 38, UNIPHIER_PIN_DRV_4_8,
+ 38, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(43, "USB1VBUS", 0,
+ 39, UNIPHIER_PIN_DRV_4_8,
+ 39, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(44, "USB1OD", 0,
+ 40, UNIPHIER_PIN_DRV_4_8,
+ 40, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(45, "PCRESET", 0,
+ 41, UNIPHIER_PIN_DRV_4_8,
+ 41, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(46, "PCREG", 0,
+ 42, UNIPHIER_PIN_DRV_4_8,
+ 42, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(47, "PCCE2", 0,
+ 43, UNIPHIER_PIN_DRV_4_8,
+ 43, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(48, "PCVS1", 0,
+ 44, UNIPHIER_PIN_DRV_4_8,
+ 44, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(49, "PCCD2", 0,
+ 45, UNIPHIER_PIN_DRV_4_8,
+ 45, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(50, "PCCD1", 0,
+ 46, UNIPHIER_PIN_DRV_4_8,
+ 46, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(51, "PCREADY", 0,
+ 47, UNIPHIER_PIN_DRV_4_8,
+ 47, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(52, "PCDOE", 0,
+ 48, UNIPHIER_PIN_DRV_4_8,
+ 48, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(53, "PCCE1", 0,
+ 49, UNIPHIER_PIN_DRV_4_8,
+ 49, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(54, "PCWE", 0,
+ 50, UNIPHIER_PIN_DRV_4_8,
+ 50, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(55, "PCOE", 0,
+ 51, UNIPHIER_PIN_DRV_4_8,
+ 51, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(56, "PCWAIT", 0,
+ 52, UNIPHIER_PIN_DRV_4_8,
+ 52, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(57, "PCIOWR", 0,
+ 53, UNIPHIER_PIN_DRV_4_8,
+ 53, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(58, "PCIORD", 0,
+ 54, UNIPHIER_PIN_DRV_4_8,
+ 54, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(59, "HS0DIN0", 0,
+ 55, UNIPHIER_PIN_DRV_4_8,
+ 55, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(60, "HS0DIN1", 0,
+ 56, UNIPHIER_PIN_DRV_4_8,
+ 56, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(61, "HS0DIN2", 0,
+ 57, UNIPHIER_PIN_DRV_4_8,
+ 57, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(62, "HS0DIN3", 0,
+ 58, UNIPHIER_PIN_DRV_4_8,
+ 58, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(63, "HS0DIN4", 0,
+ 59, UNIPHIER_PIN_DRV_4_8,
+ 59, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(64, "HS0DIN5", 0,
+ 60, UNIPHIER_PIN_DRV_4_8,
+ 60, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(65, "HS0DIN6", 0,
+ 61, UNIPHIER_PIN_DRV_4_8,
+ 61, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(66, "HS0DIN7", 0,
+ 62, UNIPHIER_PIN_DRV_4_8,
+ 62, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(67, "HS0BCLKIN", 0,
+ 63, UNIPHIER_PIN_DRV_4_8,
+ 63, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(68, "HS0VALIN", 0,
+ 64, UNIPHIER_PIN_DRV_4_8,
+ 64, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(69, "HS0SYNCIN", 0,
+ 65, UNIPHIER_PIN_DRV_4_8,
+ 65, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(70, "HSDOUT0", 0,
+ 66, UNIPHIER_PIN_DRV_4_8,
+ 66, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(71, "HSDOUT1", 0,
+ 67, UNIPHIER_PIN_DRV_4_8,
+ 67, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(72, "HSDOUT2", 0,
+ 68, UNIPHIER_PIN_DRV_4_8,
+ 68, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(73, "HSDOUT3", 0,
+ 69, UNIPHIER_PIN_DRV_4_8,
+ 69, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(74, "HSDOUT4", 0,
+ 70, UNIPHIER_PIN_DRV_4_8,
+ 70, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(75, "HSDOUT5", 0,
+ 71, UNIPHIER_PIN_DRV_4_8,
+ 71, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(76, "HSDOUT6", 0,
+ 72, UNIPHIER_PIN_DRV_4_8,
+ 72, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(77, "HSDOUT7", 0,
+ 73, UNIPHIER_PIN_DRV_4_8,
+ 73, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(78, "HSBCLKOUT", 0,
+ 74, UNIPHIER_PIN_DRV_4_8,
+ 74, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(79, "HSVALOUT", 0,
+ 75, UNIPHIER_PIN_DRV_4_8,
+ 75, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(80, "HSSYNCOUT", 0,
+ 76, UNIPHIER_PIN_DRV_4_8,
+ 76, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(81, "HS1DIN0", 0,
+ 77, UNIPHIER_PIN_DRV_4_8,
+ 77, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(82, "HS1DIN1", 0,
+ 78, UNIPHIER_PIN_DRV_4_8,
+ 78, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(83, "HS1DIN2", 0,
+ 79, UNIPHIER_PIN_DRV_4_8,
+ 79, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(84, "HS1DIN3", 0,
+ 80, UNIPHIER_PIN_DRV_4_8,
+ 80, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(85, "HS1DIN4", 0,
+ 81, UNIPHIER_PIN_DRV_4_8,
+ 81, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(86, "HS1DIN5", 0,
+ 82, UNIPHIER_PIN_DRV_4_8,
+ 82, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(87, "HS1DIN6", 0,
+ 83, UNIPHIER_PIN_DRV_4_8,
+ 83, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(88, "HS1DIN7", 0,
+ 84, UNIPHIER_PIN_DRV_4_8,
+ 84, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(89, "HS1BCLKIN", 0,
+ 85, UNIPHIER_PIN_DRV_4_8,
+ 85, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(90, "HS1VALIN", 0,
+ 86, UNIPHIER_PIN_DRV_4_8,
+ 86, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(91, "HS1SYNCIN", 0,
+ 87, UNIPHIER_PIN_DRV_4_8,
+ 87, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(92, "AGCI", 3,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 132, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(93, "AGCR", 4,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 133, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(94, "AGCBS", 5,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ 134, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(95, "IECOUT", 0,
+ 88, UNIPHIER_PIN_DRV_4_8,
+ 88, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(96, "ASMCK", 0,
+ 89, UNIPHIER_PIN_DRV_4_8,
+ 89, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(97, "ABCKO", UNIPHIER_PIN_IECTRL_NONE,
+ 90, UNIPHIER_PIN_DRV_4_8,
+ 90, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(98, "ALRCKO", UNIPHIER_PIN_IECTRL_NONE,
+ 91, UNIPHIER_PIN_DRV_4_8,
+ 91, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(99, "ASDOUT0", UNIPHIER_PIN_IECTRL_NONE,
+ 92, UNIPHIER_PIN_DRV_4_8,
+ 92, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(100, "ASDOUT1", UNIPHIER_PIN_IECTRL_NONE,
+ 93, UNIPHIER_PIN_DRV_4_8,
+ 93, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(101, "ARCOUT", 0,
+ 94, UNIPHIER_PIN_DRV_4_8,
+ 94, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(102, "SDA0", 10,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(103, "SCL0", 10,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(104, "SDA1", 11,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(105, "SCL1", 11,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(106, "DMDSDA0", 12,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(107, "DMDSCL0", 12,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(108, "DMDSDA1", 13,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(109, "DMDSCL1", 13,
+ -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(110, "SBO0", UNIPHIER_PIN_IECTRL_NONE,
+ 95, UNIPHIER_PIN_DRV_4_8,
+ 95, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(111, "SBI0", UNIPHIER_PIN_IECTRL_NONE,
+ 96, UNIPHIER_PIN_DRV_4_8,
+ 96, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(112, "SBO1", 0,
+ 97, UNIPHIER_PIN_DRV_4_8,
+ 97, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(113, "SBI1", 0,
+ 98, UNIPHIER_PIN_DRV_4_8,
+ 98, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(114, "TXD1", 0,
+ 99, UNIPHIER_PIN_DRV_4_8,
+ 99, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(115, "RXD1", 0,
+ 100, UNIPHIER_PIN_DRV_4_8,
+ 100, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(116, "HIN", 1,
+ -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(117, "VIN", 2,
+ -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(118, "TCON0", 0,
+ 101, UNIPHIER_PIN_DRV_4_8,
+ 101, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(119, "TCON1", 0,
+ 102, UNIPHIER_PIN_DRV_4_8,
+ 102, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(120, "TCON2", 0,
+ 103, UNIPHIER_PIN_DRV_4_8,
+ 103, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(121, "TCON3", 0,
+ 104, UNIPHIER_PIN_DRV_4_8,
+ 104, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(122, "TCON4", 0,
+ 105, UNIPHIER_PIN_DRV_4_8,
+ 105, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(123, "TCON5", 0,
+ 106, UNIPHIER_PIN_DRV_4_8,
+ 106, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(124, "TCON6", 0,
+ 107, UNIPHIER_PIN_DRV_4_8,
+ 107, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(125, "TCON7", 0,
+ 108, UNIPHIER_PIN_DRV_4_8,
+ 108, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(126, "TCON8", 0,
+ 109, UNIPHIER_PIN_DRV_4_8,
+ 109, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(127, "PWMA", 0,
+ 110, UNIPHIER_PIN_DRV_4_8,
+ 110, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(128, "XIRQ0", 0,
+ 111, UNIPHIER_PIN_DRV_4_8,
+ 111, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(129, "XIRQ1", 0,
+ 112, UNIPHIER_PIN_DRV_4_8,
+ 112, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(130, "XIRQ2", 0,
+ 113, UNIPHIER_PIN_DRV_4_8,
+ 113, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(131, "XIRQ3", 0,
+ 114, UNIPHIER_PIN_DRV_4_8,
+ 114, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(132, "XIRQ4", 0,
+ 115, UNIPHIER_PIN_DRV_4_8,
+ 115, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(133, "XIRQ5", 0,
+ 116, UNIPHIER_PIN_DRV_4_8,
+ 116, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(134, "XIRQ6", 0,
+ 117, UNIPHIER_PIN_DRV_4_8,
+ 117, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(135, "XIRQ7", 0,
+ 118, UNIPHIER_PIN_DRV_4_8,
+ 118, UNIPHIER_PIN_PULL_DOWN),
+};
+
+static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
+static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {102, 103};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {104, 105};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {108, 109};
+static const unsigned i2c2_muxvals[] = {2, 2};
+static const unsigned i2c3_pins[] = {108, 109};
+static const unsigned i2c3_muxvals[] = {3, 3};
+static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26,
+ 27, 28, 29, 30, 31};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {22, 23};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {70, 71};
+static const unsigned uart0_muxvals[] = {3, 3};
+static const unsigned uart1_pins[] = {114, 115};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {112, 113};
+static const unsigned uart2_muxvals[] = {1, 1};
+static const unsigned uart3_pins[] = {110, 111};
+static const unsigned uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {41, 42};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {43, 44};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {114, 115};
+static const unsigned usb2_muxvals[] = {1, 1};
+static const unsigned port_range0_pins[] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, /* PORT0x */
+ 8, 9, 10, 11, 12, 13, 14, 15, /* PORT1x */
+ 32, 33, 34, 35, 36, 37, 38, 39, /* PORT2x */
+ 59, 60, 61, 62, 63, 64, 65, 66, /* PORT3x */
+ 95, 96, 97, 98, 99, 100, 101, 57, /* PORT4x */
+ 70, 71, 72, 73, 74, 75, 76, 77, /* PORT5x */
+ 81, 83, 84, 85, 86, 89, 90, 91, /* PORT6x */
+ 118, 119, 120, 121, 122, 53, 54, 55, /* PORT7x */
+ 41, 42, 43, 44, 79, 80, 18, 19, /* PORT8x */
+ 110, 111, 112, 113, 114, 115, 16, 17, /* PORT9x */
+ 40, 67, 68, 69, 78, 92, 93, 94, /* PORT10x */
+ 48, 49, 46, 45, 123, 124, 125, 126, /* PORT11x */
+ 47, 127, 20, 56, 22, /* PORT120-124 */
+};
+static const unsigned port_range0_muxvals[] = {
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */
+ 15, 15, 15, 15, 15, /* PORT120-124 */
+};
+static const unsigned port_range1_pins[] = {
+ 116, 117, /* PORT130-131 */
+};
+static const unsigned port_range1_muxvals[] = {
+ 15, 15, /* PORT130-131 */
+};
+static const unsigned port_range2_pins[] = {
+ 102, 103, 104, 105, 106, 107, 108, 109, /* PORT14x */
+};
+static const unsigned port_range2_muxvals[] = {
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
+};
+static const unsigned port_range3_pins[] = {
+ 23, /* PORT166 */
+};
+static const unsigned port_range3_muxvals[] = {
+ 15, /* PORT166 */
+};
+static const unsigned xirq_range0_pins[] = {
+ 128, 129, 130, 131, 132, 133, 134, 135, /* XIRQ0-7 */
+ 82, 87, 88, 50, 51, /* XIRQ8-12 */
+};
+static const unsigned xirq_range0_muxvals[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, /* XIRQ0-7 */
+ 14, 14, 14, 14, 14, /* XIRQ8-12 */
+};
+static const unsigned xirq_range1_pins[] = {
+ 52, 58, /* XIRQ14-15 */
+};
+static const unsigned xirq_range1_muxvals[] = {
+ 14, 14, /* XIRQ14-15 */
+};
+
+static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range2),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range3),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range0),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range2, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range2, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range2, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range2, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range2, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range2, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range2, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range2, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range3, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq_range0, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq_range0, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq_range0, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq_range0, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq_range0, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq_range0, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq_range0, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq_range0, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq_range0, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq_range0, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq_range0, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq_range0, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq_range0, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq_range1, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq_range1, 1),
+};
+
+static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const i2c0_groups[] = {"i2c0"};
+static const char * const i2c1_groups[] = {"i2c1"};
+static const char * const i2c2_groups[] = {"i2c2"};
+static const char * const i2c3_groups[] = {"i2c3"};
+static const char * const nand_groups[] = {"nand", "nand_cs1"};
+static const char * const sd_groups[] = {"sd"};
+static const char * const uart0_groups[] = {"uart0"};
+static const char * const uart1_groups[] = {"uart1"};
+static const char * const uart2_groups[] = {"uart2"};
+static const char * const uart3_groups[] = {"uart3"};
+static const char * const usb0_groups[] = {"usb0"};
+static const char * const usb1_groups[] = {"usb1"};
+static const char * const usb2_groups[] = {"usb2"};
+static const char * const port_groups[] = {
+ "port00", "port01", "port02", "port03",
+ "port04", "port05", "port06", "port07",
+ "port10", "port11", "port12", "port13",
+ "port14", "port15", "port16", "port17",
+ "port20", "port21", "port22", "port23",
+ "port24", "port25", "port26", "port27",
+ "port30", "port31", "port32", "port33",
+ "port34", "port35", "port36", "port37",
+ "port40", "port41", "port42", "port43",
+ "port44", "port45", "port46", "port47",
+ "port50", "port51", "port52", "port53",
+ "port54", "port55", "port56", "port57",
+ "port60", "port61", "port62", "port63",
+ "port64", "port65", "port66", "port67",
+ "port70", "port71", "port72", "port73",
+ "port74", "port75", "port76", "port77",
+ "port80", "port81", "port82", "port83",
+ "port84", "port85", "port86", "port87",
+ "port90", "port91", "port92", "port93",
+ "port94", "port95", "port96", "port97",
+ "port100", "port101", "port102", "port103",
+ "port104", "port105", "port106", "port107",
+ "port110", "port111", "port112", "port113",
+ "port114", "port115", "port116", "port117",
+ "port120", "port121", "port122", "port123",
+ "port124", "port125", "port126", "port127",
+ "port130", "port131", "port132", "port133",
+ "port134", "port135", "port136", "port137",
+ "port140", "port141", "port142", "port143",
+ "port144", "port145", "port146", "port147",
+ /* port150-164 missing */
+ /* none */ "port165",
+};
+static const char * const xirq_groups[] = {
+ "xirq0", "xirq1", "xirq2", "xirq3",
+ "xirq4", "xirq5", "xirq6", "xirq7",
+ "xirq8", "xirq9", "xirq10", "xirq11",
+ "xirq12", /* none*/ "xirq14", "xirq15",
+};
+
+static const struct uniphier_pinmux_function ph1_sld8_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(i2c0),
+ UNIPHIER_PINMUX_FUNCTION(i2c1),
+ UNIPHIER_PINMUX_FUNCTION(i2c2),
+ UNIPHIER_PINMUX_FUNCTION(i2c3),
+ UNIPHIER_PINMUX_FUNCTION(nand),
+ UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(uart0),
+ UNIPHIER_PINMUX_FUNCTION(uart1),
+ UNIPHIER_PINMUX_FUNCTION(uart2),
+ UNIPHIER_PINMUX_FUNCTION(uart3),
+ UNIPHIER_PINMUX_FUNCTION(usb0),
+ UNIPHIER_PINMUX_FUNCTION(usb1),
+ UNIPHIER_PINMUX_FUNCTION(usb2),
+ UNIPHIER_PINMUX_FUNCTION(port),
+ UNIPHIER_PINMUX_FUNCTION(xirq),
+};
+
+static struct uniphier_pinctrl_socdata ph1_sld8_pindata = {
+ .groups = ph1_sld8_groups,
+ .groups_count = ARRAY_SIZE(ph1_sld8_groups),
+ .functions = ph1_sld8_functions,
+ .functions_count = ARRAY_SIZE(ph1_sld8_functions),
+ .mux_bits = 8,
+ .reg_stride = 4,
+ .load_pinctrl = false,
+};
+
+static struct pinctrl_desc ph1_sld8_pinctrl_desc = {
+ .name = DRIVER_NAME,
+ .pins = ph1_sld8_pins,
+ .npins = ARRAY_SIZE(ph1_sld8_pins),
+ .owner = THIS_MODULE,
+};
+
+static int ph1_sld8_pinctrl_probe(struct platform_device *pdev)
+{
+ return uniphier_pinctrl_probe(pdev, &ph1_sld8_pinctrl_desc,
+ &ph1_sld8_pindata);
+}
+
+static const struct of_device_id ph1_sld8_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-sld8-pinctrl" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ph1_sld8_pinctrl_match);
+
+static struct platform_driver ph1_sld8_pinctrl_driver = {
+ .probe = ph1_sld8_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = ph1_sld8_pinctrl_match,
+ },
+};
+module_platform_driver(ph1_sld8_pinctrl_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-sLD8 pinctrl driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+#ifndef __DTS_MT7623_PINFUNC_H
+#define __DTS_MT7623_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
+#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)
+
+#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
+#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)
+
+#define MT7623_PIN_2_PWRAP_INT_FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT7623_PIN_2_PWRAP_INT_FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)
+
+#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)
+
+#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)
+
+#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
+
+#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
+
+#define MT7623_PIN_7_SPI1_CSN_FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
+
+#define MT7623_PIN_8_SPI1_MI_FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
+#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
+
+#define MT7623_PIN_9_SPI1_MO_FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
+#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
+
+#define MT7623_PIN_10_RTC32K_CK_FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT7623_PIN_10_RTC32K_CK_FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
+
+#define MT7623_PIN_11_WATCHDOG_FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT7623_PIN_11_WATCHDOG_FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)
+
+#define MT7623_PIN_12_SRCLKENA_FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT7623_PIN_12_SRCLKENA_FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)
+
+#define MT7623_PIN_13_SRCLKENAI_FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT7623_PIN_13_SRCLKENAI_FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)
+
+#define MT7623_PIN_14_GPIO14_FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT7623_PIN_14_GPIO14_FUNC_URXD2 (MTK_PIN_NO(14) | 1)
+#define MT7623_PIN_14_GPIO14_FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
+
+#define MT7623_PIN_15_GPIO15_FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT7623_PIN_15_GPIO15_FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
+#define MT7623_PIN_15_GPIO15_FUNC_URXD2 (MTK_PIN_NO(15) | 2)
+
+#define MT7623_PIN_18_PCM_CLK_FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT7623_PIN_18_PCM_CLK_FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
+#define MT7623_PIN_18_PCM_CLK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(18) | 6)
+
+#define MT7623_PIN_19_PCM_SYNC_FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT7623_PIN_19_PCM_SYNC_FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
+#define MT7623_PIN_19_PCM_SYNC_FUNC_AP_PCM_SYNC (MTK_PIN_NO(19) | 6)
+
+#define MT7623_PIN_20_PCM_RX_FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT7623_PIN_20_PCM_RX_FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
+#define MT7623_PIN_20_PCM_RX_FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
+#define MT7623_PIN_20_PCM_RX_FUNC_AP_PCM_RX (MTK_PIN_NO(20) | 6)
+
+#define MT7623_PIN_21_PCM_TX_FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT7623_PIN_21_PCM_TX_FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
+#define MT7623_PIN_21_PCM_TX_FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
+#define MT7623_PIN_21_PCM_TX_FUNC_AP_PCM_TX (MTK_PIN_NO(21) | 6)
+
+#define MT7623_PIN_22_EINT0_FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT7623_PIN_22_EINT0_FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
+#define MT7623_PIN_22_EINT0_FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 2)
+
+#define MT7623_PIN_23_EINT1_FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT7623_PIN_23_EINT1_FUNC_URTS0 (MTK_PIN_NO(23) | 1)
+#define MT7623_PIN_23_EINT1_FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 2)
+
+#define MT7623_PIN_24_EINT2_FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT7623_PIN_24_EINT2_FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
+#define MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 2)
+
+#define MT7623_PIN_25_EINT3_FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT7623_PIN_25_EINT3_FUNC_URTS1 (MTK_PIN_NO(25) | 1)
+
+#define MT7623_PIN_26_EINT4_FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT7623_PIN_26_EINT4_FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
+#define MT7623_PIN_26_EINT4_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
+
+#define MT7623_PIN_27_EINT5_FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT7623_PIN_27_EINT5_FUNC_URTS3 (MTK_PIN_NO(27) | 1)
+#define MT7623_PIN_27_EINT5_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
+
+#define MT7623_PIN_28_EINT6_FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT7623_PIN_28_EINT6_FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
+#define MT7623_PIN_28_EINT6_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
+
+#define MT7623_PIN_29_EINT7_FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT7623_PIN_29_EINT7_FUNC_IDDIG (MTK_PIN_NO(29) | 1)
+#define MT7623_PIN_29_EINT7_FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
+#define MT7623_PIN_29_EINT7_FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 6)
+
+#define MT7623_PIN_33_I2S1_DATA_FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
+#define MT7623_PIN_33_I2S1_DATA_FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
+#define MT7623_PIN_33_I2S1_DATA_FUNC_AP_PCM_TX (MTK_PIN_NO(33) | 6)
+
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_AP_PCM_RX (MTK_PIN_NO(34) | 6)
+
+#define MT7623_PIN_35_I2S1_BCK_FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
+#define MT7623_PIN_35_I2S1_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
+#define MT7623_PIN_35_I2S1_BCK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(35) | 6)
+
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_AP_PCM_SYNC (MTK_PIN_NO(36) | 6)
+
+#define MT7623_PIN_37_I2S1_MCLK_FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
+
+#define MT7623_PIN_39_JTMS_FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT7623_PIN_39_JTMS_FUNC_JTMS (MTK_PIN_NO(39) | 1)
+
+#define MT7623_PIN_40_JTCK_FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT7623_PIN_40_JTCK_FUNC_JTCK (MTK_PIN_NO(40) | 1)
+
+#define MT7623_PIN_41_JTDI_FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT7623_PIN_41_JTDI_FUNC_JTDI (MTK_PIN_NO(41) | 1)
+
+#define MT7623_PIN_42_JTDO_FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT7623_PIN_42_JTDO_FUNC_JTDO (MTK_PIN_NO(42) | 1)
+
+#define MT7623_PIN_43_NCLE_FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT7623_PIN_43_NCLE_FUNC_NCLE (MTK_PIN_NO(43) | 1)
+#define MT7623_PIN_43_NCLE_FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)
+
+#define MT7623_PIN_44_NCEB1_FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT7623_PIN_44_NCEB1_FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
+#define MT7623_PIN_44_NCEB1_FUNC_IDDIG (MTK_PIN_NO(44) | 2)
+
+#define MT7623_PIN_45_NCEB0_FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT7623_PIN_45_NCEB0_FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
+#define MT7623_PIN_45_NCEB0_FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)
+
+#define MT7623_PIN_46_IR_FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT7623_PIN_46_IR_FUNC_IR (MTK_PIN_NO(46) | 1)
+
+#define MT7623_PIN_47_NREB_FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT7623_PIN_47_NREB_FUNC_NREB (MTK_PIN_NO(47) | 1)
+
+#define MT7623_PIN_48_NRNB_FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT7623_PIN_48_NRNB_FUNC_NRNB (MTK_PIN_NO(48) | 1)
+
+#define MT7623_PIN_49_I2S0_DATA_FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
+#define MT7623_PIN_49_I2S0_DATA_FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
+#define MT7623_PIN_49_I2S0_DATA_FUNC_AP_I2S_DO (MTK_PIN_NO(49) | 6)
+
+#define MT7623_PIN_53_SPI0_CSN_FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
+#define MT7623_PIN_53_SPI0_CSN_FUNC_PWM1 (MTK_PIN_NO(53) | 5)
+
+#define MT7623_PIN_54_SPI0_CK_FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
+
+#define MT7623_PIN_55_SPI0_MI_FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
+#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
+#define MT7623_PIN_55_SPI0_MI_FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
+#define MT7623_PIN_55_SPI0_MI_FUNC_PWM2 (MTK_PIN_NO(55) | 5)
+
+#define MT7623_PIN_56_SPI0_MO_FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
+#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
+
+#define MT7623_PIN_60_WB_RSTB_FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define MT7623_PIN_60_WB_RSTB_FUNC_WB_RSTB (MTK_PIN_NO(60) | 1)
+
+#define MT7623_PIN_61_GPIO61_FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define MT7623_PIN_61_GPIO61_FUNC_TEST_FD (MTK_PIN_NO(61) | 1)
+
+#define MT7623_PIN_62_GPIO62_FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define MT7623_PIN_62_GPIO62_FUNC_TEST_FC (MTK_PIN_NO(62) | 1)
+
+#define MT7623_PIN_63_WB_SCLK_FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define MT7623_PIN_63_WB_SCLK_FUNC_WB_SCLK (MTK_PIN_NO(63) | 1)
+
+#define MT7623_PIN_64_WB_SDATA_FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define MT7623_PIN_64_WB_SDATA_FUNC_WB_SDATA (MTK_PIN_NO(64) | 1)
+
+#define MT7623_PIN_65_WB_SEN_FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define MT7623_PIN_65_WB_SEN_FUNC_WB_SEN (MTK_PIN_NO(65) | 1)
+
+#define MT7623_PIN_66_WB_CRTL0_FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define MT7623_PIN_66_WB_CRTL0_FUNC_WB_CRTL0 (MTK_PIN_NO(66) | 1)
+
+#define MT7623_PIN_67_WB_CRTL1_FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define MT7623_PIN_67_WB_CRTL1_FUNC_WB_CRTL1 (MTK_PIN_NO(67) | 1)
+
+#define MT7623_PIN_68_WB_CRTL2_FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define MT7623_PIN_68_WB_CRTL2_FUNC_WB_CRTL2 (MTK_PIN_NO(68) | 1)
+
+#define MT7623_PIN_69_WB_CRTL3_FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define MT7623_PIN_69_WB_CRTL3_FUNC_WB_CRTL3 (MTK_PIN_NO(69) | 1)
+
+#define MT7623_PIN_70_WB_CRTL4_FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define MT7623_PIN_70_WB_CRTL4_FUNC_WB_CRTL4 (MTK_PIN_NO(70) | 1)
+
+#define MT7623_PIN_71_WB_CRTL5_FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define MT7623_PIN_71_WB_CRTL5_FUNC_WB_CRTL5 (MTK_PIN_NO(71) | 1)
+
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PWM0 (MTK_PIN_NO(72) | 4)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_AP_I2S_DI (MTK_PIN_NO(72) | 6)
+
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_AP_I2S_LRCK (MTK_PIN_NO(73) | 6)
+
+#define MT7623_PIN_74_I2S0_BCK_FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
+#define MT7623_PIN_74_I2S0_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
+#define MT7623_PIN_74_I2S0_BCK_FUNC_AP_I2S_BCK (MTK_PIN_NO(74) | 6)
+
+#define MT7623_PIN_75_SDA0_FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT7623_PIN_75_SDA0_FUNC_SDA0 (MTK_PIN_NO(75) | 1)
+
+#define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1)
+
+#define MT7623_PIN_83_LCM_RST_FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT7623_PIN_83_LCM_RST_FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
+
+#define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
+
+#define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1)
+
+#define MT7623_PIN_96_MIPI_TCP_FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define MT7623_PIN_96_MIPI_TCP_FUNC_TCP (MTK_PIN_NO(96) | 1)
+
+#define MT7623_PIN_97_MIPI_TDN1_FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define MT7623_PIN_97_MIPI_TDN1_FUNC_TDN1 (MTK_PIN_NO(97) | 1)
+
+#define MT7623_PIN_98_MIPI_TDP1_FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define MT7623_PIN_98_MIPI_TDP1_FUNC_TDP1 (MTK_PIN_NO(98) | 1)
+
+#define MT7623_PIN_99_MIPI_TDN0_FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define MT7623_PIN_99_MIPI_TDN0_FUNC_TDN0 (MTK_PIN_NO(99) | 1)
+
+#define MT7623_PIN_100_MIPI_TDP0_FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0 (MTK_PIN_NO(100) | 1)
+
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_SDA1 (MTK_PIN_NO(105) | 3)
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
+
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_SCL1 (MTK_PIN_NO(106) | 3)
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
+
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
+
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM0 (MTK_PIN_NO(108) | 3)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_URXD0 (MTK_PIN_NO(108) | 5)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM1 (MTK_PIN_NO(108) | 6)
+
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_SDA2 (MTK_PIN_NO(109) | 3)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_PWM2 (MTK_PIN_NO(109) | 6)
+
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_SCL2 (MTK_PIN_NO(110) | 3)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_URXD1 (MTK_PIN_NO(110) | 5)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_PWM3 (MTK_PIN_NO(110) | 6)
+
+#define MT7623_PIN_111_MSDC0_DAT7_FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
+#define MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7 (MTK_PIN_NO(111) | 4)
+
+#define MT7623_PIN_112_MSDC0_DAT6_FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
+#define MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6 (MTK_PIN_NO(112) | 4)
+
+#define MT7623_PIN_113_MSDC0_DAT5_FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
+#define MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5 (MTK_PIN_NO(113) | 4)
+
+#define MT7623_PIN_114_MSDC0_DAT4_FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
+#define MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4 (MTK_PIN_NO(114) | 4)
+
+#define MT7623_PIN_115_MSDC0_RSTB_FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
+#define MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8 (MTK_PIN_NO(115) | 4)
+
+#define MT7623_PIN_116_MSDC0_CMD_FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
+#define MT7623_PIN_116_MSDC0_CMD_FUNC_NALE (MTK_PIN_NO(116) | 4)
+
+#define MT7623_PIN_117_MSDC0_CLK_FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
+#define MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB (MTK_PIN_NO(117) | 4)
+
+#define MT7623_PIN_118_MSDC0_DAT3_FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
+#define MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3 (MTK_PIN_NO(118) | 4)
+
+#define MT7623_PIN_119_MSDC0_DAT2_FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
+#define MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2 (MTK_PIN_NO(119) | 4)
+
+#define MT7623_PIN_120_MSDC0_DAT1_FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
+#define MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1 (MTK_PIN_NO(120) | 4)
+
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0 (MTK_PIN_NO(121) | 4)
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
+
+#define MT7623_PIN_122_GPIO122_FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT7623_PIN_122_GPIO122_FUNC_TEST (MTK_PIN_NO(122) | 1)
+#define MT7623_PIN_122_GPIO122_FUNC_SDA2 (MTK_PIN_NO(122) | 4)
+#define MT7623_PIN_122_GPIO122_FUNC_URXD0 (MTK_PIN_NO(122) | 5)
+
+#define MT7623_PIN_123_GPIO123_FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT7623_PIN_123_GPIO123_FUNC_TEST (MTK_PIN_NO(123) | 1)
+#define MT7623_PIN_123_GPIO123_FUNC_SCL2 (MTK_PIN_NO(123) | 4)
+#define MT7623_PIN_123_GPIO123_FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
+
+#define MT7623_PIN_124_GPIO124_FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT7623_PIN_124_GPIO124_FUNC_TEST (MTK_PIN_NO(124) | 1)
+#define MT7623_PIN_124_GPIO124_FUNC_SDA1 (MTK_PIN_NO(124) | 4)
+#define MT7623_PIN_124_GPIO124_FUNC_PWM3 (MTK_PIN_NO(124) | 5)
+
+#define MT7623_PIN_125_GPIO125_FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT7623_PIN_125_GPIO125_FUNC_TEST (MTK_PIN_NO(125) | 1)
+#define MT7623_PIN_125_GPIO125_FUNC_SCL1 (MTK_PIN_NO(125) | 4)
+#define MT7623_PIN_125_GPIO125_FUNC_PWM4 (MTK_PIN_NO(125) | 5)
+
+#define MT7623_PIN_126_I2S0_MCLK_FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
+#define MT7623_PIN_126_I2S0_MCLK_FUNC_AP_I2S_MCLK (MTK_PIN_NO(126) | 6)
+
+#define MT7623_PIN_199_SPI1_CK_FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
+
+#define MT7623_PIN_200_URXD2_FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define MT7623_PIN_200_URXD2_FUNC_URXD2 (MTK_PIN_NO(200) | 6)
+
+#define MT7623_PIN_201_UTXD2_FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define MT7623_PIN_201_UTXD2_FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
+
+#define MT7623_PIN_203_PWM0_FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
+#define MT7623_PIN_203_PWM0_FUNC_PWM0 (MTK_PIN_NO(203) | 1)
+#define MT7623_PIN_203_PWM0_FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
+
+#define MT7623_PIN_204_PWM1_FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
+#define MT7623_PIN_204_PWM1_FUNC_PWM1 (MTK_PIN_NO(204) | 1)
+
+#define MT7623_PIN_205_PWM2_FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
+#define MT7623_PIN_205_PWM2_FUNC_PWM2 (MTK_PIN_NO(205) | 1)
+
+#define MT7623_PIN_206_PWM3_FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
+#define MT7623_PIN_206_PWM3_FUNC_PWM3 (MTK_PIN_NO(206) | 1)
+
+#define MT7623_PIN_207_PWM4_FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
+#define MT7623_PIN_207_PWM4_FUNC_PWM4 (MTK_PIN_NO(207) | 1)
+
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PWM0 (MTK_PIN_NO(208) | 2)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 3)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
+
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 3)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PWM1 (MTK_PIN_NO(209) | 5)
+
+#define MT7623_PIN_236_EXT_SDIO3_FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
+#define MT7623_PIN_236_EXT_SDIO3_FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
+#define MT7623_PIN_236_EXT_SDIO3_FUNC_IDDIG (MTK_PIN_NO(236) | 2)
+
+#define MT7623_PIN_237_EXT_SDIO2_FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
+#define MT7623_PIN_237_EXT_SDIO2_FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
+#define MT7623_PIN_237_EXT_SDIO2_FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)
+
+#define MT7623_PIN_238_EXT_SDIO1_FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
+#define MT7623_PIN_238_EXT_SDIO1_FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
+
+#define MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
+#define MT7623_PIN_239_EXT_SDIO0_FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
+
+#define MT7623_PIN_240_EXT_XCS_FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
+#define MT7623_PIN_240_EXT_XCS_FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)
+
+#define MT7623_PIN_241_EXT_SCK_FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
+#define MT7623_PIN_241_EXT_SCK_FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)
+
+#define MT7623_PIN_242_URTS2_FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
+#define MT7623_PIN_242_URTS2_FUNC_URTS2 (MTK_PIN_NO(242) | 1)
+#define MT7623_PIN_242_URTS2_FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
+#define MT7623_PIN_242_URTS2_FUNC_URXD3 (MTK_PIN_NO(242) | 3)
+#define MT7623_PIN_242_URTS2_FUNC_SCL1 (MTK_PIN_NO(242) | 4)
+
+#define MT7623_PIN_243_UCTS2_FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
+#define MT7623_PIN_243_UCTS2_FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
+#define MT7623_PIN_243_UCTS2_FUNC_URXD3 (MTK_PIN_NO(243) | 2)
+#define MT7623_PIN_243_UCTS2_FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
+#define MT7623_PIN_243_UCTS2_FUNC_SDA1 (MTK_PIN_NO(243) | 4)
+
+#define MT7623_PIN_250_GPIO250_FUNC_GPIO250 (MTK_PIN_NO(250) | 0)
+#define MT7623_PIN_250_GPIO250_FUNC_TEST_MD7 (MTK_PIN_NO(250) | 1)
+#define MT7623_PIN_250_GPIO250_FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 6)
+
+#define MT7623_PIN_251_GPIO251_FUNC_GPIO251 (MTK_PIN_NO(251) | 0)
+#define MT7623_PIN_251_GPIO251_FUNC_TEST_MD6 (MTK_PIN_NO(251) | 1)
+#define MT7623_PIN_251_GPIO251_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 6)
+
+#define MT7623_PIN_252_GPIO252_FUNC_GPIO252 (MTK_PIN_NO(252) | 0)
+#define MT7623_PIN_252_GPIO252_FUNC_TEST_MD5 (MTK_PIN_NO(252) | 1)
+#define MT7623_PIN_252_GPIO252_FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 6)
+
+#define MT7623_PIN_253_GPIO253_FUNC_GPIO253 (MTK_PIN_NO(253) | 0)
+#define MT7623_PIN_253_GPIO253_FUNC_TEST_MD4 (MTK_PIN_NO(253) | 1)
+#define MT7623_PIN_253_GPIO253_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 6)
+
+#define MT7623_PIN_254_GPIO254_FUNC_GPIO254 (MTK_PIN_NO(254) | 0)
+#define MT7623_PIN_254_GPIO254_FUNC_TEST_MD3 (MTK_PIN_NO(254) | 1)
+#define MT7623_PIN_254_GPIO254_FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 6)
+
+#define MT7623_PIN_255_GPIO255_FUNC_GPIO255 (MTK_PIN_NO(255) | 0)
+#define MT7623_PIN_255_GPIO255_FUNC_TEST_MD2 (MTK_PIN_NO(255) | 1)
+#define MT7623_PIN_255_GPIO255_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 6)
+
+#define MT7623_PIN_256_GPIO256_FUNC_GPIO256 (MTK_PIN_NO(256) | 0)
+#define MT7623_PIN_256_GPIO256_FUNC_TEST_MD1 (MTK_PIN_NO(256) | 1)
+
+#define MT7623_PIN_257_GPIO257_FUNC_GPIO257 (MTK_PIN_NO(257) | 0)
+#define MT7623_PIN_257_GPIO257_FUNC_TEST_MD0 (MTK_PIN_NO(257) | 1)
+
+#define MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
+#define MT7623_PIN_261_MSDC1_INS_FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
+
+#define MT7623_PIN_262_G2_TXEN_FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
+#define MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)
+
+#define MT7623_PIN_263_G2_TXD3_FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
+#define MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
+
+#define MT7623_PIN_264_G2_TXD2_FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
+#define MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
+
+#define MT7623_PIN_265_G2_TXD1_FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
+#define MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
+
+#define MT7623_PIN_266_G2_TXD0_FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
+#define MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
+
+#define MT7623_PIN_267_G2_TXCLK_FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
+#define MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC (MTK_PIN_NO(267) | 1)
+
+#define MT7623_PIN_268_G2_RXCLK_FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
+#define MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC (MTK_PIN_NO(268) | 1)
+
+#define MT7623_PIN_269_G2_RXD0_FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
+#define MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)
+
+#define MT7623_PIN_270_G2_RXD1_FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
+#define MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)
+
+#define MT7623_PIN_271_G2_RXD2_FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
+#define MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)
+
+#define MT7623_PIN_272_G2_RXD3_FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
+#define MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
+
+#define MT7623_PIN_274_G2_RXDV_FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
+#define MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
+
+#define MT7623_PIN_275_G2_MDC_FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
+#define MT7623_PIN_275_G2_MDC_FUNC_MDC (MTK_PIN_NO(275) | 1)
+
+#define MT7623_PIN_276_G2_MDIO_FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
+#define MT7623_PIN_276_G2_MDIO_FUNC_MDIO (MTK_PIN_NO(276) | 1)
+
+#define MT7623_PIN_278_JTAG_RESET_FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
+#define MT7623_PIN_278_JTAG_RESET_FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
+
+#endif /* __DTS_MT7623_PINFUNC_H */
projects / mirror_ubuntu-artful-kernel.git / commitdiff