drm/i915: Handle catastrophic error on engine reset

If cat error is set, we need to clear it by acking it. Further,
if it is set, we must not do a normal request for reset.

v2: avoid goto (Chris)
v3: comment, error format, direct assign (Chris)
Bspec: 12567
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190412165353.16432-1-mika.kuoppala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8ad2f0a03f287681e1fd869222ce046e20384c29..c1c0f7ab03e9afa06c66f4b05e73b11422d802fe 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2446,8 +2446,10 @@ enum i915_power_well_id {
 #define RING_HWS_PGA(base)     _MMIO((base) + 0x80)
 #define RING_HWS_PGA_GEN6(base)        _MMIO((base) + 0x2080)
 #define RING_RESET_CTL(base)   _MMIO((base) + 0xd0)
-#define   RESET_CTL_REQUEST_RESET  (1 << 0)
-#define   RESET_CTL_READY_TO_RESET (1 << 1)
+#define   RESET_CTL_CAT_ERROR     REG_BIT(2)
+#define   RESET_CTL_READY_TO_RESET REG_BIT(1)
+#define   RESET_CTL_REQUEST_RESET  REG_BIT(0)
+
 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
 
 #define HSW_GTT_CACHE_EN       _MMIO(0x4024)

diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
index 8ce819bbd8ff558bc8d14e380838a8b0e39fa96b..bc5f9c69895e2f3aea3b1db34f6c655d3d13e6bc 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -495,7 +495,17 @@ static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
        int ret;
 
        ack = intel_uncore_read_fw(uncore, reg);
-       if (!(ack & RESET_CTL_READY_TO_RESET)) {
+       if (ack & RESET_CTL_CAT_ERROR) {
+               /*
+                * For catastrophic errors, ready-for-reset sequence
+                * needs to be bypassed: HAS#396813
+                */
+               request = RESET_CTL_CAT_ERROR;
+               mask = RESET_CTL_CAT_ERROR;
+
+               /* Catastrophic errors need to be cleared by HW */
+               ack = 0;
+       } else if (!(ack & RESET_CTL_READY_TO_RESET)) {
                request = RESET_CTL_REQUEST_RESET;
                mask = RESET_CTL_READY_TO_RESET;
                ack = RESET_CTL_READY_TO_RESET;