target/tricore: Rename csfr.def -> csfr.h.inc

We use the .h.inc extension to include C headers. To be consistent
with the rest of the codebase, rename the C headers using the .def
extension.

IDE/tools using our .editorconfig / .gitattributes will leverage
this consistency.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20221025235006.7215-4-philmd@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>

diff --git a/target/tricore/csfr.def b/target/tricore/csfr.def
deleted file mode 100644 (file)
index ff004cb..0000000
--- a/target/tricore/csfr.def
+++ /dev/null
@@ -1,125 +0,0 @@
-/* A(ll) access permited
-   R(ead only) access
-   E(nd init protected) access
-
-   A|R|E(offset, register, feature introducing reg)
-
-   NOTE: PSW is handled as a special case in gen_mtcr/mfcr */
-
-A(0xfe00, PCXI, TRICORE_FEATURE_13)
-A(0xfe08, PC, TRICORE_FEATURE_13)
-A(0xfe14, SYSCON, TRICORE_FEATURE_13)
-R(0xfe18, CPU_ID, TRICORE_FEATURE_13)
-R(0xfe1c, CORE_ID, TRICORE_FEATURE_161)
-E(0xfe20, BIV, TRICORE_FEATURE_13)
-E(0xfe24, BTV, TRICORE_FEATURE_13)
-E(0xfe28, ISP, TRICORE_FEATURE_13)
-A(0xfe2c, ICR, TRICORE_FEATURE_13)
-A(0xfe38, FCX, TRICORE_FEATURE_13)
-A(0xfe3c, LCX, TRICORE_FEATURE_13)
-E(0x9400, COMPAT, TRICORE_FEATURE_131)
-/* memory protection register */
-A(0xC000, DPR0_0L, TRICORE_FEATURE_13)
-A(0xC004, DPR0_0U, TRICORE_FEATURE_13)
-A(0xC008, DPR0_1L, TRICORE_FEATURE_13)
-A(0xC00C, DPR0_1U, TRICORE_FEATURE_13)
-A(0xC010, DPR0_2L, TRICORE_FEATURE_13)
-A(0xC014, DPR0_2U, TRICORE_FEATURE_13)
-A(0xC018, DPR0_3L, TRICORE_FEATURE_13)
-A(0xC01C, DPR0_3U, TRICORE_FEATURE_13)
-A(0xC400, DPR1_0L, TRICORE_FEATURE_13)
-A(0xC404, DPR1_0U, TRICORE_FEATURE_13)
-A(0xC408, DPR1_1L, TRICORE_FEATURE_13)
-A(0xC40C, DPR1_1U, TRICORE_FEATURE_13)
-A(0xC410, DPR1_2L, TRICORE_FEATURE_13)
-A(0xC414, DPR1_2U, TRICORE_FEATURE_13)
-A(0xC418, DPR1_3L, TRICORE_FEATURE_13)
-A(0xC41C, DPR1_3U, TRICORE_FEATURE_13)
-A(0xC800, DPR2_0L, TRICORE_FEATURE_13)
-A(0xC804, DPR2_0U, TRICORE_FEATURE_13)
-A(0xC808, DPR2_1L, TRICORE_FEATURE_13)
-A(0xC80C, DPR2_1U, TRICORE_FEATURE_13)
-A(0xC810, DPR2_2L, TRICORE_FEATURE_13)
-A(0xC814, DPR2_2U, TRICORE_FEATURE_13)
-A(0xC818, DPR2_3L, TRICORE_FEATURE_13)
-A(0xC81C, DPR2_3U, TRICORE_FEATURE_13)
-A(0xCC00, DPR3_0L, TRICORE_FEATURE_13)
-A(0xCC04, DPR3_0U, TRICORE_FEATURE_13)
-A(0xCC08, DPR3_1L, TRICORE_FEATURE_13)
-A(0xCC0C, DPR3_1U, TRICORE_FEATURE_13)
-A(0xCC10, DPR3_2L, TRICORE_FEATURE_13)
-A(0xCC14, DPR3_2U, TRICORE_FEATURE_13)
-A(0xCC18, DPR3_3L, TRICORE_FEATURE_13)
-A(0xCC1C, DPR3_3U, TRICORE_FEATURE_13)
-A(0xD000, CPR0_0L, TRICORE_FEATURE_13)
-A(0xD004, CPR0_0U, TRICORE_FEATURE_13)
-A(0xD008, CPR0_1L, TRICORE_FEATURE_13)
-A(0xD00C, CPR0_1U, TRICORE_FEATURE_13)
-A(0xD010, CPR0_2L, TRICORE_FEATURE_13)
-A(0xD014, CPR0_2U, TRICORE_FEATURE_13)
-A(0xD018, CPR0_3L, TRICORE_FEATURE_13)
-A(0xD01C, CPR0_3U, TRICORE_FEATURE_13)
-A(0xD400, CPR1_0L, TRICORE_FEATURE_13)
-A(0xD404, CPR1_0U, TRICORE_FEATURE_13)
-A(0xD408, CPR1_1L, TRICORE_FEATURE_13)
-A(0xD40C, CPR1_1U, TRICORE_FEATURE_13)
-A(0xD410, CPR1_2L, TRICORE_FEATURE_13)
-A(0xD414, CPR1_2U, TRICORE_FEATURE_13)
-A(0xD418, CPR1_3L, TRICORE_FEATURE_13)
-A(0xD41C, CPR1_3U, TRICORE_FEATURE_13)
-A(0xD800, CPR2_0L, TRICORE_FEATURE_13)
-A(0xD804, CPR2_0U, TRICORE_FEATURE_13)
-A(0xD808, CPR2_1L, TRICORE_FEATURE_13)
-A(0xD80C, CPR2_1U, TRICORE_FEATURE_13)
-A(0xD810, CPR2_2L, TRICORE_FEATURE_13)
-A(0xD814, CPR2_2U, TRICORE_FEATURE_13)
-A(0xD818, CPR2_3L, TRICORE_FEATURE_13)
-A(0xD81C, CPR2_3U, TRICORE_FEATURE_13)
-A(0xDC00, CPR3_0L, TRICORE_FEATURE_13)
-A(0xDC04, CPR3_0U, TRICORE_FEATURE_13)
-A(0xDC08, CPR3_1L, TRICORE_FEATURE_13)
-A(0xDC0C, CPR3_1U, TRICORE_FEATURE_13)
-A(0xDC10, CPR3_2L, TRICORE_FEATURE_13)
-A(0xDC14, CPR3_2U, TRICORE_FEATURE_13)
-A(0xDC18, CPR3_3L, TRICORE_FEATURE_13)
-A(0xDC1C, CPR3_3U, TRICORE_FEATURE_13)
-A(0xE000, DPM0, TRICORE_FEATURE_13)
-A(0xE080, DPM1, TRICORE_FEATURE_13)
-A(0xE100, DPM2, TRICORE_FEATURE_13)
-A(0xE180, DPM3, TRICORE_FEATURE_13)
-A(0xE200, CPM0, TRICORE_FEATURE_13)
-A(0xE280, CPM1, TRICORE_FEATURE_13)
-A(0xE300, CPM2, TRICORE_FEATURE_13)
-A(0xE380, CPM3, TRICORE_FEATURE_13)
-/* memory management registers */
-A(0x8000, MMU_CON, TRICORE_FEATURE_13)
-A(0x8004, MMU_ASI, TRICORE_FEATURE_13)
-A(0x800C, MMU_TVA, TRICORE_FEATURE_13)
-A(0x8010, MMU_TPA, TRICORE_FEATURE_13)
-A(0x8014, MMU_TPX, TRICORE_FEATURE_13)
-A(0x8018, MMU_TFA, TRICORE_FEATURE_13)
-E(0x9004, BMACON, TRICORE_FEATURE_131)
-E(0x900C, SMACON, TRICORE_FEATURE_131)
-A(0x9020, DIEAR, TRICORE_FEATURE_131)
-A(0x9024, DIETR, TRICORE_FEATURE_131)
-A(0x9028, CCDIER, TRICORE_FEATURE_131)
-E(0x9044, MIECON, TRICORE_FEATURE_131)
-A(0x9210, PIEAR, TRICORE_FEATURE_131)
-A(0x9214, PIETR, TRICORE_FEATURE_131)
-A(0x9218, CCPIER, TRICORE_FEATURE_131)
-/* debug registers */
-A(0xFD00, DBGSR, TRICORE_FEATURE_13)
-A(0xFD08, EXEVT, TRICORE_FEATURE_13)
-A(0xFD0C, CREVT, TRICORE_FEATURE_13)
-A(0xFD10, SWEVT, TRICORE_FEATURE_13)
-A(0xFD20, TR0EVT, TRICORE_FEATURE_13)
-A(0xFD24, TR1EVT, TRICORE_FEATURE_13)
-A(0xFD40, DMS, TRICORE_FEATURE_13)
-A(0xFD44, DCX, TRICORE_FEATURE_13)
-A(0xFD48, DBGTCR, TRICORE_FEATURE_131)
-A(0xFC00, CCTRL, TRICORE_FEATURE_131)
-A(0xFC04, CCNT, TRICORE_FEATURE_131)
-A(0xFC08, ICNT, TRICORE_FEATURE_131)
-A(0xFC0C, M1CNT, TRICORE_FEATURE_131)
-A(0xFC10, M2CNT, TRICORE_FEATURE_131)
-A(0xFC14, M3CNT, TRICORE_FEATURE_131)

diff --git a/target/tricore/csfr.h.inc b/target/tricore/csfr.h.inc
new file mode 100644 (file)
index 0000000..ff004cb
--- /dev/null
+++ b/target/tricore/csfr.h.inc
@@ -0,0 +1,125 @@
+/* A(ll) access permited
+   R(ead only) access
+   E(nd init protected) access
+
+   A|R|E(offset, register, feature introducing reg)
+
+   NOTE: PSW is handled as a special case in gen_mtcr/mfcr */
+
+A(0xfe00, PCXI, TRICORE_FEATURE_13)
+A(0xfe08, PC, TRICORE_FEATURE_13)
+A(0xfe14, SYSCON, TRICORE_FEATURE_13)
+R(0xfe18, CPU_ID, TRICORE_FEATURE_13)
+R(0xfe1c, CORE_ID, TRICORE_FEATURE_161)
+E(0xfe20, BIV, TRICORE_FEATURE_13)
+E(0xfe24, BTV, TRICORE_FEATURE_13)
+E(0xfe28, ISP, TRICORE_FEATURE_13)
+A(0xfe2c, ICR, TRICORE_FEATURE_13)
+A(0xfe38, FCX, TRICORE_FEATURE_13)
+A(0xfe3c, LCX, TRICORE_FEATURE_13)
+E(0x9400, COMPAT, TRICORE_FEATURE_131)
+/* memory protection register */
+A(0xC000, DPR0_0L, TRICORE_FEATURE_13)
+A(0xC004, DPR0_0U, TRICORE_FEATURE_13)
+A(0xC008, DPR0_1L, TRICORE_FEATURE_13)
+A(0xC00C, DPR0_1U, TRICORE_FEATURE_13)
+A(0xC010, DPR0_2L, TRICORE_FEATURE_13)
+A(0xC014, DPR0_2U, TRICORE_FEATURE_13)
+A(0xC018, DPR0_3L, TRICORE_FEATURE_13)
+A(0xC01C, DPR0_3U, TRICORE_FEATURE_13)
+A(0xC400, DPR1_0L, TRICORE_FEATURE_13)
+A(0xC404, DPR1_0U, TRICORE_FEATURE_13)
+A(0xC408, DPR1_1L, TRICORE_FEATURE_13)
+A(0xC40C, DPR1_1U, TRICORE_FEATURE_13)
+A(0xC410, DPR1_2L, TRICORE_FEATURE_13)
+A(0xC414, DPR1_2U, TRICORE_FEATURE_13)
+A(0xC418, DPR1_3L, TRICORE_FEATURE_13)
+A(0xC41C, DPR1_3U, TRICORE_FEATURE_13)
+A(0xC800, DPR2_0L, TRICORE_FEATURE_13)
+A(0xC804, DPR2_0U, TRICORE_FEATURE_13)
+A(0xC808, DPR2_1L, TRICORE_FEATURE_13)
+A(0xC80C, DPR2_1U, TRICORE_FEATURE_13)
+A(0xC810, DPR2_2L, TRICORE_FEATURE_13)
+A(0xC814, DPR2_2U, TRICORE_FEATURE_13)
+A(0xC818, DPR2_3L, TRICORE_FEATURE_13)
+A(0xC81C, DPR2_3U, TRICORE_FEATURE_13)
+A(0xCC00, DPR3_0L, TRICORE_FEATURE_13)
+A(0xCC04, DPR3_0U, TRICORE_FEATURE_13)
+A(0xCC08, DPR3_1L, TRICORE_FEATURE_13)
+A(0xCC0C, DPR3_1U, TRICORE_FEATURE_13)
+A(0xCC10, DPR3_2L, TRICORE_FEATURE_13)
+A(0xCC14, DPR3_2U, TRICORE_FEATURE_13)
+A(0xCC18, DPR3_3L, TRICORE_FEATURE_13)
+A(0xCC1C, DPR3_3U, TRICORE_FEATURE_13)
+A(0xD000, CPR0_0L, TRICORE_FEATURE_13)
+A(0xD004, CPR0_0U, TRICORE_FEATURE_13)
+A(0xD008, CPR0_1L, TRICORE_FEATURE_13)
+A(0xD00C, CPR0_1U, TRICORE_FEATURE_13)
+A(0xD010, CPR0_2L, TRICORE_FEATURE_13)
+A(0xD014, CPR0_2U, TRICORE_FEATURE_13)
+A(0xD018, CPR0_3L, TRICORE_FEATURE_13)
+A(0xD01C, CPR0_3U, TRICORE_FEATURE_13)
+A(0xD400, CPR1_0L, TRICORE_FEATURE_13)
+A(0xD404, CPR1_0U, TRICORE_FEATURE_13)
+A(0xD408, CPR1_1L, TRICORE_FEATURE_13)
+A(0xD40C, CPR1_1U, TRICORE_FEATURE_13)
+A(0xD410, CPR1_2L, TRICORE_FEATURE_13)
+A(0xD414, CPR1_2U, TRICORE_FEATURE_13)
+A(0xD418, CPR1_3L, TRICORE_FEATURE_13)
+A(0xD41C, CPR1_3U, TRICORE_FEATURE_13)
+A(0xD800, CPR2_0L, TRICORE_FEATURE_13)
+A(0xD804, CPR2_0U, TRICORE_FEATURE_13)
+A(0xD808, CPR2_1L, TRICORE_FEATURE_13)
+A(0xD80C, CPR2_1U, TRICORE_FEATURE_13)
+A(0xD810, CPR2_2L, TRICORE_FEATURE_13)
+A(0xD814, CPR2_2U, TRICORE_FEATURE_13)
+A(0xD818, CPR2_3L, TRICORE_FEATURE_13)
+A(0xD81C, CPR2_3U, TRICORE_FEATURE_13)
+A(0xDC00, CPR3_0L, TRICORE_FEATURE_13)
+A(0xDC04, CPR3_0U, TRICORE_FEATURE_13)
+A(0xDC08, CPR3_1L, TRICORE_FEATURE_13)
+A(0xDC0C, CPR3_1U, TRICORE_FEATURE_13)
+A(0xDC10, CPR3_2L, TRICORE_FEATURE_13)
+A(0xDC14, CPR3_2U, TRICORE_FEATURE_13)
+A(0xDC18, CPR3_3L, TRICORE_FEATURE_13)
+A(0xDC1C, CPR3_3U, TRICORE_FEATURE_13)
+A(0xE000, DPM0, TRICORE_FEATURE_13)
+A(0xE080, DPM1, TRICORE_FEATURE_13)
+A(0xE100, DPM2, TRICORE_FEATURE_13)
+A(0xE180, DPM3, TRICORE_FEATURE_13)
+A(0xE200, CPM0, TRICORE_FEATURE_13)
+A(0xE280, CPM1, TRICORE_FEATURE_13)
+A(0xE300, CPM2, TRICORE_FEATURE_13)
+A(0xE380, CPM3, TRICORE_FEATURE_13)
+/* memory management registers */
+A(0x8000, MMU_CON, TRICORE_FEATURE_13)
+A(0x8004, MMU_ASI, TRICORE_FEATURE_13)
+A(0x800C, MMU_TVA, TRICORE_FEATURE_13)
+A(0x8010, MMU_TPA, TRICORE_FEATURE_13)
+A(0x8014, MMU_TPX, TRICORE_FEATURE_13)
+A(0x8018, MMU_TFA, TRICORE_FEATURE_13)
+E(0x9004, BMACON, TRICORE_FEATURE_131)
+E(0x900C, SMACON, TRICORE_FEATURE_131)
+A(0x9020, DIEAR, TRICORE_FEATURE_131)
+A(0x9024, DIETR, TRICORE_FEATURE_131)
+A(0x9028, CCDIER, TRICORE_FEATURE_131)
+E(0x9044, MIECON, TRICORE_FEATURE_131)
+A(0x9210, PIEAR, TRICORE_FEATURE_131)
+A(0x9214, PIETR, TRICORE_FEATURE_131)
+A(0x9218, CCPIER, TRICORE_FEATURE_131)
+/* debug registers */
+A(0xFD00, DBGSR, TRICORE_FEATURE_13)
+A(0xFD08, EXEVT, TRICORE_FEATURE_13)
+A(0xFD0C, CREVT, TRICORE_FEATURE_13)
+A(0xFD10, SWEVT, TRICORE_FEATURE_13)
+A(0xFD20, TR0EVT, TRICORE_FEATURE_13)
+A(0xFD24, TR1EVT, TRICORE_FEATURE_13)
+A(0xFD40, DMS, TRICORE_FEATURE_13)
+A(0xFD44, DCX, TRICORE_FEATURE_13)
+A(0xFD48, DBGTCR, TRICORE_FEATURE_131)
+A(0xFC00, CCTRL, TRICORE_FEATURE_131)
+A(0xFC04, CCNT, TRICORE_FEATURE_131)
+A(0xFC08, ICNT, TRICORE_FEATURE_131)
+A(0xFC0C, M1CNT, TRICORE_FEATURE_131)
+A(0xFC10, M2CNT, TRICORE_FEATURE_131)
+A(0xFC14, M3CNT, TRICORE_FEATURE_131)

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index c5b7bfbf201375df072af1369ea679426fd06fba..df9e46c6495ea574be7e506d9d4075f407c7dc41 100644 (file)
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -388,7 +388,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
         gen_helper_psw_read(ret, cpu_env);
     } else {
         switch (offset) {
-#include "csfr.def"
+#include "csfr.h.inc"
         }
     }
 }
@@ -418,7 +418,7 @@ static inline void gen_mtcr(DisasContext *ctx, TCGv r1,
             gen_helper_psw_write(cpu_env, r1);
         } else {
             switch (offset) {
-#include "csfr.def"
+#include "csfr.h.inc"
             }
         }
     } else {