drm/amd/display: Call DMUB for eDP power control

[Why]
If DMUB is used, LVTMA VBIOS call can be used to control eDP instead of
tranditional transmitter control.  Interface is agreed with VBIOS for
eDP to use this new path to program LVTMA registers.

[How]
Create DAL interface to send DMUB command for LVTMA as currently
implemented in VBIOS.

Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 078b7e34418550ab1910074399b1a82a63c51656..2d5c7daaee231c7b8c242a1382e170fbd06fff4e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1108,6 +1108,18 @@ static enum bp_result bios_parser_enable_disp_power_gating(
                action);
 }
 
+static enum bp_result bios_parser_enable_lvtma_control(
+       struct dc_bios *dcb,
+       uint8_t uc_pwr_on)
+{
+       struct bios_parser *bp = BP_FROM_DCB(dcb);
+
+       if (!bp->cmd_tbl.enable_lvtma_control)
+               return BP_RESULT_FAILURE;
+
+       return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on);
+}
+
 static bool bios_parser_is_accelerated_mode(
        struct dc_bios *dcb)
 {
@@ -2208,7 +2220,9 @@ static const struct dc_vbios_funcs vbios_funcs = {
        .get_board_layout_info = bios_get_board_layout_info,
        .pack_data_tables = bios_parser_pack_data_tables,
 
-       .get_atom_dc_golden_table = bios_get_atom_dc_golden_table
+       .get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
+
+       .enable_lvtma_control = bios_parser_enable_lvtma_control
 };
 
 static bool bios_parser2_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index bed91572f82a6a3bd44ab338c8ad76c2d294147e..eb3ae5c3677cbb5fbc807d413b610ba71f8f053d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -904,6 +904,33 @@ static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id)
        return 0;
 }
 
+/******************************************************************************
+ ******************************************************************************
+ **
+ **                  LVTMA CONTROL
+ **
+ ******************************************************************************
+ *****************************************************************************/
+
+static enum bp_result enable_lvtma_control(
+       struct bios_parser *bp,
+       uint8_t uc_pwr_on);
+
+static void init_enable_lvtma_control(struct bios_parser *bp)
+{
+       /* TODO add switch for table vrsion */
+       bp->cmd_tbl.enable_lvtma_control = enable_lvtma_control;
+
+}
+
+static enum bp_result enable_lvtma_control(
+       struct bios_parser *bp,
+       uint8_t uc_pwr_on)
+{
+       enum bp_result result = BP_RESULT_FAILURE;
+       return result;
+}
+
 void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
 {
        init_dig_encoder_control(bp);
@@ -919,4 +946,5 @@ void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
        init_set_dce_clock(bp);
        init_get_smu_clock_info(bp);
 
+       init_enable_lvtma_control(bp);
 }

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.h b/drivers/gpu/drm/amd/display/dc/bios/command_table2.h
index 7a2af24dfe605cd752b0139f652d3061ee825d55..7bdce013cde5ab781a58b2fa832968a5ab6a1b7e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.h
@@ -94,7 +94,8 @@ struct cmd_tbl {
                struct bp_set_dce_clock_parameters *bp_params);
        unsigned int (*get_smu_clock_info)(
                        struct bios_parser *bp, uint8_t id);
-
+       enum bp_result (*enable_lvtma_control)(struct bios_parser *bp,
+                       uint8_t uc_pwr_on);
 };
 
 void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp);

diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
index d06d07042a12014a453fc866ca40eb4c9e6c513b..0811f941f4304e8796d381159a92e96f11066e0e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
@@ -136,6 +136,10 @@ struct dc_vbios_funcs {
 
        enum bp_result (*get_atom_dc_golden_table)(
                        struct dc_bios *dcb);
+
+       enum bp_result (*enable_lvtma_control)(
+               struct dc_bios *bios,
+               uint8_t uc_pwr_on);
 };
 
 struct bios_registers {

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 49380ed3aeae14ba96839ca99ea1a4f0971d3477..45c9e90278862d2f63d98255cc338d1659491acf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -842,6 +842,17 @@ void dce110_edp_power_control(
                cntl.coherent = false;
                cntl.lanes_number = LANE_COUNT_FOUR;
                cntl.hpd_sel = link->link_enc->hpd_source;
+
+               if (ctx->dc->ctx->dmub_srv &&
+                               ctx->dc->debug.dmub_command_table) {
+                       if (cntl.action == TRANSMITTER_CONTROL_POWER_ON)
+                               bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
+                                               LVTMA_CONTROL_POWER_ON);
+                       else
+                               bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
+                                               LVTMA_CONTROL_POWER_OFF);
+               }
+
                bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 
                if (!power_up)
@@ -919,8 +930,21 @@ void dce110_edp_backlight_control(
                /*edp 1.2*/
        if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
                edp_receiver_ready_T7(link);
+
+       if (ctx->dc->ctx->dmub_srv &&
+                       ctx->dc->debug.dmub_command_table) {
+               if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
+                       ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
+                                       LVTMA_CONTROL_LCD_BLON);
+               else
+                       ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
+                                       LVTMA_CONTROL_LCD_BLOFF);
+       }
+
        link_transmitter_control(ctx->dc_bios, &cntl);
 
+
+
        if (enable && link->dpcd_sink_ext_caps.bits.oled)
                msleep(OLED_POST_T7_DELAY);
 

diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
index c30437ae839532bf1509e38ef2d959122d27e9ea..21011edea337b9cb5d62981ddb55988b460fa118 100644 (file)
--- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h
+++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
@@ -101,6 +101,13 @@ enum bp_pipe_control_action {
        ASIC_PIPE_INIT
 };
 
+enum bp_lvtma_control_action {
+       LVTMA_CONTROL_LCD_BLOFF = 2,
+       LVTMA_CONTROL_LCD_BLON = 3,
+       LVTMA_CONTROL_POWER_ON = 12,
+       LVTMA_CONTROL_POWER_OFF = 13
+};
+
 struct bp_encoder_control {
        enum bp_encoder_control_action action;
        enum engine_id engine_id;