drm/amd/amdgpu: Enable clockgating for UVD5 on Tonga

This patch enables clock gating for the UVD5 block with
Tonga.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index a14555673c402954152820964356c48ac3a39703..5c394703d0b6235d6cb0922712dfc35e20a088b0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1081,7 +1081,7 @@ static int vi_common_early_init(void *handle)
                adev->external_rev_id = adev->rev_id + 0x3c;
                break;
        case CHIP_TONGA:
-               adev->cg_flags = 0;
+               adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
                adev->pg_flags = 0;
                adev->external_rev_id = adev->rev_id + 0x14;
                break;