arm64: dts: juno: add coresight CPU debug nodes

Add Coresight CPU debug nodes for Juno r0, r1 & r2. The CPU
debug areas are mapped at the same address for all revisions,
like the ETM, even though the CPUs have changed from r1 to r2.

Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mathieu Poirier <mathieu.porier@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[arranged nodes in ascending order with respect to register addresses]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index bfe7d683a42e1b27b6e90997f9ebf18abb79afce..48bc5abb37a20e48c006a14a5659b567fea12889 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -202,6 +202,15 @@
                };
        };
 
+       cpu_debug0: cpu_debug@22010000 {
+               compatible = "arm,coresight-cpu-debug", "arm,primecell";
+               reg = <0x0 0x22010000 0x0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+       };
+
        etm0: etm@22040000 {
                compatible = "arm,coresight-etm4x", "arm,primecell";
                reg = <0 0x22040000 0 0x1000>;
@@ -252,6 +261,15 @@
                };
        };
 
+       cpu_debug1: cpu_debug@22110000 {
+               compatible = "arm,coresight-cpu-debug", "arm,primecell";
+               reg = <0x0 0x22110000 0x0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+       };
+
        etm1: etm@22140000 {
                compatible = "arm,coresight-etm4x", "arm,primecell";
                reg = <0 0x22140000 0 0x1000>;
@@ -266,6 +284,15 @@
                };
        };
 
+       cpu_debug2: cpu_debug@23010000 {
+               compatible = "arm,coresight-cpu-debug", "arm,primecell";
+               reg = <0x0 0x23010000 0x0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+       };
+
        etm2: etm@23040000 {
                compatible = "arm,coresight-etm4x", "arm,primecell";
                reg = <0 0x23040000 0 0x1000>;
@@ -330,6 +357,15 @@
                };
        };
 
+       cpu_debug3: cpu_debug@23110000 {
+               compatible = "arm,coresight-cpu-debug", "arm,primecell";
+               reg = <0x0 0x23110000 0x0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+       };
+
        etm3: etm@23140000 {
                compatible = "arm,coresight-etm4x", "arm,primecell";
                reg = <0 0x23140000 0 0x1000>;
@@ -344,6 +380,15 @@
                };
        };
 
+       cpu_debug4: cpu_debug@23210000 {
+               compatible = "arm,coresight-cpu-debug", "arm,primecell";
+               reg = <0x0 0x23210000 0x0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+       };
+
        etm4: etm@23240000 {
                compatible = "arm,coresight-etm4x", "arm,primecell";
                reg = <0 0x23240000 0 0x1000>;
@@ -358,6 +403,15 @@
                };
        };
 
+       cpu_debug5: cpu_debug@23310000 {
+               compatible = "arm,coresight-cpu-debug", "arm,primecell";
+               reg = <0x0 0x23310000 0x0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+       };
+
        etm5: etm@23340000 {
                compatible = "arm,coresight-etm4x", "arm,primecell";
                reg = <0 0x23340000 0 0x1000>;

diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index 0e8943ab94d77497ad28f6699e23d7bc4dec7958..aed6389468c4a1d386189265e2d7a0abe68f6b06 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -281,3 +281,27 @@
 &stm_out_port {
        remote-endpoint = <&csys1_funnel_in_port0>;
 };
+
+&cpu_debug0 {
+       cpu = <&A57_0>;
+};
+
+&cpu_debug1 {
+       cpu = <&A57_1>;
+};
+
+&cpu_debug2 {
+       cpu = <&A53_0>;
+};
+
+&cpu_debug3 {
+       cpu = <&A53_1>;
+};
+
+&cpu_debug4 {
+       cpu = <&A53_2>;
+};
+
+&cpu_debug5 {
+       cpu = <&A53_3>;
+};

diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
index 405e2fba025beeec73c8ba020fa2329f2438f533..b39b6d6ec5aa1be93c88e7a988bdbae3cfd40a9b 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -281,3 +281,27 @@
 &stm_out_port {
        remote-endpoint = <&csys1_funnel_in_port0>;
 };
+
+&cpu_debug0 {
+       cpu = <&A72_0>;
+};
+
+&cpu_debug1 {
+       cpu = <&A72_1>;
+};
+
+&cpu_debug2 {
+       cpu = <&A53_0>;
+};
+
+&cpu_debug3 {
+       cpu = <&A53_1>;
+};
+
+&cpu_debug4 {
+       cpu = <&A53_2>;
+};
+
+&cpu_debug5 {
+       cpu = <&A53_3>;
+};

diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index 0220494c9b80222d742fb1285e52d1a01a7066ba..c9236c4b967d2f461b91730e0b8f3f941b32d307 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -268,3 +268,27 @@
                };
        };
 };
+
+&cpu_debug0 {
+       cpu = <&A57_0>;
+};
+
+&cpu_debug1 {
+       cpu = <&A57_1>;
+};
+
+&cpu_debug2 {
+       cpu = <&A53_0>;
+};
+
+&cpu_debug3 {
+       cpu = <&A53_1>;
+};
+
+&cpu_debug4 {
+       cpu = <&A53_2>;
+};
+
+&cpu_debug5 {
+       cpu = <&A53_3>;
+};