igc: Add Receive Descriptor Minimum Threshold Count to clear HW counters

The statistics of this register are being tracked, however, the register
was inadvertently missed when implementing igc_clear_hw_cntrs_base().
The register is clear on read, so add it to the function so that the
register is cleared when requested so the tracked count is accurate.

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>

diff --git a/drivers/net/ethernet/intel/igc/igc_mac.c b/drivers/net/ethernet/intel/igc/igc_mac.c
index 2d9ca3e1bddef8db65330af26344583b2a9ff790..3a618e69514e42c34821fbb26629bd954d6d3b9e 100644 (file)
--- a/drivers/net/ethernet/intel/igc/igc_mac.c
+++ b/drivers/net/ethernet/intel/igc/igc_mac.c
@@ -308,6 +308,7 @@ void igc_clear_hw_cntrs_base(struct igc_hw *hw)
        rd32(IGC_TLPIC);
        rd32(IGC_RLPIC);
        rd32(IGC_HGPTC);
+       rd32(IGC_RXDMTC);
        rd32(IGC_HGORCL);
        rd32(IGC_HGORCH);
        rd32(IGC_HGOTCL);