drm/gk104/pwr: implement PGOB disable method

As documented at:

ftp://download.nvidia.com/open-gpu-doc/gk104-disable-graphics-power-gating/1/gk104-disable-graphics-power-gating.txt

NVIDIA were not able document the steps necessary to detect whether this
is required or not at this time.  However, they did confirm that this
procedure is safe to perform unconditionally on GK104/6.  GK107 does not
have the power gating feature, and it was recommended that we do not
perform these steps there as the effects were not verified.

The disable path is from observing the binary driver, and not
documented in the link above.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 8b307e1436328b334db839a3f66e857e21d10306..8f0dd8e32e19f568183397514e1104017eb30e3d 100644 (file)
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -169,6 +169,7 @@ nouveau-y += core/subdev/pwr/memx.o
 nouveau-y += core/subdev/pwr/nva3.o
 nouveau-y += core/subdev/pwr/nvc0.o
 nouveau-y += core/subdev/pwr/nvd0.o
+nouveau-y += core/subdev/pwr/gk104.o
 nouveau-y += core/subdev/pwr/nv108.o
 nouveau-y += core/subdev/therm/base.o
 nouveau-y += core/subdev/therm/fan.o

diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index e8958048f4155c89dd1cb7162b7aebd987c8bba2..7298438f91d12a6682761e8d33c0a5425b0c0483 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -75,7 +75,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
                device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
                device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-               device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;
+               device->oclass[NVDEV_SUBDEV_PWR    ] =  gk104_pwr_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
                device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
@@ -141,7 +141,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
                device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
                device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
-               device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;
+               device->oclass[NVDEV_SUBDEV_PWR    ] =  gk104_pwr_oclass;
                device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
                device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;

diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
index edf11182eab29f240bc8e2432ba20ba3d361d828..f73feec151db453eb8160fba6263dd7999e808fe 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
@@ -23,7 +23,8 @@ struct nouveau_pwr {
                u32 data[2];
        } recv;
 
-       int (*message)(struct nouveau_pwr *, u32[2], u32, u32, u32, u32);
+       int  (*message)(struct nouveau_pwr *, u32[2], u32, u32, u32, u32);
+       void (*pgob)(struct nouveau_pwr *, bool);
 };
 
 static inline struct nouveau_pwr *
@@ -35,6 +36,7 @@ nouveau_pwr(void *obj)
 extern struct nouveau_oclass *nva3_pwr_oclass;
 extern struct nouveau_oclass *nvc0_pwr_oclass;
 extern struct nouveau_oclass *nvd0_pwr_oclass;
+extern struct nouveau_oclass *gk104_pwr_oclass;
 extern struct nouveau_oclass *nv108_pwr_oclass;
 
 /* interface to MEMX process running on PPWR */

diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
index 12baf8151698fc63b74e7e8ca8f93b182870d020..69f1f34f6931d56f53cad1c16faf4d5caef7a935 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
@@ -26,6 +26,14 @@
 
 #include "priv.h"
 
+static void
+nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable)
+{
+       const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr);
+       if (impl->pgob)
+               impl->pgob(ppwr, enable);
+}
+
 static int
 nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2],
                 u32 process, u32 message, u32 data0, u32 data1)
@@ -188,6 +196,7 @@ _nouveau_pwr_init(struct nouveau_object *object)
 
        nv_subdev(ppwr)->intr = nouveau_pwr_intr;
        ppwr->message = nouveau_pwr_send;
+       ppwr->pgob = nouveau_pwr_pgob;
 
        /* prevent previous ucode from running, wait for idle, reset */
        nv_wr32(ppwr, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */

diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c
new file mode 100644 (file)
index 0000000..d766129
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "priv.h"
+
+#define nvd0_pwr_code gk104_pwr_code
+#define nvd0_pwr_data gk104_pwr_data
+#include "fuc/nvd0.fuc.h"
+
+static void
+gk104_pwr_pgob(struct nouveau_pwr *ppwr, bool enable)
+{
+       nv_mask(ppwr, 0x000200, 0x00001000, 0x00000000);
+       nv_rd32(ppwr, 0x000200);
+       nv_mask(ppwr, 0x000200, 0x08000000, 0x08000000);
+       msleep(50);
+
+       nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000002);
+       nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001);
+       nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000);
+
+       nv_mask(ppwr, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000);
+       msleep(50);
+
+       nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000000);
+       nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001);
+       nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000);
+
+       nv_mask(ppwr, 0x000200, 0x08000000, 0x00000000);
+       nv_mask(ppwr, 0x000200, 0x00001000, 0x00001000);
+       nv_rd32(ppwr, 0x000200);
+}
+
+struct nouveau_oclass *
+gk104_pwr_oclass = &(struct nvkm_pwr_impl) {
+       .base.handle = NV_SUBDEV(PWR, 0xe4),
+       .base.ofuncs = &(struct nouveau_ofuncs) {
+               .ctor = _nouveau_pwr_ctor,
+               .dtor = _nouveau_pwr_dtor,
+               .init = _nouveau_pwr_init,
+               .fini = _nouveau_pwr_fini,
+       },
+       .code.data = gk104_pwr_code,
+       .code.size = sizeof(gk104_pwr_code),
+       .data.data = gk104_pwr_data,
+       .data.size = sizeof(gk104_pwr_data),
+       .pgob = gk104_pwr_pgob,
+}.base;

diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h
index ddc614f9a99de551c42b47bc593d35d1de2d12c9..3814a341db3282474732ebc9a8a96242d139e1e1 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h
@@ -37,6 +37,8 @@ struct nvkm_pwr_impl {
                u32 *data;
                u32  size;
        } data;
+
+       void (*pgob)(struct nouveau_pwr *, bool);
 };
 
 #endif