drm/i915: Check hdcp key loadability

HDCP1.4 key can be loaded, only when Power well #1 is enabled and cdclk
is enabled. Using the I915 power well infrastruture, above requirement
is verified.

This patch enables the hdcp initialization for HSW, BDW, and BXT.

v2:
  Choose the PW# based on the platform.
v3:
  No Changes.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1522663834-24482-4-git-send-email-ramalingam.c@intel.com

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index d9dec32c368e03fede7669cbb3c47b434bd2dc23..98a9c81e2dc1fb05dac3d64c1900849e64344cdf 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -37,6 +37,43 @@ static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
        return 0;
 }
 
+static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
+{
+       struct i915_power_domains *power_domains = &dev_priv->power_domains;
+       struct i915_power_well *power_well;
+       enum i915_power_well_id id;
+       bool enabled = false;
+
+       /*
+        * On HSW and BDW, Display HW loads the Key as soon as Display resumes.
+        * On all BXT+, SW can load the keys only when the PW#1 is turned on.
+        */
+       if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+               id = HSW_DISP_PW_GLOBAL;
+       else
+               id = SKL_DISP_PW_1;
+
+       mutex_lock(&power_domains->lock);
+
+       /* PG1 (power well #1) needs to be enabled */
+       for_each_power_well(dev_priv, power_well) {
+               if (power_well->id == id) {
+                       enabled = power_well->ops->is_enabled(dev_priv,
+                                                             power_well);
+                       break;
+               }
+       }
+       mutex_unlock(&power_domains->lock);
+
+       /*
+        * Another req for hdcp key loadability is enabled state of pll for
+        * cdclk. Without active crtc we wont land here. So we are assuming that
+        * cdclk is already on.
+        */
+
+       return enabled;
+}
+
 static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
 {
        I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
@@ -619,8 +656,8 @@ static int _intel_hdcp_enable(struct intel_connector *connector)
        DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n",
                      connector->base.name, connector->base.base.id);
 
-       if (!(I915_READ(SKL_FUSE_STATUS) & SKL_FUSE_PG_DIST_STATUS(1))) {
-               DRM_ERROR("PG1 is disabled, cannot load keys\n");
+       if (!hdcp_key_loadable(dev_priv)) {
+               DRM_ERROR("HDCP key Load is not possible\n");
                return -ENXIO;
        }