ARM: dts: meson: provide the XTAL clock using a fixed-clock

The clock controller driver has provided the XTAL clock so far. This
does not match how the hardware actually works because the XTAL clock is
an actual crystal which is mounted on the PCB.

Add the "xtal" clock to meson.dtsi and replace all references to the
clock controller's CLKID_XTAL with the new xtal clock node.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index c4447f6c8b2cb0fa4ff6c70419cff895b6c08c1d..5d198309058aa7d4cf9af4f7ce2107a387190a64 100644 (file)
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -282,4 +282,11 @@
                        };
                };
        };
+
+       xtal: xtal-clk {
+               compatible = "fixed-clock";
+               clock-frequency = <24000000>;
+               clock-output-names = "xtal";
+               #clock-cells = <0>;
+       };
 }; /* end of / */

diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index 2d31b7ce3f8cb144eeeabe80001d3a00a21fb616..4716030a48d0ddf4aef87e5bee67de926b79e986 100644 (file)
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -36,13 +36,6 @@
                ranges = <0x0 0xd0000000 0x40000>;
        };
 
-       xtal: xtal-clk {
-               compatible = "fixed-clock";
-               clock-frequency = <24000000>;
-               clock-output-names = "xtal";
-               #clock-cells = <0>;
-       };
-
        clk81: clk@0 {
                #clock-cells = <0>;
                compatible = "fixed-clock";

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 5a7e3e5caebe2fc4e7f0880ab9f37d8ff026f9b3..4f59a4c8f03623c65333965b9cd2459c54fdd04f 100644 (file)
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -455,6 +455,8 @@
 &hhi {
        clkc: clock-controller {
                compatible = "amlogic,meson8-clkc";
+               clocks = <&xtal>;
+               clock-names = "xtal";
                #clock-cells = <1>;
                #reset-cells = <1>;
        };
@@ -529,8 +531,7 @@
 
 &saradc {
        compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
-       clocks = <&clkc CLKID_XTAL>,
-               <&clkc CLKID_SAR_ADC>;
+       clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
        clock-names = "clkin", "core";
        amlogic,hhi-sysctrl = <&hhi>;
        nvmem-cells = <&temperature_calib>;
@@ -548,31 +549,31 @@
 };
 
 &timer_abcde {
-       clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+       clocks = <&xtal>, <&clkc CLKID_CLK81>;
        clock-names = "xtal", "pclk";
 };
 
 &uart_AO {
        compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
-       clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+       clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
        clock-names = "baud", "xtal", "pclk";
 };
 
 &uart_A {
        compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
-       clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
+       clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
        clock-names = "baud", "xtal", "pclk";
 };
 
 &uart_B {
        compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
-       clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
+       clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
        clock-names = "baud", "xtal", "pclk";
 };
 
 &uart_C {
        compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
-       clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
+       clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
        clock-names = "baud", "xtal", "pclk";
 };
 

diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
index bed1dfef198578e1f56d13abfda4fcd4703a78e5..163a200d5a7b63afdbf742f47eb571aa6c21b717 100644 (file)
--- a/arch/arm/boot/dts/meson8b-ec100.dts
+++ b/arch/arm/boot/dts/meson8b-ec100.dts
@@ -377,7 +377,7 @@
        status = "okay";
        pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
        pinctrl-names = "default";
-       clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
+       clocks = <&xtal>, <&xtal>;
        clock-names = "clkin0", "clkin1";
 };
 

diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts
index 6e39ad52e42d32b0f95f15527b058337bb848c6f..33037ef62d0ad14743f241d204b13996f9f50eba 100644 (file)
--- a/arch/arm/boot/dts/meson8b-mxq.dts
+++ b/arch/arm/boot/dts/meson8b-mxq.dts
@@ -165,7 +165,7 @@
        status = "okay";
        pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
        pinctrl-names = "default";
-       clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
+       clocks = <&xtal>, <&xtal>;
        clock-names = "clkin0", "clkin1";
 };
 

diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
index a24eccc354b95851f1b48663776a26e5e74a9712..a2a47804fc4a8bdfb422b21bfa1add70e74a6729 100644 (file)
--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
@@ -340,7 +340,7 @@
        status = "okay";
        pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
        pinctrl-names = "default";
-       clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
+       clocks = <&xtal>, <&xtal>;
        clock-names = "clkin0", "clkin1";
 };
 

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 099bf8e711c94ecf3c1d974fa878c6ea9f0af211..1934666ff60f991010757f1adf0b86c24483be3d 100644 (file)
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -434,6 +434,8 @@
 &hhi {
        clkc: clock-controller {
                compatible = "amlogic,meson8-clkc";
+               clocks = <&xtal>;
+               clock-names = "xtal";
                #clock-cells = <1>;
                #reset-cells = <1>;
        };
@@ -508,8 +510,7 @@
 
 &saradc {
        compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
-       clocks = <&clkc CLKID_XTAL>,
-               <&clkc CLKID_SAR_ADC>;
+       clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
        clock-names = "clkin", "core";
        amlogic,hhi-sysctrl = <&hhi>;
        nvmem-cells = <&temperature_calib>;
@@ -523,31 +524,31 @@
 };
 
 &timer_abcde {
-       clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+       clocks = <&xtal>, <&clkc CLKID_CLK81>;
        clock-names = "xtal", "pclk";
 };
 
 &uart_AO {
        compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
-       clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+       clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
        clock-names = "baud", "xtal", "pclk";
 };
 
 &uart_A {
        compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
-       clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
+       clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
        clock-names = "baud", "xtal", "pclk";
 };
 
 &uart_B {
        compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
-       clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
+       clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
        clock-names = "baud", "xtal", "pclk";
 };
 
 &uart_C {
        compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
-       clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
+       clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
        clock-names = "baud", "xtal", "pclk";
 };