]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/commitdiff
ARM: 8641/1: treewide: Replace uses of virt_to_phys with __pa_symbol
authorFlorian Fainelli <f.fainelli@gmail.com>
Sun, 15 Jan 2017 02:59:29 +0000 (03:59 +0100)
committerRussell King <rmk+kernel@armlinux.org.uk>
Tue, 28 Feb 2017 11:06:10 +0000 (11:06 +0000)
All low-level PM/SMP code using virt_to_phys() should actually use
__pa_symbol() against kernel symbols. Update code where relevant to move
away from virt_to_phys().

Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Laura Abbott <labbott@redhat.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
54 files changed:
arch/arm/common/mcpm_entry.c
arch/arm/mach-alpine/platsmp.c
arch/arm/mach-axxia/platsmp.c
arch/arm/mach-bcm/bcm63xx_smp.c
arch/arm/mach-bcm/platsmp-brcmstb.c
arch/arm/mach-bcm/platsmp.c
arch/arm/mach-berlin/platsmp.c
arch/arm/mach-exynos/firmware.c
arch/arm/mach-exynos/mcpm-exynos.c
arch/arm/mach-exynos/platsmp.c
arch/arm/mach-exynos/pm.c
arch/arm/mach-exynos/suspend.c
arch/arm/mach-hisi/platmcpm.c
arch/arm/mach-hisi/platsmp.c
arch/arm/mach-imx/platsmp.c
arch/arm/mach-imx/pm-imx6.c
arch/arm/mach-imx/src.c
arch/arm/mach-mediatek/platsmp.c
arch/arm/mach-mvebu/pm.c
arch/arm/mach-mvebu/pmsu.c
arch/arm/mach-mvebu/system-controller.c
arch/arm/mach-omap2/control.c
arch/arm/mach-omap2/omap-mpuss-lowpower.c
arch/arm/mach-omap2/omap-smp.c
arch/arm/mach-prima2/platsmp.c
arch/arm/mach-prima2/pm.c
arch/arm/mach-pxa/palmz72.c
arch/arm/mach-pxa/pxa25x.c
arch/arm/mach-pxa/pxa27x.c
arch/arm/mach-pxa/pxa3xx.c
arch/arm/mach-realview/platsmp-dt.c
arch/arm/mach-rockchip/platsmp.c
arch/arm/mach-rockchip/pm.c
arch/arm/mach-s3c24xx/mach-jive.c
arch/arm/mach-s3c24xx/pm-s3c2410.c
arch/arm/mach-s3c24xx/pm-s3c2416.c
arch/arm/mach-s3c64xx/pm.c
arch/arm/mach-s5pv210/pm.c
arch/arm/mach-sa1100/pm.c
arch/arm/mach-shmobile/platsmp-apmu.c
arch/arm/mach-shmobile/platsmp-scu.c
arch/arm/mach-socfpga/platsmp.c
arch/arm/mach-spear/platsmp.c
arch/arm/mach-sti/platsmp.c
arch/arm/mach-sunxi/platsmp.c
arch/arm/mach-tango/platsmp.c
arch/arm/mach-tango/pm.c
arch/arm/mach-tegra/reset.c
arch/arm/mach-ux500/platsmp.c
arch/arm/mach-vexpress/dcscb.c
arch/arm/mach-vexpress/platsmp.c
arch/arm/mach-vexpress/tc2_pm.c
arch/arm/mach-zx/platsmp.c
arch/arm/mach-zynq/platsmp.c

index a923524d1040734d1f5b94b4a6e2f5d59cab99d1..cf062472e07bcb4be470bf35ab029df3438dbc7e 100644 (file)
@@ -144,7 +144,7 @@ extern unsigned long mcpm_entry_vectors[MAX_NR_CLUSTERS][MAX_CPUS_PER_CLUSTER];
 
 void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr)
 {
-       unsigned long val = ptr ? virt_to_phys(ptr) : 0;
+       unsigned long val = ptr ? __pa_symbol(ptr) : 0;
        mcpm_entry_vectors[cluster][cpu] = val;
        sync_cache_w(&mcpm_entry_vectors[cluster][cpu]);
 }
@@ -299,8 +299,8 @@ void mcpm_cpu_power_down(void)
         * the kernel as if the power_up method just had deasserted reset
         * on the CPU.
         */
-       phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
-       phys_reset(virt_to_phys(mcpm_entry_point));
+       phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
+       phys_reset(__pa_symbol(mcpm_entry_point));
 
        /* should never get here */
        BUG();
@@ -388,8 +388,8 @@ static int __init nocache_trampoline(unsigned long _arg)
        __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
        __mcpm_cpu_down(cpu, cluster);
 
-       phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
-       phys_reset(virt_to_phys(mcpm_entry_point));
+       phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
+       phys_reset(__pa_symbol(mcpm_entry_point));
        BUG();
 }
 
@@ -449,7 +449,7 @@ int __init mcpm_sync_init(
        sync_cache_w(&mcpm_sync);
 
        if (power_up_setup) {
-               mcpm_power_up_setup_phys = virt_to_phys(power_up_setup);
+               mcpm_power_up_setup_phys = __pa_symbol(power_up_setup);
                sync_cache_w(&mcpm_power_up_setup_phys);
        }
 
index dd77ea25e7ca9f6ff0cdb215fd5d190fbcfa6d11..6dc6d491f88a03d02d643a59dda67c1c2b51cce1 100644 (file)
@@ -27,7 +27,7 @@ static int alpine_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        phys_addr_t addr;
 
-       addr = virt_to_phys(secondary_startup);
+       addr = __pa_symbol(secondary_startup);
 
        if (addr > (phys_addr_t)(uint32_t)(-1)) {
                pr_err("FAIL: resume address over 32bit (%pa)", &addr);
index ffbd71d45008a00639d8a496605150a3755caac0..502e3df69f696e4a740cd09def122a923386e7c9 100644 (file)
@@ -25,7 +25,7 @@
 static void write_release_addr(u32 release_phys)
 {
        u32 *virt = (u32 *) phys_to_virt(release_phys);
-       writel_relaxed(virt_to_phys(secondary_startup), virt);
+       writel_relaxed(__pa_symbol(secondary_startup), virt);
        /* Make sure this store is visible to other CPUs */
        smp_wmb();
        __cpuc_flush_dcache_area(virt, sizeof(u32));
index 9b6727ed68cd711632f6dd9fb53d9519f0d02683..f5fb10b4376f7391bc93f5c3a44edad3612c9864 100644 (file)
@@ -135,7 +135,7 @@ static int bcm63138_smp_boot_secondary(unsigned int cpu,
        }
 
        /* Write the secondary init routine to the BootLUT reset vector */
-       val = virt_to_phys(secondary_startup);
+       val = __pa_symbol(secondary_startup);
        writel_relaxed(val, bootlut_base + BOOTLUT_RESET_VECT);
 
        /* Power up the core, will jump straight to its reset vector when we
index 40dc8448445e6e2741c8c9a91ac5cd7768809bd2..12379960e982de5ea427bfee05a28d05a78af680 100644 (file)
@@ -151,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu)
         * Set the reset vector to point to the secondary_startup
         * routine
         */
-       cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));
+       cpu_set_boot_addr(cpu, __pa_symbol(secondary_startup));
 
        /* Unhalt the cpu */
        cpu_rst_cfg_set(cpu, 0);
index 3ac3a9bc663c5889a373a798883205894589d488..582886d0d02f7243d5117a59d88c356ceb4fd11a 100644 (file)
@@ -116,7 +116,7 @@ static int nsp_write_lut(unsigned int cpu)
                return -ENOMEM;
        }
 
-       secondary_startup_phy = virt_to_phys(secondary_startup);
+       secondary_startup_phy = __pa_symbol(secondary_startup);
        BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
 
        writel_relaxed(secondary_startup_phy, sku_rom_lut);
@@ -189,7 +189,7 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
         * Secondary cores will start in secondary_startup(),
         * defined in "arch/arm/kernel/head.S"
         */
-       boot_func = virt_to_phys(secondary_startup);
+       boot_func = __pa_symbol(secondary_startup);
        BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
        BUG_ON(boot_func > (phys_addr_t)U32_MAX);
 
index 93f90688db18301b081d045a1089fe14e63ac2c1..1167b0ed92c881710cd85195425439141a170a87 100644 (file)
@@ -92,7 +92,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
         * Write the secondary startup address into the SW reset address
         * vector. This is used by boot_inst.
         */
-       writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
+       writel(__pa_symbol(secondary_startup), vectors_base + SW_RESET_ADDR);
 
        iounmap(vectors_base);
 unmap_scu:
index fd6da5419b5107e99346ae12c6c9d6d381ae0be6..e81a78b125d98af5f76568bb72f701400c45c2a9 100644 (file)
@@ -41,7 +41,7 @@ static int exynos_do_idle(unsigned long mode)
        case FW_DO_IDLE_AFTR:
                if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
                        exynos_save_cp15();
-               writel_relaxed(virt_to_phys(exynos_cpu_resume_ns),
+               writel_relaxed(__pa_symbol(exynos_cpu_resume_ns),
                               sysram_ns_base_addr + 0x24);
                writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
                if (soc_is_exynos3250()) {
@@ -135,7 +135,7 @@ static int exynos_suspend(void)
                exynos_save_cp15();
 
        writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
-       writel(virt_to_phys(exynos_cpu_resume_ns),
+       writel(__pa_symbol(exynos_cpu_resume_ns),
                sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
 
        return cpu_suspend(0, exynos_cpu_suspend);
index f086bf615b2972ee640e61256cba3438c9c9ae2a..214a9cfa92e94df2c48572e3cad8d68fc574227c 100644 (file)
@@ -221,7 +221,7 @@ static void exynos_mcpm_setup_entry_point(void)
         */
        __raw_writel(0xe59f0000, ns_sram_base_addr);     /* ldr r0, [pc, #0] */
        __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx  r0 */
-       __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
+       __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8);
 }
 
 static struct syscore_ops exynos_mcpm_syscore_ops = {
index 98ffe1e62ad5d6debe7c087743d728d5730c26d3..9f4949f7ed88258e9220be2f5d2ce3b996b4af4a 100644 (file)
@@ -353,7 +353,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
                smp_rmb();
 
-               boot_addr = virt_to_phys(exynos4_secondary_startup);
+               boot_addr = __pa_symbol(exynos4_secondary_startup);
 
                ret = exynos_set_boot_addr(core_id, boot_addr);
                if (ret)
@@ -443,7 +443,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 
                mpidr = cpu_logical_map(i);
                core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-               boot_addr = virt_to_phys(exynos4_secondary_startup);
+               boot_addr = __pa_symbol(exynos4_secondary_startup);
 
                ret = exynos_set_boot_addr(core_id, boot_addr);
                if (ret)
index 487295f4a56bc07ab2412ca73538f539421234d6..1a7e5b5d08d83234ff58a6a75d6e0c777f0be9c6 100644 (file)
@@ -132,7 +132,7 @@ static void exynos_set_wakeupmask(long mask)
 
 static void exynos_cpu_set_boot_vector(long flags)
 {
-       writel_relaxed(virt_to_phys(exynos_cpu_resume),
+       writel_relaxed(__pa_symbol(exynos_cpu_resume),
                       exynos_boot_vector_addr());
        writel_relaxed(flags, exynos_boot_vector_flag());
 }
@@ -238,7 +238,7 @@ static int exynos_cpu0_enter_aftr(void)
 
 abort:
        if (cpu_online(1)) {
-               unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
+               unsigned long boot_addr = __pa_symbol(exynos_cpu_resume);
 
                /*
                 * Set the boot vector to something non-zero
@@ -330,7 +330,7 @@ cpu1_aborted:
 
 static void exynos_pre_enter_aftr(void)
 {
-       unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
+       unsigned long boot_addr = __pa_symbol(exynos_cpu_resume);
 
        (void)exynos_set_boot_addr(1, boot_addr);
 }
index 06332f6265652e16dbd5503dcce3f45425e4fefb..97765be2cc12018cc131a05d8499f3d9f6753b9d 100644 (file)
@@ -344,7 +344,7 @@ static void exynos_pm_prepare(void)
        exynos_pm_enter_sleep_mode();
 
        /* ensure at least INFORM0 has the resume address */
-       pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+       pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
 }
 
 static void exynos3250_pm_prepare(void)
@@ -361,7 +361,7 @@ static void exynos3250_pm_prepare(void)
        exynos_pm_enter_sleep_mode();
 
        /* ensure at least INFORM0 has the resume address */
-       pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+       pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
 }
 
 static void exynos5420_pm_prepare(void)
@@ -386,7 +386,7 @@ static void exynos5420_pm_prepare(void)
 
        /* ensure at least INFORM0 has the resume address */
        if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
-               pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
+               pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
 
        tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
        tmp &= ~EXYNOS5_USE_RETENTION;
index 4b653a8cb75ce82f2a5ff163bec263591c1a2983..a6c117622d67619ae4eccc7f720b785878935585 100644 (file)
@@ -327,7 +327,7 @@ static int __init hip04_smp_init(void)
         */
        writel_relaxed(hip04_boot_method[0], relocation);
        writel_relaxed(0xa5a5a5a5, relocation + 4);     /* magic number */
-       writel_relaxed(virt_to_phys(secondary_startup), relocation + 8);
+       writel_relaxed(__pa_symbol(secondary_startup), relocation + 8);
        writel_relaxed(0, relocation + 12);
        iounmap(relocation);
 
index e1d67648d5d02ed8d96b3ce6314691459ea2e0fe..91bb02dec20f15a63f438f3ab65fe5dc62a40af7 100644 (file)
@@ -28,7 +28,7 @@ void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
        cpu = cpu_logical_map(cpu);
        if (!cpu || !ctrl_base)
                return;
-       writel_relaxed(virt_to_phys(jump_addr), ctrl_base + ((cpu - 1) << 2));
+       writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2));
 }
 
 int hi3xxx_get_cpu_jump(int cpu)
@@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        phys_addr_t jumpaddr;
 
-       jumpaddr = virt_to_phys(secondary_startup);
+       jumpaddr = __pa_symbol(secondary_startup);
        hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
        hix5hd2_set_cpu(cpu, true);
        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
@@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
        struct device_node *node;
 
 
-       jumpaddr = virt_to_phys(secondary_startup);
+       jumpaddr = __pa_symbol(secondary_startup);
        hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
 
        node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
index 711dbbd5baddaac8953d2d90ac1232776efd9f16..c2d1b329fba13da1511af56d0305a01608d55511 100644 (file)
@@ -117,7 +117,7 @@ static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
        dcfg_base = of_iomap(np, 0);
        BUG_ON(!dcfg_base);
 
-       paddr = virt_to_phys(secondary_startup);
+       paddr = __pa_symbol(secondary_startup);
        writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
 
        iounmap(dcfg_base);
index 1515e498d348c6ea1636149e35665b4fd2e2b239..e61b1d1027e12d5c5284f74f4480dbba70b47b05 100644 (file)
@@ -499,7 +499,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
        memset(suspend_ocram_base, 0, sizeof(*pm_info));
        pm_info = suspend_ocram_base;
        pm_info->pbase = ocram_pbase;
-       pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
+       pm_info->resume_addr = __pa_symbol(v7_cpu_resume);
        pm_info->pm_info_size = sizeof(*pm_info);
 
        /*
index 70b083fe934a8f7763cd4cfc4dca0fea73f66d3d..495d85d0fe7ef64daf560a9ef53914b4f82fde08 100644 (file)
@@ -99,7 +99,7 @@ void imx_enable_cpu(int cpu, bool enable)
 void imx_set_cpu_jump(int cpu, void *jump_addr)
 {
        cpu = cpu_logical_map(cpu);
-       writel_relaxed(virt_to_phys(jump_addr),
+       writel_relaxed(__pa_symbol(jump_addr),
                       src_base + SRC_GPR1 + cpu * 8);
 }
 
index b821e34474b6fc5a950e1739365b2442cac0a2c5..726eb69bb655decfbd7a817bdddcb8946c761dc4 100644 (file)
@@ -122,7 +122,7 @@ static void __init __mtk_smp_prepare_cpus(unsigned int max_cpus, int trustzone)
         * write the address of slave startup address into the system-wide
         * jump register
         */
-       writel_relaxed(virt_to_phys(secondary_startup_arm),
+       writel_relaxed(__pa_symbol(secondary_startup_arm),
                        mtk_smp_base + mtk_smp_info->jump_reg);
 }
 
index 2990c5269b18586be26dbf3405f0aa696d4d0973..c487be61d6d8c9f00ceb6e131f9ab364d4e56fdd 100644 (file)
@@ -110,7 +110,7 @@ static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr)
 {
        phys_addr_t resume_pc;
 
-       resume_pc = virt_to_phys(armada_370_xp_cpu_resume);
+       resume_pc = __pa_symbol(armada_370_xp_cpu_resume);
 
        /*
         * The bootloader expects the first two words to be a magic
index f39bd51bce18b85784e3269a61ddf82a7119d3f8..27a78c80e5b17352aafc4924d04694217bfa5c15 100644 (file)
@@ -112,7 +112,7 @@ static const struct of_device_id of_pmsu_table[] = {
 
 void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
 {
-       writel(virt_to_phys(boot_addr), pmsu_mp_base +
+       writel(__pa_symbol(boot_addr), pmsu_mp_base +
                PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
 }
 
index 76cbc82a7407e48d03317db872ddad26b8e24de4..04d9ebe6a90a0ccfe427fae9922ef9198bab3a37 100644 (file)
@@ -153,7 +153,7 @@ void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
        if (of_machine_is_compatible("marvell,armada375"))
                mvebu_armada375_smp_wa_init();
 
-       writel(virt_to_phys(boot_addr), system_controller_base +
+       writel(__pa_symbol(boot_addr), system_controller_base +
               mvebu_sc->resume_boot_addr);
 }
 #endif
index 1662071bb2cc8361023aa3a066ab963bbd411540..bd8089ff929f61847bf4fc49d4efe0c6fe9c6136 100644 (file)
@@ -315,15 +315,15 @@ void omap3_save_scratchpad_contents(void)
        scratchpad_contents.boot_config_ptr = 0x0;
        if (cpu_is_omap3630())
                scratchpad_contents.public_restore_ptr =
-                       virt_to_phys(omap3_restore_3630);
+                       __pa_symbol(omap3_restore_3630);
        else if (omap_rev() != OMAP3430_REV_ES3_0 &&
                                        omap_rev() != OMAP3430_REV_ES3_1 &&
                                        omap_rev() != OMAP3430_REV_ES3_1_2)
                scratchpad_contents.public_restore_ptr =
-                       virt_to_phys(omap3_restore);
+                       __pa_symbol(omap3_restore);
        else
                scratchpad_contents.public_restore_ptr =
-                       virt_to_phys(omap3_restore_es3);
+                       __pa_symbol(omap3_restore_es3);
 
        if (omap_type() == OMAP2_DEVICE_TYPE_GP)
                scratchpad_contents.secure_ram_restore_ptr = 0x0;
@@ -395,7 +395,7 @@ void omap3_save_scratchpad_contents(void)
        sdrc_block_contents.flags = 0x0;
        sdrc_block_contents.block_size = 0x0;
 
-       arm_context_addr = virt_to_phys(omap3_arm_context);
+       arm_context_addr = __pa_symbol(omap3_arm_context);
 
        /* Copy all the contents to the scratchpad location */
        scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
index 7d62ad48c7c9dd1dfb290cdcf5d61479b081d7a9..113ab2dd2ee91ccf9c238813bd6c4d7561ff7d97 100644 (file)
@@ -273,7 +273,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
        cpu_clear_prev_logic_pwrst(cpu);
        pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
        pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
-       set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
+       set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.resume));
        omap_pm_ops.scu_prepare(cpu, power_state);
        l2x0_pwrst_prepare(cpu, save_state);
 
@@ -325,7 +325,7 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 
        pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
        pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
-       set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
+       set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.hotplug_restart));
        omap_pm_ops.scu_prepare(cpu, power_state);
 
        /*
@@ -467,13 +467,13 @@ void __init omap4_mpuss_early_init(void)
        sar_base = omap4_get_sar_ram_base();
 
        if (cpu_is_omap443x())
-               startup_pa = virt_to_phys(omap4_secondary_startup);
+               startup_pa = __pa_symbol(omap4_secondary_startup);
        else if (cpu_is_omap446x())
-               startup_pa = virt_to_phys(omap4460_secondary_startup);
+               startup_pa = __pa_symbol(omap4460_secondary_startup);
        else if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
-               startup_pa = virt_to_phys(omap5_secondary_hyp_startup);
+               startup_pa = __pa_symbol(omap5_secondary_hyp_startup);
        else
-               startup_pa = virt_to_phys(omap5_secondary_startup);
+               startup_pa = __pa_symbol(omap5_secondary_startup);
 
        if (cpu_is_omap44xx())
                writel_relaxed(startup_pa, sar_base +
index b4de3da6dffa5e0593dad0ca305895fc9c341e6a..003353b0b7944d9363fb6446e683314823cd82f9 100644 (file)
@@ -316,9 +316,9 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
         * A barrier is added to ensure that write buffer is drained
         */
        if (omap_secure_apis_support())
-               omap_auxcoreboot_addr(virt_to_phys(cfg.startup_addr));
+               omap_auxcoreboot_addr(__pa_symbol(cfg.startup_addr));
        else
-               writel_relaxed(virt_to_phys(cfg.startup_addr),
+               writel_relaxed(__pa_symbol(cfg.startup_addr),
                               base + OMAP_AUX_CORE_BOOT_1);
 }
 
index 0875b99add1870dab41b3b6b029a9a1ef61f708d..75ef5d4be554ce9f8564f347e52da1e6766bf5ac 100644 (file)
@@ -65,7 +65,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
         * waiting for. This would wake up the secondary core from WFE
         */
 #define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2bc
-       __raw_writel(virt_to_phys(sirfsoc_secondary_startup),
+       __raw_writel(__pa_symbol(sirfsoc_secondary_startup),
                clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
 
 #define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x2b8
index 83e94c95e314414a6d85e145c9e204f186f9cc75..b0bcf1ff02dd058687a00f173090bc3183a22b63 100644 (file)
@@ -54,7 +54,7 @@ static void sirfsoc_set_sleep_mode(u32 mode)
 
 static int sirfsoc_pre_suspend_power_off(void)
 {
-       u32 wakeup_entry = virt_to_phys(cpu_resume);
+       u32 wakeup_entry = __pa_symbol(cpu_resume);
 
        sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base +
                SIRFSOC_PWRC_SCRATCH_PAD1);
index 9c308de158c6fa2c0cf07a331c68292f8d4788b6..29630061e7007f8365be536d836b617ebd57ae01 100644 (file)
@@ -249,7 +249,7 @@ static int palmz72_pm_suspend(void)
        store_ptr = *PALMZ72_SAVE_DWORD;
 
        /* Setting PSPR to a proper value */
-       PSPR = virt_to_phys(&palmz72_resume_info);
+       PSPR = __pa_symbol(&palmz72_resume_info);
 
        return 0;
 }
index c725baf119e1135e0b8f796c18e3684dc5b74862..ba431fad5c47fd4456871083c5f81092da6814da 100644 (file)
@@ -85,7 +85,7 @@ static void pxa25x_cpu_pm_enter(suspend_state_t state)
 static int pxa25x_cpu_pm_prepare(void)
 {
        /* set resume return address */
-       PSPR = virt_to_phys(cpu_resume);
+       PSPR = __pa_symbol(cpu_resume);
        return 0;
 }
 
index c0185c5c5a08b4bcc03ff110909bf7dca46c4732..9b69be4e9fe33156837fb7d520476d47cd1e23d1 100644 (file)
@@ -168,7 +168,7 @@ static int pxa27x_cpu_pm_valid(suspend_state_t state)
 static int pxa27x_cpu_pm_prepare(void)
 {
        /* set resume return address */
-       PSPR = virt_to_phys(cpu_resume);
+       PSPR = __pa_symbol(cpu_resume);
        return 0;
 }
 
index 87acc96388c7347949c685e55a5e3b2832a2daf2..0cc9f124c9ac3769c73d52973a34c959eb56ad0a 100644 (file)
@@ -123,7 +123,7 @@ static void pxa3xx_cpu_pm_suspend(void)
        PSPR = 0x5c014000;
 
        /* overwrite with the resume address */
-       *p = virt_to_phys(cpu_resume);
+       *p = __pa_symbol(cpu_resume);
 
        cpu_suspend(0, pxa3xx_finish_suspend);
 
index 70ca99eb52c6ce8d537d0148bd71bc8bbf04282e..c242423bf8db5a5e64d9818f01c42e0b23b699fd 100644 (file)
@@ -76,7 +76,7 @@ static void __init realview_smp_prepare_cpus(unsigned int max_cpus)
        }
        /* Put the boot address in this magic register */
        regmap_write(map, REALVIEW_SYS_FLAGSSET_OFFSET,
-                    virt_to_phys(versatile_secondary_startup));
+                    __pa_symbol(versatile_secondary_startup));
 }
 
 static const struct smp_operations realview_dt_smp_ops __initconst = {
index 4d827a069d49c7a9a5dcae3ce9b2f81d807b3578..3abafdbdd7f4a24d7afed4aa53f196aab838ac92 100644 (file)
@@ -156,7 +156,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
                 */
                mdelay(1); /* ensure the cpus other than cpu0 to startup */
 
-               writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
+               writel(__pa_symbol(secondary_startup), sram_base_addr + 8);
                writel(0xDEADBEAF, sram_base_addr + 4);
                dsb_sev();
        }
@@ -195,7 +195,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
        }
 
        /* set the boot function for the sram code */
-       rockchip_boot_fn = virt_to_phys(secondary_startup);
+       rockchip_boot_fn = __pa_symbol(secondary_startup);
 
        /* copy the trampoline to sram, that runs during startup of the core */
        memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
index bee8c80519299269cde5ba9c852243d6e5a47b05..0592534e0b88c47c203686faafc8ba5650cd7d54 100644 (file)
@@ -62,7 +62,7 @@ static inline u32 rk3288_l2_config(void)
 static void rk3288_config_bootdata(void)
 {
        rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
-       rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume);
+       rkpm_bootdata_cpu_code = __pa_symbol(cpu_resume);
 
        rkpm_bootdata_l2ctlr_f  = 1;
        rkpm_bootdata_l2ctlr = rk3288_l2_config();
index 895aca225952d62f137aae798f603fa2006fc60e..f5b5c49b56ac0b561576ac64acef9c1846fa6020 100644 (file)
@@ -484,7 +484,7 @@ static int jive_pm_suspend(void)
         * correct address to resume from. */
 
        __raw_writel(0x2BED, S3C2412_INFORM0);
-       __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
+       __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
 
        return 0;
 }
index 20e481d8a33a60ff10ab3a3962bf78d5b0241c0c..a4588daeddb0f6ab94b85f837c2ccdb0791c5816 100644 (file)
@@ -45,7 +45,7 @@ static void s3c2410_pm_prepare(void)
 {
        /* ensure at least GSTATUS3 has the resume address */
 
-       __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
+       __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2410_GSTATUS3);
 
        S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
        S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
index c0e328e37bd63927fd48b6cc415fef6bc86bdd44..b5bbf0d5985c818947e9b7a44c2a966e0c6c995b 100644 (file)
@@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void)
         * correct address to resume from.
         */
        __raw_writel(0x2BED, S3C2412_INFORM0);
-       __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
+       __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
 }
 
 static int s3c2416_pm_add(struct device *dev, struct subsys_interface *sif)
index 59d91b83b03d7d801a10cca757d2e9fada4be4bc..945a9d1e1a717136f49822ce94eba1f2e1309cec 100644 (file)
@@ -304,7 +304,7 @@ static void s3c64xx_pm_prepare(void)
                              wake_irqs, ARRAY_SIZE(wake_irqs));
 
        /* store address of resume. */
-       __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
+       __raw_writel(__pa_symbol(s3c_cpu_resume), S3C64XX_INFORM0);
 
        /* ensure previous wakeup state is cleared before sleeping */
        __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
index 21b4b13c5ab787f0707c00c5125b285f73dcdd60..2d5f08015e34862e356daeadaa284aa0012dab05 100644 (file)
@@ -69,7 +69,7 @@ static void s5pv210_pm_prepare(void)
        __raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK);
 
        /* ensure at least INFORM0 has the resume address */
-       __raw_writel(virt_to_phys(s5pv210_cpu_resume), S5P_INFORM0);
+       __raw_writel(__pa_symbol(s5pv210_cpu_resume), S5P_INFORM0);
 
        tmp = __raw_readl(S5P_SLEEP_CFG);
        tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
index 34853d5dfda28b9e5d5f79205c30c1a71facf5d8..9a7079f565bd394c4ae1436e8a2b14cd52acba34 100644 (file)
@@ -73,7 +73,7 @@ static int sa11x0_pm_enter(suspend_state_t state)
        RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
 
        /* set resume return address */
-       PSPR = virt_to_phys(cpu_resume);
+       PSPR = __pa_symbol(cpu_resume);
 
        /* go zzz */
        cpu_suspend(0, sa1100_finish_suspend);
index 0c6bb458b7a4512870db5e8c28517bd8cf19ddad..71729b8d1900ff04844052b48ee50d954c2c0cb3 100644 (file)
@@ -171,7 +171,7 @@ static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit))
 static void __init shmobile_smp_apmu_setup_boot(void)
 {
        /* install boot code shared by all CPUs */
-       shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
+       shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
 }
 
 void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
@@ -185,7 +185,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
 int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        /* For this particular CPU register boot vector */
-       shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
+       shmobile_smp_hook(cpu, __pa_symbol(secondary_startup), 0);
 
        return apmu_wrap(cpu, apmu_power_on);
 }
@@ -301,7 +301,7 @@ int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
 #if defined(CONFIG_SUSPEND)
 static int shmobile_smp_apmu_do_suspend(unsigned long cpu)
 {
-       shmobile_smp_hook(cpu, virt_to_phys(cpu_resume), 0);
+       shmobile_smp_hook(cpu, __pa_symbol(cpu_resume), 0);
        shmobile_smp_apmu_cpu_shutdown(cpu);
        cpu_do_idle(); /* WFI selects Core Standby */
        return 1;
index d1ecaf37d1422d214d56177f42da9af9529454fb..f1a1efde4beb19c2b520188aa9dac6fed428c224 100644 (file)
@@ -24,7 +24,7 @@ static void __iomem *shmobile_scu_base;
 static int shmobile_scu_cpu_prepare(unsigned int cpu)
 {
        /* For this particular CPU register SCU SMP boot vector */
-       shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu),
+       shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_scu),
                          shmobile_scu_base_phys);
        return 0;
 }
@@ -33,7 +33,7 @@ void __init shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys,
                                          unsigned int max_cpus)
 {
        /* install boot code shared by all CPUs */
-       shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
+       shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
 
        /* enable SCU and cache coherency on booting CPU */
        shmobile_scu_base_phys = scu_base_phys;
index 07945748b57141f2c216d729a6f895d36227be7a..0ee76772b50743f099637e18b4859d5736644b23 100644 (file)
@@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
                memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
 
-               writel(virt_to_phys(secondary_startup),
+               writel(__pa_symbol(secondary_startup),
                       sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
 
                flush_cache_all();
@@ -63,7 +63,7 @@ static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle
                       SOCFPGA_A10_RSTMGR_MODMPURST);
                memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
 
-               writel(virt_to_phys(secondary_startup),
+               writel(__pa_symbol(secondary_startup),
                       sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff));
 
                flush_cache_all();
index 8d1e2d55178684cd96c49828eb5390e24286ff7c..39038a03836acb8f3288488f063a99d5ef0f814c 100644 (file)
@@ -117,7 +117,7 @@ static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus)
         * (presently it is in SRAM). The BootMonitor waits until it receives a
         * soft interrupt, and then the secondary CPU branches to this address.
         */
-       __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
+       __raw_writel(__pa_symbol(spear13xx_secondary_startup), SYS_LOCATION);
 }
 
 const struct smp_operations spear13xx_smp_ops __initconst = {
index ea5a2277ee46b4132edfea00fd6e6c07a91be630..231f19e174365229f034c9897b6e61984b92d84c 100644 (file)
@@ -103,7 +103,7 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
        u32 __iomem *cpu_strt_ptr;
        u32 release_phys;
        int cpu;
-       unsigned long entry_pa = virt_to_phys(sti_secondary_startup);
+       unsigned long entry_pa = __pa_symbol(sti_secondary_startup);
 
        np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
 
index 6642267812c96fc3f2b0e1f694b5bf3667dd20ed..8fb5088464db3dc932d367ff8272e303d1401b48 100644 (file)
@@ -80,7 +80,7 @@ static int sun6i_smp_boot_secondary(unsigned int cpu,
        spin_lock(&cpu_lock);
 
        /* Set CPU boot address */
-       writel(virt_to_phys(secondary_startup),
+       writel(__pa_symbol(secondary_startup),
               cpucfg_membase + CPUCFG_PRIVATE0_REG);
 
        /* Assert the CPU core in reset */
@@ -162,7 +162,7 @@ static int sun8i_smp_boot_secondary(unsigned int cpu,
        spin_lock(&cpu_lock);
 
        /* Set CPU boot address */
-       writel(virt_to_phys(secondary_startup),
+       writel(__pa_symbol(secondary_startup),
               cpucfg_membase + CPUCFG_PRIVATE0_REG);
 
        /* Assert the CPU core in reset */
index 98c62a4a8623df12f3e9a4d2fdd6118af7befd75..2f0c6c050fed742de088c13b74e70f1537ca70ae 100644 (file)
@@ -5,7 +5,7 @@
 
 static int tango_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-       tango_set_aux_boot_addr(virt_to_phys(secondary_startup));
+       tango_set_aux_boot_addr(__pa_symbol(secondary_startup));
        tango_start_aux_core(cpu);
        return 0;
 }
index b05c6d6f99d072b5ef006004475776d14513745c..406c0814eb6e6195bf61990d73febbec8109bdd7 100644 (file)
@@ -5,7 +5,7 @@
 
 static int tango_pm_powerdown(unsigned long arg)
 {
-       tango_suspend(virt_to_phys(cpu_resume));
+       tango_suspend(__pa_symbol(cpu_resume));
 
        return -EIO; /* tango_suspend has failed */
 }
index 6fd9db54887eeebd400e425a216bce2cce9399b2..dc558892753c69c3c12829d27f03282f9ae1e49b 100644 (file)
@@ -94,14 +94,14 @@ void __init tegra_cpu_reset_handler_init(void)
        __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
                *((u32 *)cpu_possible_mask);
        __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
-               virt_to_phys((void *)secondary_startup);
+               __pa_symbol((void *)secondary_startup);
 #endif
 
 #ifdef CONFIG_PM_SLEEP
        __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
                TEGRA_IRAM_LPx_RESUME_AREA;
        __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
-               virt_to_phys((void *)tegra_resume);
+               __pa_symbol((void *)tegra_resume);
 #endif
 
        tegra_cpu_reset_handler_enable();
index 8f2f615ff9589d8c400ba7c59e43cefa825c6a0f..8c8f2638906704219b54767afb86252f012cb055 100644 (file)
@@ -54,7 +54,7 @@ static void wakeup_secondary(void)
         * backup ram register at offset 0x1FF0, which is what boot rom code
         * is waiting for. This will wake up the secondary core from WFE.
         */
-       writel(virt_to_phys(secondary_startup),
+       writel(__pa_symbol(secondary_startup),
               backupram + UX500_CPU1_JUMPADDR_OFFSET);
        writel(0xA1FEED01,
               backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
index 5cedcf572104bcdf82b1b75ab61f89f4cdf19651..ee2a0faafaa19309ca660543b71819cee82fc72c 100644 (file)
@@ -166,7 +166,7 @@ static int __init dcscb_init(void)
         * Future entries into the kernel can now go
         * through the cluster entry vectors.
         */
-       vexpress_flags_set(virt_to_phys(mcpm_entry_point));
+       vexpress_flags_set(__pa_symbol(mcpm_entry_point));
 
        return 0;
 }
index 98e29dee91e865f7c76408c845e99ff2af14ca92..742499bac6d09f27eaed8580e2df4b06e63a3252 100644 (file)
@@ -79,7 +79,7 @@ static void __init vexpress_smp_dt_prepare_cpus(unsigned int max_cpus)
         * until it receives a soft interrupt, and then the
         * secondary CPU branches to this address.
         */
-       vexpress_flags_set(virt_to_phys(versatile_secondary_startup));
+       vexpress_flags_set(__pa_symbol(versatile_secondary_startup));
 }
 
 const struct smp_operations vexpress_smp_dt_ops __initconst = {
index 1aa4ccece69f97cb06dacb98f146d91bde6560d2..9b5f3c427086cd28f2e3781df87b560de7161167 100644 (file)
@@ -54,7 +54,7 @@ static int tc2_pm_cpu_powerup(unsigned int cpu, unsigned int cluster)
        if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
                return -EINVAL;
        ve_spc_set_resume_addr(cluster, cpu,
-                              virt_to_phys(mcpm_entry_point));
+                              __pa_symbol(mcpm_entry_point));
        ve_spc_cpu_wakeup_irq(cluster, cpu, true);
        return 0;
 }
@@ -159,7 +159,7 @@ static int tc2_pm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
 
 static void tc2_pm_cpu_suspend_prepare(unsigned int cpu, unsigned int cluster)
 {
-       ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
+       ve_spc_set_resume_addr(cluster, cpu, __pa_symbol(mcpm_entry_point));
 }
 
 static void tc2_pm_cpu_is_up(unsigned int cpu, unsigned int cluster)
index 0297f92084e048234ed557443983735079d7ac2a..afb9a82dedc314b9b63f3bb7f0cfc8c81c8a6697 100644 (file)
@@ -76,7 +76,7 @@ void __init zx_smp_prepare_cpus(unsigned int max_cpus)
         * until it receives a soft interrupt, and then the
         * secondary CPU branches to this address.
         */
-       __raw_writel(virt_to_phys(zx_secondary_startup),
+       __raw_writel(__pa_symbol(zx_secondary_startup),
                     aonsysctrl_base + AON_SYS_CTRL_RESERVED1);
 
        iounmap(aonsysctrl_base);
@@ -94,7 +94,7 @@ void __init zx_smp_prepare_cpus(unsigned int max_cpus)
 
        /* Map the first 4 KB IRAM for suspend usage */
        sys_iram = __arm_ioremap_exec(ZX_IRAM_BASE, PAGE_SIZE, false);
-       zx_secondary_startup_pa = virt_to_phys(zx_secondary_startup);
+       zx_secondary_startup_pa = __pa_symbol(zx_secondary_startup);
        fncpy(sys_iram, &zx_resume_jump, zx_suspend_iram_sz);
 }
 
index 7cd9865bdeb7bed3c46c575fb5fea5a022ac251b..caa6d5fe9078326ea65d29d8d6359e1a82306969 100644 (file)
@@ -89,7 +89,7 @@ EXPORT_SYMBOL(zynq_cpun_start);
 
 static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-       return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
+       return zynq_cpun_start(__pa_symbol(secondary_startup), cpu);
 }
 
 /*