powerpc/perf: Initialize power10 PMU registers in cpu setup routine

Initialize Monitor Mode Control Register 3 (MMCR3)
SPR which is new in power10. For PowerISA v3.1, BHRB disable
is controlled via Monitor Mode Control Register A (MMCRA) bit,
namely "BHRB Recording Disable (BHRBRD)". This patch also initializes
MMCRA BHRBRD to disable BHRB feature at boot for power10.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: Jordan Niethe <jniethe5@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1595489557-2047-1-git-send-email-atrajeev@linux.vnet.ibm.com

diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index 86527d19348cbf1c2511abcb98cc71e38fa71c78..704e8b9501eee84ade894358b57986268c2ac17f 100644 (file)
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -94,13 +94,15 @@ _GLOBAL(__restore_cpu_power8)
 _GLOBAL(__setup_cpu_power10)
        mflr    r11
        bl      __init_FSCR_power10
+       bl      __init_PMU
+       bl      __init_PMU_ISA31
        b       1f
 
 _GLOBAL(__setup_cpu_power9)
        mflr    r11
        bl      __init_FSCR_power9
-1:     bl      __init_PMU
-       bl      __init_hvmode_206
+       bl      __init_PMU
+1:     bl      __init_hvmode_206
        mtlr    r11
        beqlr
        li      r0,0
@@ -124,13 +126,15 @@ _GLOBAL(__setup_cpu_power9)
 _GLOBAL(__restore_cpu_power10)
        mflr    r11
        bl      __init_FSCR_power10
+       bl      __init_PMU
+       bl      __init_PMU_ISA31
        b       1f
 
 _GLOBAL(__restore_cpu_power9)
        mflr    r11
        bl      __init_FSCR_power9
-1:     bl      __init_PMU
-       mfmsr   r3
+       bl      __init_PMU
+1:     mfmsr   r3
        rldicl. r0,r3,4,63
        mtlr    r11
        beqlr
@@ -239,3 +243,10 @@ __init_PMU_ISA207:
        li      r5,0
        mtspr   SPRN_MMCRS,r5
        blr
+
+__init_PMU_ISA31:
+       li      r5,0
+       mtspr   SPRN_MMCR3,r5
+       LOAD_REG_IMMEDIATE(r5, MMCRA_BHRB_DISABLE)
+       mtspr   SPRN_MMCRA,r5
+       blr