drm/i915/psr: Use WA to force HW tracking to exit PSR2

This WA also works fine for PSR2, triggering a selective update when
possible.

Acked-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181003205031.32474-4-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 1c4beaca1c0f40055fdbedfdbe0aee7f2dbfbc86..423cdf84059cee9bd4dc653cf9be6cbc6fd2fc84 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1027,20 +1027,16 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 
        /* By definition flush = invalidate + flush */
        if (frontbuffer_bits) {
-               if (dev_priv->psr.psr2_enabled) {
-                       intel_psr_exit(dev_priv);
-               } else {
-                       /*
-                        * Display WA #0884: all
-                        * This documented WA for bxt can be safely applied
-                        * broadly so we can force HW tracking to exit PSR
-                        * instead of disabling and re-enabling.
-                        * Workaround tells us to write 0 to CUR_SURFLIVE_A,
-                        * but it makes more sense write to the current active
-                        * pipe.
-                        */
-                       I915_WRITE(CURSURFLIVE(pipe), 0);
-               }
+               /*
+                * Display WA #0884: all
+                * This documented WA for bxt can be safely applied
+                * broadly so we can force HW tracking to exit PSR
+                * instead of disabling and re-enabling.
+                * Workaround tells us to write 0 to CUR_SURFLIVE_A,
+                * but it makes more sense write to the current active
+                * pipe.
+                */
+               I915_WRITE(CURSURFLIVE(pipe), 0);
        }
 
        if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)