F: hw/ppc/pnv*
F: hw/intc/pnv*
F: hw/intc/xics_pnv.c
+F: hw/pci-host/pnv*
F: include/hw/ppc/pnv*
+F: include/hw/pci-host/pnv*
F: pc-bios/skiboot.lid
F: tests/qtest/pnv*
S: Supported
F: docs/qdev-device-use.txt
F: hw/core/qdev*
+F: hw/core/bus.c
+F: hw/core/sysbus.c
F: include/hw/qdev*
F: include/monitor/qdev.h
F: include/qom/
{
trace_acpi_pci_unplug(PCI_SLOT(PCI_DEVICE(dev)->devfn),
acpi_pcihp_get_bsel(pci_get_bus(PCI_DEVICE(dev))));
- object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+ qdev_unrealize(dev);
}
void acpi_pcihp_device_unplug_request_cb(HotplugHandler *hotplug_dev,
qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm)
{
+ PCIDevice *pci_dev;
DeviceState *dev;
PIIX4PMState *s;
- dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
+ pci_dev = pci_new(devfn, TYPE_PIIX4_PM);
+ dev = DEVICE(pci_dev);
qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
if (piix4_pm) {
*piix4_pm = dev;
s->use_acpi_pci_hotplug = false;
}
- qdev_init_nofail(dev);
+ pci_realize_and_unref(pci_dev, bus, &error_fatal);
return s->smb.smbus;
}
PCIBus *b;
int i;
- dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_TYPHOON_PCI_HOST_BRIDGE);
s = TYPHOON_PCI_HOST_BRIDGE(dev);
phb = PCI_HOST_BRIDGE(dev);
&s->pchip.reg_mem, &s->pchip.reg_io,
0, 64, TYPE_PCI_BUS);
phb->bus = b;
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Host memory as seen from the PCI side, via the IOMMU. */
memory_region_init_iommu(&s->pchip.iommu, sizeof(s->pchip.iommu),
{
AwA10State *s = AW_A10(obj);
- object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
- ARM_CPU_TYPE_NAME("cortex-a8"),
- &error_abort, NULL);
+ object_initialize_child(obj, "cpu", &s->cpu,
+ ARM_CPU_TYPE_NAME("cortex-a8"));
- sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
- TYPE_AW_A10_PIC);
+ object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);
- sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
- TYPE_AW_A10_PIT);
+ object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
- sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_EMAC);
+ object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
- sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata),
- TYPE_ALLWINNER_AHCI);
+ object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
if (machine_usb(current_machine)) {
int i;
for (i = 0; i < AW_A10_NUM_USB; i++) {
- sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
- sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
- sysbus_init_child_obj(obj, "ohci[*]", OBJECT(&s->ohci[i]),
- sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI);
+ object_initialize_child(obj, "ehci[*]", &s->ehci[i],
+ TYPE_PLATFORM_EHCI);
+ object_initialize_child(obj, "ohci[*]", &s->ohci[i],
+ TYPE_SYSBUS_OHCI);
}
}
- sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
- TYPE_AW_SDHOST_SUN4I);
+ object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
- sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
- TYPE_AW_RTC_SUN4I);
+ object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);
}
static void aw_a10_realize(DeviceState *dev, Error **errp)
SysBusDevice *sysbusdev;
Error *err = NULL;
- object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
+ qdev_realize(DEVICE(&s->cpu), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->intc), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
- object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->timer), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
}
- object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->emac), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
- object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sata), &err);
if (err) {
error_propagate(errp, err);
return;
object_property_set_bool(OBJECT(&s->ehci[i]), true,
"companion-enable", &error_fatal);
- object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized",
- &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
AW_A10_EHCI_BASE + i * 0x8000);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
object_property_set_str(OBJECT(&s->ohci[i]), bus, "masterbus",
&error_fatal);
- object_property_set_bool(OBJECT(&s->ohci[i]), true, "realized",
- &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
AW_A10_OHCI_BASE + i * 0x8000);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
}
/* SD/MMC */
- qdev_init_nofail(DEVICE(&s->mmc0));
+ sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
"sd-bus");
/* RTC */
- qdev_init_nofail(DEVICE(&s->rtc));
+ sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
}
s->memmap = allwinner_h3_memmap;
for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
- object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]),
- ARM_CPU_TYPE_NAME("cortex-a7"),
- &error_abort, NULL);
+ object_initialize_child(obj, "cpu[*]", &s->cpus[i],
+ ARM_CPU_TYPE_NAME("cortex-a7"));
}
- sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
- TYPE_ARM_GIC);
+ object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
- sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
- TYPE_AW_A10_PIT);
+ object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
"clk0-freq");
object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
"clk1-freq");
- sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
- TYPE_AW_H3_CCU);
+ object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_H3_CCU);
- sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
- TYPE_AW_H3_SYSCTRL);
+ object_initialize_child(obj, "sysctrl", &s->sysctrl, TYPE_AW_H3_SYSCTRL);
- sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
- TYPE_AW_CPUCFG);
+ object_initialize_child(obj, "cpucfg", &s->cpucfg, TYPE_AW_CPUCFG);
- sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid),
- TYPE_AW_SID);
+ object_initialize_child(obj, "sid", &s->sid, TYPE_AW_SID);
object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
"identifier");
- sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
- TYPE_AW_SDHOST_SUN5I);
+ object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN5I);
- sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
- TYPE_AW_SUN8I_EMAC);
+ object_initialize_child(obj, "emac", &s->emac, TYPE_AW_SUN8I_EMAC);
- sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),
- TYPE_AW_H3_DRAMC);
+ object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_H3_DRAMC);
object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
"ram-addr");
object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
"ram-size");
- sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
- TYPE_AW_RTC_SUN6I);
+ object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
}
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
/* Mark realized */
- qdev_init_nofail(DEVICE(&s->cpus[i]));
+ qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal);
}
/* Generic Interrupt Controller */
qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
- qdev_init_nofail(DEVICE(&s->gic));
+ sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
}
/* Timer */
- qdev_init_nofail(DEVICE(&s->timer));
+ sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
&s->sram_c);
/* Clock Control Unit */
- qdev_init_nofail(DEVICE(&s->ccu));
+ sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
/* System Control */
- qdev_init_nofail(DEVICE(&s->sysctrl));
+ sysbus_realize(SYS_BUS_DEVICE(&s->sysctrl), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
/* CPU Configuration */
- qdev_init_nofail(DEVICE(&s->cpucfg));
+ sysbus_realize(SYS_BUS_DEVICE(&s->cpucfg), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
/* Security Identifier */
- qdev_init_nofail(DEVICE(&s->sid));
+ sysbus_realize(SYS_BUS_DEVICE(&s->sid), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
/* SD/MMC */
- qdev_init_nofail(DEVICE(&s->mmc0));
+ sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
}
- qdev_init_nofail(DEVICE(&s->emac));
+ sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
/* DRAMC */
- qdev_init_nofail(DEVICE(&s->dramc));
+ sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
/* RTC */
- qdev_init_nofail(DEVICE(&s->rtc));
+ sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
/* Unimplemented devices */
char *name;
name = g_strdup_printf("cluster%d", i);
- object_initialize_child(obj, name, &s->cluster[i],
- sizeof(s->cluster[i]), TYPE_CPU_CLUSTER,
- &error_abort, NULL);
+ object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER);
qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i);
g_free(name);
name = g_strdup_printf("armv7m%d", i);
- sysbus_init_child_obj(OBJECT(&s->cluster[i]), name,
- &s->armv7m[i], sizeof(s->armv7m), TYPE_ARMV7M);
+ object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i],
+ TYPE_ARMV7M);
qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type",
ARM_CPU_TYPE_NAME("cortex-m33"));
g_free(name);
}
}
- sysbus_init_child_obj(obj, "secctl", &s->secctl, sizeof(s->secctl),
- TYPE_IOTKIT_SECCTL);
- sysbus_init_child_obj(obj, "apb-ppc0", &s->apb_ppc0, sizeof(s->apb_ppc0),
- TYPE_TZ_PPC);
- sysbus_init_child_obj(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1),
- TYPE_TZ_PPC);
+ object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL);
+ object_initialize_child(obj, "apb-ppc0", &s->apb_ppc0, TYPE_TZ_PPC);
+ object_initialize_child(obj, "apb-ppc1", &s->apb_ppc1, TYPE_TZ_PPC);
for (i = 0; i < info->sram_banks; i++) {
char *name = g_strdup_printf("mpc%d", i);
- sysbus_init_child_obj(obj, name, &s->mpc[i],
- sizeof(s->mpc[i]), TYPE_TZ_MPC);
+ object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC);
g_free(name);
}
object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate,
- sizeof(s->mpc_irq_orgate), TYPE_OR_IRQ,
- &error_abort, NULL);
+ TYPE_OR_IRQ);
for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) {
char *name = g_strdup_printf("mpc-irq-splitter-%d", i);
SplitIRQ *splitter = &s->mpc_irq_splitter[i];
- object_initialize_child(obj, name, splitter, sizeof(*splitter),
- TYPE_SPLIT_IRQ, &error_abort, NULL);
+ object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ);
g_free(name);
}
- sysbus_init_child_obj(obj, "timer0", &s->timer0, sizeof(s->timer0),
- TYPE_CMSDK_APB_TIMER);
- sysbus_init_child_obj(obj, "timer1", &s->timer1, sizeof(s->timer1),
- TYPE_CMSDK_APB_TIMER);
- sysbus_init_child_obj(obj, "s32ktimer", &s->s32ktimer, sizeof(s->s32ktimer),
- TYPE_CMSDK_APB_TIMER);
- sysbus_init_child_obj(obj, "dualtimer", &s->dualtimer, sizeof(s->dualtimer),
- TYPE_CMSDK_APB_DUALTIMER);
- sysbus_init_child_obj(obj, "s32kwatchdog", &s->s32kwatchdog,
- sizeof(s->s32kwatchdog), TYPE_CMSDK_APB_WATCHDOG);
- sysbus_init_child_obj(obj, "nswatchdog", &s->nswatchdog,
- sizeof(s->nswatchdog), TYPE_CMSDK_APB_WATCHDOG);
- sysbus_init_child_obj(obj, "swatchdog", &s->swatchdog,
- sizeof(s->swatchdog), TYPE_CMSDK_APB_WATCHDOG);
- sysbus_init_child_obj(obj, "armsse-sysctl", &s->sysctl,
- sizeof(s->sysctl), TYPE_IOTKIT_SYSCTL);
- sysbus_init_child_obj(obj, "armsse-sysinfo", &s->sysinfo,
- sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO);
+ object_initialize_child(obj, "timer0", &s->timer0, TYPE_CMSDK_APB_TIMER);
+ object_initialize_child(obj, "timer1", &s->timer1, TYPE_CMSDK_APB_TIMER);
+ object_initialize_child(obj, "s32ktimer", &s->s32ktimer,
+ TYPE_CMSDK_APB_TIMER);
+ object_initialize_child(obj, "dualtimer", &s->dualtimer,
+ TYPE_CMSDK_APB_DUALTIMER);
+ object_initialize_child(obj, "s32kwatchdog", &s->s32kwatchdog,
+ TYPE_CMSDK_APB_WATCHDOG);
+ object_initialize_child(obj, "nswatchdog", &s->nswatchdog,
+ TYPE_CMSDK_APB_WATCHDOG);
+ object_initialize_child(obj, "swatchdog", &s->swatchdog,
+ TYPE_CMSDK_APB_WATCHDOG);
+ object_initialize_child(obj, "armsse-sysctl", &s->sysctl,
+ TYPE_IOTKIT_SYSCTL);
+ object_initialize_child(obj, "armsse-sysinfo", &s->sysinfo,
+ TYPE_IOTKIT_SYSINFO);
if (info->has_mhus) {
- sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]),
- TYPE_ARMSSE_MHU);
- sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]),
- TYPE_ARMSSE_MHU);
+ object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU);
+ object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU);
}
if (info->has_ppus) {
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("CPU%dCORE_PPU", i);
int ppuidx = CPU0CORE_PPU + i;
- sysbus_init_child_obj(obj, name, &s->ppu[ppuidx],
- sizeof(s->ppu[ppuidx]),
- TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, name, &s->ppu[ppuidx],
+ TYPE_UNIMPLEMENTED_DEVICE);
g_free(name);
}
- sysbus_init_child_obj(obj, "DBG_PPU", &s->ppu[DBG_PPU],
- sizeof(s->ppu[DBG_PPU]),
- TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "DBG_PPU", &s->ppu[DBG_PPU],
+ TYPE_UNIMPLEMENTED_DEVICE);
for (i = 0; i < info->sram_banks; i++) {
char *name = g_strdup_printf("RAM%d_PPU", i);
int ppuidx = RAM0_PPU + i;
- sysbus_init_child_obj(obj, name, &s->ppu[ppuidx],
- sizeof(s->ppu[ppuidx]),
- TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, name, &s->ppu[ppuidx],
+ TYPE_UNIMPLEMENTED_DEVICE);
g_free(name);
}
}
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("cachectrl%d", i);
- sysbus_init_child_obj(obj, name, &s->cachectrl[i],
- sizeof(s->cachectrl[i]),
- TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, name, &s->cachectrl[i],
+ TYPE_UNIMPLEMENTED_DEVICE);
g_free(name);
}
}
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("cpusecctrl%d", i);
- sysbus_init_child_obj(obj, name, &s->cpusecctrl[i],
- sizeof(s->cpusecctrl[i]),
- TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, name, &s->cpusecctrl[i],
+ TYPE_UNIMPLEMENTED_DEVICE);
g_free(name);
}
}
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("cpuid%d", i);
- sysbus_init_child_obj(obj, name, &s->cpuid[i],
- sizeof(s->cpuid[i]),
- TYPE_ARMSSE_CPUID);
+ object_initialize_child(obj, name, &s->cpuid[i],
+ TYPE_ARMSSE_CPUID);
g_free(name);
}
}
- object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate,
- sizeof(s->nmi_orgate), TYPE_OR_IRQ,
- &error_abort, NULL);
+ object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ);
object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate,
- sizeof(s->ppc_irq_orgate), TYPE_OR_IRQ,
- &error_abort, NULL);
+ TYPE_OR_IRQ);
object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter,
- sizeof(s->sec_resp_splitter), TYPE_SPLIT_IRQ,
- &error_abort, NULL);
+ TYPE_SPLIT_IRQ);
for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) {
char *name = g_strdup_printf("ppc-irq-splitter-%d", i);
SplitIRQ *splitter = &s->ppc_irq_splitter[i];
- object_initialize_child(obj, name, splitter, sizeof(*splitter),
- TYPE_SPLIT_IRQ, &error_abort, NULL);
+ object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ);
g_free(name);
}
if (info->num_cpus > 1) {
char *name = g_strdup_printf("cpu-irq-splitter%d", i);
SplitIRQ *splitter = &s->cpu_irq_splitter[i];
- object_initialize_child(obj, name, splitter, sizeof(*splitter),
- TYPE_SPLIT_IRQ, &error_abort, NULL);
+ object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ);
g_free(name);
}
}
qdev_prop_set_string(dev, "name", name);
qdev_prop_set_uint64(dev, "size", 0x1000);
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr);
}
error_propagate(errp, err);
return;
}
- object_property_set_bool(cpuobj, true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(cpuobj), &err);
if (err) {
error_propagate(errp, err);
return;
* CPU must exist and have been parented into the cluster before
* the cluster is realized.
*/
- object_property_set_bool(OBJECT(&s->cluster[i]),
- true, "realized", &err);
+ qdev_realize(DEVICE(&s->cluster[i]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(splitter, true, "realized", &err);
+ qdev_realize(DEVICE(splitter), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
}
/* Security controller */
- object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->secctl), &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->sec_resp_splitter), true,
- "realized", &err);
+ qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->mpc[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->mpc_irq_orgate), true,
- "realized", &err);
+ qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
* map its upstream ends to the right place in the container.
*/
qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq);
- object_property_set_bool(OBJECT(&s->timer0), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->timer0), &err);
if (err) {
error_propagate(errp, err);
return;
}
qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq);
- object_property_set_bool(OBJECT(&s->timer1), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->timer1), &err);
if (err) {
error_propagate(errp, err);
return;
qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq);
- object_property_set_bool(OBJECT(&s->dualtimer), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), &err);
if (err) {
error_propagate(errp, err);
return;
int cpunum;
SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]);
- object_property_set_bool(OBJECT(&s->mhu[i]), true,
- "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), &err);
if (err) {
error_propagate(errp, err);
return;
}
}
- object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc0), &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->ppc_irq_orgate), true,
- "realized", &err);
+ qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name);
g_free(name);
qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000);
- object_property_set_bool(OBJECT(&s->cachectrl[i]), true,
- "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), &err);
if (err) {
error_propagate(errp, err);
return;
qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name);
g_free(name);
qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000);
- object_property_set_bool(OBJECT(&s->cpusecctrl[i]), true,
- "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), &err);
if (err) {
error_propagate(errp, err);
return;
MemoryRegion *mr;
qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i);
- object_property_set_bool(OBJECT(&s->cpuid[i]), true,
- "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), &err);
if (err) {
error_propagate(errp, err);
return;
* 0x4002f000: S32K timer
*/
qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK);
- object_property_set_bool(OBJECT(&s->s32ktimer), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), &err);
if (err) {
error_propagate(errp, err);
return;
return;
}
- object_property_set_bool(OBJECT(&s->apb_ppc1), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc1), &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->sysinfo), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), &err);
if (err) {
error_propagate(errp, err);
return;
"INITSVTOR0_RST", &err);
object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
"INITSVTOR1_RST", &err);
- object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sysctl), &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->nmi_orgate), true, "realized", &err);
+ qdev_realize(DEVICE(&s->nmi_orgate), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK);
- object_property_set_bool(OBJECT(&s->s32kwatchdog), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), &err);
if (err) {
error_propagate(errp, err);
return;
/* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq);
- object_property_set_bool(OBJECT(&s->nswatchdog), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), &err);
if (err) {
error_propagate(errp, err);
return;
sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000);
qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq);
- object_property_set_bool(OBJECT(&s->swatchdog), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(splitter, true, "realized", &err);
+ qdev_realize(DEVICE(splitter), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(splitter), true, "realized", &err);
+ qdev_realize(DEVICE(splitter), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
- sysbus_init_child_obj(obj, "nvnic", &s->nvic, sizeof(s->nvic), TYPE_NVIC);
+ object_initialize_child(obj, "nvnic", &s->nvic, TYPE_NVIC);
object_property_add_alias(obj, "num-irq",
OBJECT(&s->nvic), "num-irq");
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
- sysbus_init_child_obj(obj, "bitband[*]", &s->bitband[i],
- sizeof(s->bitband[i]), TYPE_BITBAND);
+ object_initialize_child(obj, "bitband[*]", &s->bitband[i],
+ TYPE_BITBAND);
}
}
s->cpu->env.nvic = &s->nvic;
s->nvic.cpu = s->cpu;
- object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
+ qdev_realize(DEVICE(s->cpu), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
/* Note that we must realize the NVIC after the CPU */
- object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->nvic), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
memory_region_add_subregion(&s->container, 0xe000e000,
sysbus_mmio_get_region(sbd, 0));
- if (s->enable_bitband) {
- for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
+ if (s->enable_bitband) {
Object *obj = OBJECT(&s->bitband[i]);
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
}
object_property_set_link(obj, OBJECT(s->board_memory),
"source-memory", &error_abort);
- object_property_set_bool(obj, true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(obj), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
memory_region_add_subregion(&s->container, bitband_output_addr[i],
sysbus_mmio_get_region(sbd, 0));
+ } else {
+ object_unparent(OBJECT(&s->bitband[i]));
}
}
}
DriveInfo *dinfo = drive_get_next(IF_MTD);
qemu_irq cs_line;
- fl->flash = ssi_create_slave_no_init(s->spi, flashtype);
+ fl->flash = qdev_new(flashtype);
if (dinfo) {
qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
errp);
}
- qdev_init_nofail(fl->flash);
+ qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal);
cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
{
DeviceState *card;
- card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
- TYPE_SD_CARD);
+ card = qdev_new(TYPE_SD_CARD);
if (dinfo) {
qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
- object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
+ qdev_realize_and_unref(card,
+ qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
+ &error_fatal);
}
static void aspeed_machine_init(MachineState *machine)
DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
ram_addr_t max_ram_size;
int i;
+ NICInfo *nd = &nd_table[0];
bmc = g_new0(AspeedBoardState, 1);
4 * GiB);
memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
- object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
- (sizeof(bmc->soc)), amc->soc_name, &error_abort,
- NULL);
+ object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size",
&error_fatal);
+ for (i = 0; i < sc->macs_num; i++) {
+ if ((amc->macs_mask & (1 << i)) && nd->used) {
+ qemu_check_nic_model(nd, TYPE_FTGMAC100);
+ qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
+ nd++;
+ }
+ }
+
object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap1, "hw-strap1",
&error_abort);
object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap2, "hw-strap2",
&error_abort);
object_property_set_int(OBJECT(&bmc->soc), amc->num_cs, "num-cs",
&error_abort);
- object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus",
- &error_abort);
object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container),
"dram", &error_abort);
if (machine->kernel_filename) {
object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY,
"hw-prot-key", &error_abort);
}
- object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
- &error_abort);
+ qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
memory_region_add_subregion(get_system_memory(),
sc->memmap[ASPEED_SDRAM],
}
}
- if (machine->kernel_filename && bmc->soc.num_cpus > 1) {
+ if (machine->kernel_filename && sc->num_cpus > 1) {
/* With no u-boot we must set up a boot stub for the secondary CPU */
MemoryRegion *smpboot = g_new(MemoryRegion, 1);
memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot",
aspeed_board_binfo.ram_size = ram_size;
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM];
- aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
+ aspeed_board_binfo.nb_cpus = sc->num_cpus;
if (amc->i2c_init) {
amc->i2c_init(bmc);
"boot directly from CE0 flash device");
}
+static int aspeed_soc_num_cpus(const char *soc_name)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
+ return sc->num_cpus;
+}
+
static void aspeed_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
mc->init = aspeed_machine_init;
- mc->max_cpus = ASPEED_CPUS_NUM;
mc->no_floppy = 1;
mc->no_cdrom = 1;
mc->no_parallel = 1;
mc->default_ram_id = "ram";
+ amc->macs_mask = ASPEED_MAC0_ON;
aspeed_machine_class_props_init(oc);
}
amc->num_cs = 1;
amc->i2c_init = palmetto_bmc_i2c_init;
mc->default_ram_size = 256 * MiB;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
+ aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
amc->num_cs = 1;
amc->i2c_init = ast2500_evb_i2c_init;
mc->default_ram_size = 512 * MiB;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
+ aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->i2c_init = romulus_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
+ aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->i2c_init = sonorapass_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
+ aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->i2c_init = swift_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
+ aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->i2c_init = witherspoon_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
+ aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
amc->fmc_model = "w25q512jv";
amc->spi_model = "mx66u51235f";
amc->num_cs = 1;
+ amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON;
amc->i2c_init = ast2600_evb_i2c_init;
mc->default_ram_size = 1 * GiB;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
+ aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
amc->fmc_model = "mx66l1g45g";
amc->spi_model = "mx66l1g45g";
amc->num_cs = 2;
+ amc->macs_mask = ASPEED_MAC2_ON;
amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
mc->default_ram_size = 1 * GiB;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
+ aspeed_soc_num_cpus(amc->soc_name);
};
static const TypeInfo aspeed_machine_types[] = {
}
for (i = 0; i < sc->num_cpus; i++) {
- object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
- sizeof(s->cpu[i]), sc->cpu_type,
- &error_abort, NULL);
+ object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
}
snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
- sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
- typename);
+ object_initialize_child(obj, "scu", &s->scu, typename);
qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
sc->silicon_rev);
object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
"hw-prot-key");
- sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore,
- sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV);
+ object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
+ TYPE_A15MPCORE_PRIV);
- sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
- TYPE_ASPEED_RTC);
+ object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
- sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
- sizeof(s->timerctrl), typename);
+ object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
- sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
- typename);
+ object_initialize_child(obj, "i2c", &s->i2c, typename);
snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
- sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
- typename);
+ object_initialize_child(obj, "fmc", &s->fmc, typename);
object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
for (i = 0; i < sc->spis_num; i++) {
snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
- sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
- sizeof(s->spi[i]), typename);
+ object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
}
for (i = 0; i < sc->ehcis_num; i++) {
- sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
- sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
+ object_initialize_child(obj, "ehci[*]", &s->ehci[i],
+ TYPE_PLATFORM_EHCI);
}
snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
- sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
- typename);
+ object_initialize_child(obj, "sdmc", &s->sdmc, typename);
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
"ram-size");
object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
for (i = 0; i < sc->wdts_num; i++) {
snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
- sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
- sizeof(s->wdt[i]), typename);
+ object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
}
for (i = 0; i < sc->macs_num; i++) {
- sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
- sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
+ object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
+ TYPE_FTGMAC100);
- sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]),
- TYPE_ASPEED_MII);
+ object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
}
- sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
- TYPE_ASPEED_XDMA);
+ object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA);
snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
- sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
- typename);
+ object_initialize_child(obj, "gpio", &s->gpio, typename);
snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
- sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v),
- sizeof(s->gpio_1_8v), typename);
+ object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename);
- sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci),
- sizeof(s->sdhci), TYPE_ASPEED_SDHCI);
+ object_initialize_child(obj, "sd-controller", &s->sdhci,
+ TYPE_ASPEED_SDHCI);
object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
/* Init sd card slot class here so that they're under the correct parent */
for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
- sysbus_init_child_obj(obj, "sd-controller.sdhci[*]",
- OBJECT(&s->sdhci.slots[i]),
- sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
+ object_initialize_child(obj, "sd-controller.sdhci[*]",
+ &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI);
}
- sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc),
- sizeof(s->emmc), TYPE_ASPEED_SDHCI);
+ object_initialize_child(obj, "emmc-controller", &s->emmc,
+ TYPE_ASPEED_SDHCI);
object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort);
- sysbus_init_child_obj(obj, "emmc-controller.sdhci",
- OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]),
- TYPE_SYSBUS_SDHCI);
+ object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
+ TYPE_SYSBUS_SDHCI);
}
/*
create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
0x1000);
- if (s->num_cpus > sc->num_cpus) {
- warn_report("%s: invalid number of CPUs %d, using default %d",
- sc->name, s->num_cpus, sc->num_cpus);
- s->num_cpus = sc->num_cpus;
- }
-
/* CPU */
- for (i = 0; i < s->num_cpus; i++) {
+ for (i = 0; i < sc->num_cpus; i++) {
object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
"psci-conduit", &error_abort);
- if (s->num_cpus > 1) {
+ if (sc->num_cpus > 1) {
object_property_set_int(OBJECT(&s->cpu[i]),
ASPEED_A7MPCORE_ADDR,
"reset-cbar", &error_abort);
* is needed when using -kernel
*/
- object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
+ qdev_realize(DEVICE(&s->cpu[i]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
}
/* A7MPCORE */
- object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu",
+ object_property_set_int(OBJECT(&s->a7mpcore), sc->num_cpus, "num-cpu",
&error_abort);
object_property_set_int(OBJECT(&s->a7mpcore),
ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
"num-irq", &error_abort);
- object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
- for (i = 0; i < s->num_cpus; i++) {
+ for (i = 0; i < sc->num_cpus; i++) {
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
DeviceState *d = DEVICE(qemu_get_cpu(i));
irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
sysbus_connect_irq(sbd, i, irq);
irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
- sysbus_connect_irq(sbd, i + s->num_cpus, irq);
+ sysbus_connect_irq(sbd, i + sc->num_cpus, irq);
irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
- sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq);
+ sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq);
irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
- sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq);
+ sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq);
}
/* SRAM */
sc->memmap[ASPEED_SRAM], &s->sram);
/* SCU */
- object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
if (err) {
error_propagate(errp, err);
return;
sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
/* RTC */
- object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err);
if (err) {
error_propagate(errp, err);
return;
/* Timer */
object_property_set_link(OBJECT(&s->timerctrl),
OBJECT(&s->scu), "scu", &error_abort);
- object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->fmc), &err);
if (err) {
error_propagate(errp, err);
return;
return;
}
object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
- object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
- &local_err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &local_err);
error_propagate(&err, local_err);
if (err) {
error_propagate(errp, err);
/* EHCI */
for (i = 0; i < sc->ehcis_num; i++) {
- object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &err);
if (err) {
error_propagate(errp, err);
return;
}
/* SDMC - SDRAM Memory Controller */
- object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), &err);
if (err) {
error_propagate(errp, err);
return;
object_property_set_link(OBJECT(&s->wdt[i]),
OBJECT(&s->scu), "scu", &error_abort);
- object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &err);
if (err) {
error_propagate(errp, err);
return;
}
/* Net */
- for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
- qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
+ for (i = 0; i < sc->macs_num; i++) {
object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
&err);
- object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
- &local_err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), &local_err);
error_propagate(&err, local_err);
if (err) {
error_propagate(errp, err);
object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]),
"nic", &error_abort);
- object_property_set_bool(OBJECT(&s->mii[i]), true, "realized",
- &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), &err);
if (err) {
error_propagate(errp, err);
return;
}
/* XDMA */
- object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->xdma), &err);
if (err) {
error_propagate(errp, err);
return;
aspeed_soc_get_irq(s, ASPEED_XDMA));
/* GPIO */
- object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
if (err) {
error_propagate(errp, err);
return;
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
aspeed_soc_get_irq(s, ASPEED_GPIO));
- object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), &err);
if (err) {
error_propagate(errp, err);
return;
aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V));
/* SDHCI */
- object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), &err);
if (err) {
error_propagate(errp, err);
return;
aspeed_soc_get_irq(s, ASPEED_SDHCI));
/* eMMC */
- object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->emmc), &err);
if (err) {
error_propagate(errp, err);
return;
}
for (i = 0; i < sc->num_cpus; i++) {
- object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
- sizeof(s->cpu[i]), sc->cpu_type,
- &error_abort, NULL);
+ object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
}
snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
- sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
- typename);
+ object_initialize_child(obj, "scu", &s->scu, typename);
qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
sc->silicon_rev);
object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
"hw-prot-key");
- sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
- TYPE_ASPEED_VIC);
+ object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
- sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
- TYPE_ASPEED_RTC);
+ object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
- sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
- sizeof(s->timerctrl), typename);
+ object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
- sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
- typename);
+ object_initialize_child(obj, "i2c", &s->i2c, typename);
snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
- sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
- typename);
+ object_initialize_child(obj, "fmc", &s->fmc, typename);
object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
for (i = 0; i < sc->spis_num; i++) {
snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
- sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
- sizeof(s->spi[i]), typename);
+ object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
}
for (i = 0; i < sc->ehcis_num; i++) {
- sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
- sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
+ object_initialize_child(obj, "ehci[*]", &s->ehci[i],
+ TYPE_PLATFORM_EHCI);
}
snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
- sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
- typename);
+ object_initialize_child(obj, "sdmc", &s->sdmc, typename);
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
"ram-size");
object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
for (i = 0; i < sc->wdts_num; i++) {
snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
- sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
- sizeof(s->wdt[i]), typename);
+ object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
}
for (i = 0; i < sc->macs_num; i++) {
- sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
- sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
+ object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
+ TYPE_FTGMAC100);
}
- sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
- TYPE_ASPEED_XDMA);
+ object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA);
snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
- sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
- typename);
+ object_initialize_child(obj, "gpio", &s->gpio, typename);
- sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
- TYPE_ASPEED_SDHCI);
+ object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI);
object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
/* Init sd card slot class here so that they're under the correct parent */
for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
- sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
- sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
+ object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
+ TYPE_SYSBUS_SDHCI);
}
}
create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
0x1000);
- if (s->num_cpus > sc->num_cpus) {
- warn_report("%s: invalid number of CPUs %d, using default %d",
- sc->name, s->num_cpus, sc->num_cpus);
- s->num_cpus = sc->num_cpus;
- }
-
/* CPU */
- for (i = 0; i < s->num_cpus; i++) {
- object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
+ for (i = 0; i < sc->num_cpus; i++) {
+ qdev_realize(DEVICE(&s->cpu[i]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
sc->memmap[ASPEED_SRAM], &s->sram);
/* SCU */
- object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
if (err) {
error_propagate(errp, err);
return;
sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
/* VIC */
- object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->vic), &err);
if (err) {
error_propagate(errp, err);
return;
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
/* RTC */
- object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err);
if (err) {
error_propagate(errp, err);
return;
/* Timer */
object_property_set_link(OBJECT(&s->timerctrl),
OBJECT(&s->scu), "scu", &error_abort);
- object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->fmc), &err);
if (err) {
error_propagate(errp, err);
return;
/* SPI */
for (i = 0; i < sc->spis_num; i++) {
object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
- object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
- &local_err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &local_err);
error_propagate(&err, local_err);
if (err) {
error_propagate(errp, err);
/* EHCI */
for (i = 0; i < sc->ehcis_num; i++) {
- object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &err);
if (err) {
error_propagate(errp, err);
return;
}
/* SDMC - SDRAM Memory Controller */
- object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), &err);
if (err) {
error_propagate(errp, err);
return;
object_property_set_link(OBJECT(&s->wdt[i]),
OBJECT(&s->scu), "scu", &error_abort);
- object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &err);
if (err) {
error_propagate(errp, err);
return;
}
/* Net */
- for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
- qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
+ for (i = 0; i < sc->macs_num; i++) {
object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
&err);
- object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
- &local_err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), &local_err);
error_propagate(&err, local_err);
if (err) {
error_propagate(errp, err);
}
/* XDMA */
- object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->xdma), &err);
if (err) {
error_propagate(errp, err);
return;
aspeed_soc_get_irq(s, ASPEED_XDMA));
/* GPIO */
- object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
if (err) {
error_propagate(errp, err);
return;
aspeed_soc_get_irq(s, ASPEED_GPIO));
/* SDHCI */
- object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), &err);
if (err) {
error_propagate(errp, err);
return;
aspeed_soc_get_irq(s, ASPEED_SDHCI));
}
static Property aspeed_soc_properties[] = {
- DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
UnimplementedDeviceState *uds,
const char *name, hwaddr ofs, hwaddr size)
{
- sysbus_init_child_obj(OBJECT(ps), name, uds,
- sizeof(UnimplementedDeviceState),
- TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(OBJECT(ps), name, uds, TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(DEVICE(uds), "name", name);
qdev_prop_set_uint64(DEVICE(uds), "size", size);
- object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
memory_region_add_subregion_overlap(&ps->peri_mr, ofs,
sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0), -1000);
}
MBOX_CHAN_COUNT << MBOX_AS_CHAN_SHIFT);
/* Interrupt Controller */
- sysbus_init_child_obj(obj, "ic", &s->ic, sizeof(s->ic), TYPE_BCM2835_IC);
+ object_initialize_child(obj, "ic", &s->ic, TYPE_BCM2835_IC);
/* SYS Timer */
- sysbus_init_child_obj(obj, "systimer", &s->systmr, sizeof(s->systmr),
- TYPE_BCM2835_SYSTIMER);
+ object_initialize_child(obj, "systimer", &s->systmr,
+ TYPE_BCM2835_SYSTIMER);
/* UART0 */
- sysbus_init_child_obj(obj, "uart0", &s->uart0, sizeof(s->uart0),
- TYPE_PL011);
+ object_initialize_child(obj, "uart0", &s->uart0, TYPE_PL011);
/* AUX / UART1 */
- sysbus_init_child_obj(obj, "aux", &s->aux, sizeof(s->aux),
- TYPE_BCM2835_AUX);
+ object_initialize_child(obj, "aux", &s->aux, TYPE_BCM2835_AUX);
/* Mailboxes */
- sysbus_init_child_obj(obj, "mbox", &s->mboxes, sizeof(s->mboxes),
- TYPE_BCM2835_MBOX);
+ object_initialize_child(obj, "mbox", &s->mboxes, TYPE_BCM2835_MBOX);
object_property_add_const_link(OBJECT(&s->mboxes), "mbox-mr",
OBJECT(&s->mbox_mr));
/* Framebuffer */
- sysbus_init_child_obj(obj, "fb", &s->fb, sizeof(s->fb), TYPE_BCM2835_FB);
+ object_initialize_child(obj, "fb", &s->fb, TYPE_BCM2835_FB);
object_property_add_alias(obj, "vcram-size", OBJECT(&s->fb), "vcram-size");
object_property_add_const_link(OBJECT(&s->fb), "dma-mr",
OBJECT(&s->gpu_bus_mr));
/* Property channel */
- sysbus_init_child_obj(obj, "property", &s->property, sizeof(s->property),
- TYPE_BCM2835_PROPERTY);
+ object_initialize_child(obj, "property", &s->property,
+ TYPE_BCM2835_PROPERTY);
object_property_add_alias(obj, "board-rev", OBJECT(&s->property),
"board-rev");
OBJECT(&s->gpu_bus_mr));
/* Random Number Generator */
- sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng),
- TYPE_BCM2835_RNG);
+ object_initialize_child(obj, "rng", &s->rng, TYPE_BCM2835_RNG);
/* Extended Mass Media Controller */
- sysbus_init_child_obj(obj, "sdhci", &s->sdhci, sizeof(s->sdhci),
- TYPE_SYSBUS_SDHCI);
+ object_initialize_child(obj, "sdhci", &s->sdhci, TYPE_SYSBUS_SDHCI);
/* SDHOST */
- sysbus_init_child_obj(obj, "sdhost", &s->sdhost, sizeof(s->sdhost),
- TYPE_BCM2835_SDHOST);
+ object_initialize_child(obj, "sdhost", &s->sdhost, TYPE_BCM2835_SDHOST);
/* DMA Channels */
- sysbus_init_child_obj(obj, "dma", &s->dma, sizeof(s->dma),
- TYPE_BCM2835_DMA);
+ object_initialize_child(obj, "dma", &s->dma, TYPE_BCM2835_DMA);
object_property_add_const_link(OBJECT(&s->dma), "dma-mr",
OBJECT(&s->gpu_bus_mr));
/* Thermal */
- sysbus_init_child_obj(obj, "thermal", &s->thermal, sizeof(s->thermal),
- TYPE_BCM2835_THERMAL);
+ object_initialize_child(obj, "thermal", &s->thermal, TYPE_BCM2835_THERMAL);
/* GPIO */
- sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
- TYPE_BCM2835_GPIO);
+ object_initialize_child(obj, "gpio", &s->gpio, TYPE_BCM2835_GPIO);
object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci",
OBJECT(&s->sdhci.sdbus));
OBJECT(&s->sdhost.sdbus));
/* Mphi */
- sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi),
- TYPE_BCM2835_MPHI);
+ object_initialize_child(obj, "mphi", &s->mphi, TYPE_BCM2835_MPHI);
/* DWC2 */
- sysbus_init_child_obj(obj, "dwc2", &s->dwc2, sizeof(s->dwc2),
- TYPE_DWC2_USB);
+ object_initialize_child(obj, "dwc2", &s->dwc2, TYPE_DWC2_USB);
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
OBJECT(&s->gpu_bus_mr));
}
/* Interrupt Controller */
- object_property_set_bool(OBJECT(&s->ic), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ic), &err);
if (err) {
error_propagate(errp, err);
return;
sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic));
/* Sys Timer */
- object_property_set_bool(OBJECT(&s->systmr), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->systmr), &err);
if (err) {
error_propagate(errp, err);
return;
/* UART0 */
qdev_prop_set_chr(DEVICE(&s->uart0), "chardev", serial_hd(0));
- object_property_set_bool(OBJECT(&s->uart0), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->uart0), &err);
if (err) {
error_propagate(errp, err);
return;
/* AUX / UART1 */
qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hd(1));
- object_property_set_bool(OBJECT(&s->aux), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->aux), &err);
if (err) {
error_propagate(errp, err);
return;
INTERRUPT_AUX));
/* Mailboxes */
- object_property_set_bool(OBJECT(&s->mboxes), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->mboxes), &err);
if (err) {
error_propagate(errp, err);
return;
return;
}
- object_property_set_bool(OBJECT(&s->fb), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->fb), &err);
if (err) {
error_propagate(errp, err);
return;
qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_FB));
/* Property channel */
- object_property_set_bool(OBJECT(&s->property), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->property), &err);
if (err) {
error_propagate(errp, err);
return;
qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY));
/* Random Number Generator */
- object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->rng), &err);
if (err) {
error_propagate(errp, err);
return;
return;
}
- object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), &err);
if (err) {
error_propagate(errp, err);
return;
INTERRUPT_ARASANSDIO));
/* SDHOST */
- object_property_set_bool(OBJECT(&s->sdhost), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sdhost), &err);
if (err) {
error_propagate(errp, err);
return;
INTERRUPT_SDIO));
/* DMA Channels */
- object_property_set_bool(OBJECT(&s->dma), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->dma), &err);
if (err) {
error_propagate(errp, err);
return;
}
/* THERMAL */
- object_property_set_bool(OBJECT(&s->thermal), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->thermal), &err);
if (err) {
error_propagate(errp, err);
return;
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->thermal), 0));
/* GPIO */
- object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
if (err) {
error_propagate(errp, err);
return;
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus");
/* Mphi */
- object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->mphi), &err);
if (err) {
error_propagate(errp, err);
return;
INTERRUPT_HOSTPORT));
/* DWC2 */
- object_property_set_bool(OBJECT(&s->dwc2), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->dwc2), &err);
if (err) {
error_propagate(errp, err);
return;
for (n = 0; n < BCM283X_NCPUS; n++) {
object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
- sizeof(s->cpu[n].core), info->cpu_type,
- &error_abort, NULL);
+ info->cpu_type);
}
- sysbus_init_child_obj(obj, "control", &s->control, sizeof(s->control),
- TYPE_BCM2836_CONTROL);
+ object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL);
- sysbus_init_child_obj(obj, "peripherals", &s->peripherals,
- sizeof(s->peripherals), TYPE_BCM2835_PERIPHERALS);
+ object_initialize_child(obj, "peripherals", &s->peripherals,
+ TYPE_BCM2835_PERIPHERALS);
object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals),
"board-rev");
object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals),
object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);
- object_property_set_bool(OBJECT(&s->peripherals), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), &err);
if (err) {
error_propagate(errp, err);
return;
info->peri_base, 1);
/* bcm2836 interrupt controller (and mailboxes, etc.) */
- object_property_set_bool(OBJECT(&s->control), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->control), &err);
if (err) {
error_propagate(errp, err);
return;
return;
}
- object_property_set_bool(OBJECT(&s->cpu[n].core), true,
- "realized", &err);
+ qdev_realize(DEVICE(&s->cpu[n].core), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
exit(1);
}
- object_property_set_bool(OBJECT(a10), true, "realized", &err);
+ qdev_realize(DEVICE(a10), NULL, &err);
if (err != NULL) {
error_reportf_err(err, "Couldn't realize Allwinner A10: ");
exit(1);
bus = qdev_get_child_bus(DEVICE(a10), "sd-bus");
/* Plug in SD card */
- carddev = qdev_create(bus, TYPE_SD_CARD);
+ carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
+ qdev_realize_and_unref(carddev, bus, &error_fatal);
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
machine->ram);
DigicState *s = DIGIC(obj);
int i;
- object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
- ARM_CPU_TYPE_NAME("arm946"),
- &error_abort, NULL);
+ object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm946"));
for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
#define DIGIC_TIMER_NAME_MLEN 11
char name[DIGIC_TIMER_NAME_MLEN];
snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i);
- sysbus_init_child_obj(obj, name, &s->timer[i], sizeof(s->timer[i]),
- TYPE_DIGIC_TIMER);
+ object_initialize_child(obj, name, &s->timer[i], TYPE_DIGIC_TIMER);
}
- sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
- TYPE_DIGIC_UART);
+ object_initialize_child(obj, "uart", &s->uart, TYPE_DIGIC_UART);
}
static void digic_realize(DeviceState *dev, Error **errp)
return;
}
- object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
+ qdev_realize(DEVICE(&s->cpu), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
- object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0));
- object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->uart), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
exit(EXIT_FAILURE);
}
- object_property_set_bool(OBJECT(s), true, "realized", &err);
+ qdev_realize(DEVICE(s), NULL, &err);
if (err != NULL) {
error_reportf_err(err, "Couldn't realize DIGIC SoC: ");
exit(1);
DeviceState *dev;
int i;
- dev = qdev_create(NULL, "pl330");
+ dev = qdev_new("pl330");
qdev_prop_set_uint8(dev, "num_events", nevents);
qdev_prop_set_uint8(dev, "num_chnls", 8);
qdev_prop_set_uint8(dev, "num_periph_req", nreq);
qdev_prop_set_uint8(dev, "rd_q_dep", 8);
qdev_prop_set_uint8(dev, "data_width", width);
qdev_prop_set_uint16(dev, "data_buffer_dep", width);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, base);
object_property_set_int(OBJECT(orgate), nevents + 1, "num-lines",
&error_abort);
- object_property_set_bool(OBJECT(orgate), true, "realized", &error_abort);
+ qdev_realize(DEVICE(orgate), NULL, &error_abort);
for (i = 0; i < nevents + 1; i++) {
sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i));
"mp-affinity", &error_abort);
object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
"reset-cbar", &error_abort);
- object_property_set_bool(cpuobj, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
}
/*** IRQs ***/
/* IRQ Gate */
for (i = 0; i < EXYNOS4210_NCPUS; i++) {
- dev = qdev_create(NULL, "exynos4210.irq_gate");
+ dev = qdev_new("exynos4210.irq_gate");
qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Get IRQ Gate input in gate_irq */
for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
gate_irq[i][n] = qdev_get_gpio_in(dev, n);
}
/* Private memory region and Internal GIC */
- dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
+ dev = qdev_new(TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
sysbus_connect_irq(busdev, n, gate_irq[n][0]);
sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
/* External GIC */
- dev = qdev_create(NULL, "exynos4210.gic");
+ dev = qdev_new("exynos4210.gic");
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
/* Map CPU interface */
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
/* Map Distributer interface */
}
/* Internal Interrupt Combiner */
- dev = qdev_create(NULL, "exynos4210.combiner");
- qdev_init_nofail(dev);
+ dev = qdev_new("exynos4210.combiner");
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
}
sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
/* External Interrupt Combiner */
- dev = qdev_create(NULL, "exynos4210.combiner");
+ dev = qdev_new("exynos4210.combiner");
qdev_prop_set_uint32(dev, "external", 1);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
}
NULL);
/* Multi Core Timer */
- dev = qdev_create(NULL, "exynos4210.mct");
- qdev_init_nofail(dev);
+ dev = qdev_new("exynos4210.mct");
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
for (n = 0; n < 4; n++) {
/* Connect global timer interrupts to Combiner gpio_in */
sysbus_connect_irq(busdev, n,
i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
}
- dev = qdev_create(NULL, "exynos4210.i2c");
- qdev_init_nofail(dev);
+ dev = qdev_new("exynos4210.i2c");
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0, i2c_irq);
sysbus_mmio_map(busdev, 0, addr);
s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
* public datasheet which is very similar (implementing
* MMC Specification Version 4.0 being the only difference noted)
*/
- dev = qdev_create(NULL, TYPE_S3C_SDHCI);
+ dev = qdev_new(TYPE_S3C_SDHCI);
qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n));
sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]);
di = drive_get(IF_SD, 0, n);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
- carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
+ carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_abort);
- qdev_init_nofail(carddev);
+ qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
+ &error_fatal);
}
/*** Display controller (FIMD) ***/
char *name = g_strdup_printf("pl330-irq-orgate%d", i);
qemu_or_irq *orgate = &s->pl330_irq_orgate[i];
- object_initialize_child(obj, name, orgate, sizeof(*orgate),
- TYPE_OR_IRQ, &error_abort, NULL);
+ object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
g_free(name);
}
}
/* This should be a 9215 but the 9118 is close enough */
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], "lan9118");
- dev = qdev_create(NULL, TYPE_LAN9118);
+ dev = qdev_new(TYPE_LAN9118);
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_prop_set_uint32(dev, "mode_16bit", 1);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
exynos4_boards_init_ram(s, get_system_memory(),
exynos4_board_ram_size[board_type]);
- sysbus_init_child_obj(OBJECT(machine), "soc",
- &s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_fatal);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
+ TYPE_EXYNOS4210_SOC);
+ sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
return s;
}
FslIMX25State *s = FSL_IMX25(obj);
int i;
- object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
- ARM_CPU_TYPE_NAME("arm926"),
- &error_abort, NULL);
+ object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm926"));
- sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
- TYPE_IMX_AVIC);
+ object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC);
- sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM);
+ object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX25_CCM);
for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
- sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
- TYPE_IMX_SERIAL);
+ object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL);
}
for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
- sysbus_init_child_obj(obj, "gpt[*]", &s->gpt[i], sizeof(s->gpt[i]),
- TYPE_IMX25_GPT);
+ object_initialize_child(obj, "gpt[*]", &s->gpt[i], TYPE_IMX25_GPT);
}
for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
- sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
- TYPE_IMX_EPIT);
+ object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT);
}
- sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC);
+ object_initialize_child(obj, "fec", &s->fec, TYPE_IMX_FEC);
- sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc),
- TYPE_IMX_RNGC);
+ object_initialize_child(obj, "rngc", &s->rngc, TYPE_IMX_RNGC);
for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
- sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
- TYPE_IMX_I2C);
+ object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C);
}
for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
- sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
- TYPE_IMX_GPIO);
+ object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO);
}
for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
- sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
- TYPE_IMX_USDHC);
+ object_initialize_child(obj, "sdhc[*]", &s->esdhc[i], TYPE_IMX_USDHC);
}
for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
- sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]),
- TYPE_CHIPIDEA);
+ object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_CHIPIDEA);
}
- sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT);
+ object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT);
}
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
uint8_t i;
Error *err = NULL;
- object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
+ qdev_realize(DEVICE(&s->cpu), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->avic), &err);
if (err) {
error_propagate(errp, err);
return;
sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
- object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err);
if (err) {
error_propagate(errp, err);
return;
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
- object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
if (err) {
error_propagate(errp, err);
return;
s->gpt[i].ccm = IMX_CCM(&s->ccm);
- object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &err);
if (err) {
error_propagate(errp, err);
return;
s->epit[i].ccm = IMX_CCM(&s->ccm);
- object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err);
if (err) {
error_propagate(errp, err);
return;
qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
- object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->fec), &err);
if (err) {
error_propagate(errp, err);
return;
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
- object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->rngc), &err);
if (err) {
error_propagate(errp, err);
return;
{ FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
};
- object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err);
if (err) {
error_propagate(errp, err);
return;
{ FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
};
- object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err);
if (err) {
error_propagate(errp, err);
return;
&err);
object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
"capareg", &err);
- object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err);
if (err) {
error_propagate(errp, err);
return;
{ FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
};
- object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
qdev_get_gpio_in(DEVICE(&s->avic),
/* Watchdog */
object_property_set_bool(OBJECT(&s->wdt), true, "pretimeout-support",
&error_abort);
- object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0,
qdev_get_gpio_in(DEVICE(&s->avic),
FslIMX31State *s = FSL_IMX31(obj);
int i;
- object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
- ARM_CPU_TYPE_NAME("arm1136"),
- &error_abort, NULL);
+ object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm1136"));
- sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
- TYPE_IMX_AVIC);
+ object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC);
- sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM);
+ object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX31_CCM);
for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
- sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
- TYPE_IMX_SERIAL);
+ object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL);
}
- sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT);
+ object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX31_GPT);
for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
- sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
- TYPE_IMX_EPIT);
+ object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT);
}
for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
- sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
- TYPE_IMX_I2C);
+ object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C);
}
for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
- sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
- TYPE_IMX_GPIO);
+ object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO);
}
- sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT);
+ object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT);
}
static void fsl_imx31_realize(DeviceState *dev, Error **errp)
uint16_t i;
Error *err = NULL;
- object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
+ qdev_realize(DEVICE(&s->cpu), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->avic), &err);
if (err) {
error_propagate(errp, err);
return;
sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
- object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err);
if (err) {
error_propagate(errp, err);
return;
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
- object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
if (err) {
error_propagate(errp, err);
return;
s->gpt.ccm = IMX_CCM(&s->ccm);
- object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpt), &err);
if (err) {
error_propagate(errp, err);
return;
s->epit[i].ccm = IMX_CCM(&s->ccm);
- object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err);
if (err) {
error_propagate(errp, err);
return;
};
/* Initialize the I2C */
- object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err);
if (err) {
error_propagate(errp, err);
return;
object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
&error_abort);
- object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err);
if (err) {
error_propagate(errp, err);
return;
}
/* Watchdog */
- object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR);
/* On a real system, the first 16k is a `secure boot rom' */
for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
snprintf(name, NAME_SIZE, "cpu%d", i);
- object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
- ARM_CPU_TYPE_NAME("cortex-a9"),
- &error_abort, NULL);
+ object_initialize_child(obj, name, &s->cpu[i],
+ ARM_CPU_TYPE_NAME("cortex-a9"));
}
- sysbus_init_child_obj(obj, "a9mpcore", &s->a9mpcore, sizeof(s->a9mpcore),
- TYPE_A9MPCORE_PRIV);
+ object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
- sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM);
+ object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM);
- sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC);
+ object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
snprintf(name, NAME_SIZE, "uart%d", i + 1);
- sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
- TYPE_IMX_SERIAL);
+ object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
}
- sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT);
+ object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT);
for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
snprintf(name, NAME_SIZE, "epit%d", i + 1);
- sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]),
- TYPE_IMX_EPIT);
+ object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
}
for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
- sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
- TYPE_IMX_I2C);
+ object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
}
for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
snprintf(name, NAME_SIZE, "gpio%d", i + 1);
- sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
- TYPE_IMX_GPIO);
+ object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
}
for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
- sysbus_init_child_obj(obj, name, &s->esdhc[i], sizeof(s->esdhc[i]),
- TYPE_IMX_USDHC);
+ object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC);
}
for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
snprintf(name, NAME_SIZE, "usbphy%d", i);
- sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
- TYPE_IMX_USBPHY);
+ object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
}
for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
snprintf(name, NAME_SIZE, "usb%d", i);
- sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
- TYPE_CHIPIDEA);
+ object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
}
for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
snprintf(name, NAME_SIZE, "spi%d", i + 1);
- sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
- TYPE_IMX_SPI);
+ object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
}
for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
snprintf(name, NAME_SIZE, "wdt%d", i);
- sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
- TYPE_IMX2_WDT);
+ object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
}
- sysbus_init_child_obj(obj, "eth", &s->eth, sizeof(s->eth), TYPE_IMX_ENET);
+ object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
}
static void fsl_imx6_realize(DeviceState *dev, Error **errp)
"start-powered-off", &error_abort);
}
- object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
+ qdev_realize(DEVICE(&s->cpu[i]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq",
&error_abort);
- object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &err);
if (err) {
error_propagate(errp, err);
return;
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
}
- object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
- object_property_set_bool(OBJECT(&s->src), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->src), &err);
if (err) {
error_propagate(errp, err);
return;
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
- object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
if (err) {
error_propagate(errp, err);
return;
s->gpt.ccm = IMX_CCM(&s->ccm);
- object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpt), &err);
if (err) {
error_propagate(errp, err);
return;
s->epit[i].ccm = IMX_CCM(&s->ccm);
- object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err);
if (err) {
error_propagate(errp, err);
return;
{ FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
};
- object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err);
if (err) {
error_propagate(errp, err);
return;
&error_abort);
object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq",
&error_abort);
- object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err);
if (err) {
error_propagate(errp, err);
return;
&err);
object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES,
"capareg", &err);
- object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err);
if (err) {
error_propagate(errp, err);
return;
/* USB */
for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
- object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
}
FSL_IMX6_USB_HOST3_IRQ,
};
- object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
};
/* Initialize the SPI */
- object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
if (err) {
error_propagate(errp, err);
return;
}
qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
- object_property_set_bool(OBJECT(&s->eth), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->eth), &err);
if (err) {
error_propagate(errp, err);
return;
object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
&error_abort);
- object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
char name[NAME_SIZE];
int i;
- object_initialize_child(obj, "cpu0", &s->cpu, sizeof(s->cpu),
- ARM_CPU_TYPE_NAME("cortex-a7"), &error_abort, NULL);
+ object_initialize_child(obj, "cpu0", &s->cpu,
+ ARM_CPU_TYPE_NAME("cortex-a7"));
/*
* A7MPCORE
*/
- sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore),
- TYPE_A15MPCORE_PRIV);
+ object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
+ TYPE_A15MPCORE_PRIV);
/*
* CCM
*/
- sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6UL_CCM);
+ object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6UL_CCM);
/*
* SRC
*/
- sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC);
+ object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
/*
* GPCv2
*/
- sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2),
- TYPE_IMX_GPCV2);
+ object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
/*
* SNVS
*/
- sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs),
- TYPE_IMX7_SNVS);
+ object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
/*
* GPR
*/
- sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr),
- TYPE_IMX7_GPR);
+ object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
/*
* GPIOs 1 to 5
*/
for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
snprintf(name, NAME_SIZE, "gpio%d", i);
- sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
- TYPE_IMX_GPIO);
+ object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
}
/*
*/
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
snprintf(name, NAME_SIZE, "gpt%d", i);
- sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]),
- TYPE_IMX7_GPT);
+ object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
}
/*
*/
for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
snprintf(name, NAME_SIZE, "epit%d", i + 1);
- sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]),
- TYPE_IMX_EPIT);
+ object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
}
/*
*/
for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
snprintf(name, NAME_SIZE, "spi%d", i + 1);
- sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
- TYPE_IMX_SPI);
+ object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
}
/*
*/
for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
- sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
- TYPE_IMX_I2C);
+ object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
}
/*
*/
for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
snprintf(name, NAME_SIZE, "uart%d", i);
- sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
- TYPE_IMX_SERIAL);
+ object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
}
/*
*/
for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
snprintf(name, NAME_SIZE, "eth%d", i);
- sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]),
- TYPE_IMX_ENET);
+ object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
}
/* USB */
for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
snprintf(name, NAME_SIZE, "usbphy%d", i);
- sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
- TYPE_IMX_USBPHY);
+ object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
}
for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
snprintf(name, NAME_SIZE, "usb%d", i);
- sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
- TYPE_CHIPIDEA);
+ object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
}
/*
*/
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
snprintf(name, NAME_SIZE, "usdhc%d", i);
- sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]),
- TYPE_IMX_USDHC);
+ object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
}
/*
*/
for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
snprintf(name, NAME_SIZE, "wdt%d", i);
- sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
- TYPE_IMX2_WDT);
+ object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
}
}
object_property_set_int(OBJECT(&s->cpu), QEMU_PSCI_CONDUIT_SMC,
"psci-conduit", &error_abort);
- object_property_set_bool(OBJECT(&s->cpu), true,
- "realized", &error_abort);
+ qdev_realize(DEVICE(&s->cpu), NULL, &error_abort);
/*
* A7MPCORE
object_property_set_int(OBJECT(&s->a7mpcore),
FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL,
"num-irq", &error_abort);
- object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
sbd = SYS_BUS_DEVICE(&s->a7mpcore);
};
s->gpt[i].ccm = IMX_CCM(&s->ccm);
- object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0,
FSL_IMX6UL_GPTn_ADDR[i]);
};
s->epit[i].ccm = IMX_CCM(&s->ccm);
- object_property_set_bool(OBJECT(&s->epit[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0,
FSL_IMX6UL_EPITn_ADDR[i]);
FSL_IMX6UL_GPIO5_HIGH_IRQ,
};
- object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
FSL_IMX6UL_GPIOn_ADDR[i]);
/*
* CCM
*/
- object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR);
/*
* SRC
*/
- object_property_set_bool(OBJECT(&s->src), true, "realized", &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR);
/*
* GPCv2
*/
- object_property_set_bool(OBJECT(&s->gpcv2), true,
- "realized", &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
/* Initialize all ECSPI */
};
/* Initialize the SPI */
- object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
FSL_IMX6UL_SPIn_ADDR[i]);
FSL_IMX6UL_I2C4_IRQ,
};
- object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
- object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0,
FSL_IMX6UL_UARTn_ADDR[i]);
FSL_IMX6UL_ETH_NUM_TX_RINGS,
"tx-ring-num", &error_abort);
qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
- object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0,
FSL_IMX6UL_ENETn_ADDR[i]);
/* USB */
for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
- object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
}
FSL_IMX6UL_USB1_IRQ,
FSL_IMX6UL_USB2_IRQ,
};
- object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX6UL_USDHC2_IRQ,
};
- object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
FSL_IMX6UL_USDHCn_ADDR[i]);
/*
* SNVS
*/
- object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
/*
object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
&error_abort);
- object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
FSL_IMX6UL_WDOGn_ADDR[i]);
/*
* GPR
*/
- object_property_set_bool(OBJECT(&s->gpr), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
/*
for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
snprintf(name, NAME_SIZE, "cpu%d", i);
- object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
- ARM_CPU_TYPE_NAME("cortex-a7"), &error_abort,
- NULL);
+ object_initialize_child(obj, name, &s->cpu[i],
+ ARM_CPU_TYPE_NAME("cortex-a7"));
}
/*
* A7MPCORE
*/
- sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore),
- TYPE_A15MPCORE_PRIV);
+ object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
+ TYPE_A15MPCORE_PRIV);
/*
* GPIOs 1 to 7
*/
for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
snprintf(name, NAME_SIZE, "gpio%d", i);
- sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
- TYPE_IMX_GPIO);
+ object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
}
/*
*/
for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
snprintf(name, NAME_SIZE, "gpt%d", i);
- sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]),
- TYPE_IMX7_GPT);
+ object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
}
/*
* CCM
*/
- sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX7_CCM);
+ object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX7_CCM);
/*
* Analog
*/
- sysbus_init_child_obj(obj, "analog", &s->analog, sizeof(s->analog),
- TYPE_IMX7_ANALOG);
+ object_initialize_child(obj, "analog", &s->analog, TYPE_IMX7_ANALOG);
/*
* GPCv2
*/
- sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2),
- TYPE_IMX_GPCV2);
+ object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
snprintf(name, NAME_SIZE, "spi%d", i + 1);
- sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
- TYPE_IMX_SPI);
+ object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
}
for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
- sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
- TYPE_IMX_I2C);
+ object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
}
/*
*/
for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
snprintf(name, NAME_SIZE, "uart%d", i);
- sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
- TYPE_IMX_SERIAL);
+ object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
}
/*
*/
for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
snprintf(name, NAME_SIZE, "eth%d", i);
- sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]),
- TYPE_IMX_ENET);
+ object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
}
/*
*/
for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
snprintf(name, NAME_SIZE, "usdhc%d", i);
- sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]),
- TYPE_IMX_USDHC);
+ object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
}
/*
* SNVS
*/
- sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs),
- TYPE_IMX7_SNVS);
+ object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
/*
* Watchdog
*/
for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
snprintf(name, NAME_SIZE, "wdt%d", i);
- sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
- TYPE_IMX2_WDT);
+ object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
}
/*
* GPR
*/
- sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr), TYPE_IMX7_GPR);
+ object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
- sysbus_init_child_obj(obj, "pcie", &s->pcie, sizeof(s->pcie),
- TYPE_DESIGNWARE_PCIE_HOST);
+ object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
snprintf(name, NAME_SIZE, "usb%d", i);
- sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
- TYPE_CHIPIDEA);
+ object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
}
}
"start-powered-off", &error_abort);
}
- object_property_set_bool(o, true, "realized", &error_abort);
+ qdev_realize(DEVICE(o), NULL, &error_abort);
}
/*
FSL_IMX7_MAX_IRQ + GIC_INTERNAL,
"num-irq", &error_abort);
- object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
for (i = 0; i < smp_cpus; i++) {
};
s->gpt[i].ccm = IMX_CCM(&s->ccm);
- object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
}
FSL_IMX7_GPIO7_ADDR,
};
- object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
}
/*
* CCM
*/
- object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR);
/*
* Analog
*/
- object_property_set_bool(OBJECT(&s->analog), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->analog), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR);
/*
* GPCv2
*/
- object_property_set_bool(OBJECT(&s->gpcv2), true,
- "realized", &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
/* Initialize all ECSPI */
};
/* Initialize the SPI */
- object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
FSL_IMX7_SPIn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
FSL_IMX7_I2C4_IRQ,
};
- object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
- object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
object_property_set_uint(OBJECT(&s->eth[i]), FSL_IMX7_ETH_NUM_TX_RINGS,
"tx-ring-num", &error_abort);
qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
- object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
FSL_IMX7_USDHC3_IRQ,
};
- object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
FSL_IMX7_USDHCn_ADDR[i]);
/*
* SNVS
*/
- object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
/*
object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
&error_abort);
- object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
FSL_IMX7_OCOTP_SIZE);
- object_property_set_bool(OBJECT(&s->gpr), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
- object_property_set_bool(OBJECT(&s->pcie), true,
- "realized", &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ);
FSL_IMX7_USB3_IRQ,
};
- object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX7_USBn_ADDR[i]);
object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
"reset-cbar", &error_abort);
}
- object_property_set_bool(cpuobj, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ);
switch (machine_id) {
case CALXEDA_HIGHBANK:
- dev = qdev_create(NULL, "l2x0");
- qdev_init_nofail(dev);
+ dev = qdev_new("l2x0");
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xfff12000);
- dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
+ dev = qdev_new(TYPE_A9MPCORE_PRIV);
break;
case CALXEDA_MIDWAY:
- dev = qdev_create(NULL, TYPE_A15MPCORE_PRIV);
+ dev = qdev_new(TYPE_A15MPCORE_PRIV);
break;
}
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
for (n = 0; n < smp_cpus; n++) {
sysbus_connect_irq(busdev, n, cpu_irq[n]);
pic[n] = qdev_get_gpio_in(dev, n);
}
- dev = qdev_create(NULL, "sp804");
+ dev = qdev_new("sp804");
qdev_prop_set_uint32(dev, "freq0", 150000000);
qdev_prop_set_uint32(dev, "freq1", 150000000);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xfff34000);
sysbus_connect_irq(busdev, 0, pic[18]);
pl011_create(0xfff36000, pic[20], serial_hd(0));
- dev = qdev_create(NULL, TYPE_HIGHBANK_REGISTERS);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_HIGHBANK_REGISTERS);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xfff3c000);
sysbus_create_simple("pl061", 0xfff30000, pic[14]);
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], "xgmac");
- dev = qdev_create(NULL, "xgmac");
+ dev = qdev_new("xgmac");
qdev_set_nic_properties(dev, &nd_table[0]);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
qemu_check_nic_model(&nd_table[1], "xgmac");
- dev = qdev_create(NULL, "xgmac");
+ dev = qdev_new("xgmac");
qdev_set_nic_properties(dev, &nd_table[1]);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
unsigned int alias_offset;
int i;
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_FSL_IMX25, &error_abort, NULL);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_FSL_IMX25);
- object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
+ qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
/* We need to initialize our memory */
if (machine->ram_size > (FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE)) {
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus");
- carddev = qdev_create(bus, TYPE_SD_CARD);
+ carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true,
- "realized", &error_fatal);
+ qdev_realize_and_unref(carddev, bus, &error_fatal);
}
/*
object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
}
- object_property_set_bool(cpuobj, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
cpu = ARM_CPU(cpuobj);
0, ram_size);
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
- dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
+ dev = qdev_new(TYPE_INTEGRATOR_CM);
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
unsigned int alias_offset;
unsigned int i;
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_FSL_IMX31, &error_abort, NULL);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_FSL_IMX31);
- object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
+ qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
/* Check the amount of memory is compatible with the SOC */
if (machine->ram_size > (FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE)) {
s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL));
object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
- object_property_set_bool(OBJECT(s), true, "realized", &error_fatal);
+ qdev_realize(DEVICE(s), NULL, &error_fatal);
memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR,
machine->ram);
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus");
- carddev = qdev_create(bus, TYPE_SD_CARD);
+ carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true,
- "realized", &error_fatal);
+ qdev_realize_and_unref(carddev, bus, &error_fatal);
}
if (!qtest_enabled()) {
s = FSL_IMX7(object_new(TYPE_FSL_IMX7));
object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
- object_property_set_bool(OBJECT(s), true, "realized", &error_fatal);
+ qdev_realize(DEVICE(s), NULL, &error_fatal);
memory_region_add_subregion(get_system_memory(), FSL_IMX7_MMDC_ADDR,
machine->ram);
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus");
- carddev = qdev_create(bus, TYPE_SD_CARD);
+ carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true,
- "realized", &error_fatal);
+ qdev_realize_and_unref(carddev, bus, &error_fatal);
}
if (!qtest_enabled()) {
MicrobitMachineState *s = MICROBIT_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mr;
- Object *soc = OBJECT(&s->nrf51);
- Object *i2c = OBJECT(&s->i2c);
- sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51),
- TYPE_NRF51_SOC);
+ object_initialize_child(OBJECT(machine), "nrf51", &s->nrf51,
+ TYPE_NRF51_SOC);
qdev_prop_set_chr(DEVICE(&s->nrf51), "serial0", serial_hd(0));
- object_property_set_link(soc, OBJECT(system_memory), "memory",
- &error_fatal);
- object_property_set_bool(soc, true, "realized", &error_fatal);
+ object_property_set_link(OBJECT(&s->nrf51), OBJECT(system_memory),
+ "memory", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&s->nrf51), &error_fatal);
/*
* Overlap the TWI stub device into the SoC. This is a microbit-specific
* hack until we implement the nRF51 TWI controller properly and the
* magnetometer/accelerometer devices.
*/
- sysbus_init_child_obj(OBJECT(machine), "microbit.twi", i2c,
- sizeof(s->i2c), TYPE_MICROBIT_I2C);
- object_property_set_bool(i2c, true, "realized", &error_fatal);
- mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(i2c), 0);
+ object_initialize_child(OBJECT(machine), "microbit.twi", &s->i2c,
+ TYPE_MICROBIT_I2C);
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &error_fatal);
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0);
memory_region_add_subregion_overlap(&s->nrf51.container, NRF51_TWI_BASE,
mr, -1);
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
- NRF51_SOC(soc)->flash_size);
+ s->nrf51.flash_size);
}
static void microbit_machine_class_init(ObjectClass *oc, void *data)
*/
UnimplementedDeviceState *uds = opaque;
- sysbus_init_child_obj(OBJECT(mms), name, uds,
- sizeof(UnimplementedDeviceState),
- TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(DEVICE(uds), "name", name);
qdev_prop_set_uint64(DEVICE(uds), "size", size);
- object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
}
SysBusDevice *s;
DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
- sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]),
- TYPE_CMSDK_APB_UART);
+ object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART);
qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);
- object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
s = SYS_BUS_DEVICE(uart);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno));
sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno));
DeviceState *sccdev;
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
- sysbus_init_child_obj(OBJECT(mms), "scc", scc,
- sizeof(mms->scc), TYPE_MPS2_SCC);
+ object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC);
sccdev = DEVICE(scc);
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
- object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal);
return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
}
{
MPS2FPGAIO *fpgaio = opaque;
- sysbus_init_child_obj(OBJECT(mms), "fpgaio", fpgaio,
- sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO);
- object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal);
+ object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO);
+ sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal);
return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0);
}
* except that it doesn't support the checksum-offload feature.
*/
qemu_check_nic_model(nd, "lan9118");
- mms->lan9118 = qdev_create(NULL, TYPE_LAN9118);
+ mms->lan9118 = qdev_new(TYPE_LAN9118);
qdev_set_nic_properties(mms->lan9118, nd);
- qdev_init_nofail(mms->lan9118);
s = SYS_BUS_DEVICE(mms->lan9118);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16));
return sysbus_mmio_get_region(s, 0);
}
memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);
- sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]),
- TYPE_TZ_MPC);
+ object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC);
object_property_set_link(OBJECT(mpc), OBJECT(ssram),
"downstream", &error_fatal);
- object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal);
/* Map the upstream end of the MPC into system memory */
upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
memory_region_add_subregion(get_system_memory(), rambase[i], upstream);
* the MSC connects to the IoTKit AHB Slave Expansion port, so the
* DMA devices can see all devices and memory that the CPU does.
*/
- sysbus_init_child_obj(OBJECT(mms), mscname, msc, sizeof(*msc), TYPE_TZ_MSC);
+ object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC);
msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0);
object_property_set_link(OBJECT(msc), OBJECT(msc_downstream),
"downstream", &error_fatal);
object_property_set_link(OBJECT(msc), OBJECT(mms),
"idau", &error_fatal);
- object_property_set_bool(OBJECT(msc), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal);
qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0,
qdev_get_gpio_in_named(iotkitdev,
"cfg_sec_resp", 0));
msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0);
- sysbus_init_child_obj(OBJECT(mms), name, dma, sizeof(*dma), TYPE_PL081);
+ object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081);
object_property_set_link(OBJECT(dma), OBJECT(msc_upstream),
"downstream", &error_fatal);
- object_property_set_bool(OBJECT(dma), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal);
s = SYS_BUS_DEVICE(dma);
/* Wire up DMACINTR, DMACINTERR, DMACINTTC */
int i = spi - &mms->spi[0];
SysBusDevice *s;
- sysbus_init_child_obj(OBJECT(mms), name, spi, sizeof(mms->spi[0]),
- TYPE_PL022);
- object_property_set_bool(OBJECT(spi), true, "realized", &error_fatal);
+ object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022);
+ sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal);
s = SYS_BUS_DEVICE(spi);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i));
return sysbus_mmio_get_region(s, 0);
exit(EXIT_FAILURE);
}
- sysbus_init_child_obj(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
- sizeof(mms->iotkit), mmc->armsse_type);
+ object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
+ mmc->armsse_type);
iotkitdev = DEVICE(&mms->iotkit);
object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
"memory", &error_abort);
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ);
- object_property_set_bool(OBJECT(&mms->iotkit), true, "realized",
- &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
/*
* The AN521 needs us to create splitters to feed the IRQ inputs
char *name = g_strdup_printf("mps2-irq-splitter%d", i);
SplitIRQ *splitter = &mms->cpu_irq_splitter[i];
- object_initialize_child(OBJECT(machine), name,
- splitter, sizeof(*splitter),
- TYPE_SPLIT_IRQ, &error_fatal, NULL);
+ object_initialize_child_with_props(OBJECT(machine), name,
+ splitter, sizeof(*splitter),
+ TYPE_SPLIT_IRQ, &error_fatal,
+ NULL);
g_free(name);
object_property_set_int(OBJECT(splitter), 2, "num-lines",
&error_fatal);
- object_property_set_bool(OBJECT(splitter), true, "realized",
- &error_fatal);
+ qdev_realize(DEVICE(splitter), NULL, &error_fatal);
qdev_connect_gpio_out(DEVICE(splitter), 0,
qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
"EXP_IRQ", i));
* lines, one for each of the PPCs we create here, plus one per MSC.
*/
object_initialize_child(OBJECT(machine), "sec-resp-splitter",
- &mms->sec_resp_splitter,
- sizeof(mms->sec_resp_splitter),
- TYPE_SPLIT_IRQ, &error_abort, NULL);
+ &mms->sec_resp_splitter, TYPE_SPLIT_IRQ);
object_property_set_int(OBJECT(&mms->sec_resp_splitter),
ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc),
"num-lines", &error_fatal);
- object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true,
- "realized", &error_fatal);
+ qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal);
dev_splitter = DEVICE(&mms->sec_resp_splitter);
qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0,
qdev_get_gpio_in(dev_splitter, 0));
* Create the OR gate for this.
*/
object_initialize_child(OBJECT(mms), "uart-irq-orgate",
- &mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate),
- TYPE_OR_IRQ, &error_abort, NULL);
+ &mms->uart_irq_orgate, TYPE_OR_IRQ);
object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines",
&error_fatal);
- object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true,
- "realized", &error_fatal);
+ qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal);
qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,
get_sse_irq_in(mms, 15));
int port;
char *gpioname;
- sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc,
- sizeof(TZPPC), TYPE_TZ_PPC);
+ object_initialize_child(OBJECT(machine), ppcinfo->name, ppc,
+ TYPE_TZ_PPC);
ppcdev = DEVICE(ppc);
for (port = 0; port < TZ_NUM_PORTS; port++) {
g_free(portname);
}
- object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal);
for (port = 0; port < TZ_NUM_PORTS; port++) {
const PPCPortInfo *pinfo = &ppcinfo->ports[port];
g_assert_not_reached();
}
- sysbus_init_child_obj(OBJECT(mms), "armv7m", &mms->armv7m,
- sizeof(mms->armv7m), TYPE_ARMV7M);
+ object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M);
armv7m = DEVICE(&mms->armv7m);
switch (mmc->fpga_type) {
case FPGA_AN385:
qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
"memory", &error_abort);
- object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
- &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal);
create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
orgate = object_new(TYPE_OR_IRQ);
object_property_set_int(orgate, 6, "num-lines", &error_fatal);
- object_property_set_bool(orgate, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(orgate), NULL, &error_fatal);
orgate_dev = DEVICE(orgate);
qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
orgate = object_new(TYPE_OR_IRQ);
object_property_set_int(orgate, 10, "num-lines", &error_fatal);
- object_property_set_bool(orgate, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(orgate), NULL, &error_fatal);
orgate_dev = DEVICE(orgate);
qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
txrx_orgate = object_new(TYPE_OR_IRQ);
object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal);
- object_property_set_bool(txrx_orgate, true, "realized",
- &error_fatal);
+ qdev_realize(DEVICE(txrx_orgate), NULL, &error_fatal);
txrx_orgate_dev = DEVICE(txrx_orgate);
qdev_connect_gpio_out(txrx_orgate_dev, 0,
qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
- sysbus_init_child_obj(OBJECT(mms), "dualtimer", &mms->dualtimer,
- sizeof(mms->dualtimer), TYPE_CMSDK_APB_DUALTIMER);
+ object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
+ TYPE_CMSDK_APB_DUALTIMER);
qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
- object_property_set_bool(OBJECT(&mms->dualtimer), true, "realized",
- &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
qdev_get_gpio_in(armv7m, 10));
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
- sysbus_init_child_obj(OBJECT(mms), "scc", &mms->scc,
- sizeof(mms->scc), TYPE_MPS2_SCC);
+ object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
sccdev = DEVICE(&mms->scc);
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
- object_property_set_bool(OBJECT(&mms->scc), true, "realized",
- &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
/* In hardware this is a LAN9220; the LAN9118 is software compatible
MSF2State *s = MSF2_SOC(obj);
int i;
- sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
- TYPE_ARMV7M);
+ object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
- sysbus_init_child_obj(obj, "sysreg", &s->sysreg, sizeof(s->sysreg),
- TYPE_MSF2_SYSREG);
+ object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG);
- sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
- TYPE_MSS_TIMER);
+ object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER);
for (i = 0; i < MSF2_NUM_SPIS; i++) {
- sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
- TYPE_MSS_SPI);
+ object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI);
}
- sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
- TYPE_MSS_EMAC);
+ object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC);
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC);
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
"memory", &error_abort);
- object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
dev = DEVICE(&s->timer);
/* APB0 clock is the timer input clock */
qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
- object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->timer), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
dev = DEVICE(&s->sysreg);
qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
- object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
for (i = 0; i < MSF2_NUM_SPIS; i++) {
gchar *bus_name;
- object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
dev = DEVICE(&s->emac);
object_property_set_link(OBJECT(&s->emac), OBJECT(get_system_memory()),
"ahb-bus", &error_abort);
- object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->emac), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
MachineClass *mc = MACHINE_GET_CLASS(machine);
DriveInfo *dinfo = drive_get_next(IF_MTD);
qemu_irq cs_line;
- SSIBus *spi_bus;
+ BusState *spi_bus;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ddr = g_new(MemoryRegion, 1);
&error_fatal);
memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
- dev = qdev_create(NULL, TYPE_MSF2_SOC);
+ dev = qdev_new(TYPE_MSF2_SOC);
qdev_prop_set_string(dev, "part-name", "M2S010");
qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type);
qdev_prop_set_uint32(dev, "apb0div", 2);
qdev_prop_set_uint32(dev, "apb1div", 2);
- object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
soc = MSF2_SOC(dev);
/* Attach SPI flash to SPI0 controller */
- spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
- spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
+ spi_bus = qdev_get_child_bus(dev, "spi0");
+ spi_flash = qdev_new("s25sl12801");
qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
if (dinfo) {
qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
- qdev_init_nofail(spi_flash);
+ qdev_realize_and_unref(spi_flash, spi_bus, &error_fatal);
cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
*/
UnimplementedDeviceState *uds = opaque;
- sysbus_init_child_obj(OBJECT(mms), name, uds,
- sizeof(UnimplementedDeviceState),
- TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(DEVICE(uds), "name", name);
qdev_prop_set_uint64(DEVICE(uds), "size", size);
- object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
}
case MPC_CRYPTOISLAND:
/* We don't implement the CryptoIsland yet */
uds = &mms->cryptoisland;
- sysbus_init_child_obj(OBJECT(mms), name, uds,
- sizeof(UnimplementedDeviceState),
- TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(OBJECT(mms), name, uds,
+ TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(DEVICE(uds), "name", mpcinfo[i].name);
qdev_prop_set_uint64(DEVICE(uds), "size", mpcinfo[i].size);
- object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
break;
default:
g_assert_not_reached();
}
- sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->mpc[0]),
- TYPE_TZ_MPC);
+ object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC);
object_property_set_link(OBJECT(mpc), OBJECT(downstream),
"downstream", &error_fatal);
- object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal);
/* Map the upstream end of the MPC into system memory */
upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
memory_region_add_subregion(get_system_memory(), mpcinfo[i].addr, upstream);
{
PL031State *rtc = opaque;
- sysbus_init_child_obj(OBJECT(mms), name, rtc, sizeof(mms->rtc), TYPE_PL031);
- object_property_set_bool(OBJECT(rtc), true, "realized", &error_fatal);
+ object_initialize_child(OBJECT(mms), name, rtc, TYPE_PL031);
+ sysbus_realize(SYS_BUS_DEVICE(rtc), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(rtc), 0, get_sse_irq_in(mms, 39));
return sysbus_mmio_get_region(SYS_BUS_DEVICE(rtc), 0);
}
int irqbase = 7 + i * 6;
SysBusDevice *s;
- sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]),
- TYPE_PL011);
+ object_initialize_child(OBJECT(mms), name, uart, TYPE_PL011);
qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
- object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
s = SYS_BUS_DEVICE(uart);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqbase + 5)); /* combined */
sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqbase + 0)); /* RX */
exit(1);
}
- sysbus_init_child_obj(OBJECT(machine), "sse-200", &mms->sse,
- sizeof(mms->sse), TYPE_SSE200);
+ object_initialize_child(OBJECT(machine), "sse-200", &mms->sse,
+ TYPE_SSE200);
ssedev = DEVICE(&mms->sse);
object_property_set_link(OBJECT(&mms->sse), OBJECT(system_memory),
"memory", &error_fatal);
qdev_prop_set_bit(ssedev, "CPU0_FPU", true);
qdev_prop_set_bit(ssedev, "CPU0_DSP", true);
}
- object_property_set_bool(OBJECT(&mms->sse), true, "realized",
- &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&mms->sse), &error_fatal);
/*
* We need to create splitters to feed the IRQ inputs
char *name = g_strdup_printf("musca-irq-splitter%d", i);
SplitIRQ *splitter = &mms->cpu_irq_splitter[i];
- object_initialize_child(OBJECT(machine), name,
- splitter, sizeof(*splitter),
- TYPE_SPLIT_IRQ, &error_fatal, NULL);
+ object_initialize_child_with_props(OBJECT(machine), name, splitter,
+ sizeof(*splitter), TYPE_SPLIT_IRQ,
+ &error_fatal, NULL);
g_free(name);
object_property_set_int(OBJECT(splitter), 2, "num-lines",
&error_fatal);
- object_property_set_bool(OBJECT(splitter), true, "realized",
- &error_fatal);
+ qdev_realize(DEVICE(splitter), NULL, &error_fatal);
qdev_connect_gpio_out(DEVICE(splitter), 0,
qdev_get_gpio_in_named(ssedev, "EXP_IRQ", i));
qdev_connect_gpio_out(DEVICE(splitter), 1,
* The sec_resp_cfg output from the SSE-200 must be split into multiple
* lines, one for each of the PPCs we create here.
*/
- object_initialize_child(OBJECT(machine), "sec-resp-splitter",
- &mms->sec_resp_splitter,
- sizeof(mms->sec_resp_splitter),
- TYPE_SPLIT_IRQ, &error_fatal, NULL);
+ object_initialize_child_with_props(OBJECT(machine), "sec-resp-splitter",
+ &mms->sec_resp_splitter,
+ sizeof(mms->sec_resp_splitter),
+ TYPE_SPLIT_IRQ, &error_fatal, NULL);
object_property_set_int(OBJECT(&mms->sec_resp_splitter),
ARRAY_SIZE(mms->ppc), "num-lines", &error_fatal);
- object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true,
- "realized", &error_fatal);
+ qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal);
dev_splitter = DEVICE(&mms->sec_resp_splitter);
qdev_connect_gpio_out_named(ssedev, "sec_resp_cfg", 0,
qdev_get_gpio_in(dev_splitter, 0));
int port;
char *gpioname;
- sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc,
- sizeof(TZPPC), TYPE_TZ_PPC);
+ object_initialize_child(OBJECT(machine), ppcinfo->name, ppc,
+ TYPE_TZ_PPC);
ppcdev = DEVICE(ppc);
for (port = 0; port < TZ_NUM_PORTS; port++) {
g_free(portname);
}
- object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal);
for (port = 0; port < TZ_NUM_PORTS; port++) {
const PPCPortInfo *pinfo = &ppcinfo->ports[port];
sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL);
qemu_check_nic_model(&nd_table[0], "mv88w8618");
- dev = qdev_create(NULL, TYPE_MV88W8618_ETH);
+ dev = qdev_new(TYPE_MV88W8618_ETH);
qdev_set_nic_properties(dev, &nd_table[0]);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
}
wm8750_dev = i2c_create_slave(i2c, TYPE_WM8750, MP_WM_ADDR);
- dev = qdev_create(NULL, TYPE_MV88W8618_AUDIO);
+ dev = qdev_new(TYPE_MV88W8618_AUDIO);
s = SYS_BUS_DEVICE(dev);
object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev),
"wm8750", NULL);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
{
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_STM32F205_SOC);
+ dev = qdev_new(TYPE_STM32F205_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
- object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
FLASH_SIZE);
{
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_STM32F405_SOC);
+ dev = qdev_new(TYPE_STM32F405_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
- object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu),
machine->kernel_filename,
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->cpu), &err);
if (err) {
error_propagate(errp, err);
return;
memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);
/* UART */
- object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->uart), &err);
if (err) {
error_propagate(errp, err);
return;
BASE_TO_IRQ(NRF51_UART_BASE)));
/* RNG */
- object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->rng), &err);
if (err) {
error_propagate(errp, err);
return;
return;
}
- object_property_set_bool(OBJECT(&s->nvm), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->nvm), &err);
if (err) {
error_propagate(errp, err);
return;
memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);
/* GPIO */
- object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err);
if (err) {
error_propagate(errp, err);
return;
memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
- sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu),
- TYPE_ARMV7M);
+ object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
ARM_CPU_TYPE_NAME("cortex-m0"));
qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
- sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
- TYPE_NRF51_UART);
+ object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
- sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng),
- TYPE_NRF51_RNG);
+ object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG);
- sysbus_init_child_obj(obj, "nvm", &s->nvm, sizeof(s->nvm), TYPE_NRF51_NVM);
+ object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM);
- sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
- TYPE_NRF51_GPIO);
+ object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO);
for (i = 0; i < NRF51_NUM_TIMERS; i++) {
- sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
- sizeof(s->timer[i]), TYPE_NRF51_TIMER);
+ object_initialize_child(obj, "timer[*]", &s->timer[i],
+ TYPE_NRF51_TIMER);
}
}
char *otp_region;
DriveInfo *dinfo;
- s->nand = qdev_create(NULL, "onenand");
+ s->nand = qdev_new("onenand");
qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
/* Either 0x40 or 0x48 are OK for the device ID */
qdev_prop_set_uint16(s->nand, "device_id", 0x48);
qdev_prop_set_drive(s->nand, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
- qdev_init_nofail(s->nand);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(s->nand), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
static void n8x0_usb_setup(struct n800_s *s)
{
SysBusDevice *dev;
- s->usb = qdev_create(NULL, "tusb6010");
+ s->usb = qdev_new("tusb6010");
dev = SYS_BUS_DEVICE(s->usb);
- qdev_init_nofail(s->usb);
+ sysbus_realize_and_unref(dev, &error_fatal);
sysbus_connect_irq(dev, 0,
qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
/* Using the NOR interface */
omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
- s->ih[0] = qdev_create(NULL, "omap-intc");
+ s->ih[0] = qdev_new("omap-intc");
qdev_prop_set_uint32(s->ih[0], "size", 0x100);
omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck"));
- qdev_init_nofail(s->ih[0]);
busdev = SYS_BUS_DEVICE(s->ih[0]);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
sysbus_connect_irq(busdev, 1,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
sysbus_mmio_map(busdev, 0, 0xfffecb00);
- s->ih[1] = qdev_create(NULL, "omap-intc");
+ s->ih[1] = qdev_new("omap-intc");
qdev_prop_set_uint32(s->ih[1], "size", 0x800);
omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck"));
- qdev_init_nofail(s->ih[1]);
busdev = SYS_BUS_DEVICE(s->ih[1]);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ));
/* The second interrupt controller's FIQ output is not wired up */
qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO),
s->wakeup, omap_findclk(s, "clk32-kHz"));
- s->gpio = qdev_create(NULL, "omap-gpio");
+ s->gpio = qdev_new("omap-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck"));
- qdev_init_nofail(s->gpio);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(s->gpio), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000);
s->pwt = omap_pwt_init(system_memory, 0xfffb6000,
omap_findclk(s, "armxor_ck"));
- s->i2c[0] = qdev_create(NULL, "omap_i2c");
+ s->i2c[0] = qdev_new("omap_i2c");
qdev_prop_set_uint8(s->i2c[0], "revision", 0x11);
omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck"));
- qdev_init_nofail(s->i2c[0]);
busdev = SYS_BUS_DEVICE(s->i2c[0]);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C));
sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]);
sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]);
s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
/* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
- s->ih[0] = qdev_create(NULL, "omap2-intc");
+ s->ih[0] = qdev_new("omap2-intc");
qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
omap_intc_set_fclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_fclk"));
omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_iclk"));
- qdev_init_nofail(s->ih[0]);
busdev = SYS_BUS_DEVICE(s->ih[0]);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
sysbus_connect_irq(busdev, 1,
omap_findclk(s, "clk32-kHz"),
omap_findclk(s, "core_l4_iclk"));
- s->i2c[0] = qdev_create(NULL, "omap_i2c");
+ s->i2c[0] = qdev_new("omap_i2c");
qdev_prop_set_uint8(s->i2c[0], "revision", 0x34);
omap_i2c_set_iclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.iclk"));
omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.fclk"));
- qdev_init_nofail(s->i2c[0]);
busdev = SYS_BUS_DEVICE(s->i2c[0]);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ));
sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]);
sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]);
sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0));
- s->i2c[1] = qdev_create(NULL, "omap_i2c");
+ s->i2c[1] = qdev_new("omap_i2c");
qdev_prop_set_uint8(s->i2c[1], "revision", 0x34);
omap_i2c_set_iclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.iclk"));
omap_i2c_set_fclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.fclk"));
- qdev_init_nofail(s->i2c[1]);
busdev = SYS_BUS_DEVICE(s->i2c[1]);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ));
sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]);
sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]);
sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0));
- s->gpio = qdev_create(NULL, "omap2-gpio");
+ s->gpio = qdev_new("omap2-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
omap2_gpio_set_iclk(OMAP2_GPIO(s->gpio), omap_findclk(s, "gpio_iclk"));
omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 0, omap_findclk(s, "gpio1_dbclk"));
omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 4,
omap_findclk(s, "gpio5_dbclk"));
}
- qdev_init_nofail(s->gpio);
busdev = SYS_BUS_DEVICE(s->gpio);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));
sysbus_connect_irq(busdev, 3,
&error_abort);
/* Mark H3 object realized */
- object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
+ qdev_realize(DEVICE(h3), NULL, &error_abort);
/* Retrieve SD bus */
di = drive_get_next(IF_SD);
bus = qdev_get_child_bus(DEVICE(h3), "sd-bus");
/* Plug in SD card */
- carddev = qdev_create(bus, TYPE_SD_CARD);
+ carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
+ qdev_realize_and_unref(carddev, bus, &error_fatal);
/* SDRAM */
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
PXA2xxI2CState *s;
I2CBus *i2cbus;
- dev = qdev_create(NULL, TYPE_PXA2XX_I2C);
+ dev = qdev_new(TYPE_PXA2XX_I2C);
qdev_prop_set_uint32(dev, "size", region_size + 1);
qdev_prop_set_uint32(dev, "offset", base & region_size);
- qdev_init_nofail(dev);
i2c_dev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(i2c_dev, &error_fatal);
sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
sysbus_connect_irq(i2c_dev, 0, irq);
DeviceState *dev;
SysBusDevice *sbd;
- dev = qdev_create(NULL, TYPE_PXA2XX_FIR);
+ dev = qdev_new(TYPE_PXA2XX_FIR);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
sbd = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbd, &error_fatal);
sysbus_mmio_map(sbd, 0, base);
sysbus_connect_irq(sbd, 0, irq);
sysbus_connect_irq(sbd, 1, rx_dma);
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/pxa.h"
+#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
CPUState *cs = CPU(cpu);
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
+ dev = qdev_new(TYPE_PXA2XX_GPIO);
qdev_prop_set_int32(dev, "lines", lines);
qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "qemu/module.h"
#include "cpu.h"
#include "hw/arm/pxa.h"
DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
{
- DeviceState *dev = qdev_create(NULL, TYPE_PXA2XX_PIC);
+ DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
PXA2xxPICState *s = PXA2XX_PIC(dev);
s->cpu = cpu;
s->is_fiq[0] = 0;
s->is_fiq[1] = 0;
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
machine->ram, 0);
/* Setup the SOC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- board_soc_type(board_rev), &error_abort, NULL);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
+ board_soc_type(board_rev));
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram));
object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev",
&error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort);
+ qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
/* Create and plug in the SD cards */
di = drive_get_next(IF_SD);
error_report("No SD bus found in SOC object");
exit(1);
}
- carddev = qdev_create(bus, TYPE_SD_CARD);
+ carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
+ qdev_realize_and_unref(carddev, bus, &error_fatal);
vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
&error_abort);
&error_fatal);
}
- object_property_set_bool(cpuobj, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
}
}
sys_id = is_pb ? 0x01780500 : 0xc1400400;
- sysctl = qdev_create(NULL, "realview_sysctl");
+ sysctl = qdev_new("realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
- qdev_init_nofail(sysctl);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
if (is_mpcore) {
- dev = qdev_create(NULL, is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
+ dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, periphbase);
for (n = 0; n < smp_cpus; n++) {
sysbus_connect_irq(busdev, n, cpu_irq[n]);
pic[n] = qdev_get_gpio_in(dev, n);
}
- pl041 = qdev_create(NULL, "pl041");
+ pl041 = qdev_new("pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
- qdev_init_nofail(pl041);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]);
pl011_create(0x1000c000, pic[15], serial_hd(3));
/* DMA controller is optional, apparently. */
- dev = qdev_create(NULL, "pl081");
+ dev = qdev_new("pl081");
object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",
&error_fatal);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10030000);
sysbus_connect_irq(busdev, 0, pic[24]);
sysbus_create_simple("pl031", 0x10017000, pic[10]);
if (!is_pb) {
- dev = qdev_create(NULL, "realview_pci");
+ dev = qdev_new("realview_pci");
busdev = SYS_BUS_DEVICE(dev);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */
sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */
sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */
s = FSL_IMX6(object_new(TYPE_FSL_IMX6));
object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
- object_property_set_bool(OBJECT(s), true, "realized", &error_fatal);
+ qdev_realize(DEVICE(s), NULL, &error_fatal);
memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
machine->ram);
qemu_irq cs_line;
DriveInfo *dinfo = drive_get_next(IF_MTD);
- flash_dev = ssi_create_slave_no_init(spi_bus, "sst25vf016b");
+ flash_dev = qdev_new("sst25vf016b");
if (dinfo) {
qdev_prop_set_drive(flash_dev, "drive",
blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
- qdev_init_nofail(flash_dev);
+ qdev_realize_and_unref(flash_dev, BUS(spi_bus), &error_fatal);
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line);
* Create a single flash device. We use the same parameters as
* the flash devices on the Versatile Express board.
*/
- DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
+ DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE);
qdev_prop_set_uint8(dev, "width", 4);
assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE));
assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX);
qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(sysmem, base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
gictype = gicv3_class_name();
- sms->gic = qdev_create(NULL, gictype);
+ sms->gic = qdev_new(gictype);
qdev_prop_set_uint32(sms->gic, "revision", 3);
qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus);
/*
qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
- qdev_init_nofail(sms->gic);
gicbusdev = SYS_BUS_DEVICE(sms->gic);
+ sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
{
hwaddr base = sbsa_ref_memmap[uart].base;
int irq = sbsa_ref_irqmap[uart];
- DeviceState *dev = qdev_create(NULL, TYPE_PL011);
+ DeviceState *dev = qdev_new(TYPE_PL011);
SysBusDevice *s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(mem, base,
sysbus_mmio_get_region(s, 0));
sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
AHCIState *ahci;
int i;
- dev = qdev_create(NULL, "sysbus-ahci");
+ dev = qdev_new("sysbus-ahci");
qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
DeviceState *dev;
int i;
- dev = qdev_create(NULL, "arm-smmuv3");
+ dev = qdev_new("arm-smmuv3");
object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
&error_abort);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < NUM_SMMU_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
PCIHostState *pci;
int i;
- dev = qdev_create(NULL, TYPE_GPEX_HOST);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_GPEX_HOST);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Map ECAM space */
ecam_alias = g_new0(MemoryRegion, 1);
object_property_set_link(cpuobj, OBJECT(secure_sysmem),
"secure-memory", &error_abort);
- object_property_set_bool(cpuobj, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
object_unref(cpuobj);
}
{
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_SL_NAND);
+ dev = qdev_new(TYPE_SL_NAND);
qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG);
if (size == FLASH_128M)
else if (size == FLASH_1024M)
qdev_prop_set_uint8(dev, "chip_id", 0xf1);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_BASE);
}
&error_fatal);
memory_region_add_subregion(system_memory, 0x20000000, sram);
- nvic = qdev_create(NULL, TYPE_ARMV7M);
+ nvic = qdev_new(TYPE_ARMV7M);
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
qdev_prop_set_bit(nvic, "enable-bitband", true);
object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()),
"memory", &error_abort);
/* This will exit with an error if the user passed us a bad cpu_type */
- qdev_init_nofail(nvic);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
qemu_allocate_irq(&do_sys_reset, NULL, 0));
if (board->dc1 & (1 << 3)) { /* watchdog present */
- dev = qdev_create(NULL, TYPE_LUMINARY_WATCHDOG);
+ dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
/* system_clock_scale is valid now */
uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev),
0,
0x40000000u);
qemu_check_nic_model(&nd_table[0], "stellaris");
- enet = qdev_create(NULL, "stellaris_enet");
+ enet = qdev_new("stellaris_enet");
qdev_set_nic_properties(enet, &nd_table[0]);
- qdev_init_nofail(enet);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
}
STM32F205State *s = STM32F205_SOC(obj);
int i;
- sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
- TYPE_ARMV7M);
+ object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
- sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
- TYPE_STM32F2XX_SYSCFG);
+ object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG);
for (i = 0; i < STM_NUM_USARTS; i++) {
- sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
- sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
+ object_initialize_child(obj, "usart[*]", &s->usart[i],
+ TYPE_STM32F2XX_USART);
}
for (i = 0; i < STM_NUM_TIMERS; i++) {
- sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
- sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
+ object_initialize_child(obj, "timer[*]", &s->timer[i],
+ TYPE_STM32F2XX_TIMER);
}
s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
for (i = 0; i < STM_NUM_ADCS; i++) {
- sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
- TYPE_STM32F2XX_ADC);
+ object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
}
for (i = 0; i < STM_NUM_SPIS; i++) {
- sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
- TYPE_STM32F2XX_SPI);
+ object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
}
}
qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
"memory", &error_abort);
- object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
/* System configuration controller */
dev = DEVICE(&s->syscfg);
- object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
for (i = 0; i < STM_NUM_USARTS; i++) {
dev = DEVICE(&(s->usart[i]));
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
- object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
for (i = 0; i < STM_NUM_TIMERS; i++) {
dev = DEVICE(&(s->timer[i]));
qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
- object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
/* ADC 1 to 3 */
object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
"num-lines", &err);
- object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
+ qdev_realize(DEVICE(s->adc_irqs), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
for (i = 0; i < STM_NUM_ADCS; i++) {
dev = DEVICE(&(s->adc[i]));
- object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
/* SPI 1 and 2 */
for (i = 0; i < STM_NUM_SPIS; i++) {
dev = DEVICE(&(s->spi[i]));
- object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
/* At the moment only Timer 2 to 5 are modelled */
static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
0x40000800, 0x40000C00 };
-#define ADC_ADDR 0x40012000
+static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
+ 0x40012300, 0x40012400, 0x40012500 };
static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
0x40013400, 0x40015000, 0x40015400 };
#define EXTI_ADDR 0x40013C00
STM32F405State *s = STM32F405_SOC(obj);
int i;
- sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
- TYPE_ARMV7M);
+ object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
- sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
- TYPE_STM32F4XX_SYSCFG);
+ object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG);
for (i = 0; i < STM_NUM_USARTS; i++) {
- sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
- sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
+ object_initialize_child(obj, "usart[*]", &s->usart[i],
+ TYPE_STM32F2XX_USART);
}
for (i = 0; i < STM_NUM_TIMERS; i++) {
- sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
- sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
+ object_initialize_child(obj, "timer[*]", &s->timer[i],
+ TYPE_STM32F2XX_TIMER);
}
for (i = 0; i < STM_NUM_ADCS; i++) {
- sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
- TYPE_STM32F2XX_ADC);
+ object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
}
for (i = 0; i < STM_NUM_SPIS; i++) {
- sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
- TYPE_STM32F2XX_SPI);
+ object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
}
- sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti),
- TYPE_STM32F4XX_EXTI);
+ object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI);
}
static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory),
"memory", &error_abort);
- object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
/* System configuration controller */
dev = DEVICE(&s->syscfg);
- object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
for (i = 0; i < STM_NUM_USARTS; i++) {
dev = DEVICE(&(s->usart[i]));
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
- object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
for (i = 0; i < STM_NUM_TIMERS; i++) {
dev = DEVICE(&(s->timer[i]));
qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
- object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
/* ADC device, the IRQs are ORed together */
- object_initialize_child(OBJECT(s), "adc-orirq", &s->adc_irqs,
- sizeof(s->adc_irqs), TYPE_OR_IRQ,
- &err, NULL);
+ object_initialize_child_with_props(OBJECT(s), "adc-orirq", &s->adc_irqs,
+ sizeof(s->adc_irqs), TYPE_OR_IRQ, &err,
+ NULL);
if (err != NULL) {
error_propagate(errp, err);
return;
}
object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS,
"num-lines", &err);
- object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err);
+ qdev_realize(DEVICE(&s->adc_irqs), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
qdev_get_gpio_in(armv7m, ADC_IRQ));
- dev = DEVICE(&(s->adc[i]));
- object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
- if (err != NULL) {
- error_propagate(errp, err);
- return;
+ for (i = 0; i < STM_NUM_ADCS; i++) {
+ dev = DEVICE(&(s->adc[i]));
+ sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, adc_addr[i]);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
}
- busdev = SYS_BUS_DEVICE(dev);
- sysbus_mmio_map(busdev, 0, ADC_ADDR);
- sysbus_connect_irq(busdev, 0,
- qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
/* SPI devices */
for (i = 0; i < STM_NUM_SPIS; i++) {
dev = DEVICE(&(s->spi[i]));
- object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
/* EXTI device */
dev = DEVICE(&s->exti);
- object_property_set_bool(OBJECT(&s->exti), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->exti), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
#include "chardev/char-serial.h"
#include "sysemu/sysemu.h"
#include "hw/ssi/ssi.h"
+#include "qapi/error.h"
#include "qemu/cutils.h"
#include "qemu/log.h"
DeviceState *dev;
int i;
- dev = qdev_create(NULL, TYPE_STRONGARM_GPIO);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_STRONGARM_GPIO);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < 12; i++)
s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL);
for (i = 0; sa_serial[i].io_base; i++) {
- DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART);
+ DeviceState *dev = qdev_new(TYPE_STRONGARM_UART);
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
sa_serial[i].io_base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
}
- object_property_set_bool(cpuobj, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
cpu = ARM_CPU(cpuobj);
/* SDRAM at address zero. */
memory_region_add_subregion(sysmem, 0, machine->ram);
- sysctl = qdev_create(NULL, "realview_sysctl");
+ sysctl = qdev_new("realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
- qdev_init_nofail(sysctl);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
dev = sysbus_create_varargs("pl190", 0x10140000,
sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
- dev = qdev_create(NULL, "versatile_pci");
+ dev = qdev_new("versatile_pci");
busdev = SYS_BUS_DEVICE(dev);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */
sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */
sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */
pl011_create(0x101f3000, pic[14], serial_hd(2));
pl011_create(0x10009000, sic[6], serial_hd(3));
- dev = qdev_create(NULL, "pl080");
+ dev = qdev_new("pl080");
object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",
&error_fatal);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10130000);
sysbus_connect_irq(busdev, 0, pic[17]);
i2c_create_slave(i2c, "ds1338", 0x68);
/* Add PL041 AACI Interface to the LM4549 codec */
- pl041 = qdev_create(NULL, "pl041");
+ pl041 = qdev_new("pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
- qdev_init_nofail(pl041);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]);
object_property_set_int(cpuobj, periphbase,
"reset-cbar", &error_abort);
}
- object_property_set_bool(cpuobj, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
}
/* Create the private peripheral devices (including the GIC);
* this must happen after the CPUs are created because a15mpcore_priv
* wires itself up to the CPU's generic_timer gpio out lines.
*/
- dev = qdev_create(NULL, privdev);
+ dev = qdev_new(privdev);
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, periphbase);
/* Interrupts [42:0] are from the motherboard;
static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
DriveInfo *di)
{
- DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
+ DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
if (di) {
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di),
qdev_prop_set_uint16(dev, "id2", 0x00);
qdev_prop_set_uint16(dev, "id3", 0x00);
qdev_prop_set_string(dev, "name", name);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return PFLASH_CFI01(dev);
sys_id = 0x1190f500;
- sysctl = qdev_create(NULL, "realview_sysctl");
+ sysctl = qdev_new("realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
qdev_prop_set_uint32(sysctl, "len-db-voltage",
qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
g_free(propname);
}
- qdev_init_nofail(sysctl);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
/* VE_SP810: not modelled */
/* VE_SERIALPCI: not modelled */
- pl041 = qdev_create(NULL, "pl041");
+ pl041 = qdev_new("pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
- qdev_init_nofail(pl041);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
}
- dev = qdev_create(NULL, TYPE_ACPI_GED);
+ dev = qdev_new(TYPE_ACPI_GED);
qdev_prop_set_uint32(dev, "ged-event", event);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
return dev;
}
return;
}
- dev = qdev_create(NULL, itsclass);
+ dev = qdev_new(itsclass);
object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3",
&error_abort);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
fdt_add_its_gic_node(vms);
int irq = vms->irqmap[VIRT_GIC_V2M];
DeviceState *dev;
- dev = qdev_create(NULL, "arm-gicv2m");
+ dev = qdev_new("arm-gicv2m");
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
qdev_prop_set_uint32(dev, "base-spi", irq);
qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
for (i = 0; i < NUM_GICV2M_SPIS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
- vms->gic = qdev_create(NULL, gictype);
+ vms->gic = qdev_new(gictype);
qdev_prop_set_uint32(vms->gic, "revision", type);
qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
/* Note that the num-irq property counts both internal and external
vms->virt);
}
}
- qdev_init_nofail(vms->gic);
gicbusdev = SYS_BUS_DEVICE(vms->gic);
+ sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
if (type == 3) {
sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
int irq = vms->irqmap[uart];
const char compat[] = "arm,pl011\0arm,primecell";
const char clocknames[] = "uartclk\0apb_pclk";
- DeviceState *dev = qdev_create(NULL, TYPE_PL011);
+ DeviceState *dev = qdev_new(TYPE_PL011);
SysBusDevice *s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(mem, base,
sysbus_mmio_get_region(s, 0));
sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
* Create a single flash device. We use the same parameters as
* the flash devices on the Versatile Express board.
*/
- DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
+ DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
qdev_prop_set_uint8(dev, "width", 4);
assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(sysmem, base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
return;
}
- dev = qdev_create(NULL, "arm-smmuv3");
+ dev = qdev_new("arm-smmuv3");
object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
&error_abort);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < NUM_SMMU_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
int i, ecam_id;
PCIHostState *pci;
- dev = qdev_create(NULL, TYPE_GPEX_HOST);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_GPEX_HOST);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
base_ecam = vms->memmap[ecam_id].base;
int i;
MemoryRegion *sysmem = get_system_memory();
- dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
+ dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
dev->id = TYPE_PLATFORM_BUS_DEVICE;
qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
vms->platform_bus_dev = dev;
s = SYS_BUS_DEVICE(dev);
"secure-memory", &error_abort);
}
- object_property_set_bool(cpuobj, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
object_unref(cpuobj);
}
fdt_add_timer_nodes(vms);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, TYPE_CADENCE_GEM);
+ dev = qdev_new(TYPE_CADENCE_GEM);
if (nd->used) {
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(dev, nd);
}
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
- dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
+ dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
qdev_prop_set_uint8(dev, "num-busses", num_busses);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, base_addr);
if (is_qspi) {
sysbus_mmio_map(busdev, 1, 0xFC000000);
for (j = 0; j < num_ss; ++j) {
DriveInfo *dinfo = drive_get_next(IF_MTD);
- flash_dev = ssi_create_slave_no_init(spi, "n25q128");
+ flash_dev = qdev_new("n25q128");
if (dinfo) {
qdev_prop_set_drive(flash_dev, "drive",
blk_by_legacy_dinfo(dinfo), &error_fatal);
}
- qdev_init_nofail(flash_dev);
+ qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal);
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
&error_fatal);
object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
&error_fatal);
- object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
+ qdev_realize(DEVICE(cpu), NULL, &error_fatal);
/* DDR remapped to address zero. */
memory_region_add_subregion(address_space_mem, 0, machine->ram);
0);
/* Create slcr, keep a pointer to connect clocks */
- slcr = qdev_create(NULL, "xilinx,zynq_slcr");
- qdev_init_nofail(slcr);
+ slcr = qdev_new("xilinx,zynq_slcr");
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
/* Create the main clock source, and feed slcr with it */
clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
- dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
+ dev = qdev_new(TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", 1);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
* - SDIO Specification Version 2.0
* - MMC Specification Version 3.31
*/
- dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
+ dev = qdev_new(TYPE_SYSBUS_SDHCI);
qdev_prop_set_uint8(dev, "sd-spec-version", 2);
qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
- carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
+ carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true, "realized",
- &error_fatal);
+ qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
+ &error_fatal);
}
- dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_ZYNQ_XADC);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
- dev = qdev_create(NULL, "pl330");
+ dev = qdev_new("pl330");
qdev_prop_set_uint8(dev, "num_chnls", 8);
qdev_prop_set_uint8(dev, "num_periph_req", 4);
qdev_prop_set_uint8(dev, "num_events", 16);
qdev_prop_set_uint8(dev, "rd_q_dep", 16);
qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xF8003000);
sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
}
- dev = qdev_create(NULL, "xlnx.ps7-dev-cfg");
- qdev_init_nofail(dev);
+ dev = qdev_new("xlnx.ps7-dev-cfg");
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
sysbus_mmio_map(busdev, 0, 0xF8007000);
qemu_irq pic_irq;
pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
- dev = qdev_create(NULL, "virtio-mmio");
+ dev = qdev_new("virtio-mmio");
object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->soc.mr_ps, base, mr);
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
DeviceState *card;
- card = qdev_create(qdev_get_child_bus(DEVICE(sd), "sd-bus"), TYPE_SD_CARD);
+ card = qdev_new(TYPE_SD_CARD);
object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card));
qdev_prop_set_drive(card, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
+ qdev_realize_and_unref(card, qdev_get_child_bus(DEVICE(sd), "sd-bus"),
+ &error_fatal);
}
static void versal_virt_init(MachineState *machine)
psci_conduit = QEMU_PSCI_CONDUIT_SMC;
}
- sysbus_init_child_obj(OBJECT(machine), "xlnx-versal", &s->soc,
- sizeof(s->soc), TYPE_XLNX_VERSAL);
+ object_initialize_child(OBJECT(machine), "xlnx-versal", &s->soc,
+ TYPE_XLNX_VERSAL);
object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
"ddr", &error_abort);
object_property_set_int(OBJECT(&s->soc), psci_conduit,
"psci-conduit", &error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
fdt_create(s);
create_virtio_regions(s);
for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
Object *obj;
- object_initialize_child(OBJECT(s), "apu-cpu[*]",
- &s->fpd.apu.cpu[i], sizeof(s->fpd.apu.cpu[i]),
- XLNX_VERSAL_ACPU_TYPE, &error_abort, NULL);
+ object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i],
+ XLNX_VERSAL_ACPU_TYPE);
obj = OBJECT(&s->fpd.apu.cpu[i]);
object_property_set_int(obj, s->cfg.psci_conduit,
"psci-conduit", &error_abort);
"core-count", &error_abort);
object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",
&error_abort);
- object_property_set_bool(obj, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(obj), NULL, &error_fatal);
}
}
int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu);
int i;
- sysbus_init_child_obj(OBJECT(s), "apu-gic",
- &s->fpd.apu.gic, sizeof(s->fpd.apu.gic),
- gicv3_class_name());
+ object_initialize_child(OBJECT(s), "apu-gic", &s->fpd.apu.gic,
+ gicv3_class_name());
gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic);
gicdev = DEVICE(&s->fpd.apu.gic);
qdev_prop_set_uint32(gicdev, "revision", 3);
qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2);
qdev_prop_set_bit(gicdev, "has-security-extensions", true);
- object_property_set_bool(OBJECT(&s->fpd.apu.gic), true, "realized",
- &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal);
for (i = 0; i < ARRAY_SIZE(addrs); i++) {
MemoryRegion *mr;
DeviceState *dev;
MemoryRegion *mr;
- sysbus_init_child_obj(OBJECT(s), name,
- &s->lpd.iou.uart[i], sizeof(s->lpd.iou.uart[i]),
- TYPE_PL011);
+ object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i],
+ TYPE_PL011);
dev = DEVICE(&s->lpd.iou.uart[i]);
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
DeviceState *dev;
MemoryRegion *mr;
- sysbus_init_child_obj(OBJECT(s), name,
- &s->lpd.iou.gem[i], sizeof(s->lpd.iou.gem[i]),
- TYPE_CADENCE_GEM);
+ object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i],
+ TYPE_CADENCE_GEM);
dev = DEVICE(&s->lpd.iou.gem[i]);
if (nd->used) {
qemu_check_nic_model(nd, "cadence_gem");
object_property_set_link(OBJECT(dev),
OBJECT(&s->mr_ps), "dma",
&error_abort);
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
DeviceState *dev;
MemoryRegion *mr;
- sysbus_init_child_obj(OBJECT(s), name,
- &s->lpd.iou.adma[i], sizeof(s->lpd.iou.adma[i]),
- TYPE_XLNX_ZDMA);
+ object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i],
+ TYPE_XLNX_ZDMA);
dev = DEVICE(&s->lpd.iou.adma[i]);
object_property_set_int(OBJECT(dev), 128, "bus-width", &error_abort);
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->mr_ps,
DeviceState *dev;
MemoryRegion *mr;
- sysbus_init_child_obj(OBJECT(s), "sd[*]",
- &s->pmc.iou.sd[i], sizeof(s->pmc.iou.sd[i]),
- TYPE_SYSBUS_SDHCI);
+ object_initialize_child(OBJECT(s), "sd[*]", &s->pmc.iou.sd[i],
+ TYPE_SYSBUS_SDHCI);
dev = DEVICE(&s->pmc.iou.sd[i]);
object_property_set_uint(OBJECT(dev),
object_property_set_uint(OBJECT(dev), SDHCI_CAPABILITIES, "capareg",
&error_fatal);
object_property_set_uint(OBJECT(dev), UHS_I, "uhs", &error_fatal);
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->mr_ps,
SysBusDevice *sbd;
MemoryRegion *mr;
- sysbus_init_child_obj(OBJECT(s), "rtc", &s->pmc.rtc, sizeof(s->pmc.rtc),
- TYPE_XLNX_ZYNQMP_RTC);
+ object_initialize_child(OBJECT(s), "rtc", &s->pmc.rtc,
+ TYPE_XLNX_ZYNQMP_RTC);
sbd = SYS_BUS_DEVICE(&s->pmc.rtc);
- qdev_init_nofail(DEVICE(sbd));
+ sysbus_realize(SYS_BUS_DEVICE(sbd), &error_fatal);
mr = sysbus_mmio_get_region(sbd, 0);
memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr);
MemoryRegion *mr,
hwaddr base, hwaddr size)
{
- DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
+ DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
MemoryRegion *mr_dev;
qdev_prop_set_string(dev, "name", name);
qdev_prop_set_uint64(dev, "size", size);
object_property_add_child(OBJECT(s), name, OBJECT(dev));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(mr, base, mr_dev);
ram_size);
}
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_XLNX_ZYNQMP, &error_abort, NULL);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_XLNX_ZYNQMP);
object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
"ddr-ram", &error_abort);
object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization",
&error_fatal);
- object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
+ qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
/* Create and plug in the SD cards */
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
error_report("No SD bus found for SD card %d", i);
exit(1);
}
- carddev = qdev_create(bus, TYPE_SD_CARD);
+ carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true, "realized",
- &error_fatal);
+ qdev_realize_and_unref(carddev, bus, &error_fatal);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
- SSIBus *spi_bus;
+ BusState *spi_bus;
DeviceState *flash_dev;
qemu_irq cs_line;
DriveInfo *dinfo = drive_get_next(IF_MTD);
gchar *bus_name = g_strdup_printf("spi%d", i);
- spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
+ spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
g_free(bus_name);
- flash_dev = ssi_create_slave_no_init(spi_bus, "sst25wf080");
+ flash_dev = qdev_new("sst25wf080");
if (dinfo) {
qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
- qdev_init_nofail(flash_dev);
+ qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal);
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) {
- SSIBus *spi_bus;
+ BusState *spi_bus;
DeviceState *flash_dev;
qemu_irq cs_line;
DriveInfo *dinfo = drive_get_next(IF_MTD);
int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS;
gchar *bus_name = g_strdup_printf("qspi%d", bus);
- spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
+ spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
g_free(bus_name);
- flash_dev = ssi_create_slave_no_init(spi_bus, "n25q512a11");
+ flash_dev = qdev_new("n25q512a11");
if (dinfo) {
qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
- qdev_init_nofail(flash_dev);
+ qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal);
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
}
object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster,
- sizeof(s->rpu_cluster), TYPE_CPU_CLUSTER,
- &error_abort, NULL);
+ TYPE_CPU_CLUSTER);
qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1);
for (i = 0; i < num_rpus; i++) {
char *name;
object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
- &s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
- ARM_CPU_TYPE_NAME("cortex-r5f"),
- &error_abort, NULL);
+ &s->rpu_cpu[i],
+ ARM_CPU_TYPE_NAME("cortex-r5f"));
name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
if (strcmp(name, boot_cpu)) {
object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
&error_abort);
- object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
- &err);
+ qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
}
}
- qdev_init_nofail(DEVICE(&s->rpu_cluster));
+ qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
}
static void xlnx_zynqmp_init(Object *obj)
int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
- sizeof(s->apu_cluster), TYPE_CPU_CLUSTER,
- &error_abort, NULL);
+ TYPE_CPU_CLUSTER);
qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0);
for (i = 0; i < num_apus; i++) {
object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
- &s->apu_cpu[i], sizeof(s->apu_cpu[i]),
- ARM_CPU_TYPE_NAME("cortex-a53"),
- &error_abort, NULL);
+ &s->apu_cpu[i],
+ ARM_CPU_TYPE_NAME("cortex-a53"));
}
- sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
- gic_class_name());
+ object_initialize_child(obj, "gic", &s->gic, gic_class_name());
for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
- sysbus_init_child_obj(obj, "gem[*]", &s->gem[i], sizeof(s->gem[i]),
- TYPE_CADENCE_GEM);
+ object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
- sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
- TYPE_CADENCE_UART);
+ object_initialize_child(obj, "uart[*]", &s->uart[i],
+ TYPE_CADENCE_UART);
}
- sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata),
- TYPE_SYSBUS_AHCI);
+ object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
- sysbus_init_child_obj(obj, "sdhci[*]", &s->sdhci[i],
- sizeof(s->sdhci[i]), TYPE_SYSBUS_SDHCI);
+ object_initialize_child(obj, "sdhci[*]", &s->sdhci[i],
+ TYPE_SYSBUS_SDHCI);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
- sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
- TYPE_XILINX_SPIPS);
+ object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS);
}
- sysbus_init_child_obj(obj, "qspi", &s->qspi, sizeof(s->qspi),
- TYPE_XLNX_ZYNQMP_QSPIPS);
+ object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS);
- sysbus_init_child_obj(obj, "xxxdp", &s->dp, sizeof(s->dp), TYPE_XLNX_DP);
+ object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP);
- sysbus_init_child_obj(obj, "dp-dma", &s->dpdma, sizeof(s->dpdma),
- TYPE_XLNX_DPDMA);
+ object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA);
- sysbus_init_child_obj(obj, "ipi", &s->ipi, sizeof(s->ipi),
- TYPE_XLNX_ZYNQMP_IPI);
+ object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI);
- sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
- TYPE_XLNX_ZYNQMP_RTC);
+ object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC);
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
- sysbus_init_child_obj(obj, "gdma[*]", &s->gdma[i], sizeof(s->gdma[i]),
- TYPE_XLNX_ZDMA);
+ object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
- sysbus_init_child_obj(obj, "adma[*]", &s->adma[i], sizeof(s->adma[i]),
- TYPE_XLNX_ZDMA);
+ object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA);
}
}
qdev_prop_set_bit(DEVICE(&s->gic),
"has-virtualization-extensions", s->virt);
- qdev_init_nofail(DEVICE(&s->apu_cluster));
+ qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
/* Realize APUs before realizing the GIC. KVM requires this. */
for (i = 0; i < num_apus; i++) {
"reset-cbar", &error_abort);
object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus,
"core-count", &error_abort);
- object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
- &err);
+ qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
}
}
- object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
if (err) {
error_propagate(errp, err);
return;
&error_abort);
object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
&error_abort);
- object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), &err);
if (err) {
error_propagate(errp, err);
return;
for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
- object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
if (err) {
error_propagate(errp, err);
return;
object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
&error_abort);
- object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sata), &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(sdhci, true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(sdhci), &err);
if (err) {
error_propagate(errp, err);
return;
for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
gchar *bus_name;
- object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
if (err) {
error_propagate(errp, err);
return;
g_free(bus_name);
}
- object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->qspi), &err);
if (err) {
error_propagate(errp, err);
return;
g_free(target_bus);
}
- object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->dp), &err);
if (err) {
error_propagate(errp, err);
return;
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
- object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), &err);
if (err) {
error_propagate(errp, err);
return;
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
- object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ipi), &err);
if (err) {
error_propagate(errp, err);
return;
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
- object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err);
if (err) {
error_propagate(errp, err);
return;
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), &err);
if (err) {
error_propagate(errp, err);
return;
}
for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
- object_property_set_bool(OBJECT(&s->adma[i]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), &err);
if (err) {
error_propagate(errp, err);
return;
controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
hdabus = QLIST_FIRST(&controller->child_bus);
- codec = qdev_create(hdabus, "hda-duplex");
- qdev_init_nofail(codec);
+ codec = qdev_new("hda-duplex");
+ qdev_realize_and_unref(codec, hdabus, &error_fatal);
return 0;
}
continue;
}
- dev = qdev_create(&fdctrl->bus.bus, "floppy");
+ dev = qdev_new("floppy");
qdev_prop_set_uint32(dev, "unit", i);
qdev_prop_set_enum(dev, "drive-type", fdctrl->qdev_for_drives[i].type);
return;
}
- object_property_set_bool(OBJECT(dev), true, "realized", &local_err);
+ qdev_realize_and_unref(dev, &fdctrl->bus.bus, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
DeviceState *dev;
ISADevice *isadev;
- isadev = isa_try_create(bus, TYPE_ISA_FDC);
+ isadev = isa_try_new(TYPE_ISA_FDC);
if (!isadev) {
return NULL;
}
qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
&error_fatal);
}
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isadev, bus, &error_fatal);
return isadev;
}
SysBusDevice *sbd;
FDCtrlSysBus *sys;
- dev = qdev_create(NULL, "sysbus-fdc");
+ dev = qdev_new("sysbus-fdc");
sys = SYSBUS_FDC(dev);
fdctrl = &sys->state;
fdctrl->dma_chann = dma_chann; /* FIXME */
qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
&error_fatal);
}
- qdev_init_nofail(dev);
sbd = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbd, &error_fatal);
sysbus_connect_irq(sbd, 0, irq);
sysbus_mmio_map(sbd, 0, mmio_base);
}
DeviceState *dev;
FDCtrlSysBus *sys;
- dev = qdev_create(NULL, "SUNW,fdtwo");
+ dev = qdev_new("SUNW,fdtwo");
if (fds[0]) {
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
&error_fatal);
}
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sys = SYSBUS_FDC(dev);
sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
if (nand_flash_ids[chip_id].size == 0) {
hw_error("%s: Unsupported NAND chip ID.\n", __func__);
}
- dev = DEVICE(object_new(TYPE_NAND));
+ dev = qdev_new(TYPE_NAND);
qdev_prop_set_uint8(dev, "manufacturer_id", manf_id);
qdev_prop_set_uint8(dev, "chip_id", chip_id);
if (blk) {
qdev_prop_set_drive(dev, "drive", blk, &error_fatal);
}
- qdev_init_nofail(dev);
+ qdev_realize(dev, NULL, &error_fatal);
return dev;
}
uint16_t id2, uint16_t id3,
int be)
{
- DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
+ DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
if (blk) {
qdev_prop_set_drive(dev, "drive", blk, &error_abort);
qdev_prop_set_uint16(dev, "id2", id2);
qdev_prop_set_uint16(dev, "id3", id3);
qdev_prop_set_string(dev, "name", name);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return PFLASH_CFI01(dev);
uint16_t unlock_addr1,
int be)
{
- DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02);
+ DeviceState *dev = qdev_new(TYPE_PFLASH_CFI02);
if (blk) {
qdev_prop_set_drive(dev, "drive", blk, &error_abort);
qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
qdev_prop_set_string(dev, "name", name);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return PFLASH_CFI02(dev);
goto fail;
}
- xendev = XEN_DEVICE(qdev_create(BUS(xenbus), type));
+ xendev = XEN_DEVICE(qdev_new(type));
blockdev = XEN_BLOCK_DEVICE(xendev);
object_property_set_str(OBJECT(xendev), vdev, "vdev", &local_err);
blockdev->iothread = iothread;
blockdev->drive = drive;
- object_property_set_bool(OBJECT(xendev), true, "realized", &local_err);
+ qdev_realize_and_unref(DEVICE(xendev), BUS(xenbus), &local_err);
if (local_err) {
error_propagate_prepend(errp, local_err,
"realization of device %s failed: ",
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
+#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qemu/timer.h"
DeviceState *dev;
SysBusDevice *bus;
- dev = qdev_create(NULL, TYPE_EXYNOS4210_UART);
+ dev = qdev_new(TYPE_EXYNOS4210_UART);
qdev_prop_set_chr(dev, "chardev", chr);
qdev_prop_set_uint32(dev, "channel", channel);
qdev_prop_set_uint32(dev, "tx-size", fifo_size);
bus = SYS_BUS_DEVICE(dev);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(bus, &error_fatal);
if (addr != (hwaddr)-1) {
sysbus_mmio_map(bus, 0, addr);
}
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "qemu/module.h"
+#include "qapi/error.h"
#include "hw/m68k/mcf.h"
#include "hw/qdev-properties.h"
#include "chardev/char-fe.h"
{
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_MCF_UART);
+ dev = qdev_new(TYPE_MCF_UART);
if (chrdrv) {
qdev_prop_set_chr(dev, "chardev", chrdrv);
}
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
#include "hw/isa/isa.h"
#include "hw/qdev-properties.h"
#include "hw/char/parallel.h"
+#include "qapi/error.h"
static void parallel_init(ISABus *bus, int index, Chardev *chr)
{
DeviceState *dev;
ISADevice *isadev;
- isadev = isa_create(bus, "isa-parallel");
+ isadev = isa_new("isa-parallel");
dev = DEVICE(isadev);
qdev_prop_set_uint32(dev, "index", index);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isadev, bus, &error_fatal);
}
void parallel_hds_isa_init(ISABus *bus, int n)
index++;
isa_init_irq(isadev, &s->irq, isa->isairq);
- object_property_set_bool(OBJECT(s), true, "realized", errp);
+ qdev_realize(DEVICE(s), NULL, errp);
qdev_set_legacy_instance_id(dev, isa->iobase, 3);
memory_region_init_io(&s->io, OBJECT(isa), &serial_io_ops, s, "serial", 8);
{
ISASerialState *self = ISA_SERIAL(o);
- object_initialize_child(o, "serial", &self->state, sizeof(self->state),
- TYPE_SERIAL, &error_abort, NULL);
+ object_initialize_child(o, "serial", &self->state, TYPE_SERIAL);
}
static const TypeInfo serial_isa_info = {
DeviceState *dev;
ISADevice *isadev;
- isadev = isa_create(bus, TYPE_ISA_SERIAL);
+ isadev = isa_new(TYPE_ISA_SERIAL);
dev = DEVICE(isadev);
qdev_prop_set_uint32(dev, "index", index);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isadev, bus, &error_fatal);
}
void serial_hds_isa_init(ISABus *bus, int from, int to)
for (i = 0; i < pci->ports; i++) {
s = pci->state + i;
- object_property_set_bool(OBJECT(s), false, "realized", &error_abort);
+ qdev_unrealize(DEVICE(s));
memory_region_del_subregion(&pci->iobar, &s->io);
g_free(pci->name[i]);
}
for (i = 0; i < nports; i++) {
s = pci->state + i;
- object_property_set_bool(OBJECT(s), true, "realized", &err);
+ qdev_realize(DEVICE(s), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
multi_serial_pci_exit(dev);
size_t i, nports = multi_serial_get_port_count(PCI_DEVICE_GET_CLASS(dev));
for (i = 0; i < nports; i++) {
- object_initialize_child(o, "serial[*]", &pms->state[i],
- sizeof(pms->state[i]),
- TYPE_SERIAL, &error_abort, NULL);
+ object_initialize_child(o, "serial[*]", &pms->state[i], TYPE_SERIAL);
}
}
SerialState *s = &pci->state;
Error *err = NULL;
- object_property_set_bool(OBJECT(s), true, "realized", &err);
+ qdev_realize(DEVICE(s), NULL, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
SerialState *s = &pci->state;
- object_property_set_bool(OBJECT(s), false, "realized", &error_abort);
+ qdev_unrealize(DEVICE(s));
qemu_free_irq(s->irq);
}
{
PCISerialState *ps = PCI_SERIAL(o);
- object_initialize_child(o, "serial", &ps->state, sizeof(ps->state),
- TYPE_SERIAL, &error_abort, NULL);
+ object_initialize_child(o, "serial", &ps->state, TYPE_SERIAL);
}
static const TypeInfo serial_pci_info = {
SerialState *s = &sio->serial;
Error *local_err = NULL;
- object_property_set_bool(OBJECT(s), true, "realized", &local_err);
+ qdev_realize(DEVICE(s), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
{
SerialIO *sio = SERIAL_IO(o);
- object_initialize_child(o, "serial", &sio->serial, sizeof(sio->serial),
- TYPE_SERIAL, &error_abort, NULL);
+ object_initialize_child(o, "serial", &sio->serial, TYPE_SERIAL);
qdev_alias_all_properties(DEVICE(&sio->serial), o);
}
SerialState *s = &smm->serial;
Error *local_err = NULL;
- object_property_set_bool(OBJECT(s), true, "realized", &local_err);
+ qdev_realize(DEVICE(s), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
qemu_irq irq, int baudbase,
Chardev *chr, enum device_endian end)
{
- SerialMM *smm = SERIAL_MM(qdev_create(NULL, TYPE_SERIAL_MM));
+ SerialMM *smm = SERIAL_MM(qdev_new(TYPE_SERIAL_MM));
MemoryRegion *mr;
qdev_prop_set_uint8(DEVICE(smm), "regshift", regshift);
qdev_prop_set_chr(DEVICE(smm), "chardev", chr);
qdev_set_legacy_instance_id(DEVICE(smm), base, 2);
qdev_prop_set_uint8(DEVICE(smm), "endianness", end);
- qdev_init_nofail(DEVICE(smm));
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(smm), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, irq);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(smm), 0);
{
SerialMM *smm = SERIAL_MM(o);
- object_initialize_child(o, "serial", &smm->serial, sizeof(smm->serial),
- TYPE_SERIAL, &error_abort, NULL);
+ object_initialize_child(o, "serial", &smm->serial, TYPE_SERIAL);
qdev_alias_all_properties(DEVICE(&smm->serial), o);
}
{
DeviceState *dev;
- dev = qdev_create(&bus->bus, "spapr-vty");
+ dev = qdev_new("spapr-vty");
qdev_prop_set_chr(dev, "chardev", chardev);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, &bus->bus, &error_fatal);
}
static Property spapr_vty_properties[] = {
}
}
-static void qbus_realize(BusState *bus, DeviceState *parent, const char *name)
+static void qbus_init(BusState *bus, DeviceState *parent, const char *name)
{
const char *typename = object_get_typename(OBJECT(bus));
BusClass *bc;
DeviceState *parent, const char *name)
{
object_initialize(bus, size, typename);
- qbus_realize(bus, parent, name);
+ qbus_init(bus, parent, name);
}
BusState *qbus_create(const char *typename, DeviceState *parent, const char *name)
BusState *bus;
bus = BUS(object_new(typename));
- qbus_realize(bus, parent, name);
+ qbus_init(bus, parent, name);
return bus;
}
+bool qbus_realize(BusState *bus, Error **errp)
+{
+ Error *err = NULL;
+
+ object_property_set_bool(OBJECT(bus), true, "realized", &err);
+ error_propagate(errp, err);
+ return !err;
+}
+
+void qbus_unrealize(BusState *bus)
+{
+ object_property_set_bool(OBJECT(bus), false, "realized", &error_abort);
+}
+
static bool bus_get_realized(Object *obj, Error **errp)
{
BusState *bus = BUS(obj);
} else if (!value && bus->realized) {
QTAILQ_FOREACH(kid, &bus->children, sibling) {
DeviceState *dev = kid->child;
- object_property_set_bool(OBJECT(dev), false, "realized",
- &error_abort);
+ qdev_unrealize(dev);
}
if (bc->unrealize) {
bc->unrealize(bus);
{
Error *err = NULL;
CPUState *cpu = CPU(object_new(typename));
- object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+ qdev_realize(DEVICE(cpu), NULL, &err);
if (err != NULL) {
error_report_err(err);
object_unref(OBJECT(cpu));
void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
{
BusState *old_parent_bus = dev->parent_bus;
+ DeviceClass *dc = DEVICE_GET_CLASS(dev);
+
+ assert(dc->bus_type && object_dynamic_cast(OBJECT(bus), dc->bus_type));
if (old_parent_bus) {
trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)),
}
}
-/* Create a new device. This only initializes the device state
- structure and allows properties to be set. The device still needs
- to be realized. See qdev-core.h. */
-DeviceState *qdev_create(BusState *bus, const char *name)
+/*
+ * Create a device on the heap.
+ * A type @name must exist.
+ * This only initializes the device state structure and allows
+ * properties to be set. The device still needs to be realized. See
+ * qdev-core.h.
+ */
+DeviceState *qdev_new(const char *name)
{
- DeviceState *dev;
-
- dev = qdev_try_create(bus, name);
- if (!dev) {
- if (bus) {
- error_report("Unknown device '%s' for bus '%s'", name,
- object_get_typename(OBJECT(bus)));
- } else {
- error_report("Unknown device '%s' for default sysbus", name);
- }
- abort();
- }
-
- return dev;
+ return DEVICE(object_new(name));
}
-DeviceState *qdev_try_create(BusState *bus, const char *type)
+/*
+ * Try to create a device on the heap.
+ * This is like qdev_new(), except it returns %NULL when type @name
+ * does not exist.
+ */
+DeviceState *qdev_try_new(const char *name)
{
- DeviceState *dev;
-
- if (object_class_by_name(type) == NULL) {
+ if (!object_class_by_name(name)) {
return NULL;
}
- dev = DEVICE(object_new(type));
- if (!dev) {
- return NULL;
- }
-
- if (!bus) {
- /* Assert that the device really is a SysBusDevice before
- * we put it onto the sysbus. Non-sysbus devices which aren't
- * being put onto a bus should be created with object_new(TYPE_FOO),
- * not qdev_create(NULL, TYPE_FOO).
- */
- g_assert(object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE));
- bus = sysbus_get_default();
- }
- qdev_set_parent_bus(dev, bus);
- object_unref(OBJECT(dev));
- return dev;
+ return DEVICE(object_new(name));
}
static QTAILQ_HEAD(, DeviceListener) device_listeners
void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
- object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+ qdev_unrealize(dev);
}
/*
* Realize @dev.
- * Device properties should be set before calling this function. IRQs
- * and MMIO regions should be connected/mapped after calling this
- * function.
- * On failure, report an error with error_report() and terminate the
- * program. This is okay during machine creation. Don't use for
- * hotplug, because there callers need to recover from failure.
- * Exception: if you know the device's init() callback can't fail,
- * then qdev_init_nofail() can't fail either, and is therefore usable
- * even then. But relying on the device implementation that way is
- * somewhat unclean, and best avoided.
+ * @dev must not be plugged into a bus.
+ * If @bus, plug @dev into @bus. This takes a reference to @dev.
+ * If @dev has no QOM parent, make one up, taking another reference.
+ * On success, return true.
+ * On failure, store an error through @errp and return false.
*/
-void qdev_init_nofail(DeviceState *dev)
+bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp)
{
Error *err = NULL;
- assert(!dev->realized);
+ assert(!dev->realized && !dev->parent_bus);
+
+ if (bus) {
+ qdev_set_parent_bus(dev, bus);
+ } else {
+ assert(!DEVICE_GET_CLASS(dev)->bus_type);
+ }
- object_ref(OBJECT(dev));
object_property_set_bool(OBJECT(dev), true, "realized", &err);
if (err) {
- error_reportf_err(err, "Initialization of device %s failed: ",
- object_get_typename(OBJECT(dev)));
- exit(1);
+ error_propagate(errp, err);
}
+ return !err;
+}
+
+/*
+ * Realize @dev and drop a reference.
+ * This is like qdev_realize(), except the caller must hold a
+ * (private) reference, which is dropped on return regardless of
+ * success or failure. Intended use:
+ * dev = qdev_new();
+ * [...]
+ * qdev_realize_and_unref(dev, bus, errp);
+ * Now @dev can go away without further ado.
+ */
+bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp)
+{
+ bool ret;
+
+ ret = qdev_realize(dev, bus, errp);
object_unref(OBJECT(dev));
+ return ret;
+}
+
+void qdev_unrealize(DeviceState *dev)
+{
+ object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+}
+
+static int qdev_assert_realized_properly(Object *obj, void *opaque)
+{
+ DeviceState *dev = DEVICE(object_dynamic_cast(obj, TYPE_DEVICE));
+ DeviceClass *dc;
+
+ if (dev) {
+ dc = DEVICE_GET_CLASS(dev);
+ assert(dev->realized);
+ assert(dev->parent_bus || !dc->bus_type);
+ }
+ return 0;
}
void qdev_machine_creation_done(void)
* only create hotpluggable devices
*/
qdev_hotplug = true;
+
+ object_child_foreach_recursive(object_get_root(),
+ qdev_assert_realized_properly, NULL);
}
bool qdev_machine_modified(void)
resettable_state_clear(&dev->reset);
QLIST_FOREACH(bus, &dev->child_bus, sibling) {
- object_property_set_bool(OBJECT(bus), true, "realized",
- &local_err);
- if (local_err != NULL) {
+ if (!qbus_realize(bus, errp)) {
goto child_realize_fail;
}
}
} else if (!value && dev->realized) {
QLIST_FOREACH(bus, &dev->child_bus, sibling) {
- object_property_set_bool(OBJECT(bus), false, "realized",
- &error_abort);
+ qbus_unrealize(bus);
}
if (qdev_get_vmsd(dev)) {
vmstate_unregister(VMSTATE_IF(dev), qdev_get_vmsd(dev), dev);
child_realize_fail:
QLIST_FOREACH(bus, &dev->child_bus, sibling) {
- object_property_set_bool(OBJECT(bus), false, "realized",
- &error_abort);
+ qbus_unrealize(bus);
}
if (qdev_get_vmsd(dev)) {
fail:
error_propagate(errp, local_err);
if (unattached_parent) {
+ /*
+ * Beware, this doesn't just revert
+ * object_property_add_child(), it also runs bus_remove()!
+ */
object_unparent(OBJECT(dev));
unattached_count--;
}
BusState *bus;
if (dev->realized) {
- object_property_set_bool(obj, false, "realized", &error_abort);
+ qdev_unrealize(dev);
}
while (dev->num_child_bus) {
bus = QLIST_FIRST(&dev->child_bus);
* from being set to NULL to break the normal init/realize
* of some devices.
*/
-static void sysbus_realize(DeviceState *dev, Error **errp)
+static void sysbus_device_realize(DeviceState *dev, Error **errp)
{
}
qemu_irq irq;
int n;
- dev = qdev_create(NULL, name);
+ dev = qdev_new(name);
s = SYS_BUS_DEVICE(dev);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
if (addr != (hwaddr)-1) {
sysbus_mmio_map(s, 0, addr);
}
return dev;
}
+bool sysbus_realize(SysBusDevice *dev, Error **errp)
+{
+ return qdev_realize(DEVICE(dev), sysbus_get_default(), errp);
+}
+
+bool sysbus_realize_and_unref(SysBusDevice *dev, Error **errp)
+{
+ return qdev_realize_and_unref(DEVICE(dev), sysbus_get_default(), errp);
+}
+
static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent)
{
SysBusDevice *s = SYS_BUS_DEVICE(dev);
static void sysbus_device_class_init(ObjectClass *klass, void *data)
{
DeviceClass *k = DEVICE_CLASS(klass);
- k->realize = sysbus_realize;
+ k->realize = sysbus_device_realize;
k->bus_type = TYPE_SYSTEM_BUS;
/*
* device_add plugs devices into a suitable bus. For "real" buses,
.class_init = sysbus_device_class_init,
};
-/* This is a nasty hack to allow passing a NULL bus to qdev_create. */
static BusState *main_system_bus;
static void main_system_bus_create(void)
return main_system_bus;
}
-void sysbus_init_child_obj(Object *parent, const char *childname, void *child,
- size_t childsize, const char *childtype)
-{
- object_initialize_child(parent, childname, child, childsize, childtype,
- &error_abort, NULL);
- qdev_set_parent_bus(DEVICE(child), sysbus_get_default());
-}
-
static void sysbus_register_types(void)
{
type_register_static(&system_bus_info);
memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
sysbus_init_mmio(sbd, &s->container);
- sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
- gic_class_name());
+ object_initialize_child(obj, "gic", &s->gic, gic_class_name());
qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
}
qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2);
}
- object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
- sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), TYPE_A9_SCU);
+ object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU);
- sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC);
+ object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
- sysbus_init_child_obj(obj, "gtimer", &s->gtimer, sizeof(s->gtimer),
- TYPE_A9_GTIMER);
+ object_initialize_child(obj, "gtimer", &s->gtimer, TYPE_A9_GTIMER);
- sysbus_init_child_obj(obj, "mptimer", &s->mptimer, sizeof(s->mptimer),
- TYPE_ARM_MPTIMER);
+ object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER);
- sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt),
- TYPE_ARM_MPTIMER);
+ object_initialize_child(obj, "wdt", &s->wdt, TYPE_ARM_MPTIMER);
}
static void a9mp_priv_realize(DeviceState *dev, Error **errp)
scudev = DEVICE(&s->scu);
qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
- object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
object_property_get_bool(cpuobj, "has_el3", &error_abort);
qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
- object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
gtimerdev = DEVICE(&s->gtimer);
qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu);
- object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gtimer), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
mptimerdev = DEVICE(&s->mptimer);
qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
- object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
wdtdev = DEVICE(&s->wdt);
qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu);
- object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
Error *err = NULL;
qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
- object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
ARM11MPCORE_NUM_GIC_PRIORITY_BITS);
- object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);
qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
- object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu);
- object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->wdtimer), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
"mpcore-priv-container", 0x2000);
sysbus_init_mmio(sbd, &s->container);
- sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), TYPE_ARM11_SCU);
+ object_initialize_child(obj, "scu", &s->scu, TYPE_ARM11_SCU);
- sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC);
+ object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
/* Request the legacy 11MPCore GIC behaviour: */
qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0);
- sysbus_init_child_obj(obj, "mptimer", &s->mptimer, sizeof(s->mptimer),
- TYPE_ARM_MPTIMER);
+ object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER);
- sysbus_init_child_obj(obj, "wdtimer", &s->wdtimer, sizeof(s->wdtimer),
- TYPE_ARM_MPTIMER);
+ object_initialize_child(obj, "wdtimer", &s->wdtimer, TYPE_ARM_MPTIMER);
}
static Property mpcore_priv_properties[] = {
int i;
qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
- object_property_set_bool(OBJECT(&s->priv), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->priv), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
/* ??? IRQ routing is hardcoded to "normal" mode. */
for (n = 0; n < 4; n++) {
- object_property_set_bool(OBJECT(&s->gic[n]), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gic[n]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
SysBusDevice *privbusdev;
int i;
- sysbus_init_child_obj(obj, "a11priv", &s->priv, sizeof(s->priv),
- TYPE_ARM11MPCORE_PRIV);
+ object_initialize_child(obj, "a11priv", &s->priv, TYPE_ARM11MPCORE_PRIV);
privbusdev = SYS_BUS_DEVICE(&s->priv);
sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
for (i = 0; i < 4; i++) {
- sysbus_init_child_obj(obj, "gic[*]", &s->gic[i], sizeof(s->gic[i]),
- TYPE_REALVIEW_GIC);
+ object_initialize_child(obj, "gic[*]", &s->gic[i], TYPE_REALVIEW_GIC);
}
}
&gpio_state.iomem);
- dev = qdev_create(NULL, "etraxfs,pic");
- qdev_init_nofail(dev);
+ dev = qdev_new("etraxfs,pic");
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, 0x3001c000);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
/* ddc, edid */
I2CBus *i2cbus = i2c_init_bus(DEVICE(s), "ati-vga.ddc");
bitbang_i2c_init(&s->bbi2c, i2cbus);
- I2CSlave *i2cddc = I2C_SLAVE(qdev_create(BUS(i2cbus), TYPE_I2CDDC));
+ I2CSlave *i2cddc = I2C_SLAVE(qdev_new(TYPE_I2CDDC));
i2c_set_slave_address(i2cddc, 0x50);
+ qdev_realize_and_unref(DEVICE(i2cddc), BUS(i2cbus), &error_abort);
/* mmio register space */
memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s,
XFree(configs);
XCloseDisplay(d);
- dev = qdev_create(NULL, TYPE_MILKYMIST_TMU2);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_MILKYMIST_TMU2);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
/* i2c */
s->i2c_bus = i2c_init_bus(dev, "sm501.i2c");
/* ddc */
- I2CDDCState *ddc = I2CDDC(qdev_create(BUS(s->i2c_bus), TYPE_I2CDDC));
+ I2CDDCState *ddc = I2CDDC(qdev_new(TYPE_I2CDDC));
i2c_set_slave_address(I2C_SLAVE(ddc), 0x50);
+ qdev_realize_and_unref(DEVICE(ddc), BUS(s->i2c_bus), &error_abort);
/* mmio */
memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE);
sysbus_init_mmio(sbd, &s->state.mmio_region);
/* bridge to usb host emulation module */
- usb_dev = qdev_create(NULL, "sysbus-ohci");
+ usb_dev = qdev_new("sysbus-ohci");
qdev_prop_set_uint32(usb_dev, "num-ports", 2);
qdev_prop_set_uint64(usb_dev, "dma-offset", s->base);
- qdev_init_nofail(usb_dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(usb_dev), &error_fatal);
memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST,
sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0));
sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));
/* bridge to serial emulation module */
- qdev_init_nofail(DEVICE(&s->serial));
+ sysbus_realize(SYS_BUS_DEVICE(&s->serial), &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial), 0);
memory_region_add_subregion(&s->state.mmio_region, SM501_UART0, mr);
/* TODO : chain irq to IRL */
SM501SysBusState *sm501 = SYSBUS_SM501(o);
SerialMM *smm = &sm501->serial;
- sysbus_init_child_obj(o, "serial", smm, sizeof(SerialMM), TYPE_SERIAL_MM);
+ object_initialize_child(o, "serial", smm, TYPE_SERIAL_MM);
qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2);
qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
int i;
Error *local_error = NULL;
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
virtio_pci_force_virtio_1(vpci_dev);
- object_property_set_bool(OBJECT(vdev), true, "realized", &local_error);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), &local_error);
if (local_error) {
error_propagate(errp, local_error);
vpci_dev->common.offset = offset;
/* init virtio bits */
- qdev_set_parent_bus(DEVICE(g), BUS(&vpci_dev->bus));
virtio_pci_force_virtio_1(vpci_dev);
- object_property_set_bool(OBJECT(g), true, "realized", &err);
+ qdev_realize(DEVICE(g), BUS(&vpci_dev->bus), &err);
if (err) {
error_propagate(errp, err);
return;
/*
* Initialize AUX Bus.
*/
- s->aux_bus = aux_init_bus(DEVICE(obj), "aux");
+ s->aux_bus = aux_bus_init(DEVICE(obj), "aux");
/*
* Initialize DPCD and EDID..
*/
- s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd"));
+ s->dpcd = DPCD(qdev_new("dpcd"));
object_property_add_child(OBJECT(s), "dpcd", OBJECT(s->dpcd));
- s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc"));
+ s->edid = I2CDDC(qdev_new("i2c-ddc"));
i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50);
object_property_add_child(OBJECT(s), "edid", OBJECT(s->edid));
DisplaySurface *surface;
struct audsettings as;
- qdev_init_nofail(DEVICE(s->dpcd));
+ aux_bus_realize(s->aux_bus);
+
+ qdev_realize(DEVICE(s->dpcd), BUS(s->aux_bus), &error_fatal);
aux_map_slave(AUX_SLAVE(s->dpcd), 0x0000);
+ qdev_realize_and_unref(DEVICE(s->edid), BUS(aux_get_i2c_bus(s->aux_bus)),
+ &error_fatal);
+
s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s);
surface = qemu_console_surface(s->console);
xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "hw/dma/i8257.h"
+#include "qapi/error.h"
#include "qemu/main-loop.h"
#include "qemu/module.h"
#include "qemu/log.h"
ISADevice *isa1, *isa2;
DeviceState *d;
- isa1 = isa_create(bus, TYPE_I8257);
+ isa1 = isa_new(TYPE_I8257);
d = DEVICE(isa1);
qdev_prop_set_int32(d, "base", 0x00);
qdev_prop_set_int32(d, "page-base", 0x80);
qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x480 : -1);
qdev_prop_set_int32(d, "dshift", 0);
- qdev_init_nofail(d);
+ isa_realize_and_unref(isa1, bus, &error_fatal);
- isa2 = isa_create(bus, TYPE_I8257);
+ isa2 = isa_new(TYPE_I8257);
d = DEVICE(isa2);
qdev_prop_set_int32(d, "base", 0xc0);
qdev_prop_set_int32(d, "page-base", 0x88);
qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x488 : -1);
qdev_prop_set_int32(d, "dshift", 1);
- qdev_init_nofail(d);
+ isa_realize_and_unref(isa2, bus, &error_fatal);
isa_bus_dma(bus, ISADMA(isa1), ISADMA(isa2));
}
{
DeviceState *dev;
- dev = qdev_create(NULL, "pxa2xx-dma");
+ dev = qdev_new("pxa2xx-dma");
qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
{
DeviceState *dev;
- dev = qdev_create(NULL, "pxa2xx-dma");
+ dev = qdev_new("pxa2xx-dma");
qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
#include "hw/mips/mips.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
+#include "qapi/error.h"
#include "qemu/timer.h"
#include "qemu/log.h"
#include "qemu/module.h"
{
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_RC4030);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_RC4030);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
*dmas = rc4030_allocate_dmas(dev, 4);
*dma_mr = &RC4030(dev)->dma_mr;
SysBusESPState *sysbus;
ESPState *esp;
- d = qdev_create(NULL, TYPE_ESP);
+ d = qdev_new(TYPE_ESP);
object_property_add_child(OBJECT(dev), "esp", OBJECT(d));
sysbus = ESP_STATE(d);
esp = &sysbus->esp;
esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
sysbus->it_shift = 2;
esp->dma_enabled = 1;
- qdev_init_nofail(d);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal);
}
static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
qemu_check_nic_model(nd, TYPE_LANCE);
- d = qdev_create(NULL, TYPE_LANCE);
+ d = qdev_new(TYPE_LANCE);
object_property_add_child(OBJECT(dev), "lance", OBJECT(d));
qdev_set_nic_properties(d, nd);
object_property_set_link(OBJECT(d), OBJECT(dev), "dma", errp);
- qdev_init_nofail(d);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal);
}
static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
return;
}
- espdma = qdev_create(NULL, TYPE_SPARC32_ESPDMA_DEVICE);
+ espdma = qdev_new(TYPE_SPARC32_ESPDMA_DEVICE);
object_property_set_link(OBJECT(espdma), iommu, "iommu", errp);
object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma));
- qdev_init_nofail(espdma);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(espdma), &error_fatal);
esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
sbd = SYS_BUS_DEVICE(esp);
memory_region_add_subregion(&s->dmamem, 0x0,
sysbus_mmio_get_region(sbd, 0));
- ledma = qdev_create(NULL, TYPE_SPARC32_LEDMA_DEVICE);
+ ledma = qdev_new(TYPE_SPARC32_LEDMA_DEVICE);
object_property_set_link(OBJECT(ledma), iommu, "iommu", errp);
object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma));
- qdev_init_nofail(ledma);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(ledma), &error_fatal);
lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
sbd = SYS_BUS_DEVICE(lance);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
object_initialize_child(OBJECT(s), "axistream-connected-target",
- &s->rx_data_dev, sizeof(s->rx_data_dev),
- TYPE_XILINX_AXI_DMA_DATA_STREAM, &error_abort,
- NULL);
+ &s->rx_data_dev, TYPE_XILINX_AXI_DMA_DATA_STREAM);
object_initialize_child(OBJECT(s), "axistream-control-connected-target",
- &s->rx_control_dev, sizeof(s->rx_control_dev),
- TYPE_XILINX_AXI_DMA_CONTROL_STREAM, &error_abort,
- NULL);
+ &s->rx_control_dev,
+ TYPE_XILINX_AXI_DMA_CONTROL_STREAM);
object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
(Object **)&s->dma_mr,
qdev_prop_allow_set_link_before_realize,
PCIBus *b;
int i;
- dev = qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_DINO_PCI_HOST_BRIDGE);
s = DINO_PCI_HOST_BRIDGE(dev);
s->iar0 = s->iar1 = CPU_HPA + 3;
s->toc_addr = 0xFFFA0030; /* IO_COMMAND of CPU */
&s->pci_mem, get_system_io(),
PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS);
s->parent_obj.bus = b;
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Set up windows into PCI bus memory. */
for (i = 1; i < 31; i++) {
DeviceState *dev;
LasiState *s;
- dev = qdev_create(NULL, TYPE_LASI_CHIP);
+ dev = qdev_new(TYPE_LASI_CHIP);
s = LASI_CHIP(dev);
s->iar = CPU_HPA + 3;
s, "lasi", 0x100000);
memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* LAN */
if (enable_lasi_lan()) {
/* Graphics setup. */
if (machine->enable_graphics && vga_interface_type != VGA_NONE) {
- dev = qdev_create(NULL, "artist");
- qdev_init_nofail(dev);
+ dev = qdev_new("artist");
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, LASI_GFX_HPA);
sysbus_mmio_map(s, 1, ARTIST_FB_ADDR);
}
synic->cs = cs;
object_property_add_child(OBJECT(cs), "synic", obj);
object_unref(obj);
- object_property_set_bool(obj, true, "realized", &error_abort);
+ qdev_realize(DEVICE(obj), NULL, &error_abort);
synic_enabled = true;
}
#include "hw/i2c/i2c.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
+#include "qapi/error.h"
#include "qemu/module.h"
#include "trace.h"
{
DeviceState *dev;
- dev = qdev_create(&bus->qbus, name);
+ dev = qdev_new(name);
qdev_prop_set_uint8(dev, "address", addr);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, &bus->qbus, &error_fatal);
return dev;
}
{
DeviceState *dev;
- dev = qdev_create((BusState *) smbus, TYPE_SMBUS_EEPROM);
+ dev = qdev_new(TYPE_SMBUS_EEPROM);
qdev_prop_set_uint8(dev, "address", address);
/* FIXME: use an array of byte or block backend property? */
SMBUS_EEPROM(dev)->init_data = eeprom_buf;
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, (BusState *)smbus, &error_fatal);
}
void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
/* This device should take care of IOMMU PCI properties */
x86_iommu->type = TYPE_AMD;
- qdev_set_parent_bus(DEVICE(&s->pci), &bus->qbus);
- object_property_set_bool(OBJECT(&s->pci), true, "realized", errp);
+ qdev_realize(DEVICE(&s->pci), &bus->qbus, errp);
ret = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0,
AMDVI_CAPAB_SIZE, errp);
if (ret < 0) {
i8042 = isa_create_simple(isa_bus, "i8042");
if (!no_vmport) {
isa_create_simple(isa_bus, TYPE_VMPORT);
- vmmouse = isa_try_create(isa_bus, "vmmouse");
+ vmmouse = isa_try_new("vmmouse");
} else {
vmmouse = NULL;
}
if (vmmouse) {
object_property_set_link(OBJECT(vmmouse), OBJECT(i8042),
"i8042", &error_abort);
- qdev_init_nofail(DEVICE(vmmouse));
+ isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
}
port92 = isa_create_simple(isa_bus, TYPE_PORT92);
* when the HPET wants to take over. Thus we have to disable the latter.
*/
if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
- hpet = qdev_try_create(NULL, TYPE_HPET);
+ hpet = qdev_try_new(TYPE_HPET);
if (hpet) {
/* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
* and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
if (!compat) {
qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
}
- qdev_init_nofail(hpet);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
for (i = 0; i < GSI_NUM_PINS; i++) {
}
pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
- object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+ qdev_unrealize(dev);
out:
error_propagate(errp, local_err);
}
found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
found_cpu->cpu = NULL;
- object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+ qdev_unrealize(dev);
/* decrement the number of CPUs */
x86ms->boot_cpus--;
return -1;
}
- ehci = pci_create_multifunction(bus, PCI_DEVFN(slot, 7), true, name);
- qdev_init_nofail(&ehci->qdev);
+ ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name);
+ pci_realize_and_unref(ehci, bus, &error_fatal);
usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
for (i = 0; i < 3; i++) {
- uhci = pci_create_multifunction(bus, PCI_DEVFN(slot, comp[i].func),
- true, comp[i].name);
+ uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true,
+ comp[i].name);
qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
- qdev_init_nofail(&uhci->qdev);
+ pci_realize_and_unref(uhci, bus, &error_fatal);
}
return 0;
}
}
/* create pci host bus */
- q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
+ q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE));
object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host));
object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory),
object_property_set_int(OBJECT(q35_host), x86ms->above_4g_mem_size,
PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
/* pci */
- qdev_init_nofail(DEVICE(q35_host));
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal);
phb = PCI_HOST_BRIDGE(q35_host);
host_bus = phb->bus;
/* create ISA bus */
const char *name,
const char *alias_prop_name)
{
- DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
+ DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
qdev_prop_set_uint64(dev, "sector-length", FLASH_SECTOR_SIZE);
qdev_prop_set_uint8(dev, "width", 1);
total_size += size;
qdev_prop_set_uint32(DEVICE(system_flash), "num-blocks",
size / FLASH_SECTOR_SIZE);
- qdev_init_nofail(DEVICE(system_flash));
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(system_flash), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(system_flash), 0,
0x100000000ULL - total_size);
cpu = object_new(MACHINE(x86ms)->cpu_type);
object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
- object_property_set_bool(cpu, true, "realized", &local_err);
+ qdev_realize(DEVICE(cpu), NULL, &local_err);
object_unref(cpu);
error_propagate(errp, local_err);
assert(parent_name);
if (kvm_ioapic_in_kernel()) {
- dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
+ dev = qdev_new(TYPE_KVM_IOAPIC);
} else {
- dev = qdev_create(NULL, TYPE_IOAPIC);
+ dev = qdev_new(TYPE_IOAPIC);
}
object_property_add_child(object_resolve_path(parent_name, NULL),
"ioapic", OBJECT(dev));
- qdev_init_nofail(dev);
d = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(d, &error_fatal);
sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
#include "hw/isa/isa.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
+#include "qapi/error.h"
#include "qemu/module.h"
#include "sysemu/dma.h"
ISADevice *isadev;
ISAIDEState *s;
- isadev = isa_create(bus, TYPE_ISA_IDE);
+ isadev = isa_new(TYPE_ISA_IDE);
dev = DEVICE(isadev);
qdev_prop_set_uint32(dev, "iobase", iobase);
qdev_prop_set_uint32(dev, "iobase2", iobase2);
qdev_prop_set_uint32(dev, "irq", isairq);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isadev, bus, &error_fatal);
s = ISA_IDE(dev);
if (hd0) {
#include "qemu/osdep.h"
#include "hw/pcmcia.h"
#include "migration/vmstate.h"
+#include "qapi/error.h"
#include "qemu/module.h"
#include "sysemu/dma.h"
MicroDriveState *md;
md = MICRODRIVE(object_new(TYPE_DSCM1XXXX));
- qdev_init_nofail(DEVICE(md));
+ qdev_realize(DEVICE(md), NULL, &error_fatal);
if (dinfo != NULL) {
ide_create_drive(&md->bus, 0, dinfo);
{
DeviceState *dev;
- dev = qdev_create(&bus->qbus, drive->media_cd ? "ide-cd" : "ide-hd");
+ dev = qdev_new(drive->media_cd ? "ide-cd" : "ide-hd");
qdev_prop_set_uint32(dev, "unit", unit);
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(drive),
&error_fatal);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, &bus->qbus, &error_fatal);
return DO_UPCAST(IDEDevice, qdev, dev);
}
s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2;
- object_property_set_bool(OBJECT(&s->systick[M_REG_NS]), true,
- "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
* as we didn't know then if the CPU had the security extensions;
* so we have to do it here.
*/
- sysbus_init_child_obj(OBJECT(dev), "systick-reg-s",
- &s->systick[M_REG_S],
- sizeof(s->systick[M_REG_S]), TYPE_SYSTICK);
+ object_initialize_child(OBJECT(dev), "systick-reg-s",
+ &s->systick[M_REG_S], TYPE_SYSTICK);
- object_property_set_bool(OBJECT(&s->systick[M_REG_S]), true,
- "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
NVICState *nvic = NVIC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
- sysbus_init_child_obj(obj, "systick-reg-ns", &nvic->systick[M_REG_NS],
- sizeof(nvic->systick[M_REG_NS]), TYPE_SYSTICK);
+ object_initialize_child(obj, "systick-reg-ns", &nvic->systick[M_REG_NS],
+ TYPE_SYSTICK);
/* We can't initialize the secure systick here, as we don't know
* yet if we need it.
*/
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
+#include "qapi/error.h"
#include "qemu/module.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
uint32_t n = s->num_cpu;
uint32_t i;
- s->gic = qdev_create(NULL, "arm_gic");
+ s->gic = qdev_new("arm_gic");
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ);
- qdev_init_nofail(s->gic);
gicbusdev = SYS_BUS_DEVICE(s->gic);
+ sysbus_realize_and_unref(gicbusdev, &error_fatal);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(sbd, gicbusdev);
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
+#include "qapi/error.h"
static int irq_level[16];
static uint64_t irq_count[16];
DeviceState *dev;
ISADevice *isadev;
- isadev = isa_create(bus, name);
+ isadev = isa_new(name);
dev = DEVICE(isadev);
qdev_prop_set_uint32(dev, "iobase", master ? 0x20 : 0xa0);
qdev_prop_set_uint32(dev, "elcr_addr", master ? 0x4d0 : 0x4d1);
qdev_prop_set_uint8(dev, "elcr_mask", master ? 0xf8 : 0xde);
qdev_prop_set_bit(dev, "master", master);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isadev, bus, &error_fatal);
return isadev;
}
PnvXive *xive = PNV_XIVE(obj);
object_initialize_child(obj, "ipi_source", &xive->ipi_source,
- sizeof(xive->ipi_source), TYPE_XIVE_SOURCE,
- &error_abort, NULL);
+ TYPE_XIVE_SOURCE);
object_initialize_child(obj, "end_source", &xive->end_source,
- sizeof(xive->end_source), TYPE_XIVE_END_SOURCE,
- &error_abort, NULL);
+ TYPE_XIVE_END_SOURCE);
}
/*
&error_fatal);
object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive",
&error_abort);
- object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
+ qdev_realize(DEVICE(xsrc), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
&error_fatal);
object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive",
&error_abort);
- object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err);
+ qdev_realize(DEVICE(end_xsrc), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
int numirq = 96;
qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", numirq);
- object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
"realview-gic-container", 0x2000);
sysbus_init_mmio(sbd, &s->container);
- sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC);
+ object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", 1);
}
DeviceState *dev;
if (kvm_enabled()) {
- dev = qdev_create(NULL, TYPE_KVM_S390_FLIC);
+ dev = qdev_new(TYPE_KVM_S390_FLIC);
object_property_add_child(qdev_get_machine(), TYPE_KVM_S390_FLIC,
OBJECT(dev));
} else {
- dev = qdev_create(NULL, TYPE_QEMU_S390_FLIC);
+ dev = qdev_new(TYPE_QEMU_S390_FLIC);
object_property_add_child(qdev_get_machine(), TYPE_QEMU_S390_FLIC,
OBJECT(dev));
}
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
}
static int qemu_s390_register_io_adapter(S390FLICState *fs, uint32_t id,
{
SpaprXive *xive = SPAPR_XIVE(obj);
- object_initialize_child(obj, "source", &xive->source, sizeof(xive->source),
- TYPE_XIVE_SOURCE, &error_abort, NULL);
+ object_initialize_child(obj, "source", &xive->source, TYPE_XIVE_SOURCE);
object_initialize_child(obj, "end_source", &xive->end_source,
- sizeof(xive->end_source), TYPE_XIVE_END_SOURCE,
- &error_abort, NULL);
+ TYPE_XIVE_END_SOURCE);
/* Not connected to the KVM XIVE device */
xive->fd = -1;
&error_fatal);
object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive",
&error_abort);
- object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
+ qdev_realize(DEVICE(xsrc), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
&error_fatal);
object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive",
&error_abort);
- object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err);
+ qdev_realize(DEVICE(end_xsrc), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
object_unref(obj);
object_property_set_link(obj, OBJECT(xi), ICP_PROP_XICS, &error_abort);
object_property_set_link(obj, cpu, ICP_PROP_CPU, &error_abort);
- object_property_set_bool(obj, true, "realized", &local_err);
+ qdev_realize(DEVICE(obj), NULL, &local_err);
if (local_err) {
object_unparent(obj);
error_propagate(errp, local_err);
object_unref(obj);
object_property_set_link(obj, cpu, "cpu", &error_abort);
object_property_set_link(obj, OBJECT(xptr), "presenter", &error_abort);
- object_property_set_bool(obj, true, "realized", &local_err);
+ qdev_realize(DEVICE(obj), NULL, &local_err);
if (local_err) {
goto error;
}
return NULL;
}
if (!dev) {
- dev = qdev_create(NULL, "isabus-bridge");
- qdev_init_nofail(dev);
+ dev = qdev_new("isabus-bridge");
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
}
isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL));
dev->isairq[1] = -1;
}
-ISADevice *isa_create(ISABus *bus, const char *name)
+ISADevice *isa_new(const char *name)
{
- DeviceState *dev;
-
- dev = qdev_create(BUS(bus), name);
- return ISA_DEVICE(dev);
+ return ISA_DEVICE(qdev_new(name));
}
-ISADevice *isa_try_create(ISABus *bus, const char *name)
+ISADevice *isa_try_new(const char *name)
{
- DeviceState *dev;
-
- dev = qdev_try_create(BUS(bus), name);
- return ISA_DEVICE(dev);
+ return ISA_DEVICE(qdev_try_new(name));
}
ISADevice *isa_create_simple(ISABus *bus, const char *name)
{
ISADevice *dev;
- dev = isa_create(bus, name);
- qdev_init_nofail(DEVICE(dev));
+ dev = isa_new(name);
+ isa_realize_and_unref(dev, bus, &error_fatal);
return dev;
}
+bool isa_realize_and_unref(ISADevice *dev, ISABus *bus, Error **errp)
+{
+ return qdev_realize_and_unref(&dev->parent_obj, &bus->parent_obj, errp);
+}
+
ISADevice *isa_vga_init(ISABus *bus)
{
switch (vga_interface_type) {
} else {
name = g_strdup_printf("parallel%d", i);
}
- isa = isa_create(bus, "isa-parallel");
+ isa = isa_new("isa-parallel");
d = DEVICE(isa);
qdev_prop_set_uint32(d, "index", i);
if (k->parallel.get_iobase) {
}
qdev_prop_set_chr(d, "chardev", chr);
object_property_add_child(OBJECT(dev), name, OBJECT(isa));
- qdev_init_nofail(d);
+ isa_realize_and_unref(isa, bus, &error_fatal);
sio->parallel[i] = isa;
trace_superio_create_parallel(i,
k->parallel.get_iobase ?
} else {
name = g_strdup_printf("serial%d", i);
}
- isa = isa_create(bus, TYPE_ISA_SERIAL);
+ isa = isa_new(TYPE_ISA_SERIAL);
d = DEVICE(isa);
qdev_prop_set_uint32(d, "index", i);
if (k->serial.get_iobase) {
}
qdev_prop_set_chr(d, "chardev", chr);
object_property_add_child(OBJECT(dev), name, OBJECT(isa));
- qdev_init_nofail(d);
+ isa_realize_and_unref(isa, bus, &error_fatal);
sio->serial[i] = isa;
trace_superio_create_serial(i,
k->serial.get_iobase ?
/* Floppy disc */
if (!k->floppy.is_enabled || k->floppy.is_enabled(sio, 0)) {
- isa = isa_create(bus, "isa-fdc");
+ isa = isa_new("isa-fdc");
d = DEVICE(isa);
if (k->floppy.get_iobase) {
qdev_prop_set_uint32(d, "iobase", k->floppy.get_iobase(sio, 0));
&error_fatal);
}
object_property_add_child(OBJECT(sio), "isa-fdc", OBJECT(isa));
- qdev_init_nofail(d);
+ isa_realize_and_unref(isa, bus, &error_fatal);
sio->floppy = isa;
trace_superio_create_floppy(0,
k->floppy.get_iobase ?
}
/* Keyboard, mouse */
- isa = isa_create(bus, TYPE_I8042);
+ isa = isa_new(TYPE_I8042);
object_property_add_child(OBJECT(sio), TYPE_I8042, OBJECT(isa));
- qdev_init_nofail(DEVICE(isa));
+ isa_realize_and_unref(isa, bus, &error_fatal);
sio->kbc = isa;
/* IDE */
if (k->ide.count && (!k->ide.is_enabled || k->ide.is_enabled(sio, 0))) {
- isa = isa_create(bus, "isa-ide");
+ isa = isa_new("isa-ide");
d = DEVICE(isa);
if (k->ide.get_iobase) {
qdev_prop_set_uint32(d, "iobase", k->ide.get_iobase(sio, 0));
if (k->ide.get_irq) {
qdev_prop_set_uint32(d, "irq", k->ide.get_irq(sio, 0));
}
- qdev_init_nofail(d);
+ isa_realize_and_unref(isa, bus, &error_fatal);
object_property_add_child(OBJECT(sio), "isa-ide", OBJECT(isa));
sio->ide = isa;
trace_superio_create_ide(0,
i8257_dma_init(isa_bus, 0);
/* RTC */
- qdev_set_parent_bus(DEVICE(&s->rtc), BUS(isa_bus));
qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
- object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
+ qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), &err);
if (err) {
error_propagate(errp, err);
return;
#include "hw/isa/apm.h"
#include "hw/acpi/acpi.h"
#include "hw/i2c/pm_smbus.h"
+#include "qapi/error.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "exec/address-spaces.h"
{
PCIDevice *dev;
- dev = pci_create(bus, devfn, TYPE_VT82C686B_AC97_DEVICE);
- qdev_init_nofail(&dev->qdev);
+ dev = pci_new(devfn, TYPE_VT82C686B_AC97_DEVICE);
+ pci_realize_and_unref(dev, bus, &error_fatal);
}
static void via_ac97_class_init(ObjectClass *klass, void *data)
{
PCIDevice *dev;
- dev = pci_create(bus, devfn, TYPE_VT82C686B_MC97_DEVICE);
- qdev_init_nofail(&dev->qdev);
+ dev = pci_new(devfn, TYPE_VT82C686B_MC97_DEVICE);
+ pci_realize_and_unref(dev, bus, &error_fatal);
}
static void via_mc97_class_init(ObjectClass *klass, void *data)
PCIDevice *dev;
VT686PMState *s;
- dev = pci_create(bus, devfn, TYPE_VT82C686B_PM_DEVICE);
+ dev = pci_new(devfn, TYPE_VT82C686B_PM_DEVICE);
qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
s = VT82C686B_PM_DEVICE(dev);
- qdev_init_nofail(&dev->qdev);
+ pci_realize_and_unref(dev, bus, &error_fatal);
return s->smb.smbus;
}
#include "hw/char/lm32_juart.h"
#include "hw/qdev-properties.h"
+#include "qapi/error.h"
static inline DeviceState *lm32_pic_init(qemu_irq cpu_irq)
{
DeviceState *dev;
SysBusDevice *d;
- dev = qdev_create(NULL, "lm32-pic");
- qdev_init_nofail(dev);
+ dev = qdev_new("lm32-pic");
d = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(d, &error_fatal);
sysbus_connect_irq(d, 0, cpu_irq);
return dev;
{
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_LM32_JUART);
+ dev = qdev_new(TYPE_LM32_JUART);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
return dev;
}
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "lm32-uart");
+ dev = qdev_new("lm32-uart");
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, irq);
return dev;
#include "hw/qdev-core.h"
#include "net/net.h"
+#include "qapi/error.h"
static inline DeviceState *milkymist_uart_create(hwaddr base,
qemu_irq irq,
{
DeviceState *dev;
- dev = qdev_create(NULL, "milkymist-uart");
+ dev = qdev_new("milkymist-uart");
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
{
DeviceState *dev;
- dev = qdev_create(NULL, "milkymist-hpdmc");
- qdev_init_nofail(dev);
+ dev = qdev_new("milkymist-hpdmc");
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return dev;
{
DeviceState *dev;
- dev = qdev_create(NULL, "milkymist-memcard");
- qdev_init_nofail(dev);
+ dev = qdev_new("milkymist-memcard");
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return dev;
{
DeviceState *dev;
- dev = qdev_create(NULL, "milkymist-vgafb");
+ dev = qdev_new("milkymist-vgafb");
qdev_prop_set_uint32(dev, "fb_offset", fb_offset);
qdev_prop_set_uint32(dev, "fb_mask", fb_mask);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return dev;
{
DeviceState *dev;
- dev = qdev_create(NULL, "milkymist-sysctl");
+ dev = qdev_new("milkymist-sysctl");
qdev_prop_set_uint32(dev, "frequency", freq_hz);
qdev_prop_set_uint32(dev, "systemid", system_id);
qdev_prop_set_uint32(dev, "capabilities", capabilities);
qdev_prop_set_uint32(dev, "gpio_strappings", gpio_strappings);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, gpio_irq);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, timer0_irq);
{
DeviceState *dev;
- dev = qdev_create(NULL, "milkymist-pfpu");
- qdev_init_nofail(dev);
+ dev = qdev_new("milkymist-pfpu");
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
return dev;
{
DeviceState *dev;
- dev = qdev_create(NULL, "milkymist-ac97");
- qdev_init_nofail(dev);
+ dev = qdev_new("milkymist-ac97");
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, crrequest_irq);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, crreply_irq);
DeviceState *dev;
qemu_check_nic_model(&nd_table[0], "minimac2");
- dev = qdev_create(NULL, "milkymist-minimac2");
+ dev = qdev_new("milkymist-minimac2");
qdev_set_nic_properties(dev, &nd_table[0]);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, buffers_base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, rx_irq);
{
DeviceState *dev;
- dev = qdev_create(NULL, "milkymist-softusb");
+ dev = qdev_new("milkymist-softusb");
qdev_prop_set_uint32(dev, "pmem_size", pmem_size);
qdev_prop_set_uint32(dev, "dmem_size", dmem_size);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, pmem_base);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, dmem_base);
int i;
qemu_check_nic_model(nd, TYPE_MCF_FEC_NET);
- dev = qdev_create(NULL, TYPE_MCF_FEC_NET);
+ dev = qdev_new(TYPE_MCF_FEC_NET);
qdev_set_nic_properties(dev, nd);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
for (i = 0; i < FEC_NUM_IRQ; i++) {
sysbus_connect_irq(s, i, irqs[i]);
}
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "qemu/module.h"
#include "qemu/log.h"
#include "cpu.h"
DeviceState *dev;
mcf_intc_state *s;
- dev = qdev_create(NULL, TYPE_MCF_INTC);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_MCF_INTC);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
s = MCF_INTC(dev);
s->cpu = cpu;
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, TYPE_ESCC);
+ dev = qdev_new(TYPE_ESCC);
qdev_prop_set_uint32(dev, "disabled", 0);
qdev_prop_set_uint32(dev, "frequency", 9600 * 384);
qdev_prop_set_uint32(dev, "it_shift", 0);
qdev_prop_set_chr(dev, "chrA", serial_hd(0));
qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, ser_irq[0]);
sysbus_connect_irq(s, 1, ser_irq[1]);
sysbus_mmio_map(s, 0, 0x2118000);
memory_region_add_subregion(sysmem, 0x04000000, machine->ram);
/* Framebuffer */
- dev = qdev_create(NULL, TYPE_NEXTFB);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_NEXTFB);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0B000000);
/* MMIO */
memory_region_add_subregion(sysmem, 0x02100000, scrmem);
/* KBD */
- dev = qdev_create(NULL, TYPE_NEXTKBD);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_NEXTKBD);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0200e000);
/* Load ROM here */
/* VIA */
- via_dev = qdev_create(NULL, TYPE_MAC_VIA);
+ via_dev = qdev_new(TYPE_MAC_VIA);
dinfo = drive_get(IF_MTD, 0, 0);
if (dinfo) {
qdev_prop_set_drive(via_dev, "drive", blk_by_legacy_dinfo(dinfo),
&error_abort);
}
- qdev_init_nofail(via_dev);
sysbus = SYS_BUS_DEVICE(via_dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, VIA_BASE);
qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 0, pic[0]);
qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 1, pic[1]);
adb_bus = qdev_get_child_bus(via_dev, "adb.0");
- dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
- qdev_init_nofail(dev);
- dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_ADB_KEYBOARD);
+ qdev_realize_and_unref(dev, adb_bus, &error_fatal);
+ dev = qdev_new(TYPE_ADB_MOUSE);
+ qdev_realize_and_unref(dev, adb_bus, &error_fatal);
/* MACSONIC */
nd_table[0].macaddr.a[1] = 0x00;
nd_table[0].macaddr.a[2] = 0x07;
- dev = qdev_create(NULL, "dp8393x");
+ dev = qdev_new("dp8393x");
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_prop_set_uint8(dev, "it_shift", 2);
qdev_prop_set_bit(dev, "big_endian", true);
object_property_set_link(OBJECT(dev), OBJECT(get_system_memory()),
"dma_mr", &error_abort);
- qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, SONIC_BASE);
sysbus_mmio_map(sysbus, 1, SONIC_PROM_BASE);
sysbus_connect_irq(sysbus, 0, pic[2]);
/* SCC */
- dev = qdev_create(NULL, TYPE_ESCC);
+ dev = qdev_new(TYPE_ESCC);
qdev_prop_set_uint32(dev, "disabled", 0);
qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK);
qdev_prop_set_uint32(dev, "it_shift", 1);
qdev_prop_set_chr(dev, "chrB", serial_hd(1));
qdev_prop_set_uint32(dev, "chnBtype", 0);
qdev_prop_set_uint32(dev, "chnAtype", 0);
- qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_connect_irq(sysbus, 0, pic[3]);
sysbus_connect_irq(sysbus, 1, pic[3]);
sysbus_mmio_map(sysbus, 0, SCC_BASE);
/* SCSI */
- dev = qdev_create(NULL, TYPE_ESP);
+ dev = qdev_new(TYPE_ESP);
sysbus_esp = ESP_STATE(dev);
esp = &sysbus_esp->esp;
esp->dma_memory_read = NULL;
esp->dma_opaque = NULL;
sysbus_esp->it_shift = 4;
esp->dma_enabled = 1;
- qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in_named(via_dev,
"via2-irq",
VIA2_IRQ_SCSI_BIT));
/* SWIM floppy controller */
- dev = qdev_create(NULL, TYPE_SWIM);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_SWIM);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE);
/* NuBus */
- dev = qdev_create(NULL, TYPE_MAC_NUBUS_BRIDGE);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_MAC_NUBUS_BRIDGE);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, NUBUS_SUPER_SLOT_BASE);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, NUBUS_SLOT_BASE);
/* framebuffer in nubus slot #9 */
- dev = qdev_create(BUS(nubus), TYPE_NUBUS_MACFB);
+ dev = qdev_new(TYPE_NUBUS_MACFB);
qdev_prop_set_uint32(dev, "width", graphic_width);
qdev_prop_set_uint32(dev, "height", graphic_height);
qdev_prop_set_uint8(dev, "depth", graphic_depth);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, BUS(nubus), &error_fatal);
cs = CPU(cpu);
if (linux_boot) {
object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
&error_abort);
object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
- object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
+ qdev_realize(DEVICE(cpu), NULL, &error_abort);
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
64 * KiB, 2, 0x89, 0x18, 0x0000, 0x0, 0);
- dev = qdev_create(NULL, "xlnx.xps-intc");
+ dev = qdev_new("xlnx.xps-intc");
qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
DEVICE_LITTLE_ENDIAN);
/* 2 timers at irq 2 @ 100 Mhz. */
- dev = qdev_create(NULL, "xlnx.xps-timer");
+ dev = qdev_new("xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
/* axi ethernet and dma initialization. */
qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet");
- eth0 = qdev_create(NULL, "xlnx.axi-ethernet");
- dma = qdev_create(NULL, "xlnx.axi-dma");
+ eth0 = qdev_new("xlnx.axi-ethernet");
+ dma = qdev_new("xlnx.axi-dma");
/* FIXME: attach to the sysbus instead */
object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0));
"axistream-connected", &error_abort);
object_property_set_link(OBJECT(eth0), cs,
"axistream-control-connected", &error_abort);
- qdev_init_nofail(eth0);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(eth0), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);
"axistream-connected", &error_abort);
object_property_set_link(OBJECT(dma), cs,
"axistream-control-connected", &error_abort);
- qdev_init_nofail(dma);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);
{
SSIBus *spi;
- dev = qdev_create(NULL, "xlnx.xps-spi");
+ dev = qdev_new("xlnx.xps-spi");
qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
- qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, SPI_BASEADDR);
sysbus_connect_irq(busdev, 0, irq[SPI_IRQ]);
DriveInfo *dinfo = drive_get_next(IF_MTD);
qemu_irq cs_line;
- dev = ssi_create_slave_no_init(spi, "n25q128");
+ dev = qdev_new("n25q128");
if (dinfo) {
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, BUS(spi), &error_fatal);
cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
sysbus_connect_irq(busdev, i+1, cs_line);
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
object_property_set_str(OBJECT(cpu), "7.10.d", "version", &error_abort);
- object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
+ qdev_realize(DEVICE(cpu), NULL, &error_abort);
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
- dev = qdev_create(NULL, "xlnx.xps-intc");
+ dev = qdev_new("xlnx.xps-intc");
qdev_prop_set_uint32(dev, "kind-of-intr",
1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
serial_hd(0));
/* 2 timers at irq 2 @ 62 Mhz. */
- dev = qdev_create(NULL, "xlnx.xps-timer");
+ dev = qdev_new("xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
qemu_check_nic_model(&nd_table[0], "xlnx.xps-ethernetlite");
- dev = qdev_create(NULL, "xlnx.xps-ethernetlite");
+ dev = qdev_new("xlnx.xps-ethernetlite");
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
{
XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj);
- object_initialize_child(obj, "pmu-cpu", &s->cpu, sizeof(s->cpu),
- TYPE_MICROBLAZE_CPU, &error_abort, NULL);
+ object_initialize_child(obj, "pmu-cpu", &s->cpu, TYPE_MICROBLAZE_CPU);
- sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
- TYPE_XLNX_PMU_IO_INTC);
+ object_initialize_child(obj, "intc", &s->intc, TYPE_XLNX_PMU_IO_INTC);
/* Create the IPI device */
for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
char *name = g_strdup_printf("ipi%d", i);
- sysbus_init_child_obj(obj, name, &s->ipi[i],
- sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI);
+ object_initialize_child(obj, name, &s->ipi[i], TYPE_XLNX_ZYNQMP_IPI);
g_free(name);
}
}
object_property_set_str(OBJECT(&s->cpu), "8.40.b", "version",
&error_abort);
object_property_set_uint(OBJECT(&s->cpu), 0, "pvr", &error_abort);
- object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
+ qdev_realize(DEVICE(&s->cpu), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
&error_abort);
object_property_set_uint(OBJECT(&s->intc), 0xffff, "intc-positive",
&error_abort);
- object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->intc), &err);
if (err) {
error_propagate(errp, err);
return;
/* Connect the IPI device */
for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
- object_property_set_bool(OBJECT(&s->ipi[i]), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ipi[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi[i]), 0, ipi_addr[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi[i]), 0,
qdev_get_gpio_in(DEVICE(&s->intc), ipi_irq[i]));
/* Create the PMU device */
object_initialize_child(OBJECT(machine), "pmu", pmu,
- sizeof(XlnxZynqMPPMUSoCState),
- TYPE_XLNX_ZYNQMP_PMU_SOC, &error_abort, NULL);
- object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);
+ TYPE_XLNX_ZYNQMP_PMU_SOC);
+ qdev_realize(DEVICE(pmu), NULL, &error_fatal);
/* Load the kernel */
microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
DeviceState *dev;
MemoryRegion *cfg, *mmio;
- dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST);
+ dev = qdev_new(TYPE_XILINX_PCIE_HOST);
qdev_prop_set_uint32(dev, "bus_nr", bus_nr);
qdev_prop_set_uint64(dev, "cfg_base", cfg_base);
qdev_prop_set_uint64(dev, "mmio_size", mmio_size);
qdev_prop_set_bit(dev, "link_up", link_up);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
exit(1);
}
- dev = qdev_create(NULL, TYPE_MIPS_BOSTON);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_MIPS_BOSTON);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
s = BOSTON(dev);
s->mach = machine;
is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64);
- sysbus_init_child_obj(OBJECT(machine), "cps", OBJECT(&s->cps),
- sizeof(s->cps), TYPE_MIPS_CPS);
+ object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS);
object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type",
&error_fatal);
object_property_set_int(OBJECT(&s->cps), machine->smp.cpus, "num-vp",
&error_fatal);
- object_property_set_bool(OBJECT(&s->cps), true, "realized",
- &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
/* Inter-Thread Communication Unit */
if (itu_present) {
- sysbus_init_child_obj(OBJECT(dev), "itu", &s->itu, sizeof(s->itu),
- TYPE_MIPS_ITU);
+ object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU);
object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);
object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present",
if (saar_present) {
s->itu.saar = &env->CP0_SAAR;
}
- object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->itu), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
/* Cluster Power Controller */
- sysbus_init_child_obj(OBJECT(dev), "cpc", &s->cpc, sizeof(s->cpc),
- TYPE_MIPS_CPC);
+ object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC);
object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err);
- object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->cpc), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
/* Global Interrupt Controller */
- sysbus_init_child_obj(OBJECT(dev), "gic", &s->gic, sizeof(s->gic),
- TYPE_MIPS_GIC);
+ object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC);
object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err);
- object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
/* Global Configuration Registers */
gcr_base = env->CP0_CMGCRBase << 4;
- sysbus_init_child_obj(OBJECT(dev), "gcr", &s->gcr, sizeof(s->gcr),
- TYPE_MIPS_GCR);
+ object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR);
object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);
object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);
object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", &err);
object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err);
- object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gcr), &err);
if (err != NULL) {
error_propagate(errp, err);
return;
long bios_size;
uint8_t *spd_data;
int64_t kernel_entry;
+ PCIDevice *pci_dev;
PCIBus *pci_bus;
ISABus *isa_bus;
I2CBus *smbus;
/* GPU */
if (vga_interface_type != VGA_NONE) {
- dev = DEVICE(pci_create(pci_bus, -1, "ati-vga"));
+ pci_dev = pci_new(-1, "ati-vga");
+ dev = DEVICE(pci_dev);
qdev_prop_set_uint32(dev, "vgamem_mb", 16);
qdev_prop_set_uint16(dev, "x-device-id", 0x5159);
- qdev_init_nofail(dev);
+ pci_realize_and_unref(pci_dev, pci_bus, &error_fatal);
}
/* Populate SPD eeprom data */
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "qemu/units.h"
#include "qemu/log.h"
#include "hw/mips/mips.h"
PCIHostState *phb;
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_GT64120_PCI_HOST_BRIDGE);
d = GT64120_PCI_HOST_BRIDGE(dev);
phb = PCI_HOST_BRIDGE(dev);
memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
&d->pci0_mem,
get_system_io(),
PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d,
"isd-mem", 0x1000);
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
- dev = qdev_create(NULL, "sysbus-g364");
- qdev_init_nofail(dev);
+ dev = qdev_new("sysbus-g364");
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, 0x60080000);
sysbus_mmio_map(sysbus, 1, 0x40000000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
if (strcmp(nd->model, "dp83932") == 0) {
qemu_check_nic_model(nd, "dp83932");
- dev = qdev_create(NULL, "dp8393x");
+ dev = qdev_new("dp8393x");
qdev_set_nic_properties(dev, nd);
qdev_prop_set_uint8(dev, "it_shift", 2);
object_property_set_link(OBJECT(dev), OBJECT(rc4030_dma_mr),
"dma_mr", &error_abort);
- qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, 0x80001000);
sysbus_mmio_map(sysbus, 1, 0x8000b000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
}
/* SCSI adapter */
- dev = qdev_create(NULL, TYPE_ESP);
+ dev = qdev_new(TYPE_ESP);
sysbus_esp = ESP_STATE(dev);
esp = &sysbus_esp->esp;
esp->dma_memory_read = rc4030_dma_read;
sysbus_esp->it_shift = 0;
/* XXX for now until rc4030 has been changed to use DMA enable signal */
esp->dma_enabled = 1;
- qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5));
sysbus_mmio_map(sysbus, 0, 0x80002000);
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
/* NVRAM */
- dev = qdev_create(NULL, "ds1225y");
- qdev_init_nofail(dev);
+ dev = qdev_new("ds1225y");
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, 0x80009000);
/* LED indicator */
static void create_cps(MachineState *ms, MaltaState *s,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
- sysbus_init_child_obj(OBJECT(s), "cps", OBJECT(&s->cps), sizeof(s->cps),
- TYPE_MIPS_CPS);
+ object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS);
object_property_set_str(OBJECT(&s->cps), ms->cpu_type, "cpu-type",
&error_fatal);
object_property_set_int(OBJECT(&s->cps), ms->smp.cpus, "num-vp",
&error_fatal);
- object_property_set_bool(OBJECT(&s->cps), true, "realized",
- &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
int fl_idx = 0;
int be;
- DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA);
+ DeviceState *dev = qdev_new(TYPE_MIPS_MALTA);
MaltaState *s = MIPS_MALTA(dev);
/*
*/
empty_slot_init("GT64120", 0, 0x20000000);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* create CPU */
mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "mipsnet");
+ dev = qdev_new("mipsnet");
qdev_set_nic_properties(dev, nd);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, irq);
memory_region_add_subregion(get_system_io(),
base,
* MIPS CPU INT2, which is interrupt 4.
*/
if (serial_hd(0)) {
- DeviceState *dev = qdev_create(NULL, TYPE_SERIAL_IO);
+ DeviceState *dev = qdev_new(TYPE_SERIAL_IO);
qdev_prop_set_chr(dev, "chardev", serial_hd(0));
qdev_set_legacy_instance_id(dev, 0x3f8, 2);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]);
sysbus_add_io(SYS_BUS_DEVICE(dev), 0x3f8,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
k->print_dev = aux_slave_dev_print;
}
-AUXBus *aux_init_bus(DeviceState *parent, const char *name)
+AUXBus *aux_bus_init(DeviceState *parent, const char *name)
{
AUXBus *bus;
Object *auxtoi2c;
bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
auxtoi2c = object_new_with_props(TYPE_AUXTOI2C, OBJECT(bus), "i2c",
&error_abort, NULL);
- qdev_set_parent_bus(DEVICE(auxtoi2c), BUS(bus));
bus->bridge = AUXTOI2C(auxtoi2c);
return bus;
}
+void aux_bus_realize(AUXBus *bus)
+{
+ qdev_realize(DEVICE(bus->bridge), BUS(bus), &error_fatal);
+}
+
void aux_map_slave(AUXSlave *aux_dev, hwaddr addr)
{
DeviceState *dev = DEVICE(aux_dev);
DeviceClass *dc = DEVICE_CLASS(oc);
/* This device is private and is created only once for each
- * aux-bus in aux_init_bus(..). So don't allow the user to add one.
+ * aux-bus in aux_bus_init(..). So don't allow the user to add one.
*/
dc->user_creatable = false;
}
static const TypeInfo aux_to_i2c_type_info = {
.name = TYPE_AUXTOI2C,
- .parent = TYPE_DEVICE,
+ .parent = TYPE_AUX_SLAVE,
.class_init = aux_bridge_class_init,
.instance_size = sizeof(AUXTOI2CState),
.instance_init = aux_bridge_init
memory_region_size(s->mmio));
}
-DeviceState *aux_create_slave(AUXBus *bus, const char *type)
-{
- DeviceState *dev;
-
- dev = DEVICE(object_new(type));
- assert(dev);
- qdev_set_parent_bus(dev, &bus->qbus);
- return dev;
-}
-
void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio)
{
assert(!aux_slave->mmio);
#include "hw/sysbus.h"
#include "hw/qdev-properties.h"
#include "hw/misc/empty_slot.h"
+#include "qapi/error.h"
#include "trace.h"
#define TYPE_EMPTY_SLOT "empty_slot"
/* Only empty slots larger than 0 byte need handling. */
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_EMPTY_SLOT);
+ dev = qdev_new(TYPE_EMPTY_SLOT);
qdev_prop_set_uint64(dev, "size", slot_size);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, addr, -10000);
}
int ret;
/* Init VIAs 1 and 2 */
- sysbus_init_child_obj(OBJECT(dev), "via1", &m->mos6522_via1,
- sizeof(m->mos6522_via1), TYPE_MOS6522_Q800_VIA1);
+ object_initialize_child(OBJECT(dev), "via1", &m->mos6522_via1,
+ TYPE_MOS6522_Q800_VIA1);
- sysbus_init_child_obj(OBJECT(dev), "via2", &m->mos6522_via2,
- sizeof(m->mos6522_via2), TYPE_MOS6522_Q800_VIA2);
+ object_initialize_child(OBJECT(dev), "via2", &m->mos6522_via2,
+ TYPE_MOS6522_Q800_VIA2);
/* Pass through mos6522 output IRQs */
ms = MOS6522(&m->mos6522_via1);
object_property_add_alias(OBJECT(dev), "irq[1]", OBJECT(ms),
SYSBUS_DEVICE_GPIO_IRQ "[0]");
+ sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via1), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via2), &error_abort);
+
/* Pass through mos6522 input IRQs */
qdev_pass_gpios(DEVICE(&m->mos6522_via1), dev, "via1-irq");
qdev_pass_gpios(DEVICE(&m->mos6522_via2), dev, "via2-irq");
#include "hw/input/adb.h"
#include "hw/misc/mos6522.h"
#include "hw/misc/macio/cuda.h"
+#include "qapi/error.h"
#include "qemu/timer.h"
#include "sysemu/runstate.h"
+#include "qapi/error.h"
#include "qemu/cutils.h"
#include "qemu/log.h"
#include "qemu/module.h"
static void cuda_realize(DeviceState *dev, Error **errp)
{
CUDAState *s = CUDA(dev);
+ Error *err = NULL;
SysBusDevice *sbd;
- MOS6522State *ms;
- DeviceState *d;
struct tm tm;
+ sysbus_realize(SYS_BUS_DEVICE(&s->mos6522_cuda), &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
/* Pass IRQ from 6522 */
- d = DEVICE(&s->mos6522_cuda);
- ms = MOS6522(d);
sbd = SYS_BUS_DEVICE(s);
- sysbus_pass_irq(sbd, SYS_BUS_DEVICE(ms));
+ sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->mos6522_cuda));
qemu_get_timedate(&tm, 0);
s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
CUDAState *s = CUDA(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
- sysbus_init_child_obj(obj, "mos6522-cuda", &s->mos6522_cuda,
- sizeof(s->mos6522_cuda), TYPE_MOS6522_CUDA);
+ object_initialize_child(obj, "mos6522-cuda", &s->mos6522_cuda,
+ TYPE_MOS6522_CUDA);
memory_region_init_io(&s->mem, obj, &mos6522_cuda_ops, s, "cuda", 0x2000);
sysbus_init_mmio(sbd, &s->mem);
macio_escc_legacy_setup(s);
}
-static void macio_init_child_obj(MacIOState *s, const char *childname,
- void *child, size_t childsize,
- const char *childtype)
-{
- object_initialize_child(OBJECT(s), childname, child, childsize, childtype,
- &error_abort, NULL);
- qdev_set_parent_bus(DEVICE(child), BUS(&s->macio_bus));
-}
-
static void macio_common_realize(PCIDevice *d, Error **errp)
{
MacIOState *s = MACIO(d);
SysBusDevice *sysbus_dev;
Error *err = NULL;
- object_property_set_bool(OBJECT(&s->dbdma), true, "realized", &err);
+ qdev_realize(DEVICE(&s->dbdma), BUS(&s->macio_bus), &err);
if (err) {
error_propagate(errp, err);
return;
qdev_prop_set_chr(DEVICE(&s->escc), "chrB", serial_hd(1));
qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial);
qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial);
- object_property_set_bool(OBJECT(&s->escc), true, "realized", &err);
+ qdev_realize(DEVICE(&s->escc), BUS(&s->macio_bus), &err);
if (err) {
error_propagate(errp, err);
return;
object_property_set_link(OBJECT(ide), OBJECT(&s->dbdma), "dbdma", errp);
macio_ide_register_dma(ide);
- object_property_set_bool(OBJECT(ide), true, "realized", errp);
+ qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp);
}
static void macio_oldworld_realize(PCIDevice *d, Error **errp)
qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
s->frequency);
- object_property_set_bool(OBJECT(&s->cuda), true, "realized", &err);
+ qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), &err);
if (err) {
error_propagate(errp, err);
return;
sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev,
OLDWORLD_ESCCA_IRQ));
- object_property_set_bool(OBJECT(&os->nvram), true, "realized", &err);
+ qdev_realize(DEVICE(&os->nvram), BUS(&s->macio_bus), &err);
if (err) {
error_propagate(errp, err);
return;
}
}
-static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, size_t ide_size,
- int index)
+static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, int index)
{
gchar *name = g_strdup_printf("ide[%i]", index);
uint32_t addr = 0x1f000 + ((index + 1) * 0x1000);
- macio_init_child_obj(s, name, ide, ide_size, TYPE_MACIO_IDE);
+ object_initialize_child(OBJECT(s), name, ide, TYPE_MACIO_IDE);
qdev_prop_set_uint32(DEVICE(ide), "addr", addr);
memory_region_add_subregion(&s->bar, addr, &ide->mem);
g_free(name);
qdev_prop_allow_set_link_before_realize,
0);
- macio_init_child_obj(s, "cuda", &s->cuda, sizeof(s->cuda), TYPE_CUDA);
+ object_initialize_child(OBJECT(s), "cuda", &s->cuda, TYPE_CUDA);
- object_initialize(&os->nvram, sizeof(os->nvram), TYPE_MACIO_NVRAM);
+ object_initialize_child(OBJECT(s), "nvram", &os->nvram, TYPE_MACIO_NVRAM);
dev = DEVICE(&os->nvram);
qdev_prop_set_uint32(dev, "size", 0x2000);
qdev_prop_set_uint32(dev, "it_shift", 4);
for (i = 0; i < 2; i++) {
- macio_init_ide(s, &os->ide[i], sizeof(os->ide[i]), i);
+ macio_init_ide(s, &os->ide[i], i);
}
}
&error_abort);
memory_region_add_subregion(&s->bar, 0x50,
sysbus_mmio_get_region(sysbus_dev, 0));
- object_property_set_bool(OBJECT(&ns->gpio), true, "realized", &err);
+ qdev_realize(DEVICE(&ns->gpio), BUS(&s->macio_bus), &err);
/* PMU */
- object_initialize_child(OBJECT(s), "pmu", &s->pmu, sizeof(s->pmu),
- TYPE_VIA_PMU, &error_abort, NULL);
+ object_initialize_child(OBJECT(s), "pmu", &s->pmu, TYPE_VIA_PMU);
object_property_set_link(OBJECT(&s->pmu), OBJECT(sysbus_dev), "gpio",
&error_abort);
qdev_prop_set_bit(DEVICE(&s->pmu), "has-adb", ns->has_adb);
- qdev_set_parent_bus(DEVICE(&s->pmu), BUS(&s->macio_bus));
-
- object_property_set_bool(OBJECT(&s->pmu), true, "realized", &err);
+ qdev_realize(DEVICE(&s->pmu), BUS(&s->macio_bus), &err);
if (err) {
error_propagate(errp, err);
return;
memory_region_add_subregion(&s->bar, 0x16000,
sysbus_mmio_get_region(sysbus_dev, 0));
} else {
+ object_unparent(OBJECT(&ns->gpio));
+
/* CUDA */
- object_initialize_child(OBJECT(s), "cuda", &s->cuda, sizeof(s->cuda),
- TYPE_CUDA, &error_abort, NULL);
- qdev_set_parent_bus(DEVICE(&s->cuda), BUS(&s->macio_bus));
+ object_initialize_child(OBJECT(s), "cuda", &s->cuda, TYPE_CUDA);
qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
s->frequency);
- object_property_set_bool(OBJECT(&s->cuda), true, "realized", &err);
+ qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), &err);
if (err) {
error_propagate(errp, err);
return;
qdev_prop_allow_set_link_before_realize,
0);
- macio_init_child_obj(s, "gpio", &ns->gpio, sizeof(ns->gpio),
- TYPE_MACIO_GPIO);
+ object_initialize_child(OBJECT(s), "gpio", &ns->gpio, TYPE_MACIO_GPIO);
for (i = 0; i < 2; i++) {
- macio_init_ide(s, &ns->ide[i], sizeof(ns->ide[i]), i);
+ macio_init_ide(s, &ns->ide[i], i);
}
}
qbus_create_inplace(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS,
DEVICE(obj), "macio.0");
- macio_init_child_obj(s, "dbdma", &s->dbdma, sizeof(s->dbdma),
- TYPE_MAC_DBDMA);
+ object_initialize_child(OBJECT(s), "dbdma", &s->dbdma, TYPE_MAC_DBDMA);
- macio_init_child_obj(s, "escc", &s->escc, sizeof(s->escc), TYPE_ESCC);
+ object_initialize_child(OBJECT(s), "escc", &s->escc, TYPE_ESCC);
}
static const VMStateDescription vmstate_macio_oldworld = {
static const TypeInfo macio_bus_info = {
.name = TYPE_MACIO_BUS,
- .parent = TYPE_BUS,
+ .parent = TYPE_SYSTEM_BUS,
.instance_size = sizeof(MacIOBusState),
};
#include "hw/misc/mos6522.h"
#include "hw/misc/macio/gpio.h"
#include "hw/misc/macio/pmu.h"
+#include "qapi/error.h"
#include "qemu/timer.h"
#include "sysemu/runstate.h"
+#include "qapi/error.h"
#include "qemu/cutils.h"
#include "qemu/log.h"
#include "qemu/module.h"
static void pmu_realize(DeviceState *dev, Error **errp)
{
PMUState *s = VIA_PMU(dev);
+ Error *err = NULL;
SysBusDevice *sbd;
- MOS6522State *ms;
- DeviceState *d;
struct tm tm;
+ sysbus_realize(SYS_BUS_DEVICE(&s->mos6522_pmu), &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
/* Pass IRQ from 6522 */
- d = DEVICE(&s->mos6522_pmu);
- ms = MOS6522(d);
sbd = SYS_BUS_DEVICE(s);
- sysbus_pass_irq(sbd, SYS_BUS_DEVICE(ms));
+ sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->mos6522_pmu));
qemu_get_timedate(&tm, 0);
s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
qdev_prop_allow_set_link_before_realize,
0);
- sysbus_init_child_obj(obj, "mos6522-pmu", &s->mos6522_pmu,
- sizeof(s->mos6522_pmu), TYPE_MOS6522_PMU);
+ object_initialize_child(obj, "mos6522-pmu", &s->mos6522_pmu,
+ TYPE_MOS6522_PMU);
memory_region_init_io(&s->mem, obj, &mos6522_pmu_ops, s, "via-pmu",
0x2000);
DeviceState *dev;
qemu_check_nic_model(nd, "fseth");
- dev = qdev_create(NULL, "etraxfs-eth");
+ dev = qdev_new("etraxfs-eth");
qdev_set_nic_properties(dev, nd);
qdev_prop_set_uint32(dev, "phyaddr", phyaddr);
*/
ETRAX_FS_ETH(dev)->dma_out = dma_out;
ETRAX_FS_ETH(dev)->dma_in = dma_in;
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return dev;
#include "hw/qdev-properties.h"
#include "etsec.h"
#include "registers.h"
+#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
{
DeviceState *dev;
- dev = qdev_create(NULL, "eTSEC");
+ dev = qdev_new("eTSEC");
qdev_set_nic_properties(dev, nd);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, tx_irq);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, rx_irq);
#include "hw/net/lan9118.h"
#include "hw/ptimer.h"
#include "hw/qdev-properties.h"
+#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
/* For crc32 */
SysBusDevice *s;
qemu_check_nic_model(nd, "lan9118");
- dev = qdev_create(NULL, TYPE_LAN9118);
+ dev = qdev_new(TYPE_LAN9118);
qdev_set_nic_properties(dev, nd);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "qemu/timer.h"
#include "hw/sysbus.h"
#include "net/eth.h"
.a = { 0x08, 0x00, 0x09, 0xef, 0x34, 0xf6 } };
qemu_check_nic_model(&nd_table[0], TYPE_LASI_82596);
- dev = qdev_create(NULL, TYPE_LASI_82596);
+ dev = qdev_new(TYPE_LASI_82596);
s = SYSBUS_I82596(dev);
s->state.irq = lan_irq;
qdev_set_nic_properties(dev, &nd_table[0]);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
s->state.conf.macaddr = HP_MAC; /* set HP MAC prefix */
/* LASI 82596 ports in main memory. */
#include "hw/irq.h"
#include "hw/net/smc91c111.h"
#include "hw/qdev-properties.h"
+#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
/* For crc32 */
SysBusDevice *s;
qemu_check_nic_model(nd, "smc91c111");
- dev = qdev_create(NULL, TYPE_SMC91C111);
+ dev = qdev_new(TYPE_SMC91C111);
qdev_set_nic_properties(dev, nd);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
{
DeviceState *dev;
- dev = qdev_create(&bus->bus, "spapr-vlan");
+ dev = qdev_new("spapr-vlan");
qdev_set_nic_properties(dev, nd);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, &bus->bus, &error_fatal);
}
static int spapr_vlan_devnode(SpaprVioDevice *dev, void *fdt, int node_off)
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
object_initialize_child(OBJECT(s), "axistream-connected-target",
- &s->rx_data_dev, sizeof(s->rx_data_dev),
- TYPE_XILINX_AXI_ENET_DATA_STREAM, &error_abort,
- NULL);
+ &s->rx_data_dev, TYPE_XILINX_AXI_ENET_DATA_STREAM);
object_initialize_child(OBJECT(s), "axistream-control-connected-target",
- &s->rx_control_dev, sizeof(s->rx_control_dev),
- TYPE_XILINX_AXI_ENET_CONTROL_STREAM, &error_abort,
- NULL);
+ &s->rx_control_dev,
+ TYPE_XILINX_AXI_ENET_CONTROL_STREAM);
sysbus_init_irq(sbd, &s->irq);
memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000);
cpu_irq = nios2_cpu_pic_init(cpu);
/* Register: Internal Interrupt Controller (IIC) */
- dev = qdev_create(NULL, "altera,iic");
+ dev = qdev_new("altera,iic");
object_property_add_const_link(OBJECT(dev), "cpu", OBJECT(cpu));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(dev, i);
serial_hd(0), DEVICE_NATIVE_ENDIAN);
/* Register: Timer sys_clk_timer */
- dev = qdev_create(NULL, "ALTR.timer");
+ dev = qdev_new("ALTR.timer");
qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xf8001440);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[0]);
/* Register: Timer sys_clk_timer_1 */
- dev = qdev_create(NULL, "ALTR.timer");
+ dev = qdev_new("ALTR.timer");
qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]);
FWCfgState *s;
bool dma_requested = dma_iobase && dma_as;
- dev = qdev_create(NULL, TYPE_FW_CFG_IO);
+ dev = qdev_new(TYPE_FW_CFG_IO);
if (!dma_requested) {
qdev_prop_set_bit(dev, "dma_enabled", false);
}
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(dev));
- qdev_init_nofail(dev);
sbd = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbd, &error_fatal);
ios = FW_CFG_IO(dev);
sysbus_add_io(sbd, iobase, &ios->comb_iomem);
FWCfgState *s;
bool dma_requested = dma_addr && dma_as;
- dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
+ dev = qdev_new(TYPE_FW_CFG_MEM);
qdev_prop_set_uint32(dev, "data_width", data_width);
if (!dma_requested) {
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(dev));
- qdev_init_nofail(dev);
sbd = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbd, &error_fatal);
sysbus_mmio_map(sbd, 0, ctl_addr);
sysbus_mmio_map(sbd, 1, data_addr);
SysBusDevice *s;
int i;
- dev = qdev_create(NULL, "open_eth");
+ dev = qdev_new("open_eth");
qdev_set_nic_properties(dev, nd);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
for (i = 0; i < num_cpus; i++) {
sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]);
}
SysBusDevice *s;
int i;
- dev = qdev_create(NULL, "or1k-ompic");
+ dev = qdev_new("or1k-ompic");
qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
for (i = 0; i < num_cpus; i++) {
sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]);
}
#include "qemu/osdep.h"
#include "dec.h"
#include "hw/sysbus.h"
+#include "qapi/error.h"
#include "qemu/module.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
PCIDevice *dev;
PCIBridge *br;
- dev = pci_create_multifunction(parent_bus, devfn, false,
- "dec-21154-p2p-bridge");
+ dev = pci_new_multifunction(devfn, false, "dec-21154-p2p-bridge");
br = PCI_BRIDGE(dev);
pci_bridge_map_irq(br, "DEC 21154 PCI-PCI bridge", dec_map_irq);
- qdev_init_nofail(&dev->qdev);
+ pci_realize_and_unref(dev, parent_bus, &error_fatal);
return pci_bridge_get_sec_bus(br);
}
dev_name = dev->qdev.id;
}
- ds = qdev_create(NULL, TYPE_PXB_HOST);
+ ds = qdev_new(TYPE_PXB_HOST);
if (pcie) {
bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS);
} else {
bus = pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_PXB_BUS);
- bds = qdev_create(BUS(bus), "pci-bridge");
+ bds = qdev_new("pci-bridge");
bds->id = dev_name;
qdev_prop_set_uint8(bds, PCI_BRIDGE_DEV_PROP_CHASSIS_NR, pxb->bus_nr);
qdev_prop_set_bit(bds, PCI_BRIDGE_DEV_PROP_SHPC, false);
goto err_register_bus;
}
- qdev_init_nofail(ds);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(ds), &error_fatal);
if (bds) {
- qdev_init_nofail(bds);
+ qdev_realize_and_unref(bds, &bus->qbus, &error_fatal);
}
pci_word_test_and_set_mask(dev->config + PCI_STATUS,
#include "qemu/osdep.h"
#include "qemu/units.h"
+#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/pci/pci.h"
#include "hw/irq.h"
PCIBonitoState *s;
PCIDevice *d;
- dev = qdev_create(NULL, TYPE_BONITO_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_BONITO_PCI_HOST_BRIDGE);
phb = PCI_HOST_BRIDGE(dev);
pcihost = BONITO_PCI_HOST_BRIDGE(dev);
pcihost->pic = pic;
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- d = pci_create(phb->bus, PCI_DEVFN(0, 0), TYPE_PCI_BONITO);
+ d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO);
s = PCI_BONITO(d);
s->pcihost = pcihost;
pcihost->pci_dev = s;
- qdev_init_nofail(DEVICE(d));
+ pci_realize_and_unref(d, phb->bus, &error_fatal);
return phb->bus;
}
"pcie-bus-address-space");
pci_setup_iommu(pci->bus, designware_pcie_host_set_iommu, s);
- qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus));
- qdev_init_nofail(DEVICE(&s->root));
+ qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal);
}
static const VMStateDescription vmstate_designware_pcie_host = {
DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(obj);
DesignwarePCIERoot *root = &s->root;
- object_initialize_child(obj, "root", root, sizeof(*root),
- TYPE_DESIGNWARE_PCIE_ROOT, &error_abort, NULL);
+ object_initialize_child(obj, "root", root, TYPE_DESIGNWARE_PCIE_ROOT);
qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
qdev_prop_set_bit(DEVICE(root), "multifunction", false);
}
pci_swizzle_map_irq_fn, s, &s->io_mmio,
&s->io_ioport, 0, 4, TYPE_PCIE_BUS);
- qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));
pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
- qdev_init_nofail(DEVICE(&s->gpex_root));
+ qdev_realize(DEVICE(&s->gpex_root), BUS(pci->bus), &error_fatal);
}
static const char *gpex_host_root_bus_path(PCIHostState *host_bridge,
GPEXHost *s = GPEX_HOST(obj);
GPEXRootState *root = &s->gpex_root;
- object_initialize_child(obj, "gpex_root", root, sizeof(*root),
- TYPE_GPEX_ROOT_DEVICE, &error_abort, NULL);
+ object_initialize_child(obj, "gpex_root", root, TYPE_GPEX_ROOT_DEVICE);
qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
qdev_prop_set_bit(DEVICE(root), "multifunction", false);
}
unsigned i;
I440FXState *i440fx;
- dev = qdev_create(NULL, host_type);
+ dev = qdev_new(host_type);
s = PCI_HOST_BRIDGE(dev);
b = pci_root_bus_new(dev, NULL, pci_address_space,
address_space_io, 0, TYPE_PCI_BUS);
s->bus = b;
object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
d = pci_create_simple(b, 0, pci_type);
*pi440fx_state = I440FX_PCI_DEVICE(d);
QLIST_INIT(&phb->dma_spaces);
/* LSI sources */
- object_initialize_child(obj, "lsi", &phb->lsis, sizeof(phb->lsis),
- TYPE_ICS, &error_abort, NULL);
+ object_initialize_child(obj, "lsi", &phb->lsis, TYPE_ICS);
/* Default init ... will be fixed by HW inits */
phb->lsis.offset = 0;
/* MSI sources */
- object_initialize_child(obj, "msi", &phb->msis, sizeof(phb->msis),
- TYPE_PHB3_MSI, &error_abort, NULL);
+ object_initialize_child(obj, "msi", &phb->msis, TYPE_PHB3_MSI);
/* Power Bus Common Queue */
- object_initialize_child(obj, "pbcq", &phb->pbcq, sizeof(phb->pbcq),
- TYPE_PNV_PBCQ, &error_abort, NULL);
+ object_initialize_child(obj, "pbcq", &phb->pbcq, TYPE_PNV_PBCQ);
/* Root Port */
- object_initialize_child(obj, "root", &phb->root, sizeof(phb->root),
- TYPE_PNV_PHB3_ROOT_PORT, &error_abort, NULL);
+ object_initialize_child(obj, "root", &phb->root, TYPE_PNV_PHB3_ROOT_PORT);
qdev_prop_set_int32(DEVICE(&phb->root), "addr", PCI_DEVFN(0, 0));
qdev_prop_set_bit(DEVICE(&phb->root), "multifunction", false);
}
&error_abort);
object_property_set_int(OBJECT(&phb->lsis), PNV_PHB3_NUM_LSI, "nr-irqs",
&error_abort);
- object_property_set_bool(OBJECT(&phb->lsis), true, "realized", &local_err);
+ qdev_realize(DEVICE(&phb->lsis), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
&error_abort);
object_property_set_int(OBJECT(&phb->msis), PHB3_MAX_MSI, "nr-irqs",
&error_abort);
- object_property_set_bool(OBJECT(&phb->msis), true, "realized", &local_err);
+ qdev_realize(DEVICE(&phb->msis), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
/* Power Bus Common Queue */
object_property_set_link(OBJECT(&phb->pbcq), OBJECT(phb), "phb",
&error_abort);
- object_property_set_bool(OBJECT(&phb->pbcq), true, "realized", &local_err);
+ qdev_realize(DEVICE(&phb->pbcq), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
/* Add a single Root port */
qdev_prop_set_uint8(DEVICE(&phb->root), "chassis", phb->chip_id);
qdev_prop_set_uint16(DEVICE(&phb->root), "slot", phb->phb_id);
- qdev_set_parent_bus(DEVICE(&phb->root), BUS(pci->bus));
- qdev_init_nofail(DEVICE(&phb->root));
+ qdev_realize(DEVICE(&phb->root), BUS(pci->bus), &error_fatal);
}
void pnv_phb3_update_regions(PnvPHB3 *phb)
QLIST_INIT(&phb->dma_spaces);
/* XIVE interrupt source object */
- object_initialize_child(obj, "source", &phb->xsrc, sizeof(XiveSource),
- TYPE_XIVE_SOURCE, &error_abort, NULL);
+ object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE);
/* Root Port */
- object_initialize_child(obj, "root", &phb->root, sizeof(phb->root),
- TYPE_PNV_PHB4_ROOT_PORT, &error_abort, NULL);
+ object_initialize_child(obj, "root", &phb->root, TYPE_PNV_PHB4_ROOT_PORT);
qdev_prop_set_int32(DEVICE(&phb->root), "addr", PCI_DEVFN(0, 0));
qdev_prop_set_bit(DEVICE(&phb->root), "multifunction", false);
/* Add a single Root port */
qdev_prop_set_uint8(DEVICE(&phb->root), "chassis", phb->chip_id);
qdev_prop_set_uint16(DEVICE(&phb->root), "slot", phb->phb_id);
- qdev_set_parent_bus(DEVICE(&phb->root), BUS(pci->bus));
- qdev_init_nofail(DEVICE(&phb->root));
+ qdev_realize(DEVICE(&phb->root), BUS(pci->bus), &error_fatal);
/* Setup XIVE Source */
if (phb->big_phb) {
}
object_property_set_int(OBJECT(xsrc), nr_irqs, "nr-irqs", &error_fatal);
object_property_set_link(OBJECT(xsrc), OBJECT(phb), "xive", &error_fatal);
- object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
+ qdev_realize(DEVICE(xsrc), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
for (i = 0; i < PHB4_PEC_MAX_STACKS; i++) {
object_initialize_child(obj, "stack[*]", &pec->stacks[i],
- sizeof(pec->stacks[i]), TYPE_PNV_PHB4_PEC_STACK,
- &error_abort, NULL);
+ TYPE_PNV_PHB4_PEC_STACK);
}
}
object_property_set_int(stk_obj, i, "stack-no", &error_abort);
object_property_set_link(stk_obj, OBJECT(pec), "pec", &error_abort);
- object_property_set_bool(stk_obj, true, "realized", &local_err);
+ qdev_realize(DEVICE(stk_obj), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
}
+ for (; i < PHB4_PEC_MAX_STACKS; i++) {
+ object_unparent(OBJECT(&pec->stacks[i]));
+ }
/* Initialize the XSCOM regions for the PEC registers */
snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id,
{
PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(obj);
- object_initialize_child(obj, "phb", &stack->phb, sizeof(stack->phb),
- TYPE_PNV_PHB4, &error_abort, NULL);
+ object_initialize_child(obj, "phb", &stack->phb, TYPE_PNV_PHB4);
}
static void pnv_pec_stk_realize(DeviceState *dev, Error **errp)
s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
object_property_set_int(OBJECT(s->or_irq), PCI_NUM_PINS, "num-lines",
&error_fatal);
- object_property_set_bool(OBJECT(s->or_irq), true, "realized",
- &error_fatal);
+ qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal);
sysbus_init_irq(dev, &s->or_irq->out_irq);
for (i = 0; i < PCI_NUM_PINS; i++) {
memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
/* TODO Remove once realize propagates to child devices. */
- object_property_set_bool(OBJECT(&s->pci_bus), true, "realized", errp);
- object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
+ qdev_realize(DEVICE(&s->pci_dev), BUS(&s->pci_bus), errp);
}
static void raven_pcihost_initfn(Object *obj)
object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
pci_dev = DEVICE(&s->pci_dev);
- qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
NULL);
qdev_prop_set_bit(pci_dev, "multifunction", false);
s->mch.address_space_io,
0, TYPE_PCIE_BUS);
PC_MACHINE(qdev_get_machine())->bus = pci->bus;
- qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
- qdev_init_nofail(DEVICE(&s->mch));
+ qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal);
}
static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
"pci-conf-data", 4);
- object_initialize_child(OBJECT(s), "mch", &s->mch, sizeof(s->mch),
- TYPE_MCH_PCI_DEVICE, &error_abort, NULL);
+ object_initialize_child(OBJECT(s), "mch", &s->mch, TYPE_MCH_PCI_DEVICE);
qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
/* mch's object_initialize resets the default value, set it again */
#include "hw/pci-bridge/simba.h"
#include "hw/pci-host/sabre.h"
#include "exec/address-spaces.h"
+#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "sysemu/runstate.h"
pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu);
/* APB secondary busses */
- pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
- TYPE_SIMBA_PCI_BRIDGE);
+ pci_dev = pci_new_multifunction(PCI_DEVFN(1, 0), true,
+ TYPE_SIMBA_PCI_BRIDGE);
s->bridgeB = PCI_BRIDGE(pci_dev);
pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq);
- qdev_init_nofail(&pci_dev->qdev);
+ pci_realize_and_unref(pci_dev, phb->bus, &error_fatal);
- pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
- TYPE_SIMBA_PCI_BRIDGE);
+ pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), true,
+ TYPE_SIMBA_PCI_BRIDGE);
s->bridgeA = PCI_BRIDGE(pci_dev);
pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq);
- qdev_init_nofail(&pci_dev->qdev);
+ pci_realize_and_unref(pci_dev, phb->bus, &error_fatal);
}
static void sabre_init(Object *obj)
h->bus = &s->pci_bus;
object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_VERSATILE_PCI_HOST);
- qdev_set_parent_bus(DEVICE(&s->pci_dev), BUS(&s->pci_bus));
for (i = 0; i < 4; i++) {
sysbus_init_irq(sbd, &s->irq[i]);
}
/* TODO Remove once realize propagates to child devices. */
- object_property_set_bool(OBJECT(&s->pci_bus), true, "realized", errp);
- object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
+ qdev_realize(DEVICE(&s->pci_dev), BUS(&s->pci_bus), errp);
}
static void versatile_pci_host_realize(PCIDevice *d, Error **errp)
pci_swizzle_map_irq_fn, s, &s->mmio,
&s->io, 0, 4, TYPE_PCIE_BUS);
- qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus));
- qdev_init_nofail(DEVICE(&s->root));
+ qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal);
}
static const char *xilinx_pcie_host_root_bus_path(PCIHostState *host_bridge,
XilinxPCIEHost *s = XILINX_PCIE_HOST(obj);
XilinxPCIERoot *root = &s->root;
- object_initialize_child(obj, "root", root, sizeof(*root),
- TYPE_XILINX_PCIE_ROOT, &error_abort, NULL);
+ object_initialize_child(obj, "root", root, TYPE_XILINX_PCIE_ROOT);
qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
qdev_prop_set_bit(DEVICE(root), "multifunction", false);
}
{
pci_bus_uninit(bus);
/* the caller of the unplug hotplug handler will delete this device */
- object_property_set_bool(OBJECT(bus), false, "realized", &error_abort);
+ qbus_unrealize(BUS(bus));
}
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
exit(1);
}
- pci_dev = pci_create(bus, devfn, nd->model);
+ pci_dev = pci_new(devfn, nd->model);
dev = &pci_dev->qdev;
qdev_set_nic_properties(dev, nd);
- qdev_init_nofail(dev);
+ pci_realize_and_unref(pci_dev, bus, &error_fatal);
g_ptr_array_free(pci_nic_models, true);
return pci_dev;
}
}
}
-PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
- const char *name)
+PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
+ const char *name)
{
DeviceState *dev;
- dev = qdev_create(&bus->qbus, name);
+ dev = qdev_new(name);
qdev_prop_set_int32(dev, "addr", devfn);
qdev_prop_set_bit(dev, "multifunction", multifunction);
return PCI_DEVICE(dev);
}
+PCIDevice *pci_new(int devfn, const char *name)
+{
+ return pci_new_multifunction(devfn, false, name);
+}
+
+bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp)
+{
+ return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp);
+}
+
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
bool multifunction,
const char *name)
{
- PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
- qdev_init_nofail(&dev->qdev);
+ PCIDevice *dev = pci_new_multifunction(devfn, multifunction, name);
+ pci_realize_and_unref(dev, bus, &error_fatal);
return dev;
}
-PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
-{
- return pci_create_multifunction(bus, devfn, false, name);
-}
-
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
{
return pci_create_simple_multifunction(bus, devfn, false, name);
void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
- object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+ qdev_unrealize(dev);
}
static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque)
void shpc_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
- object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+ qdev_unrealize(dev);
}
void shpc_device_unplug_request_cb(HotplugHandler *hotplug_dev,
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
+#include "qapi/error.h"
#include "qemu/module.h"
#include "hw/pcmcia.h"
#include "hw/arm/pxa.h"
DeviceState *dev;
PXA2xxPCMCIAState *s;
- dev = qdev_create(NULL, TYPE_PXA2XX_PCMCIA);
+ dev = qdev_new(TYPE_PXA2XX_PCMCIA);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
s = PXA2XX_PCMCIA(dev);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
return s;
}
unsigned int smp_cpus = machine->smp.cpus;
const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
- dev = qdev_create(NULL, TYPE_OPENPIC);
+ dev = qdev_new(TYPE_OPENPIC);
object_property_add_child(OBJECT(machine), "pic", OBJECT(dev));
qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
k = 0;
for (i = 0; i < smp_cpus; i++) {
DeviceState *dev;
CPUState *cs;
- dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
+ dev = qdev_new(TYPE_KVM_OPENPIC);
qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
- object_property_set_bool(OBJECT(dev), true, "realized", &err);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &err);
if (err) {
error_propagate(errp, err);
object_unparent(OBJECT(dev));
/* Register Memory */
memory_region_add_subregion(address_space_mem, 0, machine->ram);
- dev = qdev_create(NULL, "e500-ccsr");
+ dev = qdev_new("e500-ccsr");
object_property_add_child(qdev_get_machine(), "e500-ccsr",
OBJECT(dev));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ccsr = CCSR(dev);
ccsr_addr_space = &ccsr->ccsr_space;
memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
serial_hd(1), DEVICE_BIG_ENDIAN);
}
/* I2C */
- dev = qdev_create(NULL, "mpc-i2c");
+ dev = qdev_new("mpc-i2c");
s = SYS_BUS_DEVICE(dev);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ));
memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET,
sysbus_mmio_get_region(s, 0));
/* General Utility device */
- dev = qdev_create(NULL, "mpc8544-guts");
- qdev_init_nofail(dev);
+ dev = qdev_new("mpc8544-guts");
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
sysbus_mmio_get_region(s, 0));
/* PCI */
- dev = qdev_create(NULL, "e500-pcihost");
+ dev = qdev_new("e500-pcihost");
object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev));
qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
for (i = 0; i < PCI_NUM_PINS; i++) {
sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
}
if (pmc->has_mpc8xxx_gpio) {
qemu_irq poweroff_irq;
- dev = qdev_create(NULL, "mpc8xxx_gpio");
+ dev = qdev_new("mpc8xxx_gpio");
s = SYS_BUS_DEVICE(dev);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
sysbus_mmio_get_region(s, 0));
/* Platform Bus Device */
if (pmc->has_platform_bus) {
- dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
+ dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
dev->id = TYPE_PLATFORM_BUS_DEVICE;
qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
s = SYS_BUS_DEVICE(pms->pbus_dev);
long kernel_size, initrd_size;
UNINHostState *uninorth_pci;
PCIBus *pci_bus;
- NewWorldMacIOState *macio;
+ PCIDevice *macio;
bool has_pmu, has_adb;
MACIOIDEState *macio_ide;
BusState *adb_bus;
}
/* UniN init */
- dev = qdev_create(NULL, TYPE_UNI_NORTH);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_UNI_NORTH);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
memory_region_add_subregion(get_system_memory(), 0xf8000000,
sysbus_mmio_get_region(s, 0));
}
}
- pic_dev = qdev_create(NULL, TYPE_OPENPIC);
+ pic_dev = qdev_new(TYPE_OPENPIC);
qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO);
- qdev_init_nofail(pic_dev);
s = SYS_BUS_DEVICE(pic_dev);
+ sysbus_realize_and_unref(s, &error_fatal);
k = 0;
for (i = 0; i < smp_cpus; i++) {
for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
/* 970 gets a U3 bus */
/* Uninorth AGP bus */
- dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
+ dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
s = SYS_BUS_DEVICE(dev);
/* PCI hole */
} else {
/* Use values found on a real PowerMac */
/* Uninorth AGP bus */
- dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
+ dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000);
/* Uninorth internal bus */
- dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, 0xf4800000);
sysbus_mmio_map(s, 1, 0xf4c00000);
/* Uninorth main bus */
- dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev);
s = SYS_BUS_DEVICE(dev);
/* PCI hole */
pci_bus = PCI_HOST_BRIDGE(uninorth_pci)->bus;
/* MacIO */
- macio = NEWWORLD_MACIO(pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO));
+ macio = pci_new(-1, TYPE_NEWWORLD_MACIO);
dev = DEVICE(macio);
qdev_prop_set_uint64(dev, "frequency", tbfreq);
qdev_prop_set_bit(dev, "has-pmu", has_pmu);
qdev_prop_set_bit(dev, "has-adb", has_adb);
object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_init_nofail(dev);
+ pci_realize_and_unref(macio, pci_bus, &error_fatal);
/* We only emulate 2 out of 3 IDE controllers for now */
ide_drive_get(hd, ARRAY_SIZE(hd));
}
adb_bus = qdev_get_child_bus(dev, "adb.0");
- dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
+ dev = qdev_new(TYPE_ADB_KEYBOARD);
qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, adb_bus, &error_fatal);
- dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
+ dev = qdev_new(TYPE_ADB_MOUSE);
qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, adb_bus, &error_fatal);
}
if (machine->usb) {
move the NVRAM out of ROM again for KVM */
nvram_addr = 0xFFE00000;
}
- dev = qdev_create(NULL, TYPE_MACIO_NVRAM);
+ dev = qdev_new(TYPE_MACIO_NVRAM);
qdev_prop_set_uint32(dev, "size", 0x2000);
qdev_prop_set_uint32(dev, "it_shift", 1);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
nvr = MACIO_NVRAM(dev);
pmac_format_nvram_partition(nvr, 0x2000);
/* No PCI init: the BIOS will do it */
- dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
+ dev = qdev_new(TYPE_FW_CFG_MEM);
fw_cfg = FW_CFG(dev);
qdev_prop_set_uint32(dev, "data_width", 1);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg));
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
uint32_t kernel_base, initrd_base, cmdline_base = 0;
int32_t kernel_size, initrd_size;
PCIBus *pci_bus;
- OldWorldMacIOState *macio;
+ PCIDevice *macio;
MACIOIDEState *macio_ide;
SysBusDevice *s;
DeviceState *dev, *pic_dev;
}
/* XXX: we register only 1 output pin for heathrow PIC */
- pic_dev = qdev_create(NULL, TYPE_HEATHROW);
- qdev_init_nofail(pic_dev);
+ pic_dev = qdev_new(TYPE_HEATHROW);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(pic_dev), &error_fatal);
/* Connect the heathrow PIC outputs to the 6xx bus */
for (i = 0; i < smp_cpus; i++) {
}
/* Grackle PCI host bridge */
- dev = qdev_create(NULL, TYPE_GRACKLE_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, GRACKLE_BASE);
sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
/* PCI hole */
ide_drive_get(hd, ARRAY_SIZE(hd));
/* MacIO */
- macio = OLDWORLD_MACIO(pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO));
+ macio = pci_new(-1, TYPE_OLDWORLD_MACIO);
dev = DEVICE(macio);
qdev_prop_set_uint64(dev, "frequency", tbfreq);
object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_init_nofail(dev);
+ pci_realize_and_unref(macio, pci_bus, &error_fatal);
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide[0]"));
dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
adb_bus = qdev_get_child_bus(dev, "adb.0");
- dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
- qdev_init_nofail(dev);
- dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_ADB_KEYBOARD);
+ qdev_realize_and_unref(dev, adb_bus, &error_fatal);
+ dev = qdev_new(TYPE_ADB_MOUSE);
+ qdev_realize_and_unref(dev, adb_bus, &error_fatal);
if (machine_usb(machine)) {
pci_create_simple(pci_bus, -1, "pci-ohci");
/* No PCI init: the BIOS will do it */
- dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
+ dev = qdev_new(TYPE_FW_CFG_MEM);
fw_cfg = FW_CFG(dev);
qdev_prop_set_uint32(dev, "data_width", 1);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg));
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
{
- Object *obj;
+ ISADevice *dev = isa_new("isa-ipmi-bt");
- obj = OBJECT(isa_create(bus, "isa-ipmi-bt"));
- object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal);
- object_property_set_int(obj, irq, "irq", &error_fatal);
- object_property_set_bool(obj, true, "realized", &error_fatal);
+ object_property_set_link(OBJECT(dev), OBJECT(bmc), "bmc", &error_fatal);
+ object_property_set_int(OBJECT(dev), irq, "irq", &error_fatal);
+ isa_realize_and_unref(dev, bus, &error_fatal);
}
static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
/*
* Create our simple PNOR device
*/
- dev = qdev_create(NULL, TYPE_PNV_PNOR);
+ dev = qdev_new(TYPE_PNV_PNOR);
if (pnor) {
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor),
&error_abort);
}
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
pnv->pnor = PNV_PNOR(dev);
/* load skiboot firmware */
pnv->chips = g_new0(PnvChip *, pnv->num_chips);
for (i = 0; i < pnv->num_chips; i++) {
char chip_name[32];
- Object *chip = object_new(chip_typename);
+ Object *chip = OBJECT(qdev_new(chip_typename));
pnv->chips[i] = PNV_CHIP(chip);
object_property_set_link(chip, OBJECT(pnv), "xive-fabric",
&error_abort);
}
- object_property_set_bool(chip, true, "realized", &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
}
g_free(chip_typename);
object_property_allow_set_link,
OBJ_PROP_LINK_STRONG);
- object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
- TYPE_PNV8_PSI, &error_abort, NULL);
+ object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
- object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
- TYPE_PNV8_LPC, &error_abort, NULL);
+ object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
- object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
- TYPE_PNV8_OCC, &error_abort, NULL);
+ object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
- object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
- TYPE_PNV8_HOMER, &error_abort, NULL);
+ object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
for (i = 0; i < pcc->num_phbs; i++) {
- object_initialize_child(obj, "phb[*]", &chip8->phbs[i],
- sizeof(chip8->phbs[i]), TYPE_PNV_PHB3,
- &error_abort, NULL);
+ object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3);
}
/*
"bar", &error_fatal);
object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics),
ICS_PROP_XICS, &error_abort);
- object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
+ qdev_realize(DEVICE(&chip8->psi), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
/* Create LPC controller */
object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi",
&error_abort);
- object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
- &error_fatal);
+ qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
/* Create the simplified OCC model */
object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi",
&error_abort);
- object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
+ qdev_realize(DEVICE(&chip8->occ), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
/* HOMER */
object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip",
&error_abort);
- object_property_set_bool(OBJECT(&chip8->homer), true, "realized",
- &local_err);
+ qdev_realize(DEVICE(&chip8->homer), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
object_property_set_int(OBJECT(phb), i, "index", &error_fatal);
object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id",
&error_fatal);
- object_property_set_bool(OBJECT(phb), true, "realized", &local_err);
+ sysbus_realize(SYS_BUS_DEVICE(phb), &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
- qdev_set_parent_bus(DEVICE(phb), sysbus_get_default());
/* Populate the XSCOM address space. */
pnv_xscom_add_subregion(chip,
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
int i;
- object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
- TYPE_PNV_XIVE, &error_abort, NULL);
+ object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
"xive-fabric");
- object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
- TYPE_PNV9_PSI, &error_abort, NULL);
+ object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
- object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc),
- TYPE_PNV9_LPC, &error_abort, NULL);
+ object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
- object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ),
- TYPE_PNV9_OCC, &error_abort, NULL);
+ object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
- object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer),
- TYPE_PNV9_HOMER, &error_abort, NULL);
+ object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
- sizeof(chip9->pecs[i]), TYPE_PNV_PHB4_PEC,
- &error_abort, NULL);
+ TYPE_PNV_PHB4_PEC);
}
/*
int core_id = CPU_CORE(pnv_core)->core_id;
snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
- object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq),
- TYPE_PNV_QUAD, &error_fatal, NULL);
+ object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
+ sizeof(*eq), TYPE_PNV_QUAD,
+ &error_fatal, NULL);
object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
- object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
+ qdev_realize(DEVICE(eq), NULL, &error_fatal);
pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
&eq->xscom_regs);
&error_fatal);
object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()),
"system-memory", &error_abort);
- object_property_set_bool(OBJECT(pec), true, "realized", &local_err);
+ qdev_realize(DEVICE(pec), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id",
&error_fatal);
object_property_set_link(obj, OBJECT(stack), "stack", &error_abort);
- object_property_set_bool(obj, true, "realized", &local_err);
+ sysbus_realize(SYS_BUS_DEVICE(obj), &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
- qdev_set_parent_bus(DEVICE(obj), sysbus_get_default());
/* Populate the XSCOM address space. */
pnv_xscom_add_subregion(chip,
"tm-bar", &error_fatal);
object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip",
&error_abort);
- object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
- &local_err);
+ sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
/* Processor Service Interface (PSI) Host Bridge */
object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
"bar", &error_fatal);
- object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
+ qdev_realize(DEVICE(&chip9->psi), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
/* LPC */
object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi",
&error_abort);
- object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err);
+ qdev_realize(DEVICE(&chip9->lpc), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
/* Create the simplified OCC model */
object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi",
&error_abort);
- object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err);
+ qdev_realize(DEVICE(&chip9->occ), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
/* HOMER */
object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip",
&error_abort);
- object_property_set_bool(OBJECT(&chip9->homer), true, "realized",
- &local_err);
+ qdev_realize(DEVICE(&chip9->homer), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
{
Pnv10Chip *chip10 = PNV10_CHIP(obj);
- object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi),
- TYPE_PNV10_PSI, &error_abort, NULL);
- object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc),
- TYPE_PNV10_LPC, &error_abort, NULL);
+ object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
+ object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
}
static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
/* Processor Service Interface (PSI) Host Bridge */
object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip),
"bar", &error_fatal);
- object_property_set_bool(OBJECT(&chip10->psi), true, "realized",
- &local_err);
+ qdev_realize(DEVICE(&chip10->psi), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
/* LPC */
object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi",
&error_abort);
- object_property_set_bool(OBJECT(&chip10->lpc), true, "realized",
- &local_err);
+ qdev_realize(DEVICE(&chip10->lpc), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
"hrmor", &error_fatal);
object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip",
&error_abort);
- object_property_set_bool(OBJECT(pnv_core), true, "realized",
- &error_fatal);
+ qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
/* Each core has an XSCOM MMIO region */
xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
obj = object_new(TYPE_IPMI_BMC_SIMULATOR);
object_ref(OBJECT(pnor));
object_property_add_const_link(obj, "pnor", OBJECT(pnor));
- object_property_set_bool(obj, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(obj), NULL, &error_fatal);
/* Install the HIOMAP protocol handlers to access the PNOR */
ipmi_sim_register_netfn(IPMI_BMC_SIMULATOR(obj), IPMI_NETFN_OEM,
Error *local_err = NULL;
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
- object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
+ qdev_realize(DEVICE(cpu), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
{
Pnv8Psi *psi8 = PNV8_PSI(obj);
- object_initialize_child(obj, "ics-psi", &psi8->ics, sizeof(psi8->ics),
- TYPE_ICS, &error_abort, NULL);
+ object_initialize_child(obj, "ics-psi", &psi8->ics, TYPE_ICS);
object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics),
ICS_PROP_XICS);
}
error_propagate(errp, err);
return;
}
- object_property_set_bool(OBJECT(ics), true, "realized", &err);
+ qdev_realize(DEVICE(ics), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
{
Pnv9Psi *psi = PNV9_PSI(obj);
- object_initialize_child(obj, "source", &psi->source, sizeof(psi->source),
- TYPE_XIVE_SOURCE, &error_abort, NULL);
+ object_initialize_child(obj, "source", &psi->source, TYPE_XIVE_SOURCE);
}
static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(xsrc), PSIHB9_NUM_IRQS, "nr-irqs",
&error_fatal);
object_property_set_link(OBJECT(xsrc), OBJECT(psi), "xive", &error_abort);
- object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
+ qdev_realize(DEVICE(xsrc), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
static const TypeInfo pnv_psi_info = {
.name = TYPE_PNV_PSI,
- .parent = TYPE_SYS_BUS_DEVICE,
+ .parent = TYPE_DEVICE,
.instance_size = sizeof(PnvPsi),
.class_init = pnv_psi_class_init,
.class_size = sizeof(PnvPsiClass),
{
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST);
+ dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE);
- qdev_init_nofail(dev);
- object_property_set_bool(OBJECT(dev), true, "realized", NULL);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
- dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST);
+ dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE);
- qdev_init_nofail(dev);
- object_property_set_bool(OBJECT(dev), true, "realized", NULL);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
}
#include "hw/pci/pci_host.h"
#include "hw/ppc/ppc.h"
#include "hw/boards.h"
+#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "hw/irq.h"
SysBusDevice *pcihost, *s;
Nvram *m48t59 = NULL;
PCIBus *pci_bus;
+ ISADevice *isa_dev;
ISABus *isa_bus;
void *fw_cfg;
int i;
qemu_register_reset(ppc_prep_reset, cpu);
/* PCI host */
- dev = qdev_create(NULL, "raven-pcihost");
+ dev = qdev_new("raven-pcihost");
if (!bios_name) {
bios_name = "openbios-ppc";
}
qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
pcihost = SYS_BUS_DEVICE(dev);
object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(pcihost, &error_fatal);
pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
if (!pci_bus) {
error_report("could not create PCI host controller");
isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
/* Memory controller */
- dev = DEVICE(isa_create(isa_bus, "rs6000-mc"));
+ isa_dev = isa_new("rs6000-mc");
+ dev = DEVICE(isa_dev);
qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
/* RTC */
- dev = DEVICE(isa_create(isa_bus, TYPE_MC146818_RTC));
+ isa_dev = isa_new(TYPE_MC146818_RTC);
+ dev = DEVICE(isa_dev);
qdev_prop_set_int32(dev, "base_year", 1900);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
/* initialize CMOS checksums */
cmos_checksum = 0x6aa9;
if (defaults_enabled()) {
m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
- dev = DEVICE(isa_create(isa_bus, "cs4231a"));
+ isa_dev = isa_new("cs4231a");
+ dev = DEVICE(isa_dev);
qdev_prop_set_uint32(dev, "iobase", 0x830);
qdev_prop_set_uint32(dev, "irq", 10);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
- dev = DEVICE(isa_create(isa_bus, "pc87312"));
+ isa_dev = isa_new("pc87312");
+ dev = DEVICE(isa_dev);
qdev_prop_set_uint32(dev, "config", 12);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
- dev = DEVICE(isa_create(isa_bus, "prep-systemio"));
+ isa_dev = isa_new("prep-systemio");
+ dev = DEVICE(isa_dev);
qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
qdev_prop_set_uint32(dev, "equipment", 0xc0);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
"lsi53c810"));
}
/* Prepare firmware configuration for OpenBIOS */
- dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
+ dev = qdev_new(TYPE_FW_CFG_MEM);
fw_cfg = FW_CFG(dev);
qdev_prop_set_uint32(dev, "data_width", 1);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg));
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
/* USB */
sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]);
- dev = qdev_create(NULL, "sysbus-ohci");
+ dev = qdev_new("sysbus-ohci");
qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
qdev_prop_set_uint32(dev, "num-ports", 6);
- qdev_init_nofail(dev);
sbdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbdev, &error_fatal);
sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
sysbus_connect_irq(sbdev, 0, uic[2][30]);
usb_create_simple(usb_bus_find(-1), "usb-kbd");
static void spapr_create_nvram(SpaprMachineState *spapr)
{
- DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
+ DeviceState *dev = qdev_new("spapr-nvram");
DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
if (dinfo) {
&error_fatal);
}
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal);
spapr->nvram = (struct SpaprNvram *)dev;
}
static void spapr_rtc_create(SpaprMachineState *spapr)
{
- object_initialize_child(OBJECT(spapr), "rtc",
- &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC,
- &error_fatal, NULL);
- object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
- &error_fatal);
+ object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc,
+ sizeof(spapr->rtc), TYPE_SPAPR_RTC,
+ &error_fatal, NULL);
+ qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal);
object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
"date");
}
&error_fatal);
object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
&error_fatal);
- object_property_set_bool(core, true, "realized", &error_fatal);
+ qdev_realize(DEVICE(core), NULL, &error_fatal);
object_unref(core);
}
{
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "index", 0);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
return PCI_HOST_BRIDGE(dev);
}
SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev));
- object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+ qdev_unrealize(dev);
spapr_pending_dimm_unplugs_remove(spapr, ds);
}
assert(core_slot);
core_slot->cpu = NULL;
- object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+ qdev_unrealize(dev);
}
static
static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
{
- object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+ qdev_unrealize(dev);
}
static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev,
{
SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
- object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+ qdev_unrealize(dev);
object_unparent(OBJECT(dev));
spapr->tpm_proxy = NULL;
}
CPUState *cs = CPU(cpu);
Error *local_err = NULL;
- object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
+ qdev_realize(DEVICE(cpu), NULL, &local_err);
if (local_err) {
goto error;
}
spapr_drc_index(drc));
object_property_add_child(owner, prop_name, OBJECT(drc));
object_unref(OBJECT(drc));
- object_property_set_bool(OBJECT(drc), true, "realized", NULL);
+ qdev_realize(DEVICE(drc), NULL, NULL);
g_free(prop_name);
return drc;
g_free(tmp);
object_unref(OBJECT(tcet));
- object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
+ qdev_realize(DEVICE(tcet), NULL, NULL);
return tcet;
}
object_property_set_link(obj, OBJECT(spapr), ICS_PROP_XICS,
&error_abort);
object_property_set_int(obj, smc->nr_xirqs, "nr-irqs", &error_abort);
- object_property_set_bool(obj, true, "realized", &local_err);
+ qdev_realize(DEVICE(obj), NULL, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
DeviceState *dev;
int i;
- dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
+ dev = qdev_new(TYPE_SPAPR_XIVE);
qdev_prop_set_uint32(dev, "nr-irqs", smc->nr_xirqs + SPAPR_XIRQ_BASE);
/*
* 8 XIVE END structures per CPU. One for each available
qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
object_property_set_link(OBJECT(dev), OBJECT(spapr), "xive-fabric",
&error_abort);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
spapr->xive = SPAPR_XIVE(dev);
return;
}
- object_property_set_bool(OBJECT(plugged_dev), false, "realized",
- &error_abort);
+ qdev_unrealize(plugged_dev);
}
static void spapr_pci_unplug_request(HotplugHandler *plug_handler,
DeviceState *dev;
/* Create bridge device */
- dev = qdev_create(NULL, TYPE_SPAPR_VIO_BRIDGE);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_SPAPR_VIO_BRIDGE);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Create bus on bridge device */
qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");
#include "sysemu/device_tree.h"
#include "hw/loader.h"
#include "elf.h"
+#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "qemu/option.h"
64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
- dev = qdev_create(NULL, "xlnx.xps-intc");
+ dev = qdev_new("xlnx.xps-intc");
qdev_prop_set_uint32(dev, "kind-of-intr", 0);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
for (i = 0; i < 32; i++) {
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
/* 2 timers at irq 2 @ 62 Mhz. */
- dev = qdev_create(NULL, "xlnx.xps-timer");
+ dev = qdev_new("xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
/* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc,
- sizeof(s->soc), TYPE_RISCV_IBEX_SOC,
- &error_abort, NULL);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
+ TYPE_RISCV_IBEX_SOC);
+ qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
memmap[IBEX_RAM].size, &error_fatal);
{
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
- object_initialize_child(obj, "cpus", &s->cpus,
- sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
- &error_abort, NULL);
+ object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
}
static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
&error_abort);
object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort);
- object_property_set_bool(OBJECT(&s->cpus), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
/* Boot ROM */
memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
{
Error *err = NULL;
- object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
- sizeof(RISCVCPU), cpu_type,
- &error_abort, NULL);
+ object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
s->harts[idx].env.mhartid = s->hartid_base + idx;
qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
- object_property_set_bool(OBJECT(&s->harts[idx]), true,
- "realized", &err);
+ qdev_realize(DEVICE(&s->harts[idx]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "hw/sysbus.h"
env->timecmp = 0;
}
- DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_CLINT);
+ DeviceState *dev = qdev_new(TYPE_SIFIVE_CLINT);
qdev_prop_set_uint32(dev, "num-harts", num_harts);
qdev_prop_set_uint32(dev, "sip-base", sip_base);
qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
qdev_prop_set_uint32(dev, "time-base", time_base);
qdev_prop_set_uint32(dev, "aperture-size", size);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
}
int i;
/* Initialize SoC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc,
- sizeof(s->soc), TYPE_RISCV_E_SOC,
- &error_abort, NULL);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
+ qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
/* Data Tightly Integrated Memory */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
MachineState *ms = MACHINE(qdev_get_machine());
SiFiveESoCState *s = RISCV_E_SOC(obj);
- object_initialize_child(obj, "cpus", &s->cpus,
- sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
- &error_abort, NULL);
+ object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort);
- sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0",
- &s->gpio, sizeof(s->gpio),
- TYPE_SIFIVE_GPIO);
+ object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
+ TYPE_SIFIVE_GPIO);
}
static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
&error_abort);
- object_property_set_bool(OBJECT(&s->cpus), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
/* Mask ROM */
memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
/* GPIO */
- object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
if (err) {
error_propagate(errp, err);
return;
#include "qemu/osdep.h"
#include "hw/sysbus.h"
+#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/hw.h"
*/
DeviceState *sifive_e_prci_create(hwaddr addr)
{
- DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_E_PRCI);
- qdev_init_nofail(dev);
+ DeviceState *dev = qdev_new(TYPE_SIFIVE_E_PRCI);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
}
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/error-report.h"
uint32_t context_base, uint32_t context_stride,
uint32_t aperture_size)
{
- DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PLIC);
+ DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
assert(enable_stride == (enable_stride & -enable_stride));
assert(context_stride == (context_stride & -context_stride));
qdev_prop_set_string(dev, "hart-config", hart_config);
qdev_prop_set_uint32(dev, "context-base", context_base);
qdev_prop_set_uint32(dev, "context-stride", context_stride);
qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
}
#include "qemu/osdep.h"
#include "hw/sysbus.h"
+#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "sysemu/runstate.h"
*/
DeviceState *sifive_test_create(hwaddr addr)
{
- DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_TEST);
- qdev_init_nofail(dev);
+ DeviceState *dev = qdev_new(TYPE_SIFIVE_TEST);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
}
int i;
/* Initialize SoC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc,
- sizeof(s->soc), TYPE_RISCV_U_SOC,
- &error_abort, NULL);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
object_property_set_uint(OBJECT(&s->soc), s->serial, "serial",
&error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
+ qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
/* register RAM */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
MachineState *ms = MACHINE(qdev_get_machine());
SiFiveUSoCState *s = RISCV_U_SOC(obj);
- object_initialize_child(obj, "e-cluster", &s->e_cluster,
- sizeof(s->e_cluster), TYPE_CPU_CLUSTER,
- &error_abort, NULL);
+ object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
- object_initialize_child(OBJECT(&s->e_cluster), "e-cpus",
- &s->e_cpus, sizeof(s->e_cpus),
- TYPE_RISCV_HART_ARRAY, &error_abort,
- NULL);
+ object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
+ TYPE_RISCV_HART_ARRAY);
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
- object_initialize_child(obj, "u-cluster", &s->u_cluster,
- sizeof(s->u_cluster), TYPE_CPU_CLUSTER,
- &error_abort, NULL);
+ object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
- object_initialize_child(OBJECT(&s->u_cluster), "u-cpus",
- &s->u_cpus, sizeof(s->u_cpus),
- TYPE_RISCV_HART_ARRAY, &error_abort,
- NULL);
+ object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
+ TYPE_RISCV_HART_ARRAY);
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
- sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
- TYPE_SIFIVE_U_PRCI);
- sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
- TYPE_SIFIVE_U_OTP);
- sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
- TYPE_CADENCE_GEM);
+ object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
+ object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
+ object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
}
static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
Error *err = NULL;
NICInfo *nd = &nd_table[0];
- object_property_set_bool(OBJECT(&s->e_cpus), true, "realized",
- &error_abort);
- object_property_set_bool(OBJECT(&s->u_cpus), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
/*
* The cluster must be realized after the RISC-V hart array container,
* as the container's CPU object is only created on realize, and the
* CPU must exist and have been parented into the cluster before the
* cluster is realized.
*/
- object_property_set_bool(OBJECT(&s->e_cluster), true, "realized",
- &error_abort);
- object_property_set_bool(OBJECT(&s->u_cluster), true, "realized",
- &error_abort);
+ qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
+ qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
/* boot rom */
memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
- object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->prci), &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
- object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->otp), &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
}
object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
&error_abort);
- object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gem), &err);
if (err) {
error_propagate(errp, err);
return;
unsigned int smp_cpus = machine->smp.cpus;
/* Initialize SOC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
+ TYPE_RISCV_HART_ARRAY);
object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
&error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
/* register system main memory (actual RAM) */
memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
* Create a single flash device. We use the same parameters as
* the flash devices on the ARM virt board.
*/
- DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
+ DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
qdev_prop_set_uint8(dev, "width", 4);
assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(sysmem, base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
qemu_irq irq;
int i;
- dev = qdev_create(NULL, TYPE_GPEX_HOST);
+ dev = qdev_new(TYPE_GPEX_HOST);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ecam_alias = g_new0(MemoryRegion, 1);
ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
unsigned int smp_cpus = machine->smp.cpus;
/* Initialize SOC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
+ TYPE_RISCV_HART_ARRAY);
object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
&error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
/* register system main memory (actual RAM) */
memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
#include "hw/qdev-properties.h"
#include "hw/rtc/m48t59.h"
#include "m48t59-internal.h"
+#include "qapi/error.h"
#include "qemu/module.h"
#define TYPE_M48TXX_ISA "isa-m48txx"
Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
int base_year, int model)
{
+ ISADevice *isa_dev;
DeviceState *dev;
int i;
continue;
}
- dev = DEVICE(isa_create(bus, m48txx_isa_info[i].bus_name));
+ isa_dev = isa_new(m48txx_isa_info[i].bus_name);
+ dev = DEVICE(isa_dev);
qdev_prop_set_uint32(dev, "iobase", io_base);
qdev_prop_set_int32(dev, "base-year", base_year);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isa_dev, bus, &error_fatal);
return NVRAM(dev);
}
#include "sysemu/sysemu.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
+#include "qapi/error.h"
#include "qemu/bcd.h"
#include "qemu/module.h"
#include "trace.h"
continue;
}
- dev = qdev_create(NULL, m48txx_sysbus_info[i].bus_name);
+ dev = qdev_new(m48txx_sysbus_info[i].bus_name);
qdev_prop_set_int32(dev, "base-year", base_year);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, IRQ);
if (io_base != 0) {
memory_region_add_subregion(get_system_io(), io_base,
DeviceState *dev;
ISADevice *isadev;
- isadev = isa_create(bus, TYPE_MC146818_RTC);
+ isadev = isa_new(TYPE_MC146818_RTC);
dev = DEVICE(isadev);
qdev_prop_set_int32(dev, "base_year", base_year);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isadev, bus, &error_fatal);
if (intercept_irq) {
qdev_connect_gpio_out(dev, 0, intercept_irq);
} else {
#include "qemu/osdep.h"
#include "hw/sysbus.h"
+#include "qapi/error.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "hw/rtc/sun4v-rtc.h"
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, TYPE_SUN4V_RTC);
+ dev = qdev_new(TYPE_SUN4V_RTC);
s = SYS_BUS_DEVICE(dev);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
}
}
/* Create bridge device */
- dev = qdev_create(NULL, TYPE_AP_BRIDGE);
+ dev = qdev_new(TYPE_AP_BRIDGE);
object_property_add_child(qdev_get_machine(), TYPE_AP_BRIDGE,
OBJECT(dev));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Create bus on bridge device */
bus = qbus_create(TYPE_AP_BUS, dev, TYPE_AP_BUS);
css_generate_sch_crws(sch->cssid, sch->ssid, sch->schid, 1, 0);
- object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+ qdev_unrealize(dev);
}
static void virtual_css_bus_reset(BusState *qbus)
DeviceState *dev;
/* Create bridge device */
- dev = qdev_create(NULL, TYPE_VIRTUAL_CSS_BRIDGE);
+ dev = qdev_new(TYPE_VIRTUAL_CSS_BRIDGE);
object_property_add_child(qdev_get_machine(), TYPE_VIRTUAL_CSS_BRIDGE,
OBJECT(dev));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Create bus on bridge device */
bus = qbus_create(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");
struct SCLPEventFacility {
SysBusDevice parent_obj;
SCLPEventsBus sbus;
+ SCLPEvent quiesce, cpu_hotplug;
/* guest's receive mask */
union {
uint32_t receive_mask_pieces[2];
#define TYPE_SCLP_EVENTS_BUS "s390-sclp-events-bus"
-static void sclp_events_bus_realize(BusState *bus, Error **errp)
-{
- Error *err = NULL;
- BusChild *kid;
-
- /* TODO: recursive realization has to be done in common code */
- QTAILQ_FOREACH(kid, &bus->children, sibling) {
- DeviceState *dev = kid->child;
-
- object_property_set_bool(OBJECT(dev), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
- return;
- }
- }
-}
-
-static void sclp_events_bus_class_init(ObjectClass *klass, void *data)
-{
- BusClass *bc = BUS_CLASS(klass);
-
- bc->realize = sclp_events_bus_realize;
-}
-
static const TypeInfo sclp_events_bus_info = {
.name = TYPE_SCLP_EVENTS_BUS,
.parent = TYPE_BUS,
- .class_init = sclp_events_bus_class_init,
};
static void command_handler(SCLPEventFacility *ef, SCCB *sccb, uint64_t code)
{
SCLPEventFacility *event_facility = EVENT_FACILITY(obj);
DeviceState *sdev = DEVICE(obj);
- Object *new;
event_facility->mask_length = 4;
event_facility->allow_all_mask_sizes = true;
object_property_add_bool(obj, "allow_all_mask_sizes",
sclp_event_get_allow_all_mask_sizes,
sclp_event_set_allow_all_mask_sizes);
+
/* Spawn a new bus for SCLP events */
qbus_create_inplace(&event_facility->sbus, sizeof(event_facility->sbus),
TYPE_SCLP_EVENTS_BUS, sdev, NULL);
- new = object_new(TYPE_SCLP_QUIESCE);
- object_property_add_child(obj, TYPE_SCLP_QUIESCE, new);
- object_unref(new);
- qdev_set_parent_bus(DEVICE(new), BUS(&event_facility->sbus));
+ object_initialize_child(obj, TYPE_SCLP_QUIESCE,
+ &event_facility->quiesce,
+ TYPE_SCLP_QUIESCE);
- new = object_new(TYPE_SCLP_CPU_HOTPLUG);
- object_property_add_child(obj, TYPE_SCLP_CPU_HOTPLUG, new);
- object_unref(new);
- qdev_set_parent_bus(DEVICE(new), BUS(&event_facility->sbus));
- /* the facility will automatically realize the devices via the bus */
+ object_initialize_child(obj, TYPE_SCLP_CPU_HOTPLUG,
+ &event_facility->cpu_hotplug,
+ TYPE_SCLP_CPU_HOTPLUG);
+}
+
+static void realize_event_facility(DeviceState *dev, Error **errp)
+{
+ SCLPEventFacility *event_facility = EVENT_FACILITY(dev);
+ Error *local_err = NULL;
+
+ qdev_realize(DEVICE(&event_facility->quiesce),
+ BUS(&event_facility->sbus), &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+ qdev_realize(DEVICE(&event_facility->cpu_hotplug),
+ BUS(&event_facility->sbus), &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ qdev_unrealize(DEVICE(&event_facility->quiesce));
+ return;
+ }
}
static void reset_event_facility(DeviceState *dev)
DeviceClass *dc = DEVICE_CLASS(sbdc);
SCLPEventFacilityClass *k = EVENT_FACILITY_CLASS(dc);
+ dc->realize = realize_event_facility;
dc->reset = reset_event_facility;
dc->vmsd = &vmstate_event_facility;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
Error *local_err = NULL;
DeviceState *dev;
- dev = qdev_try_create(BUS(s->bus), TYPE_S390_PCI_DEVICE);
+ dev = qdev_try_new(TYPE_S390_PCI_DEVICE);
if (!dev) {
error_setg(errp, "zPCI device could not be created");
return NULL;
"zPCI device could not be created: ");
return NULL;
}
- object_property_set_bool(OBJECT(dev), true, "realized", &local_err);
+ qdev_realize_and_unref(dev, BUS(s->bus), &local_err);
if (local_err) {
object_unparent(OBJECT(dev));
error_propagate_prepend(errp, local_err,
pbdev->fh, pbdev->fid);
bus = pci_get_bus(pci_dev);
devfn = pci_dev->devfn;
- object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+ qdev_unrealize(dev);
s390_pci_msix_free(pbdev);
s390_pci_iommu_free(s, bus, devfn);
pbdev->fid = 0;
QTAILQ_REMOVE(&s->zpci_devs, pbdev, link);
g_hash_table_remove(s->zpci_table, &pbdev->idx);
- object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
+ qdev_unrealize(dev);
}
}
obj);
object_unref(obj);
- qdev_init_nofail(DEVICE(obj));
+ qdev_realize(DEVICE(obj), NULL, &error_fatal);
}
static void write_keys(FILE *f, uint8_t *keys, uint64_t startgfn,
obj);
object_unref(obj);
- qdev_init_nofail(DEVICE(obj));
+ qdev_realize(DEVICE(obj), NULL, &error_fatal);
}
/* Console commands: */
if (err != NULL) {
goto out;
}
- object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+ qdev_realize(DEVICE(cpu), NULL, &err);
out:
object_unref(OBJECT(cpu));
object_property_add_child(qdev_get_machine(), TYPE_S390_IPL,
new);
object_unref(new);
- qdev_init_nofail(dev);
+ qdev_realize(dev, NULL, &error_fatal);
}
static void s390_create_virtio_net(BusState *bus, const char *name)
qemu_check_nic_model(nd, "virtio");
- dev = qdev_create(bus, name);
+ dev = qdev_new(name);
qdev_set_nic_properties(dev, nd);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
}
}
{
DeviceState *dev;
- dev = qdev_create(sclp_get_event_facility_bus(), type);
+ dev = qdev_new(type);
qdev_prop_set_chr(dev, "chardev", chardev);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, sclp_get_event_facility_bus(), &error_fatal);
}
static void ccw_init(MachineState *machine)
machine->initrd_filename, "s390-ccw.img",
"s390-netboot.img", true);
- dev = qdev_create(NULL, TYPE_S390_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_S390_PCI_HOST_BRIDGE);
object_property_add_child(qdev_get_machine(), TYPE_S390_PCI_HOST_BRIDGE,
OBJECT(dev));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* register hypercalls */
virtio_ccw_register_hcalls();
object_property_add_child(qdev_get_machine(), TYPE_SCLP, new);
object_unref(new);
- qdev_init_nofail(DEVICE(new));
+ qdev_realize(DEVICE(new), NULL, &error_fatal);
}
static void sclp_realize(DeviceState *dev, Error **errp)
uint64_t hw_limit;
int ret;
- object_property_set_bool(OBJECT(sclp->event_facility), true, "realized",
- &err);
- if (err) {
- goto out;
- }
/*
* qdev_device_add searches the sysbus for TYPE_SCLP_EVENTS_BUS. As long
* as we can't find a fitting bus via the qom tree, we have to add the
* event facility to the sysbus, so e.g. a sclp console can be created.
*/
- qdev_set_parent_bus(DEVICE(sclp->event_facility), sysbus_get_default());
+ sysbus_realize(SYS_BUS_DEVICE(sclp->event_facility), &err);
+ if (err) {
+ goto out;
+ }
ret = s390_set_memory_limit(machine->maxram_size, &hw_limit);
if (ret == -E2BIG) {
object_property_add_child(qdev_get_machine(), TYPE_S390_TOD, obj);
object_unref(obj);
- qdev_init_nofail(DEVICE(obj));
+ qdev_realize(DEVICE(obj), NULL, &error_fatal);
}
S390TODState *s390_get_todstate(void)
VHostVSockCCWState *dev = VHOST_VSOCK_CCW(ccw_dev);
DeviceState *vdev = DEVICE(&dev->vdev);
- qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&ccw_dev->bus), errp);
}
static void vhost_vsock_ccw_class_init(ObjectClass *klass, void *data)
V9fsCCWState *dev = VIRTIO_9P_CCW(ccw_dev);
DeviceState *vdev = DEVICE(&dev->vdev);
- qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&ccw_dev->bus), errp);
}
static void virtio_ccw_9p_instance_init(Object *obj)
VirtIOBalloonCcw *dev = VIRTIO_BALLOON_CCW(ccw_dev);
DeviceState *vdev = DEVICE(&dev->vdev);
- qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&ccw_dev->bus), errp);
}
static void virtio_ccw_balloon_instance_init(Object *obj)
VirtIOBlkCcw *dev = VIRTIO_BLK_CCW(ccw_dev);
DeviceState *vdev = DEVICE(&dev->vdev);
- qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&ccw_dev->bus), errp);
}
static void virtio_ccw_blk_instance_init(Object *obj)
DeviceState *vdev = DEVICE(&dev->vdev);
Error *err = NULL;
- qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", &err);
+ qdev_realize(vdev, BUS(&ccw_dev->bus), &err);
if (err) {
error_propagate(errp, err);
return;
VirtIOGPUCcw *dev = VIRTIO_GPU_CCW(ccw_dev);
DeviceState *vdev = DEVICE(&dev->vdev);
- qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&ccw_dev->bus), errp);
}
static void virtio_ccw_gpu_instance_init(Object *obj)
VirtIOInputCcw *dev = VIRTIO_INPUT_CCW(ccw_dev);
DeviceState *vdev = DEVICE(&dev->vdev);
- qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&ccw_dev->bus), errp);
}
static Property virtio_ccw_input_properties[] = {
virtio_net_set_netclient_name(&dev->vdev, qdev->id,
object_get_typename(OBJECT(qdev)));
- qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&ccw_dev->bus), errp);
}
static void virtio_ccw_net_instance_init(Object *obj)
DeviceState *vdev = DEVICE(&dev->vdev);
Error *err = NULL;
- qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", &err);
+ qdev_realize(vdev, BUS(&ccw_dev->bus), &err);
if (err) {
error_propagate(errp, err);
return;
g_free(bus_name);
}
- qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&ccw_dev->bus), errp);
}
static void virtio_ccw_scsi_instance_init(Object *obj)
VHostSCSICcw *dev = VHOST_SCSI_CCW(ccw_dev);
DeviceState *vdev = DEVICE(&dev->vdev);
- qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&ccw_dev->bus), errp);
}
static void vhost_ccw_scsi_instance_init(Object *obj)
g_free(bus_name);
}
- qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&ccw_dev->bus), errp);
}
driver = "scsi-hd";
}
}
- dev = qdev_create(&bus->qbus, driver);
+ dev = qdev_new(driver);
name = g_strdup_printf("legacy[%d]", unit);
object_property_add_child(OBJECT(bus), name, OBJECT(dev));
g_free(name);
qdev_prop_set_enum(dev, "rerror", rerror);
qdev_prop_set_enum(dev, "werror", werror);
- object_property_set_bool(OBJECT(dev), true, "realized", &err);
+ qdev_realize_and_unref(dev, &bus->qbus, &err);
if (err != NULL) {
error_propagate(errp, err);
object_unparent(OBJECT(dev));
{
DeviceState *dev;
- dev = qdev_create(&bus->bus, "spapr-vscsi");
+ dev = qdev_new("spapr-vscsi");
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, &bus->bus, &error_fatal);
scsi_bus_legacy_handle_cmdline(&VIO_SPAPR_VSCSI_DEVICE(dev)->bus);
}
return;
}
- object_property_set_bool(sdhci_slot, true, "realized", &err);
+ sysbus_realize(sbd_slot, &err);
if (err) {
error_propagate(errp, err);
return;
/* FIXME use a qdev drive property instead of drive_get_next() */
dinfo = drive_get_next(IF_SD);
blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
- carddev = qdev_create(BUS(&s->sdbus), TYPE_SD_CARD);
+ carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &err);
- object_property_set_bool(OBJECT(carddev), true, "realized", &err);
+ qdev_realize_and_unref(carddev, BUS(&s->sdbus), &err);
if (err) {
error_setg(errp, "failed to init SD card: %s", error_get_pretty(err));
return;
PXA2xxMMCIState *s;
Error *err = NULL;
- dev = qdev_create(NULL, TYPE_PXA2XX_MMCI);
+ dev = qdev_new(TYPE_PXA2XX_MMCI);
s = PXA2XX_MMCI(dev);
sbd = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sbd, 0, base);
sysbus_connect_irq(sbd, 0, irq);
qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
+ sysbus_realize_and_unref(sbd, &error_fatal);
/* Create and plug in the sd card */
- carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
+ carddev = qdev_new(TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &err);
if (err) {
error_reportf_err(err, "failed to init SD card: ");
return NULL;
}
- object_property_set_bool(OBJECT(carddev), true, "realized", &err);
+ qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), &err);
if (err) {
error_reportf_err(err, "failed to init SD card: ");
return NULL;
struct SDState {
DeviceState parent_obj;
+ /* If true, created by sd_init() for a non-qdevified caller */
+ /* TODO purge them with fire */
+ bool me_no_qdev_me_kill_mammoth_with_rocks;
+
/* SD Memory Card Registers */
uint32_t ocr;
uint8_t scr[8];
bool cmd_line;
};
+static void sd_realize(DeviceState *dev, Error **errp);
+
static const char *sd_state_name(enum SDCardStates state)
{
static const char *state_name[] = {
{
SDState *sd = opaque;
DeviceState *dev = DEVICE(sd);
- SDBus *sdbus = SD_BUS(qdev_get_parent_bus(dev));
+ SDBus *sdbus;
bool inserted = sd_get_inserted(sd);
bool readonly = sd_get_readonly(sd);
trace_sdcard_ejected();
}
- /* The IRQ notification is for legacy non-QOM SD controller devices;
- * QOMified controllers use the SDBus APIs.
- */
- if (sdbus) {
- sdbus_set_inserted(sdbus, inserted);
+ if (sd->me_no_qdev_me_kill_mammoth_with_rocks) {
+ qemu_set_irq(sd->inserted_cb, inserted);
if (inserted) {
- sdbus_set_readonly(sdbus, readonly);
+ qemu_set_irq(sd->readonly_cb, readonly);
}
} else {
- qemu_set_irq(sd->inserted_cb, inserted);
+ sdbus = SD_BUS(qdev_get_parent_bus(dev));
+ sdbus_set_inserted(sdbus, inserted);
if (inserted) {
- qemu_set_irq(sd->readonly_cb, readonly);
+ sdbus_set_readonly(sdbus, readonly);
}
}
}
{
Object *obj;
DeviceState *dev;
+ SDState *sd;
Error *err = NULL;
obj = object_new(TYPE_SD_CARD);
return NULL;
}
qdev_prop_set_bit(dev, "spi", is_spi);
- object_property_set_bool(obj, true, "realized", &err);
+
+ /*
+ * Realizing the device properly would put it into the QOM
+ * composition tree even though it is not plugged into an
+ * appropriate bus. That's a no-no. Hide the device from
+ * QOM/qdev, and call its qdev realize callback directly.
+ */
+ object_ref(obj);
+ object_unparent(obj);
+ sd_realize(dev, &err);
if (err) {
error_reportf_err(err, "sd_init failed: ");
return NULL;
}
- return SD_CARD(dev);
+ sd = SD_CARD(dev);
+ sd->me_no_qdev_me_kill_mammoth_with_rocks = true;
+ return sd;
}
void sd_set_cb(SDState *sd, qemu_irq readonly, qemu_irq insert)
/* Create and plug in the sd card */
/* FIXME use a qdev drive property instead of drive_get_next() */
dinfo = drive_get_next(IF_SD);
- carddev = qdev_create(BUS(&s->sdbus), TYPE_SD_CARD);
+ carddev = qdev_new(TYPE_SD_CARD);
if (dinfo) {
qdev_prop_set_drive(carddev, "drive", blk_by_legacy_dinfo(dinfo), &err);
if (err) {
goto fail;
}
- object_property_set_bool(OBJECT(carddev), true, "realized", &err);
+ qdev_realize_and_unref(carddev, BUS(&s->sdbus), &err);
if (err) {
goto fail;
}
s = sh7750_init(cpu, address_space_mem);
irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
- dev = qdev_create(NULL, "sh_pci");
+ dev = qdev_new("sh_pci");
busdev = SYS_BUS_DEVICE(dev);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);
- dev = qdev_create(NULL, "sysbus-sm501");
+ dev = qdev_new("sysbus-sm501");
busdev = SYS_BUS_DEVICE(dev);
qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE);
qdev_prop_set_uint32(dev, "base", 0x10000000);
qdev_prop_set_chr(dev, "chardev", serial_hd(2));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10000000);
sysbus_mmio_map(busdev, 1, 0x13e00000);
sysbus_connect_irq(busdev, 0, irq[SM501]);
/* onboard CF (True IDE mode, Master only). */
dinfo = drive_get(IF_IDE, 0, 0);
- dev = qdev_create(NULL, "mmio-ide");
+ dev = qdev_new("mmio-ide");
busdev = SYS_BUS_DEVICE(dev);
sysbus_connect_irq(busdev, 0, irq[CF_IDE]);
qdev_prop_set_uint32(dev, "shift", 1);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x14001000);
sysbus_mmio_map(busdev, 1, 0x1400080c);
mmio_ide_init_drives(dev, dinfo, NULL);
reset_info->sp = LEON3_RAM_OFFSET + ram_size;
qemu_register_reset(main_cpu_reset, reset_info);
- ahb_pnp = GRLIB_AHB_PNP(object_new(TYPE_GRLIB_AHB_PNP));
- object_property_set_bool(OBJECT(ahb_pnp), true, "realized", &error_fatal);
+ ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP));
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET);
grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER,
GRLIB_LEON3_DEV, GRLIB_AHB_MASTER,
GRLIB_CPU_AREA);
- apb_pnp = GRLIB_APB_PNP(object_new(TYPE_GRLIB_APB_PNP));
- object_property_set_bool(OBJECT(apb_pnp), true, "realized", &error_fatal);
+ apb_pnp = GRLIB_APB_PNP(qdev_new(TYPE_GRLIB_APB_PNP));
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(apb_pnp), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET);
grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF,
GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV,
GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA);
/* Allocate IRQ manager */
- dev = qdev_create(NULL, TYPE_GRLIB_IRQMP);
+ dev = qdev_new(TYPE_GRLIB_IRQMP);
qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in,
env, "pil", 1);
qdev_connect_gpio_out_named(dev, "grlib-irq", 0,
qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_IRQMP_OFFSET);
env->irq_manager = dev;
env->qemu_irq_ack = leon3_irq_manager;
}
/* Allocate timers */
- dev = qdev_create(NULL, TYPE_GRLIB_GPTIMER);
+ dev = qdev_new(TYPE_GRLIB_GPTIMER);
qdev_prop_set_uint32(dev, "nr-timers", LEON3_TIMER_COUNT);
qdev_prop_set_uint32(dev, "frequency", CPU_CLK);
qdev_prop_set_uint32(dev, "irq-line", LEON3_TIMER_IRQ);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET);
for (i = 0; i < LEON3_TIMER_COUNT; i++) {
0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA);
/* Allocate uart */
- dev = qdev_create(NULL, TYPE_GRLIB_APB_UART);
+ dev = qdev_new(TYPE_GRLIB_APB_UART);
qdev_prop_set_chr(dev, "chrdev", serial_hd(0));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[LEON3_UART_IRQ]);
grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
+ dev = qdev_new(TYPE_SUN4M_IOMMU);
qdev_prop_set_uint32(dev, "version", version);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, irq);
sysbus_mmio_map(s, 0, addr);
SysBusESPState *esp;
SysBusPCNetState *lance;
- dma = qdev_create(NULL, TYPE_SPARC32_DMA);
- qdev_init_nofail(dma);
+ dma = qdev_new(TYPE_SPARC32_DMA);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
SysBusDevice *s;
unsigned int i, j;
- dev = qdev_create(NULL, "slavio_intctl");
- qdev_init_nofail(dev);
+ dev = qdev_new("slavio_intctl");
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
for (i = 0; i < MAX_CPUS; i++) {
for (j = 0; j < MAX_PILS; j++) {
SysBusDevice *s;
unsigned int i;
- dev = qdev_create(NULL, "slavio_timer");
+ dev = qdev_new("slavio_timer");
qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, master_irq);
sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "slavio_misc");
- qdev_init_nofail(dev);
+ dev = qdev_new("slavio_misc");
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
if (base) {
/* 8 bit registers */
/* Slavio control */
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "eccmemctl");
+ dev = qdev_new("eccmemctl");
qdev_prop_set_uint32(dev, "version", version);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, irq);
sysbus_mmio_map(s, 0, base);
if (version == 0) { // SS-600MP only
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "apc");
- qdev_init_nofail(dev);
+ dev = qdev_new("apc");
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
/* Power management (APC) XXX: not a Slavio device */
sysbus_mmio_map(s, 0, power_base);
sysbus_connect_irq(s, 0, cpu_halt);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "SUNW,tcx");
+ dev = qdev_new("SUNW,tcx");
qdev_prop_set_uint32(dev, "vram_size", vram_size);
qdev_prop_set_uint16(dev, "width", width);
qdev_prop_set_uint16(dev, "height", height);
qdev_prop_set_uint16(dev, "depth", depth);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
/* 10/ROM : FCode ROM */
sysbus_mmio_map(s, 0, addr);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "cgthree");
+ dev = qdev_new("cgthree");
qdev_prop_set_uint32(dev, "vram-size", vram_size);
qdev_prop_set_uint16(dev, "width", width);
qdev_prop_set_uint16(dev, "height", height);
qdev_prop_set_uint16(dev, "depth", depth);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
/* FCode ROM */
sysbus_mmio_map(s, 0, addr);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_MACIO_ID_REGISTER);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
address_space_write_rom(&address_space_memory, addr,
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, TYPE_TCX_AFX);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_TCX_AFX);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
}
char *filename;
int ret;
- dev = qdev_create(NULL, TYPE_OPENPROM);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_OPENPROM);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
/* Create and map RAM frontend */
- dev = qdev_create(NULL, "memory");
+ dev = qdev_new("memory");
object_property_set_link(OBJECT(dev), ram_memdev, "memdev", &error_fatal);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0);
/* models without ECC don't trap when missing ram is accessed */
/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
- dev = qdev_create(NULL, TYPE_ESCC);
+ dev = qdev_new(TYPE_ESCC);
qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
qdev_prop_set_uint32(dev, "it_shift", 1);
qdev_prop_set_chr(dev, "chrA", NULL);
qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, slavio_irq[14]);
sysbus_connect_irq(s, 1, slavio_irq[14]);
sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
- dev = qdev_create(NULL, TYPE_ESCC);
+ dev = qdev_new(TYPE_ESCC);
qdev_prop_set_uint32(dev, "disabled", 0);
qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
qdev_prop_set_uint32(dev, "it_shift", 1);
qdev_prop_set_chr(dev, "chrA", serial_hd(0));
qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, slavio_irq[15]);
sysbus_connect_irq(s, 1, slavio_irq[15]);
sysbus_mmio_map(s, 0, hwdef->serial_base);
ecc_init(hwdef->ecc_base, slavio_irq[28],
hwdef->ecc_version);
- dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
+ dev = qdev_new(TYPE_FW_CFG_MEM);
fw_cfg = FW_CFG(dev);
qdev_prop_set_uint32(dev, "data_width", 1);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg));
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
static void ebus_realize(PCIDevice *pci_dev, Error **errp)
{
EbusState *s = EBUS(pci_dev);
+ ISADevice *isa_dev;
SysBusDevice *sbd;
DeviceState *dev;
qemu_irq *isa_irq;
for (i = 0; i < MAX_FD; i++) {
fd[i] = drive_get(IF_FLOPPY, 0, i);
}
- dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
+ isa_dev = isa_new(TYPE_ISA_FDC);
+ dev = DEVICE(isa_dev);
if (fd[0]) {
qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
&error_abort);
&error_abort);
}
qdev_prop_set_uint32(dev, "dma", -1);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isa_dev, s->isa_bus, &error_fatal);
/* Power */
- dev = qdev_create(NULL, TYPE_SUN4U_POWER);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_SUN4U_POWER);
sbd = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbd, &error_fatal);
memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
sysbus_mmio_get_region(sbd, 0));
char *filename;
int ret;
- dev = qdev_create(NULL, TYPE_OPENPROM);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_OPENPROM);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
RamDevice *d;
/* allocate RAM */
- dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
+ dev = qdev_new(TYPE_SUN4U_MEMORY);
s = SYS_BUS_DEVICE(dev);
d = SUN4U_RAM(dev);
d->size = RAM_size;
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
}
cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
/* IOMMU */
- iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
- qdev_init_nofail(iommu);
+ iommu = qdev_new(TYPE_SUN4U_IOMMU);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu), &error_fatal);
/* set up devices */
ram_init(0, machine->ram_size);
prom_init(hwdef->prom_addr, bios_name);
/* Init sabre (PCI host bridge) */
- sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
+ sabre = SABRE_DEVICE(qdev_new(TYPE_SABRE));
qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
&error_abort);
- qdev_init_nofail(DEVICE(sabre));
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal);
/* Wire up PCI interrupts to CPU */
for (i = 0; i < IVEC_MAX; i++) {
pci_busA->slot_reserved_mask = 0xfffffff1;
pci_busB->slot_reserved_mask = 0xfffffff0;
- ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
+ ebus = pci_new_multifunction(PCI_DEVFN(1, 0), true, TYPE_EBUS);
qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
hwdef->console_serial_base);
- qdev_init_nofail(DEVICE(ebus));
+ pci_realize_and_unref(ebus, pci_busA, &error_fatal);
/* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
memset(&macaddr, 0, sizeof(MACAddr));
onboard_nic = false;
for (i = 0; i < nb_nics; i++) {
+ PCIBus *bus;
nd = &nd_table[i];
if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
if (!onboard_nic) {
- pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
+ pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1),
true, "sunhme");
+ bus = pci_busA;
memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
onboard_nic = true;
} else {
- pci_dev = pci_create(pci_busB, -1, "sunhme");
+ pci_dev = pci_new(-1, "sunhme");
+ bus = pci_busB;
}
} else {
- pci_dev = pci_create(pci_busB, -1, nd->model);
+ pci_dev = pci_new(-1, nd->model);
+ bus = pci_busB;
}
dev = &pci_dev->qdev;
qdev_set_nic_properties(dev, nd);
- qdev_init_nofail(dev);
+ pci_realize_and_unref(pci_dev, bus, &error_fatal);
}
/* If we don't have an onboard NIC, grab a default MAC address so that
qemu_macaddr_default_if_unset(&macaddr);
}
- pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
+ pci_dev = pci_new(PCI_DEVFN(3, 0), "cmd646-ide");
qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
- qdev_init_nofail(&pci_dev->qdev);
+ pci_realize_and_unref(pci_dev, pci_busA, &error_fatal);
pci_ide_create_devs(pci_dev);
/* Map NVRAM into I/O (ebus) space */
graphic_width, graphic_height, graphic_depth,
(uint8_t *)&macaddr);
- dev = qdev_create(NULL, TYPE_FW_CFG_IO);
+ dev = qdev_new(TYPE_FW_CFG_IO);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev));
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
&FW_CFG_IO(dev)->comb_iomem);
/* Setup cs_lines for slaves */
s->cs_lines = g_new0(qemu_irq, s->num_cs);
- ssi_auto_connect_slaves(dev, s->cs_lines, s->spi);
for (i = 0; i < s->num_cs; ++i) {
sysbus_init_irq(sbd, &s->cs_lines[i]);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
- ssi_auto_connect_slaves(dev, s->cs_lines, s->bus);
-
for (i = 0; i < 4; ++i) {
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
}
s->spi = ssi_create_bus(dev, "spi");
sysbus_init_irq(sbd, &s->irq);
- ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
sysbus_init_irq(sbd, &s->cs_line);
memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
#include "hw/ssi/ssi.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
+#include "qapi/error.h"
struct SSIBus {
BusState parent_obj;
.abstract = true,
};
-DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name)
-{
- return qdev_create(BUS(bus), name);
-}
-
DeviceState *ssi_create_slave(SSIBus *bus, const char *name)
{
- DeviceState *dev = ssi_create_slave_no_init(bus, name);
+ DeviceState *dev = qdev_new(name);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, &bus->parent_obj, &error_fatal);
return dev;
}
}
type_init(ssi_slave_register_types)
-
-typedef struct SSIAutoConnectArg {
- qemu_irq **cs_linep;
- SSIBus *bus;
-} SSIAutoConnectArg;
-
-static int ssi_auto_connect_slave(Object *child, void *opaque)
-{
- SSIAutoConnectArg *arg = opaque;
- SSISlave *dev = (SSISlave *)object_dynamic_cast(child, TYPE_SSI_SLAVE);
- qemu_irq cs_line;
-
- if (!dev) {
- return 0;
- }
-
- cs_line = qdev_get_gpio_in_named(DEVICE(dev), SSI_GPIO_CS, 0);
- qdev_set_parent_bus(DEVICE(dev), BUS(arg->bus));
- **arg->cs_linep = cs_line;
- (*arg->cs_linep)++;
- return 0;
-}
-
-void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_line,
- SSIBus *bus)
-{
- SSIAutoConnectArg arg = {
- .cs_linep = &cs_line,
- .bus = bus
- };
-
- object_child_foreach(OBJECT(parent), ssi_auto_connect_slave, &arg);
-}
sysbus_init_irq(sbd, &s->irq);
s->cs_lines = g_new0(qemu_irq, s->num_cs);
- ssi_auto_connect_slaves(dev, s->cs_lines, s->spi);
for (i = 0; i < s->num_cs; ++i) {
sysbus_init_irq(sbd, &s->cs_lines[i]);
}
XilinxSPIPS *s = XILINX_SPIPS(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
- qemu_irq *cs;
int i;
DB_PRINT_L(0, "realized spips\n");
s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses);
- for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) {
- ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]);
- }
sysbus_init_irq(sbd, &s->irq);
for (i = 0; i < s->num_cs * s->num_busses; ++i) {
{
const char *name;
const char *usbdevice_name;
- USBDevice *(*usbdevice_init)(USBBus *bus, const char *params);
+ USBDevice *(*usbdevice_init)(const char *params);
} LegacyUSBFactory;
static GSList *legacy_usb_factory;
void usb_legacy_register(const char *typename, const char *usbdevice_name,
- USBDevice *(*usbdevice_init)(USBBus *bus,
- const char *params))
+ USBDevice *(*usbdevice_init)(const char *params))
{
if (usbdevice_name) {
LegacyUSBFactory *f = g_malloc0(sizeof(*f));
}
}
-USBDevice *usb_create(USBBus *bus, const char *name)
+USBDevice *usb_new(const char *name)
{
- DeviceState *dev;
-
- dev = qdev_create(&bus->qbus, name);
- return USB_DEVICE(dev);
+ return USB_DEVICE(qdev_new(name));
}
-static USBDevice *usb_try_create_simple(USBBus *bus, const char *name,
- Error **errp)
+static USBDevice *usb_try_new(const char *name)
{
- Error *err = NULL;
- USBDevice *dev;
+ return USB_DEVICE(qdev_try_new(name));
+}
- dev = USB_DEVICE(qdev_try_create(&bus->qbus, name));
- if (!dev) {
- error_setg(errp, "Failed to create USB device '%s'", name);
- return NULL;
- }
- object_property_set_bool(OBJECT(dev), true, "realized", &err);
- if (err) {
- error_propagate_prepend(errp, err,
- "Failed to initialize USB device '%s': ",
- name);
- return NULL;
- }
- return dev;
+bool usb_realize_and_unref(USBDevice *dev, USBBus *bus, Error **errp)
+{
+ return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp);
}
USBDevice *usb_create_simple(USBBus *bus, const char *name)
{
- return usb_try_create_simple(bus, name, &error_abort);
+ USBDevice *dev = usb_new(name);
+
+ usb_realize_and_unref(dev, bus, &error_abort);
+ return dev;
}
static void usb_fill_port(USBPort *port, void *opaque, int index,
{
USBBus *bus = usb_bus_from_device(dev);
USBPort *port;
+ USBDevice *hub;
assert(dev->port == NULL);
} else {
if (bus->nfree == 1 && strcmp(object_get_typename(OBJECT(dev)), "usb-hub") != 0) {
/* Create a new hub and chain it on */
- usb_try_create_simple(bus, "usb-hub", NULL);
+ hub = usb_try_new("usb-hub");
+ if (hub) {
+ usb_realize_and_unref(hub, bus, NULL);
+ }
}
if (bus->nfree == 0) {
error_setg(errp, "tried to attach usb device %s to a bus "
}
if (f->usbdevice_init) {
- dev = f->usbdevice_init(bus, params);
+ dev = f->usbdevice_init(params);
} else {
if (*params) {
error_report("usbdevice %s accepts no params", driver);
return NULL;
}
- dev = usb_create(bus, f->name);
+ dev = usb_new(f->name);
}
if (!dev) {
error_report("Failed to create USB device '%s'", f->name);
return NULL;
}
- object_property_set_bool(OBJECT(dev), true, "realized", &err);
+ usb_realize_and_unref(dev, bus, &err);
if (err) {
error_reportf_err(err, "Failed to initialize USB device '%s': ",
f->name);
s->intr = usb_ep_get(dev, USB_TOKEN_IN, 1);
}
-static USBDevice *usb_braille_init(USBBus *bus, const char *unused)
+static USBDevice *usb_braille_init(const char *unused)
{
USBDevice *dev;
Chardev *cdrv;
if (!cdrv)
return NULL;
- dev = usb_create(bus, "usb-braille");
+ dev = usb_new("usb-braille");
qdev_prop_set_chr(&dev->qdev, "chardev", cdrv);
return dev;
}
vpci_dev->nvectors = vs->conf.num_queues + 3;
}
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static void vhost_scsi_pci_class_init(ObjectClass *klass, void *data)
vpci_dev->nvectors = dev->vdev.num_queues + 1;
}
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static void vhost_user_blk_pci_class_init(ObjectClass *klass, void *data)
vpci_dev->nvectors = dev->vdev.conf.num_request_queues + 2;
}
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static void vhost_user_fs_pci_class_init(ObjectClass *klass, void *data)
vpci_dev->nvectors = vs->conf.num_queues + 3;
}
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static void vhost_user_scsi_pci_class_init(ObjectClass *klass, void *data)
VHostUserVSockPCI *dev = VHOST_USER_VSOCK_PCI(vpci_dev);
DeviceState *vdev = DEVICE(&dev->vdev);
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static void vhost_user_vsock_pci_class_init(ObjectClass *klass, void *data)
VHostVSockPCI *dev = VHOST_VSOCK_PCI(vpci_dev);
DeviceState *vdev = DEVICE(&dev->vdev);
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static void vhost_vsock_pci_class_init(ObjectClass *klass, void *data)
V9fsPCIState *dev = VIRTIO_9P_PCI(vpci_dev);
DeviceState *vdev = DEVICE(&dev->vdev);
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static Property virtio_9p_pci_properties[] = {
vpci_dev->class_code = PCI_CLASS_OTHERS;
}
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static void virtio_balloon_pci_class_init(ObjectClass *klass, void *data)
vpci_dev->nvectors = dev->vdev.conf.num_queues + 1;
}
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static void virtio_blk_pci_class_init(ObjectClass *klass, void *data)
return;
}
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
virtio_pci_force_virtio_1(vpci_dev);
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
object_property_set_link(OBJECT(vcrypto),
OBJECT(vcrypto->vdev.conf.cryptodev), "cryptodev",
NULL);
VirtIOInputPCI *vinput = VIRTIO_INPUT_PCI(vpci_dev);
DeviceState *vdev = DEVICE(&vinput->vdev);
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
virtio_pci_force_virtio_1(vpci_dev);
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static void virtio_input_pci_class_init(ObjectClass *klass, void *data)
"-no-acpi\n");
return;
}
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
object_property_set_link(OBJECT(dev),
OBJECT(pci_get_bus(&vpci_dev->pci_dev)),
"primary-bus", errp);
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static void virtio_iommu_pci_class_init(ObjectClass *klass, void *data)
virtio_net_set_netclient_name(&dev->vdev, qdev->id,
object_get_typename(OBJECT(qdev)));
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static void virtio_net_pci_class_init(ObjectClass *klass, void *data)
VirtIOPMEMPCI *pmem_pci = VIRTIO_PMEM_PCI(vpci_dev);
DeviceState *vdev = DEVICE(&pmem_pci->vdev);
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static void virtio_pmem_pci_set_addr(MemoryDeviceState *md, uint64_t addr,
DeviceState *vdev = DEVICE(&vrng->vdev);
Error *err = NULL;
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", &err);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), &err);
if (err) {
error_propagate(errp, err);
return;
g_free(bus_name);
}
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static void virtio_scsi_pci_class_init(ObjectClass *klass, void *data)
g_free(bus_name);
}
- qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- object_property_set_bool(OBJECT(vdev), true, "realized", errp);
+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
}
static Property virtio_serial_pci_properties[] = {
{
DeviceState *vdev = data;
- object_initialize_child(proxy_obj, "virtio-backend", vdev, vdev_size,
- vdev_name, &error_abort, NULL);
+ object_initialize_child_with_props(proxy_obj, "virtio-backend", vdev,
+ vdev_size, vdev_name, &error_abort,
+ NULL);
qdev_alias_all_properties(vdev, proxy_obj);
}
void xen_bus_init(void)
{
- DeviceState *dev = qdev_create(NULL, TYPE_XEN_BRIDGE);
+ DeviceState *dev = qdev_new(TYPE_XEN_BRIDGE);
BusState *bus = qbus_create(TYPE_XEN_BUS, dev, NULL);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
qbus_set_bus_hotplug_handler(bus, &error_abort);
}
xendev = g_malloc0(ops->size);
object_initialize(&xendev->qdev, ops->size, TYPE_XENBACKEND);
OBJECT(xendev)->free = g_free;
- qdev_set_parent_bus(DEVICE(xendev), xen_sysbus);
qdev_set_id(DEVICE(xendev), g_strdup_printf("xen-%s-%d", type, dev));
- qdev_init_nofail(DEVICE(xendev));
+ qdev_realize(DEVICE(xendev), xen_sysbus, &error_fatal);
object_unref(OBJECT(xendev));
xendev->type = type;
xengnttab_close(gnttabdev);
}
- xen_sysdev = qdev_create(NULL, TYPE_XENSYSDEV);
- qdev_init_nofail(xen_sysdev);
+ xen_sysdev = qdev_new(TYPE_XENSYSDEV);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(xen_sysdev), &error_fatal);
xen_sysbus = qbus_create(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus");
qbus_set_bus_hotplug_handler(xen_sysbus, &error_abort);
qemu_irq *extints;
int i;
- dev = qdev_create(NULL, TYPE_GPEX_HOST);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_GPEX_HOST);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Map only the first size_ecam bytes of ECAM space. */
ecam_alias = g_new0(MemoryRegion, 1);
SysBusDevice *s;
MemoryRegion *ram;
- dev = qdev_create(NULL, "open_eth");
+ dev = qdev_new("open_eth");
qdev_set_nic_properties(dev, nd);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, irq);
memory_region_add_subregion(address_space, base,
sysbus_mmio_get_region(s, 0));
DriveInfo *dinfo, int be)
{
SysBusDevice *s;
- DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
+ DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
&error_abort);
qdev_prop_set_uint8(dev, "width", 2);
qdev_prop_set_bit(dev, "big-endian", be);
qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
memory_region_add_subregion(address_space, board->flash->base,
sysbus_mmio_get_region(s, 0));
return PFLASH_CFI01(dev);
bool mmio_exec;
} AspeedMachine;
+#define ASPEED_MAC0_ON (1 << 0)
+#define ASPEED_MAC1_ON (1 << 1)
+#define ASPEED_MAC2_ON (1 << 2)
+#define ASPEED_MAC3_ON (1 << 3)
+
#define ASPEED_MACHINE_CLASS(klass) \
OBJECT_CLASS_CHECK(AspeedMachineClass, (klass), TYPE_ASPEED_MACHINE)
#define ASPEED_MACHINE_GET_CLASS(obj) \
const char *fmc_model;
const char *spi_model;
uint32_t num_cs;
+ uint32_t macs_mask;
void (*i2c_init)(AspeedBoardState *bmc);
} AspeedMachineClass;
/*< public >*/
ARMCPU cpu[ASPEED_CPUS_NUM];
- uint32_t num_cpus;
A15MPPrivState a7mpcore;
MemoryRegion *dram_mr;
MemoryRegion sram;
#include "hw/isa/isa.h"
#include "hw/qdev-properties.h"
+#include "qapi/error.h"
#define TYPE_PC_SPEAKER "isa-pcspk"
DeviceState *dev;
ISADevice *isadev;
- isadev = isa_create(bus, TYPE_PC_SPEAKER);
+ isadev = isa_new(TYPE_PC_SPEAKER);
dev = DEVICE(isadev);
qdev_prop_set_uint32(dev, "iobase", 0x61);
object_property_set_link(OBJECT(dev), OBJECT(pit), "pit", NULL);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(isadev, bus, &error_fatal);
return isadev;
}
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
+#include "qapi/error.h"
#include "qemu/timer.h"
#define CADENCE_UART_RX_FIFO_SIZE 16
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, TYPE_CADENCE_UART);
+ dev = qdev_new(TYPE_CADENCE_UART);
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, irq);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, TYPE_CMSDK_APB_UART);
+ dev = qdev_new(TYPE_CMSDK_APB_UART);
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, txint);
sysbus_connect_irq(s, 1, rxint);
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
+#include "qapi/error.h"
#define TYPE_PL011 "pl011"
#define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011)
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "pl011");
+ dev = qdev_new("pl011");
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, irq);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "pl011_luminary");
+ dev = qdev_new("pl011_luminary");
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, irq);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "xlnx.xps-uartlite");
+ dev = qdev_new("xlnx.xps-uartlite");
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, irq);
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "etraxfs,serial");
+ dev = qdev_new("etraxfs,serial");
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, irq);
return dev;
IsaDma *isa_get_dma(ISABus *bus, int nchan);
MemoryRegion *isa_address_space(ISADevice *dev);
MemoryRegion *isa_address_space_io(ISADevice *dev);
-ISADevice *isa_create(ISABus *bus, const char *name);
-ISADevice *isa_try_create(ISABus *bus, const char *name);
+ISADevice *isa_new(const char *name);
+ISADevice *isa_try_new(const char *name);
+bool isa_realize_and_unref(ISADevice *dev, ISABus *bus, Error **errp);
ISADevice *isa_create_simple(ISABus *bus, const char *name);
ISADevice *isa_vga_init(ISABus *bus);
};
/**
- * aux_init_bus: Initialize an AUX bus.
+ * aux_bus_init: Initialize an AUX bus.
*
* Returns the new AUX bus created.
*
* @parent The device where this bus is located.
* @name The name of the bus.
*/
-AUXBus *aux_init_bus(DeviceState *parent, const char *name);
+AUXBus *aux_bus_init(DeviceState *parent, const char *name);
+
+/**
+ * aux_bus_realize: Realize an AUX bus.
+ *
+ * @bus: The AUX bus.
+ */
+void aux_bus_realize(AUXBus *bus);
/*
* aux_request: Make a request on the bus.
*/
void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio);
-/* aux_create_slave: Create a new device on an AUX bus
- *
- * @bus The AUX bus for the new device.
- * @name The type of the device to be created.
- */
-DeviceState *aux_create_slave(AUXBus *bus, const char *name);
-
/* aux_map_slave: Map the mmio for an AUX slave on the bus.
*
* @dev The AUX slave.
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
+#include "qapi/error.h"
#define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device"
hwaddr base,
hwaddr size)
{
- DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
+ DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(dev, "name", name);
qdev_prop_set_uint64(dev, "size", size);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, -1000);
}
#include "hw/isa/isa.h"
#include "hw/qdev-properties.h"
#include "net/net.h"
+#include "qapi/error.h"
#define TYPE_ISA_NE2000 "ne2k_isa"
qemu_check_nic_model(nd, "ne2k_isa");
- d = isa_try_create(bus, TYPE_ISA_NE2000);
+ d = isa_try_new(TYPE_ISA_NE2000);
if (d) {
DeviceState *dev = DEVICE(d);
qdev_prop_set_uint32(dev, "iobase", base);
qdev_prop_set_uint32(dev, "irq", irq);
qdev_set_nic_properties(dev, nd);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(d, bus, &error_fatal);
}
return d;
}
return (val & mask) >> ctz32(mask);
}
-PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
+PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
const char *name);
+PCIDevice *pci_new(int devfn, const char *name);
+bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
+
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
bool multifunction,
const char *name);
-PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
#define PSIHB_XSCOM_MAX 0x20
typedef struct PnvPsi {
- SysBusDevice parent;
+ DeviceState parent;
MemoryRegion regs_mr;
uint64_t bar;
* After successful realization, setting static properties will fail.
*
* As an interim step, the #DeviceState:realized property can also be
- * set with qdev_init_nofail().
+ * set with qdev_realize().
* In the future, devices will propagate this state change to their children
* and along busses they expose.
* The point in time will be deferred to machine creation, so that values
/*** Board API. This should go away once we have a machine config file. ***/
-DeviceState *qdev_create(BusState *bus, const char *name);
-DeviceState *qdev_try_create(BusState *bus, const char *name);
-void qdev_init_nofail(DeviceState *dev);
+DeviceState *qdev_new(const char *name);
+DeviceState *qdev_try_new(const char *name);
+bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp);
+bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp);
+void qdev_unrealize(DeviceState *dev);
void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id,
int required_for_version);
HotplugHandler *qdev_get_bus_hotplug_handler(DeviceState *dev);
void qbus_create_inplace(void *bus, size_t size, const char *typename,
DeviceState *parent, const char *name);
BusState *qbus_create(const char *typename, DeviceState *parent, const char *name);
+bool qbus_realize(BusState *bus, Error **errp);
+void qbus_unrealize(BusState *bus);
+
/* Returns > 0 if either devfn or busfn skip walk somewhere in cursion,
* < 0 if either devfn or busfn terminate walk somewhere in cursion,
* 0 otherwise. */
typedef struct SiFiveESoCState {
/*< private >*/
- SysBusDevice parent_obj;
+ DeviceState parent_obj;
/*< public >*/
RISCVHartArrayState cpus;
typedef struct SiFiveUSoCState {
/*< private >*/
- SysBusDevice parent_obj;
+ DeviceState parent_obj;
/*< public >*/
CPUClusterState e_cluster;
}
DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
-DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name);
/* Master interface. */
SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
uint32_t ssi_transfer(SSIBus *bus, uint32_t val);
-/* Automatically connect all children nodes a spi controller as slaves */
-void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_lines,
- SSIBus *bus);
-
/* max111x.c */
void max111x_set_input(DeviceState *dev, int line, uint8_t value);
MemoryRegion *mem);
MemoryRegion *sysbus_address_space(SysBusDevice *dev);
-/**
- * sysbus_init_child_obj:
- * @parent: The parent object
- * @childname: Used as name of the "child<>" property in the parent
- * @child: A pointer to the memory to be used for the object.
- * @childsize: The maximum size available at @child for the object.
- * @childtype: The name of the type of the object to instantiate.
- *
- * This function will initialize an object and attach it to the main system
- * bus. The memory for the object should have already been allocated. The
- * object will then be added as child to the given parent. The returned object
- * has a reference count of 1 (for the "child<...>" property from the parent),
- * so the object will be finalized automatically when the parent gets removed.
- */
-void sysbus_init_child_obj(Object *parent, const char *childname, void *child,
- size_t childsize, const char *childtype);
+bool sysbus_realize(SysBusDevice *dev, Error **errp);
+bool sysbus_realize_and_unref(SysBusDevice *dev, Error **errp);
/* Call func for every dynamically created sysbus device in the system */
void foreach_dynamic_sysbus_device(FindSysbusDeviceFunc *func, void *opaque);
return sysbus_create_varargs(name, addr, irq, NULL);
}
-
#endif /* HW_SYSBUS_H */
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, TYPE_CMSDK_APB_TIMER);
+ dev = qdev_new(TYPE_CMSDK_APB_TIMER);
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, timerint);
return dev;
#include "hw/qdev-properties.h"
#include "hw/isa/isa.h"
+#include "qapi/error.h"
#define PIT_FREQ 1193182
DeviceState *dev;
ISADevice *d;
- d = isa_create(bus, TYPE_I8254);
+ d = isa_new(TYPE_I8254);
dev = DEVICE(d);
qdev_prop_set_uint32(dev, "iobase", base);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(d, bus, &error_fatal);
qdev_connect_gpio_out(dev, 0,
isa_irq >= 0 ? isa_get_irq(d, isa_irq) : alt_irq);
DeviceState *dev;
ISADevice *d;
- d = isa_create(bus, TYPE_KVM_I8254);
+ d = isa_new(TYPE_KVM_I8254);
dev = DEVICE(d);
qdev_prop_set_uint32(dev, "iobase", base);
- qdev_init_nofail(dev);
+ isa_realize_and_unref(d, bus, &error_fatal);
return d;
}
void usb_bus_release(USBBus *bus);
USBBus *usb_bus_find(int busnr);
void usb_legacy_register(const char *typename, const char *usbdevice_name,
- USBDevice *(*usbdevice_init)(USBBus *bus,
- const char *params));
-USBDevice *usb_create(USBBus *bus, const char *name);
+ USBDevice *(*usbdevice_init)(const char *params));
+USBDevice *usb_new(const char *name);
+bool usb_realize_and_unref(USBDevice *dev, USBBus *bus, Error **errp);
USBDevice *usb_create_simple(USBBus *bus, const char *name);
USBDevice *usbdevice_create(const char *cmdline);
void usb_register_port(USBBus *bus, USBPort *port, void *opaque, int index,
void object_initialize(void *obj, size_t size, const char *typename);
/**
- * object_initialize_child:
+ * object_initialize_child_with_props:
* @parentobj: The parent object to add a property to
* @propname: The name of the property
* @childobj: A pointer to the memory to be used for the object.
* If the object implements the user creatable interface, the object will
* be marked complete once all the properties have been processed.
*/
-void object_initialize_child(Object *parentobj, const char *propname,
+void object_initialize_child_with_props(Object *parentobj,
+ const char *propname,
void *childobj, size_t size, const char *type,
Error **errp, ...) QEMU_SENTINEL;
/**
- * object_initialize_childv:
+ * object_initialize_child_with_propsv:
* @parentobj: The parent object to add a property to
* @propname: The name of the property
* @childobj: A pointer to the memory to be used for the object.
*
* See object_initialize_child() for documentation.
*/
-void object_initialize_childv(Object *parentobj, const char *propname,
+void object_initialize_child_with_propsv(Object *parentobj,
+ const char *propname,
void *childobj, size_t size, const char *type,
Error **errp, va_list vargs);
+/**
+ * object_initialize_child:
+ * @parent: The parent object to add a property to
+ * @propname: The name of the property
+ * @child: A precisely typed pointer to the memory to be used for the
+ * object.
+ * @type: The name of the type of the object to instantiate.
+ *
+ * This is like
+ * object_initialize_child_with_props(parent, propname,
+ * child, sizeof(*child), type,
+ * &error_abort, NULL)
+ */
+#define object_initialize_child(parent, propname, child, type) \
+ object_initialize_child_internal((parent), (propname), \
+ (child), sizeof(*(child)), (type))
+void object_initialize_child_internal(Object *parent, const char *propname,
+ void *child, size_t size,
+ const char *type);
+
/**
* object_dynamic_cast:
* @obj: The object to cast.
* path is the path within the composition tree starting from the root.
* %NULL if the object doesn't have a parent (and thus a canonical path).
*/
-char *object_get_canonical_path_component(Object *obj);
+char *object_get_canonical_path_component(const Object *obj);
/**
* object_get_canonical_path:
* Returns: The canonical path for a object. This is the path within the
* composition tree starting from the root.
*/
-char *object_get_canonical_path(Object *obj);
+char *object_get_canonical_path(const Object *obj);
/**
* object_resolve_path:
.name = TYPE_MIGRATION,
/*
* NOTE: TYPE_MIGRATION is not really a device, as the object is
- * not created using qdev_create(), it is not attached to the qdev
+ * not created using qdev_new(), it is not attached to the qdev
* device tree, and it is never realized.
*
* TODO: Make this TYPE_OBJECT once QOM provides something like
}
/* create device */
- dev = DEVICE(object_new(driver));
+ dev = qdev_new(driver);
/* Check whether the hotplug is allowed by the machine */
if (qdev_hotplug && !qdev_hotplug_allowed(dev, &err)) {
goto err_del_dev;
}
- if (bus) {
- qdev_set_parent_bus(dev, bus);
- } else if (qdev_hotplug && !qdev_get_machine_hotplug_handler(dev)) {
+ if (!bus && qdev_hotplug && !qdev_get_machine_hotplug_handler(dev)) {
/* No bus, no machine hotplug handler --> device is not hotpluggable */
error_setg(&err, "Device '%s' can not be hotplugged on this machine",
driver);
}
dev->opts = opts;
- object_property_set_bool(OBJECT(dev), true, "realized", &err);
+ qdev_realize(DEVICE(dev), bus, &err);
if (err != NULL) {
dev->opts = NULL;
goto err_del_dev;
object_initialize_with_type(data, size, type);
}
-void object_initialize_child(Object *parentobj, const char *propname,
+void object_initialize_child_with_props(Object *parentobj,
+ const char *propname,
void *childobj, size_t size, const char *type,
Error **errp, ...)
{
va_list vargs;
va_start(vargs, errp);
- object_initialize_childv(parentobj, propname, childobj, size, type, errp,
- vargs);
+ object_initialize_child_with_propsv(parentobj, propname,
+ childobj, size, type, errp, vargs);
va_end(vargs);
}
-void object_initialize_childv(Object *parentobj, const char *propname,
+void object_initialize_child_with_propsv(Object *parentobj,
+ const char *propname,
void *childobj, size_t size, const char *type,
Error **errp, va_list vargs)
{
error_propagate(errp, local_err);
}
+void object_initialize_child_internal(Object *parent,
+ const char *propname,
+ void *child, size_t size,
+ const char *type)
+{
+ object_initialize_child_with_props(parent, propname, child, size, type,
+ &error_abort, NULL);
+}
+
static inline bool object_property_is_child(ObjectProperty *prop)
{
return strstart(prop->type, "child<", NULL);
NULL, OBJ_PROP_LINK_DIRECT);
}
-char *object_get_canonical_path_component(Object *obj)
+char *object_get_canonical_path_component(const Object *obj)
{
ObjectProperty *prop = NULL;
GHashTableIter iter;
return NULL;
}
-char *object_get_canonical_path(Object *obj)
+char *object_get_canonical_path(const Object *obj)
{
Object *root = object_get_root();
char *newpath, *path = NULL;
static void print_qom_composition(Monitor *mon, Object *obj, int indent);
-static int print_qom_composition_child(Object *obj, void *opaque)
+static int qom_composition_compare(const void *a, const void *b, void *ignore)
{
- QOMCompositionState *s = opaque;
+ return g_strcmp0(a ? object_get_canonical_path_component(a) : NULL,
+ b ? object_get_canonical_path_component(b) : NULL);
+}
- print_qom_composition(s->mon, obj, s->indent);
+static int insert_qom_composition_child(Object *obj, void *opaque)
+{
+ GQueue *children = opaque;
+ g_queue_insert_sorted(children, obj, qom_composition_compare, NULL);
return 0;
}
static void print_qom_composition(Monitor *mon, Object *obj, int indent)
{
- QOMCompositionState s = {
- .mon = mon,
- .indent = indent + 2,
- };
char *name;
+ GQueue children;
+ Object *child;
if (obj == object_get_root()) {
name = g_strdup("");
monitor_printf(mon, "%*s/%s (%s)\n", indent, "", name,
object_get_typename(obj));
g_free(name);
- object_child_foreach(obj, print_qom_composition_child, &s);
+
+ g_queue_init(&children);
+ object_child_foreach(obj, insert_qom_composition_child, &children);
+ while ((child = g_queue_pop_head(&children))) {
+ print_qom_composition(mon, child, indent + 2);
+ }
}
void hmp_info_qom_tree(Monitor *mon, const QDict *dict)
if (cpu->apic_state == NULL) {
return;
}
- object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
- errp);
+ qdev_realize(DEVICE(cpu->apic_state), NULL, errp);
/* Map APIC MMIO area */
apic = APIC_COMMON(cpu->apic_state);
#include "hw/qdev-properties.h"
#include "qom/object.h"
+#include "qapi/error.h"
#include "qapi/visitor.h"
MyType *mt;
mt = STATIC_TYPE(object_new(TYPE_STATIC_PROPS));
- qdev_init_nofail(DEVICE(mt));
+ qdev_realize(DEVICE(mt), NULL, &error_fatal);
g_assert_cmpuint(mt->prop1, ==, PROP_DEFAULT);
}
register_global_properties(props);
mt = STATIC_TYPE(object_new(TYPE_STATIC_PROPS));
- qdev_init_nofail(DEVICE(mt));
+ qdev_realize(DEVICE(mt), NULL, &error_fatal);
g_assert_cmpuint(mt->prop1, ==, 200);
g_assert_cmpuint(mt->prop2, ==, PROP_DEFAULT);
register_global_properties(props);
mt = DYNAMIC_TYPE(object_new(TYPE_DYNAMIC_PROPS));
- qdev_init_nofail(DEVICE(mt));
+ qdev_realize(DEVICE(mt), NULL, &error_fatal);
g_assert_cmpuint(mt->prop1, ==, 101);
g_assert_cmpuint(mt->prop2, ==, 102);
register_global_properties(props);
mt = STATIC_TYPE(object_new(TYPE_SUBCLASS));
- qdev_init_nofail(DEVICE(mt));
+ qdev_realize(DEVICE(mt), NULL, &error_fatal);
g_assert_cmpuint(mt->prop1, ==, 102);
g_assert_cmpuint(mt->prop2, ==, 104);
projects / mirror_qemu.git / commitdiff