ath9k: add bits definition of BTCoex MODE2/3 for SOC chips

Add bits definition for AR_BT_COEX_MODE2 and AR_BT_COEX_MODE3, which
needed by SOC chips (AR9340, AR9531, AR9550, AR9561).

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>

diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 909c6b5f4f7b027a917395d0cef8f11487bf5167..9272ca90632b983b5eec1a57612ac29307f15973 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -1892,15 +1892,33 @@ enum {
 
 #define AR9300_BT_WGHT             0xcccc4444
 
-#define AR_BT_COEX_MODE2           0x817c
-#define AR_BT_BCN_MISS_THRESH      0x000000ff
-#define AR_BT_BCN_MISS_THRESH_S    0
-#define AR_BT_BCN_MISS_CNT         0x0000ff00
-#define AR_BT_BCN_MISS_CNT_S       8
-#define AR_BT_HOLD_RX_CLEAR        0x00010000
-#define AR_BT_HOLD_RX_CLEAR_S      16
-#define AR_BT_DISABLE_BT_ANT       0x00100000
-#define AR_BT_DISABLE_BT_ANT_S     20
+#define AR_BT_COEX_MODE2               0x817c
+#define AR_BT_BCN_MISS_THRESH          0x000000ff
+#define AR_BT_BCN_MISS_THRESH_S                0
+#define AR_BT_BCN_MISS_CNT             0x0000ff00
+#define AR_BT_BCN_MISS_CNT_S           8
+#define AR_BT_HOLD_RX_CLEAR            0x00010000
+#define AR_BT_HOLD_RX_CLEAR_S          16
+#define AR_BT_PROTECT_BT_AFTER_WAKEUP  0x00080000
+#define AR_BT_PROTECT_BT_AFTER_WAKEUP_S 19
+#define AR_BT_DISABLE_BT_ANT           0x00100000
+#define AR_BT_DISABLE_BT_ANT_S         20
+#define AR_BT_QUIET_2_WIRE             0x00200000
+#define AR_BT_QUIET_2_WIRE_S           21
+#define AR_BT_WL_ACTIVE_MODE           0x00c00000
+#define AR_BT_WL_ACTIVE_MODE_S         22
+#define AR_BT_WL_TXRX_SEPARATE         0x01000000
+#define AR_BT_WL_TXRX_SEPARATE_S       24
+#define AR_BT_RS_DISCARD_EXTEND                0x02000000
+#define AR_BT_RS_DISCARD_EXTEND_S      25
+#define AR_BT_TSF_BT_ACTIVE_CTRL       0x0c000000
+#define AR_BT_TSF_BT_ACTIVE_CTRL_S     26
+#define AR_BT_TSF_BT_PRIORITY_CTRL     0x30000000
+#define AR_BT_TSF_BT_PRIORITY_CTRL_S   28
+#define AR_BT_INTERRUPT_ENABLE         0x40000000
+#define AR_BT_INTERRUPT_ENABLE_S       30
+#define AR_BT_PHY_ERR_BT_COLL_ENABLE   0x80000000
+#define AR_BT_PHY_ERR_BT_COLL_ENABLE_S 31
 
 #define AR_TXSIFS              0x81d0
 #define AR_TXSIFS_TIME         0x000000FF
@@ -1909,6 +1927,16 @@ enum {
 #define AR_TXSIFS_ACK_SHIFT    0x00007000
 #define AR_TXSIFS_ACK_SHIFT_S  12
 
+#define AR_BT_COEX_MODE3                       0x81d4
+#define AR_BT_WL_ACTIVE_TIME                   0x000000ff
+#define AR_BT_WL_ACTIVE_TIME_S                 0
+#define AR_BT_WL_QC_TIME                       0x0000ff00
+#define AR_BT_WL_QC_TIME_S                     8
+#define AR_BT_ALLOW_CONCURRENT_ACCESS          0x000f0000
+#define AR_BT_ALLOW_CONCURRENT_ACCESS_S                16
+#define AR_BT_AGC_SATURATION_CNT_ENABLE                0x00100000
+#define AR_BT_AGC_SATURATION_CNT_ENABLE_S      20
+
 #define AR_TXOP_X          0x81ec
 #define AR_TXOP_X_VAL      0x000000FF