arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances

J721E Common Processor Board has PCIe connectors for the 1st three PCIe
instances. Configure the three PCIe instances in RC mode and disable the
4th PCIe instance.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20200914152115.1788-3-kishon@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 648267284582d0a89acb100d5de41987adb5a5c0..f35a5d5b1cd8040c691da98483c0ffdb1bb115f0 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -558,3 +558,83 @@
 
        status = "okay";
 };
+
+&serdes0 {
+       serdes0_pcie_link: link@0 {
+               reg = <0>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz0 1>;
+       };
+};
+
+&serdes1 {
+       serdes1_pcie_link: link@0 {
+               reg = <0>;
+               cdns,num-lanes = <2>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+       };
+};
+
+&serdes2 {
+       serdes2_pcie_link: link@0 {
+               reg = <0>;
+               cdns,num-lanes = <2>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
+       };
+};
+
+&pcie0_rc {
+       reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
+       phys = <&serdes0_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <1>;
+};
+
+&pcie1_rc {
+       reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+       phys = <&serdes1_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <2>;
+};
+
+&pcie2_rc {
+       reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
+       phys = <&serdes2_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <2>;
+};
+
+&pcie0_ep {
+       phys = <&serdes0_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <1>;
+       status = "disabled";
+};
+
+&pcie1_ep {
+       phys = <&serdes1_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <2>;
+       status = "disabled";
+};
+
+&pcie2_ep {
+       phys = <&serdes2_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <2>;
+       status = "disabled";
+};
+
+&pcie3_rc {
+       status = "disabled";
+};
+
+&pcie3_ep {
+       status = "disabled";
+};