drm/i915/gtt: Disable read-only support under GVT

GVT is not propagating the PTE bits, and is always setting the
read-write bit, thus breaking read-only support.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Reviewed-by: Jon Bloomfield <jon.bloomfield@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180712185315.3288-3-chris@chris-wilson.co.uk
CVE-2019-0155

(backported from commit c9e666880de5a1fed04dc412b046916d542b72dd)
[tyhicks: Backport to 4.15
 - ggtt.vm is ggtt.base
 - Pass dev_priv as the argument to intel_vgpu_active()]
Signed-off-by: Tyler Hicks <tyhicks@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a4f3964840dcbf1891868ec372f41110fb14080a..430b4bf70469afe7e9ed138feb2e939bf2835bc2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1575,8 +1575,12 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
                1ULL << 48 :
                1ULL << 32;
 
-       /* From bdw, there is support for read-only pages in the PPGTT */
-       ppgtt->base.has_read_only = true;
+       /*
+        * From bdw, there is support for read-only pages in the PPGTT.
+        *
+        * XXX GVT is not honouring the lack of RW in the PTE bits.
+        */
+       ppgtt->base.has_read_only = !intel_vgpu_active(dev_priv);
 
        /* There are only few exceptions for gen >=6. chv and bxt.
         * And we are not sure about the latter so play safe for now.