drm/i915/icl: WaCL2SFHalfMaxAlloc

This workarounds an issue with insufficient storage for the
CL2 and SF units.

v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
v6:
  - Rebased
  - s/MACALLOC/MAXALLOC (Mika)
  - C, not lisp (Chris)

References: HSDES#1405766107
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-8-git-send-email-oscar.mateo@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a7bd739fde8231d19a043ed6c7cc7847dfe32865..d325fad480f0c5647470b2271f5ff7bd3b4c071d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8269,6 +8269,10 @@ enum {
 #define   GEN11_HASH_CTRL_BIT0                 (1 << 0)
 #define   GEN11_HASH_CTRL_BIT4                 (1 << 12)
 
+#define GEN11_LSN_UNSLCVC                              _MMIO(0xB43C)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC     (1 << 9)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC      (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)         _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK     (0x7ff<<14)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 7e8bcc2ae091625db3bd1b36427d9044fc88c48b..a6758bdd74dd0199368915b5cd6bb6fee0cfbeaf 100644 (file)
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -726,6 +726,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
         */
        I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
                                   GEN11_LQSC_CLEAN_EVICT_DISABLE);
+
+       /* Wa_1405766107:icl
+        * Formerly known as WaCL2SFHalfMaxAlloc
+        */
+       I915_WRITE(GEN11_LSN_UNSLCVC, I915_READ(GEN11_LSN_UNSLCVC) |
+                                     GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+                                     GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)