/* PCI configuration space */
s->pci_config_handler.read = apb_pci_config_read;
s->pci_config_handler.write = apb_pci_config_write;
- pci_config = cpu_register_io_memory_simple(&s->pci_config_handler);
+ pci_config = cpu_register_io_memory_simple(&s->pci_config_handler,
+ DEVICE_NATIVE_ENDIAN);
assert(pci_config >= 0);
/* at region 1 */
sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
{
pci_host_init(s);
if (swap) {
- return cpu_register_io_memory_simple(&s->conf_handler);
+ return cpu_register_io_memory_simple(&s->conf_handler,
+ DEVICE_NATIVE_ENDIAN);
} else {
- return cpu_register_io_memory_simple(&s->conf_noswap_handler);
+ return cpu_register_io_memory_simple(&s->conf_noswap_handler,
+ DEVICE_NATIVE_ENDIAN);
}
}
{
pci_host_init(s);
if (swap) {
- return cpu_register_io_memory_simple(&s->data_handler);
+ return cpu_register_io_memory_simple(&s->data_handler,
+ DEVICE_NATIVE_ENDIAN);
} else {
- return cpu_register_io_memory_simple(&s->data_noswap_handler);
+ return cpu_register_io_memory_simple(&s->data_noswap_handler,
+ DEVICE_NATIVE_ENDIAN);
}
}
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
s->data_handler.read = unin_data_read;
s->data_handler.write = unin_data_write;
- pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
+ pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
s->data_handler.read = unin_data_read;
s->data_handler.write = unin_data_write;
- pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
+ pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
&cpu_io_memory_simple_readl,
};
-int cpu_register_io_memory_simple(struct ReadWriteHandler *handler)
+int cpu_register_io_memory_simple(struct ReadWriteHandler *handler, int endian)
{
if (!handler->read || !handler->write) {
return -1;
}
return cpu_register_io_memory(cpu_io_memory_simple_read,
cpu_io_memory_simple_write,
- handler, DEVICE_NATIVE_ENDIAN);
+ handler, endian);
}
RWHANDLER_WRITE(ioport_simple_writeb, 1, uint32_t);
/* Helpers for when we want to use a single routine with length. */
/* CPU memory handler: both read and write must be present. */
-int cpu_register_io_memory_simple(ReadWriteHandler *);
+int cpu_register_io_memory_simple(ReadWriteHandler *, int endian);
/* io port handler: can supply only read or write handlers. */
int register_ioport_simple(ReadWriteHandler *,
pio_addr_t start, int length, int size);