drm/amd/display: Driver message to SMU to indicate display off

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f41f15faf0195f55be81d226c21866b58a0463b9..47f16a4b9f27146cc43fe97681683a2e2a8f3bc5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -763,7 +763,7 @@ static bool dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
        if (!dcb->funcs->is_accelerated_mode(dcb))
                dc->hwss.enable_accelerated_mode(dc);
 
-       dc->hwss.ready_shared_resources(dc);
+       dc->hwss.ready_shared_resources(dc, context);
 
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
                pipe = &context->res_ctx.pipe_ctx[i];

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index de154329b04931dfdc0b7e9b33ee44248e504717..b3448a41718e0a28df8d313ed40bb890d4be6088 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1889,6 +1889,7 @@ enum dc_status dce110_apply_ctx_to_hw(
                        return status;
        }
 
+       /* pplib is notified if disp_num changed */
        dc->hwss.set_bandwidth(dc, context, true);
 
        /* to save power */
@@ -2683,7 +2684,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
        }
 }
 
-static void ready_shared_resources(struct dc *dc) {}
+static void ready_shared_resources(struct dc *dc, struct dc_state *context) {}
 
 static void optimize_shared_resources(struct dc *dc) {}
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d3fee15aeb7937015db34813e3eb4fc8d39be7af..e60be00abcf231a39521b0f85868a09c86a669d2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -802,18 +802,14 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc)
                        IP_REQUEST_EN, 0);
 }
 
-static void ready_shared_resources(struct dc *dc)
-{
-       if (dc->current_state->stream_count == 0 &&
-                       !dc->debug.disable_stutter)
-               undo_DEGVIDCN10_253_wa(dc);
-}
-
 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 {
        struct dce_hwseq *hws = dc->hwseq;
        struct mem_input *mi = dc->res_pool->mis[0];
 
+       if (dc->debug.disable_stutter)
+               return;
+
        REG_SET(DC_IP_REQUEST_CNTL, 0,
                        IP_REQUEST_EN, 1);
 
@@ -824,13 +820,6 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
        mi->funcs->set_hubp_blank_en(mi, false);
 }
 
-static void optimize_shared_resources(struct dc *dc)
-{
-       if (dc->current_state->stream_count == 0 &&
-                       !dc->debug.disable_stutter)
-               apply_DEGVIDCN10_253_wa(dc);
-}
-
 static void bios_golden_init(struct dc *dc)
 {
        struct dc_bios *bp = dc->ctx->dc_bios;
@@ -2445,6 +2434,27 @@ static void dcn10_pplib_apply_display_requirements(
        dc->prev_display_config = *pp_display_cfg;
 }
 
+static void optimize_shared_resources(struct dc *dc)
+{
+       if (dc->current_state->stream_count == 0) {
+               apply_DEGVIDCN10_253_wa(dc);
+               /* S0i2 message */
+               dcn10_pplib_apply_display_requirements(dc, dc->current_state);
+       }
+}
+
+static void ready_shared_resources(struct dc *dc, struct dc_state *context)
+{
+       if (dc->current_state->stream_count == 0 &&
+                       !dc->debug.disable_stutter)
+               undo_DEGVIDCN10_253_wa(dc);
+
+       /* S0i2 message */
+       if (dc->current_state->stream_count == 0 &&
+                       context->stream_count != 0)
+               dcn10_pplib_apply_display_requirements(dc, context);
+}
+
 static void dcn10_apply_ctx_for_surface(
                struct dc *dc,
                const struct dc_stream_state *stream,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index aae7629b1c08da1c87d75494a2ee94860fe0ea15..1fa2edc6cfb19d4d380d725145b545fb3c48a494 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -174,7 +174,7 @@ struct hw_sequencer_funcs {
                        struct resource_pool *res_pool,
                        struct pipe_ctx *pipe_ctx);
 
-       void (*ready_shared_resources)(struct dc *dc);
+       void (*ready_shared_resources)(struct dc *dc, struct dc_state *context);
        void (*optimize_shared_resources)(struct dc *dc);
 };