static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
{
struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
- uint32_t scratch, tmp = 0;
uint64_t queue_mask = 0;
int r, i;
queue_mask |= (1ull << i);
}
- r = amdgpu_gfx_scratch_get(adev, &scratch);
- if (r) {
- DRM_ERROR("Failed to get scratch reg (%d).\n", r);
- return r;
- }
- WREG32(scratch, 0xCAFEDEAD);
-
- r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 11);
+ kiq_ring->ready = true;
+ r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8);
if (r) {
DRM_ERROR("Failed to lock KIQ (%d).\n", r);
- amdgpu_gfx_scratch_free(adev, scratch);
return r;
}
/* set resources */
amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
}
- /* write to scratch for completion */
- amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
- amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
- amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
- amdgpu_ring_commit(kiq_ring);
- for (i = 0; i < adev->usec_timeout; i++) {
- tmp = RREG32(scratch);
- if (tmp == 0xDEADBEEF)
- break;
- DRM_UDELAY(1);
- }
- if (i >= adev->usec_timeout) {
- DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
- scratch, tmp);
- r = -EINVAL;
+ r = amdgpu_ring_test_ring(kiq_ring);
+ if (r) {
+ DRM_ERROR("KCQ enable failed\n");
+ kiq_ring->ready = false;
}
- amdgpu_gfx_scratch_free(adev, scratch);
-
return r;
}
if (r)
goto done;
- /* Test KIQ */
- ring = &adev->gfx.kiq.ring;
- ring->ready = true;
- r = amdgpu_ring_test_ring(ring);
- if (r) {
- ring->ready = false;
- goto done;
- }
-
/* Test KCQs */
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i];
static int gfx_v8_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
{
- struct amdgpu_device *adev = kiq_ring->adev;
- uint32_t scratch, tmp = 0;
- int r, i;
-
- r = amdgpu_gfx_scratch_get(adev, &scratch);
- if (r) {
- DRM_ERROR("Failed to get scratch reg (%d).\n", r);
- return r;
- }
- WREG32(scratch, 0xCAFEDEAD);
+ int r;
- r = amdgpu_ring_alloc(kiq_ring, 10);
- if (r) {
+ r = amdgpu_ring_alloc(kiq_ring, 6);
+ if (r)
DRM_ERROR("Failed to lock KIQ (%d).\n", r);
- amdgpu_gfx_scratch_free(adev, scratch);
- return r;
- }
/* unmap queues */
amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
amdgpu_ring_write(kiq_ring, 0);
amdgpu_ring_write(kiq_ring, 0);
amdgpu_ring_write(kiq_ring, 0);
- /* write to scratch for completion */
- amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
- amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
- amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
- amdgpu_ring_commit(kiq_ring);
- for (i = 0; i < adev->usec_timeout; i++) {
- tmp = RREG32(scratch);
- if (tmp == 0xDEADBEEF)
- break;
- DRM_UDELAY(1);
- }
- if (i >= adev->usec_timeout) {
- DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
- r = -EINVAL;
- }
- amdgpu_gfx_scratch_free(adev, scratch);
+ r = amdgpu_ring_test_ring(kiq_ring);
+ if (r)
+ DRM_ERROR("KCQ disable failed\n");
+
return r;
}