/* ACCESS_FBINFO(capable.cfb4) = 0; ... preinitialized by 0 */
ACCESS_FBINFO(capable.text) = 1;
ACCESS_FBINFO(capable.vxres) = vxres_mystique;
- ACCESS_FBINFO(features.accel.has_cacheflush) = 1;
ACCESS_FBINFO(outputs[0]).output = &m1064;
ACCESS_FBINFO(outputs[0]).src = ACCESS_FBINFO(outputs[0]).default_src;
/* ACCESS_FBINFO(capable.cfb4) = 0; ... preinitialized by 0 */
ACCESS_FBINFO(capable.text) = 1;
ACCESS_FBINFO(capable.vxres) = vxres_g100;
- ACCESS_FBINFO(features.accel.has_cacheflush) = 1;
ACCESS_FBINFO(capable.plnwt) = ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG100
? ACCESS_FBINFO(devflags.sgram) : 1;
vaddr_t vm;
unsigned int offs;
unsigned int offs2;
- unsigned char store, orig;
+ unsigned char orig;
unsigned char bytes[32];
unsigned char* tmp;
orig = mga_inb(M_EXTVGA_DATA);
mga_outb(M_EXTVGA_DATA, orig | 0x80);
- store = mga_readb(vm, 0x1234);
tmp = bytes;
for (offs = 0x100000; offs < maxSize; offs += 0x200000)
*tmp++ = mga_readb(vm, offs);
for (offs = 0x100000; offs < maxSize; offs += 0x200000)
mga_writeb(vm, offs, 0x02);
- if (ACCESS_FBINFO(features.accel.has_cacheflush))
- mga_outb(M_CACHEFLUSH, 0x00);
- else
- mga_writeb(vm, 0x1234, 0x99);
+ mga_outb(M_CACHEFLUSH, 0x00);
for (offs = 0x100000; offs < maxSize; offs += 0x200000) {
if (mga_readb(vm, offs) != 0x02)
break;
tmp = bytes;
for (offs2 = 0x100000; offs2 < maxSize; offs2 += 0x200000)
mga_writeb(vm, offs2, *tmp++);
- mga_writeb(vm, 0x1234, store);
mga_outb(M_EXTVGA_INDEX, 0x03);
mga_outb(M_EXTVGA_DATA, orig);
u_int8_t xmiscctrl;
};
-struct matrox_accel_features {
- int has_cacheflush;
-};
-
/* current hardware status */
struct mavenregs {
u_int8_t regs[256];
struct {
struct matrox_pll_features pll;
struct matrox_DAC1064_features DAC1064;
- struct matrox_accel_features accel;
} features;
struct {
spinlock_t DAC;