drm/amd/display: Refactor SDR cursor boosting in HDR mode

[Why]
Cursor boosting is done via CNVC_CUR register which is DPP, not HUBP
Previous commit was implementing it in HUBP functions,
and also breaking diags tests.

[How]
1. Undo original commit as well as Eric's diags test fix, almost completely
2. Move programming to DPP and call via new dc_stream function
3. Also removing cur_rom_en from dpp_cursor_attributes and programming
as part of normal cursor attributes as it depends on cursor color format

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 0223f4867e8d0bf644389182b4dc5627dfe813f5..4717330a42f498aac4aa10a0fa69b5877f35ae50 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -214,6 +214,7 @@ bool dc_stream_set_cursor_attributes(
                }
 
                core_dc->hwss.set_cursor_attribute(pipe_ctx);
+               core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
        }
 
        if (pipe_to_program)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index da787e279319073b3e4244331b4aefc9ef0aa5a6..9cfd7ea845e3ffe31840f06cfaeea056fcc1940d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -500,6 +500,11 @@ struct dc_cursor_attributes {
        union dc_cursor_attribute_flags attribute_flags;
 };
 
+struct dpp_cursor_attributes {
+       int bias;
+       int scale;
+};
+
 /* OPP */
 
 enum dc_color_space {

diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 64eeb440e3d31ed5d050c7ce1daa2923400082b3..cbfe418006cbade10cbfc58313fcfee45d1482f6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -100,6 +100,7 @@ struct dc_stream_state {
 
        struct dc_cursor_attributes cursor_attributes;
        struct dc_cursor_position cursor_position;
+       uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
 
        /* from stream struct */
        struct kref refcount;
@@ -255,6 +256,7 @@ bool dc_stream_set_cursor_position(
        struct dc_stream_state *stream,
        const struct dc_cursor_position *position);
 
+
 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
                                struct dc_stream_state **stream,
                                int num_streams,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index a558efa9b34a45f36982c4344763fb131fa15eef..bf8b68f8db4f7ffab3329b7170906abbbdc42d2d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -459,6 +459,18 @@ void dpp1_set_cursor_position(
 
 }
 
+void dpp1_cnv_set_optional_cursor_attributes(
+               struct dpp *dpp_base,
+               struct dpp_cursor_attributes *attr)
+{
+       struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+
+       if (attr) {
+               REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_BIAS,  attr->bias);
+               REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_SCALE, attr->scale);
+       }
+}
+
 void dpp1_dppclk_control(
                struct dpp *dpp_base,
                bool dppclk_div,
@@ -499,6 +511,7 @@ static const struct dpp_funcs dcn10_dpp_funcs = {
                .dpp_full_bypass                = dpp1_full_bypass,
                .set_cursor_attributes = dpp1_set_cursor_attributes,
                .set_cursor_position = dpp1_set_cursor_position,
+               .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
                .dpp_dppclk_control = dpp1_dppclk_control,
                .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
 };

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index e862cafa6501b78e7601fe9e95ebf7f81b728130..e2889e61b18c682dd796de5b756fb2a1815631a6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -119,6 +119,7 @@
        SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
        SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
        SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
+       SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \
        SRI(DPP_CONTROL, DPP_TOP, id), \
        SRI(CM_HDR_MULT_COEF, CM, id)
 
@@ -324,6 +325,8 @@
        TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
        TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
        TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
+       TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \
+       TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \
        TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
        TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh)
 
@@ -1076,7 +1079,9 @@
        type CUR0_COLOR1; \
        type DPPCLK_RATE_CONTROL; \
        type DPP_CLOCK_ENABLE; \
-       type CM_HDR_MULT_COEF;
+       type CM_HDR_MULT_COEF; \
+       type CUR0_FP_BIAS; \
+       type CUR0_FP_SCALE;
 
 struct dcn_dpp_shift {
        TF_REG_FIELD_LIST(uint8_t)
@@ -1329,7 +1334,8 @@ struct dcn_dpp_mask {
        uint32_t CURSOR0_COLOR0; \
        uint32_t CURSOR0_COLOR1; \
        uint32_t DPP_CONTROL; \
-       uint32_t CM_HDR_MULT_COEF;
+       uint32_t CM_HDR_MULT_COEF; \
+       uint32_t CURSOR0_FP_SCALE_BIAS;
 
 struct dcn_dpp_registers {
        DPP_COMMON_REG_VARIABLE_LIST
@@ -1370,6 +1376,10 @@ void dpp1_set_cursor_position(
                const struct dc_cursor_mi_param *param,
                uint32_t width);
 
+void dpp1_cnv_set_optional_cursor_attributes(
+                       struct dpp *dpp_base,
+                       struct dpp_cursor_attributes *attr);
+
 bool dpp1_dscl_is_lb_conf_valid(
                int ceil_vratio,
                int num_partitions,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 5c4ad8a67e62ae20ab7b662f5b8908688ec5ac71..d6dc61ecf4a157090d0062ccd718a4ec6cb51d42 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -27,7 +27,6 @@
 #include "reg_helper.h"
 #include "basics/conversion.h"
 #include "dcn10_hubp.h"
-#include "custom_float.h"
 
 #define REG(reg)\
        hubp1->hubp_regs->reg
@@ -1039,18 +1038,6 @@ void hubp1_cursor_set_attributes(
        enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
        enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk(
                        attr->width, attr->color_format);
-       struct fixed31_32 multiplier;
-       uint32_t hw_mult = 0x3c00; // 1.0 default multiplier
-       struct custom_float_format fmt;
-
-       fmt.exponenta_bits = 5;
-       fmt.mantissa_bits = 10;
-       fmt.sign = true;
-
-       if (attr->sdr_white_level > 80) {
-               multiplier = dc_fixpt_from_fraction(attr->sdr_white_level, 80);
-               convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
-       }
 
        hubp->curs_attr = *attr;
 
@@ -1073,8 +1060,6 @@ void hubp1_cursor_set_attributes(
                        CURSOR0_DST_Y_OFFSET, 0,
                         /* used to shift the cursor chunk request deadline */
                        CURSOR0_CHUNK_HDL_ADJUST, 3);
-
-       REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, hw_mult);
 }
 
 void hubp1_cursor_set_position(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index 9991da50bf29b1d5af0ad11082e0d66b2a89d6a2..f689feace82d189ef1e99a16a955b364c1b61e34 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -133,8 +133,7 @@
        SRI(CURSOR_CONTROL, CURSOR, id), \
        SRI(CURSOR_POSITION, CURSOR, id), \
        SRI(CURSOR_HOT_SPOT, CURSOR, id), \
-       SRI(CURSOR_DST_OFFSET, CURSOR, id), \
-       SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id)
+       SRI(CURSOR_DST_OFFSET, CURSOR, id)
 
 #define HUBP_COMMON_REG_VARIABLE_LIST \
        uint32_t DCHUBP_CNTL; \
@@ -242,8 +241,7 @@
        uint32_t CURSOR_POSITION; \
        uint32_t CURSOR_HOT_SPOT; \
        uint32_t CURSOR_DST_OFFSET; \
-       uint32_t HUBP_CLK_CNTL; \
-       uint32_t CURSOR0_FP_SCALE_BIAS
+       uint32_t HUBP_CLK_CNTL
 
 #define HUBP_SF(reg_name, field_name, post_fix)\
        .field_name = reg_name ## __ ## field_name ## post_fix
@@ -426,8 +424,7 @@
        HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
        HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
        HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
-       HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
-       HUBP_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh)
+       HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
 
 #define DCN_HUBP_REG_FIELD_LIST(type) \
        type HUBP_BLANK_EN;\
@@ -618,8 +615,7 @@
        type CURSOR_HOT_SPOT_X; \
        type CURSOR_HOT_SPOT_Y; \
        type CURSOR_DST_X_OFFSET; \
-       type OUTPUT_FP; \
-       type CUR0_FP_SCALE
+       type OUTPUT_FP
 
 struct dcn_mi_registers {
        HUBP_COMMON_REG_VARIABLE_LIST;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 2e145aa663a4a25a81f6bf75a1de001d202eec6a..6e8127cb2e56557995c8ce9ff86da6ffc94069a4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2555,6 +2555,33 @@ static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
                pipe_ctx->plane_res.dpp, attributes->color_format);
 }
 
+static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
+{
+       uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;
+       struct fixed31_32 multiplier;
+       struct dpp_cursor_attributes opt_attr = { 0 };
+       uint32_t hw_scale = 0x3c00; // 1.0 default multiplier
+       struct custom_float_format fmt;
+
+       if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)
+               return;
+
+       fmt.exponenta_bits = 5;
+       fmt.mantissa_bits = 10;
+       fmt.sign = true;
+
+       if (sdr_white_level > 80) {
+               multiplier = dc_fixpt_from_fraction(sdr_white_level, 80);
+               convert_to_custom_float_format(multiplier, &fmt, &hw_scale);
+       }
+
+       opt_attr.scale = hw_scale;
+       opt_attr.bias = 0;
+
+       pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(
+                       pipe_ctx->plane_res.dpp, &opt_attr);
+}
+
 static const struct hw_sequencer_funcs dcn10_funcs = {
        .program_gamut_remap = program_gamut_remap,
        .program_csc_matrix = program_csc_matrix,
@@ -2602,7 +2629,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
        .edp_power_control = hwss_edp_power_control,
        .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
        .set_cursor_position = dcn10_set_cursor_position,
-       .set_cursor_attribute = dcn10_set_cursor_attribute
+       .set_cursor_attribute = dcn10_set_cursor_attribute,
+       .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level
 };
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 582458f028f8479f52951ac1948f3101e2abb8e8..74ad94b0e4f088cd5c0cc14a2fe3d90fcc3fe9b8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -151,6 +151,9 @@ struct dpp_funcs {
        void (*dpp_set_hdr_multiplier)(
                        struct dpp *dpp_base,
                        uint32_t multiplier);
+       void (*set_optional_cursor_attributes)(
+                       struct dpp *dpp_base,
+                       struct dpp_cursor_attributes *attr);
 
        void (*dpp_dppclk_control)(
                        struct dpp *dpp_base,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index c2277d1e195b4544635aa0f218b95884af595c3b..a14ce4de80b264856f73ad20236f5844aa9005c9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -223,6 +223,7 @@ struct hw_sequencer_funcs {
 
        void (*set_cursor_position)(struct pipe_ctx *pipe);
        void (*set_cursor_attribute)(struct pipe_ctx *pipe);
+       void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);
 
 };