]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/commitdiff
rtlwifi: Remove unused defines from driver-specific def.h
authorPriit Laes <plaes@plaes.org>
Mon, 16 Feb 2015 12:59:55 +0000 (14:59 +0200)
committerKalle Valo <kvalo@codeaurora.org>
Tue, 3 Mar 2015 13:30:01 +0000 (15:30 +0200)
HAL_RETRY_LIMIT_*
RESET_DELAY_8185
RT_IBSS_INT_MASKS
RT_AC_INT_MASKS
NUM_OF_*
BT_*,
MAX_{LINES,BYTES}_*,
*_THREE_WIRE
*_QUEUE related

Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
drivers/net/wireless/rtlwifi/rtl8188ee/def.h
drivers/net/wireless/rtlwifi/rtl8192ce/def.h
drivers/net/wireless/rtlwifi/rtl8192de/def.h
drivers/net/wireless/rtlwifi/rtl8192se/def.h
drivers/net/wireless/rtlwifi/rtl8723ae/def.h
drivers/net/wireless/rtlwifi/rtl8821ae/def.h

index d9ea9d0c79a526694210f7f9f46c7e9747a31285..0532b985244445d81f925dfd960950688a95de44 100644 (file)
 #ifndef __RTL92C_DEF_H__
 #define __RTL92C_DEF_H__
 
-#define HAL_RETRY_LIMIT_INFRA                          48
-#define HAL_RETRY_LIMIT_AP_ADHOC                       7
-
-#define RESET_DELAY_8185                               20
-
-#define RT_IBSS_INT_MASKS      (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
-#define RT_AC_INT_MASKS                (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
-
-#define NUM_OF_FIRMWARE_QUEUE                          10
-#define NUM_OF_PAGES_IN_FW                             0x100
-#define NUM_OF_PAGE_IN_FW_QUEUE_BK                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_BE                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_VI                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_VO                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA                   0x0
-#define NUM_OF_PAGE_IN_FW_QUEUE_CMD                    0x0
-#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT                   0x02
-#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH                   0x02
-#define NUM_OF_PAGE_IN_FW_QUEUE_BCN                    0x2
-#define NUM_OF_PAGE_IN_FW_QUEUE_PUB                    0xA1
-
-#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM                 0x026
-#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM                 0x048
-#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM                 0x048
-#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM                 0x026
-#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM                        0x00
-
-#define MAX_LINES_HWCONFIG_TXT                         1000
-#define MAX_BYTES_LINE_HWCONFIG_TXT                    256
-
-#define SW_THREE_WIRE                                  0
-#define HW_THREE_WIRE                                  2
-
-#define BT_DEMO_BOARD                                  0
-#define BT_QA_BOARD                                    1
-#define BT_FPGA                                                2
-
 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE                        0
 #define HAL_PRIME_CHNL_OFFSET_LOWER                    1
 #define HAL_PRIME_CHNL_OFFSET_UPPER                    2
 
-#define MAX_H2C_QUEUE_NUM                              10
-
 #define RX_MPDU_QUEUE                                  0
 #define RX_CMD_QUEUE                                   1
-#define RX_MAX_QUEUE                                   2
-#define AC2QUEUEID(_AC)                                        (_AC)
 
 #define        C2H_RX_CMD_HDR_LEN                              8
 #define        GET_C2H_CMD_CMD_LEN(__prxhdr)                   \
index 9b660df6fd712fd517638723bb0616b17b9df257..690a7a1675e2019c16932e08b4cfa86731e03566 100644 (file)
 #ifndef __RTL92C_DEF_H__
 #define __RTL92C_DEF_H__
 
-#define HAL_RETRY_LIMIT_INFRA                          48
-#define HAL_RETRY_LIMIT_AP_ADHOC                       7
-
 #define        PHY_RSSI_SLID_WIN_MAX                           100
 #define        PHY_LINKQUALITY_SLID_WIN_MAX                    20
 #define        PHY_BEACON_RSSI_SLID_WIN_MAX                    10
 
-#define RESET_DELAY_8185                               20
-
-#define RT_IBSS_INT_MASKS      (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
-#define RT_AC_INT_MASKS                (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
-
-#define NUM_OF_FIRMWARE_QUEUE                          10
-#define NUM_OF_PAGES_IN_FW                             0x100
-#define NUM_OF_PAGE_IN_FW_QUEUE_BK                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_BE                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_VI                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_VO                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA                   0x0
-#define NUM_OF_PAGE_IN_FW_QUEUE_CMD                    0x0
-#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT                   0x02
-#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH                   0x02
-#define NUM_OF_PAGE_IN_FW_QUEUE_BCN                    0x2
-#define NUM_OF_PAGE_IN_FW_QUEUE_PUB                    0xA1
-
-#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM                 0x026
-#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM                 0x048
-#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM                 0x048
-#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM                 0x026
-#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM                        0x00
-
-#define MAX_LINES_HWCONFIG_TXT                         1000
-#define MAX_BYTES_LINE_HWCONFIG_TXT                    256
-
-#define SW_THREE_WIRE                                  0
-#define HW_THREE_WIRE                                  2
-
-#define BT_DEMO_BOARD                                  0
-#define BT_QA_BOARD                                    1
-#define BT_FPGA                                                2
-
 #define RX_SMOOTH_FACTOR                               20
 
 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE                        0
 #define HAL_PRIME_CHNL_OFFSET_LOWER                    1
 #define HAL_PRIME_CHNL_OFFSET_UPPER                    2
 
-#define MAX_H2C_QUEUE_NUM                              10
-
 #define RX_MPDU_QUEUE                                  0
 #define RX_CMD_QUEUE                                   1
-#define RX_MAX_QUEUE                                   2
-#define AC2QUEUEID(_AC)                                        (_AC)
 
 #define        C2H_RX_CMD_HDR_LEN                              8
 #define        GET_C2H_CMD_CMD_LEN(__prxhdr)           \
index 939c905f547fd179c8e1af49b266893bdbc14694..4ca1fe1de1f502c3f16e5534ace040ea16924d59 100644 (file)
 #define RF6052_MAX_REG                                 0x3F
 #define RF6052_MAX_PATH                                        2
 
-#define HAL_RETRY_LIMIT_INFRA                          48
-#define HAL_RETRY_LIMIT_AP_ADHOC                       7
-
 #define        PHY_RSSI_SLID_WIN_MAX                           100
 #define        PHY_LINKQUALITY_SLID_WIN_MAX                    20
 #define        PHY_BEACON_RSSI_SLID_WIN_MAX                    10
 
-#define RESET_DELAY_8185                               20
-
-#define RT_IBSS_INT_MASKS      (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
 #define RT_AC_INT_MASKS                (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
 
-#define NUM_OF_FIRMWARE_QUEUE                          10
-#define NUM_OF_PAGES_IN_FW                             0x100
-#define NUM_OF_PAGE_IN_FW_QUEUE_BK                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_BE                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_VI                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_VO                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA                   0x0
-#define NUM_OF_PAGE_IN_FW_QUEUE_CMD                    0x0
-#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT                   0x02
-#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH                   0x02
-#define NUM_OF_PAGE_IN_FW_QUEUE_BCN                    0x2
-#define NUM_OF_PAGE_IN_FW_QUEUE_PUB                    0xA1
-
-#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM                 0x026
-#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM                 0x048
-#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM                 0x048
-#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM                 0x026
-#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM                        0x00
-
-#define MAX_LINES_HWCONFIG_TXT                         1000
-#define MAX_BYTES_LINE_HWCONFIG_TXT                    256
-
-#define SW_THREE_WIRE                                  0
-#define HW_THREE_WIRE                                  2
-
-#define BT_DEMO_BOARD                                  0
-#define BT_QA_BOARD                                    1
-#define BT_FPGA                                                2
-
 #define RX_SMOOTH_FACTOR                               20
 
 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE                        0
 #define HAL_PRIME_CHNL_OFFSET_LOWER                    1
 #define HAL_PRIME_CHNL_OFFSET_UPPER                    2
 
-#define MAX_H2C_QUEUE_NUM                              10
-
 #define RX_MPDU_QUEUE                                  0
 #define RX_CMD_QUEUE                                   1
-#define RX_MAX_QUEUE                                   2
 
 #define        C2H_RX_CMD_HDR_LEN                              8
 #define        GET_C2H_CMD_CMD_LEN(__prxhdr)                   \
index ef87c09b77d0c877ad10d3beddbc8045f0d9de43..41466f957cdc055b4f00588ab95f1281c8ea2d77 100644 (file)
@@ -31,7 +31,6 @@
 
 #define RX_MPDU_QUEUE                          0
 #define RX_CMD_QUEUE                           1
-#define RX_MAX_QUEUE                           2
 
 #define SHORT_SLOT_TIME                                9
 #define NON_SHORT_SLOT_TIME                    20
index 94bdd4bbca5dfcfb6aa537fd70365180df2dd8bf..bcdf2273688ebad1224e99166036c75c859adfbe 100644 (file)
 #ifndef __RTL8723E_DEF_H__
 #define __RTL8723E_DEF_H__
 
-#define HAL_RETRY_LIMIT_INFRA                          48
-#define HAL_RETRY_LIMIT_AP_ADHOC                       7
-
-#define RESET_DELAY_8185                                       20
-
-#define RT_IBSS_INT_MASKS      (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
-#define RT_AC_INT_MASKS                (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
-
-#define NUM_OF_FIRMWARE_QUEUE                          10
-#define NUM_OF_PAGES_IN_FW                                     0x100
-#define NUM_OF_PAGE_IN_FW_QUEUE_BK                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_BE                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_VI                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_VO                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA           0x0
-#define NUM_OF_PAGE_IN_FW_QUEUE_CMD                    0x0
-#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT           0x02
-#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH           0x02
-#define NUM_OF_PAGE_IN_FW_QUEUE_BCN                    0x2
-#define NUM_OF_PAGE_IN_FW_QUEUE_PUB                    0xA1
-
-#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM         0x026
-#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM         0x048
-#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM         0x048
-#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM         0x026
-#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM                0x00
-
-#define MAX_LINES_HWCONFIG_TXT                         1000
-#define MAX_BYTES_LINE_HWCONFIG_TXT                    256
-
-#define SW_THREE_WIRE                                          0
-#define HW_THREE_WIRE                                          2
-
-#define BT_DEMO_BOARD                                          0
-#define BT_QA_BOARD                                                    1
-#define BT_FPGA                                                                2
-
 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE                0
 #define HAL_PRIME_CHNL_OFFSET_LOWER                    1
 #define HAL_PRIME_CHNL_OFFSET_UPPER                    2
 
-#define MAX_H2C_QUEUE_NUM                                      10
-
 #define RX_MPDU_QUEUE                                          0
 #define RX_CMD_QUEUE                                           1
-#define RX_MAX_QUEUE                                           2
-#define AC2QUEUEID(_AC)                                                (_AC)
 
 #define        C2H_RX_CMD_HDR_LEN                                      8
 #define        GET_C2H_CMD_CMD_LEN(__prxhdr)           \
index ee7c208bd070944850c5f560fcaff58d432e1a18..dfbdf539de1a1fc0b6163543c462082c6301a9c4 100644 (file)
 #define        WIFI_NAV_UPPER_US                               30000
 #define HAL_92C_NAV_UPPER_UNIT                 128
 
-#define HAL_RETRY_LIMIT_INFRA                          48
-#define HAL_RETRY_LIMIT_AP_ADHOC                       7
-
-#define RESET_DELAY_8185                                       20
-
-#define RT_IBSS_INT_MASKS      (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
-#define RT_AC_INT_MASKS                (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
-
-#define NUM_OF_FIRMWARE_QUEUE                          10
-#define NUM_OF_PAGES_IN_FW                                     0x100
-#define NUM_OF_PAGE_IN_FW_QUEUE_BK                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_BE                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_VI                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_VO                     0x07
-#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA           0x0
-#define NUM_OF_PAGE_IN_FW_QUEUE_CMD                    0x0
-#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT           0x02
-#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH           0x02
-#define NUM_OF_PAGE_IN_FW_QUEUE_BCN                    0x2
-#define NUM_OF_PAGE_IN_FW_QUEUE_PUB                    0xA1
-
-#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM         0x026
-#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM         0x048
-#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM         0x048
-#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM         0x026
-#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM                0x00
-
 #define MAX_RX_DMA_BUFFER_SIZE                         0x3E80
 
-#define MAX_LINES_HWCONFIG_TXT                         1000
-#define MAX_BYTES_LINE_HWCONFIG_TXT                    256
-
-#define SW_THREE_WIRE                                          0
-#define HW_THREE_WIRE                                          2
-
-#define BT_DEMO_BOARD                                          0
-#define BT_QA_BOARD                                                    1
-#define BT_FPGA                                                                2
-
 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE                0
 #define HAL_PRIME_CHNL_OFFSET_LOWER                    1
 #define HAL_PRIME_CHNL_OFFSET_UPPER                    2
 
-#define MAX_H2C_QUEUE_NUM                                      10
-
 #define RX_MPDU_QUEUE                                          0
 #define RX_CMD_QUEUE                                           1
-#define RX_MAX_QUEUE                                           2
-#define AC2QUEUEID(_AC)                                                (_AC)
 
 #define MAX_RX_DMA_BUFFER_SIZE_8812    0x3E80