drm/amd/display: fix surface update sequence

An earlier change added update of interdependent dlg/ttu params for pipes
not being updated in the current call. The code fails to check if the other
pipes are actually active yet causing an assert.

This change adds a check for surface presence on the pipes before updating
the interdepenednt params.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e917bdce477acdc6eebd89c80dd3916e438ac615..91e015e143550d9a4b10d8a6249df35db72c6e62 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2357,7 +2357,8 @@ static void dcn10_apply_ctx_for_surface(
                        struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 
                        /* Skip inactive pipes and ones already updated */
-                       if (!pipe_ctx->stream || pipe_ctx->stream == stream)
+                       if (!pipe_ctx->stream || pipe_ctx->stream == stream
+                                       || !pipe_ctx->plane_state)
                                continue;
 
                        pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
@@ -2371,7 +2372,8 @@ static void dcn10_apply_ctx_for_surface(
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 
-               if (!pipe_ctx->stream || pipe_ctx->stream == stream)
+               if (!pipe_ctx->stream || pipe_ctx->stream == stream
+                               || !pipe_ctx->plane_state)
                        continue;
 
                dcn10_pipe_control_lock(dc, pipe_ctx, false);