powerpc: Rewrite FSL_BOOKE flush_cache_instruction() in C

Nothing prevents flush_cache_instruction() from being writen in C.

Do it to improve readability and maintainability.

This function is only use by low level callers, it is not
intended to be used by module. Don't export it.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/f989eff8296800c427622c0985384148404e4f0b.1597384512.git.christophe.leroy@csgroup.eu

diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 9e8f730fe04d4f2ed5395675aa84d09a22a3e774..717e658b90fd845af254e60f3fec065b003dda51 100644 (file)
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -255,28 +255,6 @@ _ASM_NOKPROBE_SYMBOL(real_writeb)
 
 #endif /* CONFIG_40x */
 
-
-/*
- * Flush instruction cache.
- */
-#ifdef CONFIG_FSL_BOOKE
-_GLOBAL(flush_instruction_cache)
-#ifdef CONFIG_E200
-       mfspr   r3,SPRN_L1CSR0
-       ori     r3,r3,L1CSR0_CFI|L1CSR0_CLFC
-       /* msync; isync recommended here */
-       mtspr   SPRN_L1CSR0,r3
-       isync
-       blr
-#endif
-       mfspr   r3,SPRN_L1CSR1
-       ori     r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
-       mtspr   SPRN_L1CSR1,r3
-       isync
-       blr
-EXPORT_SYMBOL(flush_instruction_cache)
-#endif
-
 /*
  * Copy a whole page.  We use the dcbz instruction on the destination
  * to reduce memory traffic (it eliminates the unnecessary reads of

diff --git a/arch/powerpc/mm/nohash/fsl_booke.c b/arch/powerpc/mm/nohash/fsl_booke.c
index 0c294827d6e51942e2e84400438eb8f4783f12a4..36bda962d3b335ac98463416f3385acd01454714 100644 (file)
--- a/arch/powerpc/mm/nohash/fsl_booke.c
+++ b/arch/powerpc/mm/nohash/fsl_booke.c
@@ -219,6 +219,22 @@ unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
        return tlbcam_addrs[tlbcam_index - 1].limit - PAGE_OFFSET + 1;
 }
 
+void flush_instruction_cache(void)
+{
+       unsigned long tmp;
+
+       if (IS_ENABLED(CONFIG_E200)) {
+               tmp = mfspr(SPRN_L1CSR0);
+               tmp |= L1CSR0_CFI | L1CSR0_CLFC;
+               mtspr(SPRN_L1CSR0, tmp);
+       } else {
+               tmp = mfspr(SPRN_L1CSR1);
+               tmp |= L1CSR1_ICFI | L1CSR1_ICLFR;
+               mtspr(SPRN_L1CSR1, tmp);
+       }
+       isync();
+}
+
 /*
  * MMU_init_hw does the chip-specific initialization of the MMU hardware.
  */