net: mvpp2: fix the number of queues per cpu for PPv2.2

The Marvell PPv2.2 engine only has 8 Rx queues per CPU, while PPv2.1 has
16 of them. This patch updates the code so that the Rx queues mask width
is selected given the version of the network controller used.

Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 43f9d8372b285478bd0fdbbe88aad9d9c2aa9a5e..014e3343b660797ec5e5fcf59f6652ffb7edcc51 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -253,7 +253,8 @@
 #define     MVPP2_ISR_ENABLE_INTERRUPT(mask)   ((mask) & 0xffff)
 #define     MVPP2_ISR_DISABLE_INTERRUPT(mask)  (((mask) << 16) & 0xffff0000)
 #define MVPP2_ISR_RX_TX_CAUSE_REG(port)                (0x5480 + 4 * (port))
-#define     MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK        0xffff
+#define     MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(version) \
+                                       ((version) == MVPP21 ? 0xffff : 0xff)
 #define     MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK        0xff0000
 #define     MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET      16
 #define     MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK   BIT(24)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index fdd463a080d5e30fdfce517eb0f28f371e9579f0..e91b4f02dd48e299edb48e461e0c8dde12f5fd63 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -908,7 +908,7 @@ static void mvpp2_interrupts_unmask(void *arg)
        u32 val;
 
        val = MVPP2_CAUSE_MISC_SUM_MASK |
-               MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
+               MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
        if (port->has_tx_irqs)
                val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
 
@@ -928,7 +928,7 @@ mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
        if (mask)
                val = 0;
        else
-               val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
+               val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
 
        for (i = 0; i < port->nqvecs; i++) {
                struct mvpp2_queue_vector *v = port->qvecs + i;
@@ -3062,7 +3062,8 @@ static int mvpp2_poll(struct napi_struct *napi, int budget)
        }
 
        /* Process RX packets */
-       cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
+       cause_rx = cause_rx_tx &
+                  MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
        cause_rx <<= qv->first_rxq;
        cause_rx |= qv->pending_cause_rx;
        while (cause_rx && budget > 0) {