drm/amd/display: separate out wm change request dcn workaround

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index 63b75ac4a1d520c2801b2532d79b14aad3c2da9b..623db09389b5c5082dd8a487e7307779b6302e54 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -190,6 +190,12 @@ static uint32_t convert_and_clamp(
 }
 
 
+void hubbub1_wm_change_req_wa(struct hubbub *hubbub)
+{
+       REG_UPDATE_SEQ(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+                       DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0, 1);
+}
+
 void hubbub1_program_watermarks(
                struct hubbub *hubbub,
                struct dcn_watermark_set *watermarks,
@@ -203,8 +209,6 @@ void hubbub1_program_watermarks(
         */
        uint32_t prog_wm_value;
 
-       REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
-                       DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
 
        /* Repeat for water mark set A, B, C and D. */
        /* clock state A */
@@ -459,9 +463,6 @@ void hubbub1_program_watermarks(
                        watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
        }
 
-       REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
-                       DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
-
        REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
                        DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
        REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index 0ca39cb71968d2dea573702252006e9e865ed256..d6e596eef4c5523b03f0b98e36583108c5819986 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -195,6 +195,8 @@ void hubbub1_update_dchub(
 bool hubbub1_verify_allow_pstate_change_high(
        struct hubbub *hubbub);
 
+void hubbub1_wm_change_req_wa(struct hubbub *hubbub);
+
 void hubbub1_program_watermarks(
                struct hubbub *hubbub,
                struct dcn_watermark_set *watermarks,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index cc12c4757f8b67560bf3cffeac2fc5a11f6eedea..378bb19b98de2e91c1b162c5563f71f98ee02a20 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2305,6 +2305,9 @@ static void dcn10_apply_ctx_for_surface(
                hubbub1_program_watermarks(dc->res_pool->hubbub,
                                &context->bw.dcn.watermarks, ref_clk_mhz, true);
 
+               if (dc->hwseq->wa.DEGVIDCN10_254)
+                       hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
+
                if (dc->debug.sanity_checks) {
                        /* pstate stuck check after watermark update */
                        dcn10_verify_allow_pstate_change_high(dc);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 2db08b99db561d8f109f8a5e83b32144d349892f..68be66eabc40230ee502067578c8cc94ea747041 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -743,6 +743,7 @@ static struct dce_hwseq *dcn10_hwseq_create(
                hws->masks = &hwseq_mask;
                hws->wa.DEGVIDCN10_253 = true;
                hws->wa.false_optc_underflow = true;
+               hws->wa.DEGVIDCN10_254 = true;
        }
        return hws;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index a71770ed4b9f6ca52de5a9981ccf82dfa29b2674..1c94dae6bbde6ff8cf570d0815e43c9bf0ff0266 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -44,6 +44,7 @@ struct dce_hwseq_wa {
        bool blnd_crtc_trigger;
        bool DEGVIDCN10_253;
        bool false_optc_underflow;
+       bool DEGVIDCN10_254;
 };
 
 struct hwseq_wa_state {