drm/i915/icl:Add Wa_1606682166

Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
Disable the Sampler state prefetch functionality in the SARB by
programming 0xB000[30] to '1'. This is to be done at boot time
and the feature must remain disabled permanently.

Fixes flaky tex-mip-level-selection* piglit tests with Mesa i965
driver.

Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181004182939.7668-6-radhakrishna.sripada@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c7e75f81bd70fd67fb7cb7ec31cd2ae08647bba0..20785417953d187d74ccde37de00440984f05c4b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7414,6 +7414,7 @@ enum {
 
 #define GEN7_SARCHKMD                          _MMIO(0xB000)
 #define GEN7_DISABLE_DEMAND_PREFETCH           (1 << 31)
+#define GEN7_DISABLE_SAMPLER_PREFETCH           (1 << 30)
 
 #define GEN7_L3SQCREG1                         _MMIO(0xB010)
 #define  VLV_B0_WA_L3SQCREG1_VALUE             0x00D30000

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index b298f53c99d4733bb3062e23a917c5aa2d64b807..e4136590fed9b2975bed7742eb1611c5a1521d5d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -910,7 +910,8 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
        if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
                I915_WRITE(GEN7_SARCHKMD,
                           I915_READ(GEN7_SARCHKMD) |
-                          GEN7_DISABLE_DEMAND_PREFETCH);
+                          GEN7_DISABLE_DEMAND_PREFETCH |
+                          GEN7_DISABLE_SAMPLER_PREFETCH);
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)