ARM: dts: meson8b: ec100: enable the SDHC controller

EC-100 has built-in eMMC flash which is hard-wired to 3.3V VCC (which
means it's limited to high-speed MMC modes). Enable the SDHC controller
to access the contents of the eMMC flash.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200620163654.37207-3-martin.blumenstingl@googlemail.com

diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
index 163a200d5a7b63afdbf742f47eb571aa6c21b717..ed06102a4014081a2ca144f5d02b0a9aa423eeae 100644 (file)
--- a/arch/arm/boot/dts/meson8b-ec100.dts
+++ b/arch/arm/boot/dts/meson8b-ec100.dts
@@ -27,6 +27,11 @@
                reg = <0x40000000 0x40000000>;
        };
 
+       emmc_pwrseq: emmc-pwrseq {
+               compatible = "mmc-pwrseq-emmc";
+               reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+       };
+
        gpio-keys {
                compatible = "gpio-keys-polled";
                #address-cells = <1>;
@@ -299,6 +304,26 @@
        vref-supply = <&vcc_1v8>;
 };
 
+&sdhc {
+       status = "okay";
+
+       pinctrl-0 = <&sdxc_c_pins>;
+       pinctrl-names = "default";
+
+       bus-width = <8>;
+       max-frequency = <50000000>;
+
+       cap-mmc-highspeed;
+       disable-wp;
+       non-removable;
+       no-sdio;
+
+       mmc-pwrseq = <&emmc_pwrseq>;
+
+       vmmc-supply = <&vcc_3v3>;
+       vqmmc-supply = <&vcc_3v3>;
+};
+
 &sdio {
        status = "okay";