PCI: aardvark: Clear all MSIs at setup

BugLink: https://bugs.launchpad.net/bugs/1978240
commit 7d8dc1f7cd007a7ce94c5b4c20d63a8b8d6d7751 upstream.

We already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT).

Define a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs,
to ensure that we don't start receiving spurious interrupts.

Use this new mask in advk_pcie_handle_msi();

Link: https://lore.kernel.org/r/20211130172913.9727-5-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 708734afc254abc00c9ade81ff001c3a243758b3..0d02ae8bb4a6db68579d4f7e5a5eb23398d092da 100644 (file)
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -115,6 +115,7 @@
 #define PCIE_MSI_ADDR_HIGH_REG                 (CONTROL_BASE_ADDR + 0x54)
 #define PCIE_MSI_STATUS_REG                    (CONTROL_BASE_ADDR + 0x58)
 #define PCIE_MSI_MASK_REG                      (CONTROL_BASE_ADDR + 0x5C)
+#define     PCIE_MSI_ALL_MASK                  GENMASK(31, 0)
 #define PCIE_MSI_PAYLOAD_REG                   (CONTROL_BASE_ADDR + 0x9C)
 #define     PCIE_MSI_DATA_MASK                 GENMASK(15, 0)
 
@@ -570,6 +571,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
        advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
 
        /* Clear all interrupts */
+       advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
        advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
        advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
        advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
@@ -582,7 +584,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
        advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
 
        /* Unmask all MSIs */
-       advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
+       advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
 
        /* Enable summary interrupt for GIC SPI source */
        reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
@@ -1389,7 +1391,7 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
 
        msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
        msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
-       msi_status = msi_val & ~msi_mask;
+       msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);
 
        for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
                if (!(BIT(msi_idx) & msi_status))