drm/i915/icl: track dbuf slice-2 status

This patch adds support to start tracking status of DBUF slices.
This is foundation to introduce support for enabling/disabling second
DBUF slice dynamically for ICL.

Changes Since V1:
 - use kernel type u8 over uint8_t

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180426142517.16643-2-mahesh1.kumar@intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8444ca8d5aa305f22a32e240cd6cc01cf92c9166..193176bcddf5fcc7e6f43f6cb1a9716487fb4b0a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1189,6 +1189,7 @@ struct skl_ddb_allocation {
        /* packed/y */
        struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
        struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
+       u8 enabled_slices; /* GEN11 has configurable 2 slices */
 };
 
 struct skl_ddb_values {

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index efa8822f63d10f1bd394f5a73a76387eec00166c..338570e61a1f8e4628ff43886edcbdc6c0693563 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11447,6 +11447,11 @@ static void verify_wm_state(struct drm_crtc *crtc,
        skl_ddb_get_hw_state(dev_priv, &hw_ddb);
        sw_ddb = &dev_priv->wm.skl_hw.ddb;
 
+       if (INTEL_GEN(dev_priv) >= 11)
+               if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)
+                       DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
+                                 sw_ddb->enabled_slices,
+                                 hw_ddb.enabled_slices);
        /* planes */
        for_each_universal_plane(dev_priv, pipe, plane) {
                hw_plane_wm = &hw_wm.planes[plane];

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4baab858e4427e9139e6fce33b0da6ab61224d62..a29e6d512771f1fd252802ecfc6d77dabec56798 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3567,6 +3567,23 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
        return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
+static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
+{
+       u8 enabled_slices;
+
+       /* Slice 1 will always be enabled */
+       enabled_slices = 1;
+
+       /* Gen prior to GEN11 have only one DBuf slice */
+       if (INTEL_GEN(dev_priv) < 11)
+               return enabled_slices;
+
+       if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
+               enabled_slices++;
+
+       return enabled_slices;
+}
+
 /*
  * FIXME: We still don't have the proper code detect if we need to apply the WA,
  * so assume we'll always need it in order to avoid underruns.
@@ -3870,6 +3887,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 
        memset(ddb, 0, sizeof(*ddb));
 
+       ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+
        for_each_intel_crtc(&dev_priv->drm, crtc) {
                enum intel_display_power_domain power_domain;
                enum plane_id plane_id;
@@ -5088,6 +5107,7 @@ skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
               sizeof(dst->ddb.uv_plane[pipe]));
        memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
               sizeof(dst->ddb.plane[pipe]));
+       dst->ddb.enabled_slices = src->ddb.enabled_slices;
 }
 
 static void

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ec59992cf87a55ef35c0fb22a4c733d8c9b4d3f3..afc6ef81ca0c1c0f1e3d30f3f367023d7ee8b536 100644 (file)
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2656,6 +2656,8 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
        if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
            !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
                DRM_ERROR("DBuf power enable timeout\n");
+       else
+               dev_priv->wm.skl_hw.ddb.enabled_slices = 2;
 }
 
 static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
@@ -2669,6 +2671,8 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
        if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
            (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
                DRM_ERROR("DBuf power disable timeout!\n");
+       else
+               dev_priv->wm.skl_hw.ddb.enabled_slices = 0;
 }
 
 static void icl_mbus_init(struct drm_i915_private *dev_priv)