drm/i915: fix DP AUX register definitions on Haswell

The old rule that the AUX registers are just an offset (+4 and +10)
from output_reg is not true anymore, since output_reg in on the CPU
and some AUX regs are on the PCH.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: use the existing #defines as spotted by Damien Lespiau.]
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 57dbb49ff5c5ef88ba714128f058050f5417dfee..07208bcea77cb247d5622cc36c53eada061ccb66 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -356,6 +356,29 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
        uint32_t aux_clock_divider;
        int try, precharge;
 
+       if (IS_HASWELL(dev)) {
+               switch (intel_dp->port) {
+               case PORT_A:
+                       ch_ctl = DPA_AUX_CH_CTL;
+                       ch_data = DPA_AUX_CH_DATA1;
+                       break;
+               case PORT_B:
+                       ch_ctl = PCH_DPB_AUX_CH_CTL;
+                       ch_data = PCH_DPB_AUX_CH_DATA1;
+                       break;
+               case PORT_C:
+                       ch_ctl = PCH_DPC_AUX_CH_CTL;
+                       ch_data = PCH_DPC_AUX_CH_DATA1;
+                       break;
+               case PORT_D:
+                       ch_ctl = PCH_DPD_AUX_CH_CTL;
+                       ch_data = PCH_DPD_AUX_CH_DATA1;
+                       break;
+               default:
+                       BUG();
+               }
+       }
+
        intel_dp_check_edp(intel_dp);
        /* The clock divider is based off the hrawclk,
         * and would like to run at 2MHz. So, take the