drm/amdgpu: Don't write GCVM_L2_CNTL* regs on navi12 VF

This change disables programming of GCVM_L2_CNTL* regs on VF.

Signed-off-by: Rohit Khaire <Rohit.Khaire@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index b70c7b483c247eae52ca8f68aa03352a351e27c6..e0654a216ab5cb471f253cb00f740524fc66924e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -135,6 +135,10 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
 {
        uint32_t tmp;
 
+       /* These regs are not accessible for VF, PF will program these in SRIOV */
+       if (amdgpu_sriov_vf(adev))
+               return;
+
        /* Setup L2 cache */
        tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
        tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -298,9 +302,11 @@ void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)
                            ENABLE_ADVANCED_DRIVER_MODEL, 0);
        WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
 
-       /* Setup L2 cache */
-       WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
-       WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
+       if (!amdgpu_sriov_vf(adev)) {
+               /* Setup L2 cache */
+               WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
+               WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
+       }
 }
 
 /**