ARM: dts: sunxi: Use macros for references to CCU clocks

A few clocks from the CCU were exported later, and references to them in
the device tree were using raw numbers.

Now that the DT binding header changes are in as well, switch to the
macros for more clarity.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 9f0b645fd45e2eef9a31695fbe05e427cf224b5f..0b526e6e5a95b05c624bca0078627ae621e581ee 100644 (file)
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -185,7 +185,7 @@
                mbus: dram-controller@1c01000 {
                        compatible = "allwinner,sun5i-a13-mbus";
                        reg = <0x01c01000 0x1000>;
-                       clocks = <&ccu 99>;
+                       clocks = <&ccu CLK_MBUS>;
                        dma-ranges = <0x00000000 0x40000000 0x20000000>;
                        #interconnect-cells = <1>;
                };

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 93a6df11cb189c2c9e9c35f0c421cc4798580ce8..74ac7ee9383cf89ca1d60e543332ab8c71748722 100644 (file)
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1006,9 +1006,9 @@
                        reg = <0x01c30000 0x104>;
                        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "macirq";
-                       resets = <&ccu 13>;
+                       resets = <&ccu CLK_BUS_EMAC>;
                        reset-names = "stmmaceth";
-                       clocks = <&ccu 27>;
+                       clocks = <&ccu RST_BUS_EMAC>;
                        clock-names = "stmmaceth";
                        status = "disabled";
 
@@ -1102,7 +1102,7 @@
                        compatible = "allwinner,sun8i-a83t-r-ccu";
                        reg = <0x01f01400 0x400>;
                        clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
-                                <&ccu 6>;
+                                <&ccu CLK_PLL_PERIPH>;
                        clock-names = "hosc", "losc", "iosc", "pll-periph";
                        #clock-cells = <1>;
                        #reset-cells = <1>;

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 13668a16353dcdbd4e96987d7f7d875d54365bf0..8f09a24b36ec080e5823fe7768a3b4eae7722742 100644 (file)
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -995,7 +995,7 @@
                        compatible = "allwinner,sun8i-r40-hdmi-phy";
                        reg = <0x01ef0000 0x10000>;
                        clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
-                                <&ccu 7>, <&ccu 16>;
+                                <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
                        clock-names = "bus", "mod", "pll-0", "pll-1";
                        resets = <&ccu RST_BUS_HDMI0>;
                        reset-names = "phy";

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 6e68ed8310159d74c9b37c52075911900ce93c6c..5e9c3060aa08baed801cca8b461bd46cef60f4ea 100644 (file)
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -559,7 +559,7 @@
                mbus: dram-controller@1c62000 {
                        compatible = "allwinner,sun8i-h3-mbus";
                        reg = <0x01c62000 0x1000>;
-                       clocks = <&ccu 113>;
+                       clocks = <&ccu CLK_MBUS>;
                        dma-ranges = <0x00000000 0x40000000 0xc0000000>;
                        #interconnect-cells = <1>;
                };
@@ -817,7 +817,7 @@
                        compatible = "allwinner,sun8i-h3-hdmi-phy";
                        reg = <0x01ef0000 0x10000>;
                        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
-                                <&ccu 6>;
+                                <&ccu CLK_PLL_VIDEO>;
                        clock-names = "bus", "mod", "pll-0";
                        resets = <&ccu RST_BUS_HDMI0>;
                        reset-names = "phy";
@@ -837,7 +837,8 @@
                r_ccu: clock@1f01400 {
                        compatible = "allwinner,sun8i-h3-r-ccu";
                        reg = <0x01f01400 0x100>;
-                       clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 9>;
+                       clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
+                                <&ccu CLK_PLL_PERIPH0>;
                        clock-names = "hosc", "losc", "iosc", "pll-periph";
                        #clock-cells = <1>;
                        #reset-cells = <1>;