]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/commitdiff
ARM: dts: imx: specify the value of audmux pinctrl instead of 0x80000000
authorNicolin Chen <b42378@freescale.com>
Sat, 8 Feb 2014 02:14:28 +0000 (10:14 +0800)
committerShawn Guo <shawn.guo@linaro.org>
Sun, 9 Feb 2014 13:29:04 +0000 (21:29 +0800)
We must specify the value of audmux pinctrl if we want to use pinctrl_pm().
Thus change bypass value 0x80000000 to what we exactly need.

This patch also seperately unset PUE bit for TXD so that IOMUX won't pull
up/down the pin after turning into tristate. When we use SSI normal mode to
playback monaural audio via I2S signal, there'd be a pulled curve occur to
its signal at the second slot if setting PUE bit for TXD. And it will make
the second channel to play a constant noise. So by keeping the signal level
in the second slot, we can get a constant high level signal (-1) or a low
level one (0).

Signed-off-by: Nicolin Chen <b42378@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
arch/arm/boot/dts/imx6q-sabrelite.dts
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
arch/arm/boot/dts/imx6qdl-wandboard.dtsi

index 3d7fd795a3fd9d9caf92179799f41b779e634244..7debf6f7d81087f1781423e2603541fed2c62ea7 100644 (file)
 
                pinctrl_audmux: audmuxgrp {
                        fsl,pins = <
-                               MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x80000000
-                               MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x80000000
-                               MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x80000000
-                               MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x80000000
+                               MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
+                               MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
+                               MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
+                               MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
                        >;
                };
 
index cb5c7f08f10b81f5abcb806786df12b6c517b608..5f53a50aad1724adb0be32204428898318bc292d 100644 (file)
 
                pinctrl_audmux: audmuxgrp {
                        fsl,pins = <
-                               MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x80000000
-                               MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x80000000
-                               MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x80000000
-                               MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x80000000
+                               MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
+                               MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
+                               MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
+                               MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
                        >;
                };
 
index 815b160037505aaf6e91f417e552e58d92ff2e8e..81138b70c863049960da65cf786d5745874993ca 100644 (file)
 
                pinctrl_audmux: audmuxgrp {
                        fsl,pins = <
-                               MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x80000000
-                               MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x80000000
-                               MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x80000000
-                               MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x80000000
+                               MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
+                               MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
+                               MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
+                               MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
                        >;
                };