]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/commitdiff
sh_eth: use TSU register accessors for TSU_POST<n>
authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Wed, 2 May 2018 19:54:48 +0000 (22:54 +0300)
committerDavid S. Miller <davem@davemloft.net>
Fri, 4 May 2018 13:11:45 +0000 (09:11 -0400)
There's no particularly good reason TSU_POST<n> registers get accessed
circumventing sh_eth_tsu_{read|write}() -- start using those, removing
(badly named) sh_eth_tsu_get_post_reg_offset(),  while at it...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/renesas/sh_eth.c

index b6b90a6314e31d2d59223c7b57ff8e47d49f66c4..e2e8838fa981a68303875373b9f0f9fe0ad5dca0 100644 (file)
@@ -2610,12 +2610,6 @@ static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
 }
 
 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
-static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
-                                           int entry)
-{
-       return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
-}
-
 static u32 sh_eth_tsu_get_post_mask(int entry)
 {
        return 0x0f << (28 - ((entry % 8) * 4));
@@ -2630,27 +2624,25 @@ static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
                                             int entry)
 {
        struct sh_eth_private *mdp = netdev_priv(ndev);
+       int reg = TSU_POST1 + entry / 8;
        u32 tmp;
-       void *reg_offset;
 
-       reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
-       tmp = ioread32(reg_offset);
-       iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
+       tmp = sh_eth_tsu_read(mdp, reg);
+       sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
 }
 
 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
                                              int entry)
 {
        struct sh_eth_private *mdp = netdev_priv(ndev);
+       int reg = TSU_POST1 + entry / 8;
        u32 post_mask, ref_mask, tmp;
-       void *reg_offset;
 
-       reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
        post_mask = sh_eth_tsu_get_post_mask(entry);
        ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
 
-       tmp = ioread32(reg_offset);
-       iowrite32(tmp & ~post_mask, reg_offset);
+       tmp = sh_eth_tsu_read(mdp, reg);
+       sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
 
        /* If other port enables, the function returns "true" */
        return tmp & ref_mask;