{
int rc = HCF_SUCCESS;
- HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic )
+ HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic );
#if HCF_INT_ON
- HCFLOGENTRY( action == HCF_ACT_INT_FORCE_ON ? HCF_TRACE_ACTION_KLUDGE : HCF_TRACE_ACTION, action ) /* 0 */
+ HCFLOGENTRY( action == HCF_ACT_INT_FORCE_ON ? HCF_TRACE_ACTION_KLUDGE : HCF_TRACE_ACTION, action ); /* 0 */
#if (HCF_SLEEP)
HCFASSERT( ifbp->IFB_IntOffCnt != 0xFFFE || action == HCF_ACT_INT_OFF,
- MERGE_2( action, ifbp->IFB_IntOffCnt ) )
+ MERGE_2( action, ifbp->IFB_IntOffCnt ) );
#else
- HCFASSERT( ifbp->IFB_IntOffCnt != 0xFFFE, action )
+ HCFASSERT( ifbp->IFB_IntOffCnt != 0xFFFE, action );
#endif // HCF_SLEEP
HCFASSERT( ifbp->IFB_IntOffCnt != 0xFFFF ||
- action == HCF_ACT_INT_OFF || action == HCF_ACT_INT_FORCE_ON, action )
+ action == HCF_ACT_INT_OFF || action == HCF_ACT_INT_FORCE_ON, action );
HCFASSERT( ifbp->IFB_IntOffCnt <= 16 || ifbp->IFB_IntOffCnt >= 0xFFFE,
- MERGE_2( action, ifbp->IFB_IntOffCnt ) ) //nesting more than 16 deep seems unreasonable
+ MERGE_2( action, ifbp->IFB_IntOffCnt ) ); //nesting more than 16 deep seems unreasonable
#endif // HCF_INT_ON
switch (action) {
cmd_exe( ifbp, HCMD_SLEEP, 0 );
break;
// case HCF_ACT_WAKEUP: // DDS Wakeup request
-// HCFASSERT( ifbp->IFB_IntOffCnt == 0xFFFE, ifbp->IFB_IntOffCnt )
+// HCFASSERT( ifbp->IFB_IntOffCnt == 0xFFFE, ifbp->IFB_IntOffCnt );
// ifbp->IFB_IntOffCnt++; // restore conventional I/F
// OPW( HREG_IO, HREG_IO_WAKEUP_ASYNC );
// MSF_WAIT(800); // MSF-defined function to wait n microseconds.
break;
default:
- HCFASSERT( DO_ASSERT, action )
+ HCFASSERT( DO_ASSERT, action );
break;
}
//! do not HCFASSERT( rc == HCF_SUCCESS, rc ) /* 30*/
- HCFLOGEXIT( HCF_TRACE_ACTION )
+ HCFLOGEXIT( HCF_TRACE_ACTION );
return rc;
} // hcf_action
#endif // HCF_DL_ONLY
x &= ~HFS_TX_CNTL_PORT;
}
HCFASSERT( x==HCF_CNTL_ENABLE || x==HCF_CNTL_DISABLE || HCF_CNTL_CONTINUE ||
- x==HCF_CNTL_CONNECT || x==HCF_CNTL_DISCONNECT, cmd )
+ x==HCF_CNTL_CONNECT || x==HCF_CNTL_DISCONNECT, cmd );
}
#endif // HCF_ASSERT
// #if (HCF_SLEEP) & HCF_DDS
-// HCFASSERT( ifbp->IFB_IntOffCnt != 0xFFFE, cmd )
+// HCFASSERT( ifbp->IFB_IntOffCnt != 0xFFFE, cmd );
// #endif // HCF_DDS
- HCFLOGENTRY( HCF_TRACE_CNTL, cmd )
+ HCFLOGENTRY( HCF_TRACE_CNTL, cmd );
if ( ifbp->IFB_CardStat == 0 ) { /*2*/
/*6*/ rc = cmd_exe( ifbp, cmd, 0 );
#if (HCF_SLEEP) & HCF_DDS
* as additional beneficiary side effect, the SOP and EOP bits will also be cleared
*/
ifbp->IFB_CntlOpt |= DMA_ENABLED;
- HCFASSERT( NT_ASSERT, NEVER_TESTED )
+ HCFASSERT( NT_ASSERT, NEVER_TESTED );
// make the entire rx descriptor chain DMA-owned, so the DMA engine can (re-)use it.
p = ifbp->IFB_FirstDesc[DMA_RX];
if (p != NULL) { //;? Think this over again in the light of the new chaining strategy
if ( 1 ) { //begin alternative
- HCFASSERT( NT_ASSERT, NEVER_TESTED )
+ HCFASSERT( NT_ASSERT, NEVER_TESTED );
put_frame_lst( ifbp, ifbp->IFB_FirstDesc[DMA_RX], DMA_RX );
if ( ifbp->IFB_FirstDesc[DMA_RX] ) {
put_frame_lst( ifbp, ifbp->IFB_FirstDesc[DMA_RX]->next_desc_addr, DMA_RX );
}
}
#endif // HCF_DMA
- HCFASSERT( rc == HCF_SUCCESS, rc )
- HCFLOGEXIT( HCF_TRACE_CNTL )
+ HCFASSERT( rc == HCF_SUCCESS, rc );
+ HCFLOGEXIT( HCF_TRACE_CNTL );
return rc;
} // hcf_cntl
ifbp->IFB_AssertStrct.frag_buf[0].frag_addr = &ifbp->IFB_AssertLine;
#endif // HCF_ASSERT_MB
#endif // HCF_ASSERT
- IF_PROT_TIME( prot_cnt = ifbp->IFB_TickIni = INI_TICK_INI; )
+ IF_PROT_TIME( prot_cnt = ifbp->IFB_TickIni = INI_TICK_INI );
#if ( (HCF_TYPE) & HCF_TYPE_PRELOADED ) == 0
//!! No asserts before Reset-bit in HREG_IO is cleared
OPW( HREG_IO, 0x0000 ); //OPW useable /* 2b*/
HCF_WAIT_WHILE( (IPW( HREG_EV_STAT) & HREG_EV_CMD) == 0 );
- IF_PROT_TIME( HCFASSERT( prot_cnt, IPW( HREG_EV_STAT) ) )
- IF_PROT_TIME( if ( prot_cnt ) prot_cnt = ifbp->IFB_TickIni; )
+ IF_PROT_TIME( HCFASSERT( prot_cnt, IPW( HREG_EV_STAT) ) );
+ IF_PROT_TIME( if ( prot_cnt ) prot_cnt = ifbp->IFB_TickIni );
#endif // HCF_TYPE_PRELOADED
//!! No asserts before Reset-bit in HREG_IO is cleared
- HCFASSERT( DO_ASSERT, MERGE_2( HCF_ASSERT, 0xCAF0 ) ) //just to proof that the complete assert machinery is working
- HCFASSERT( xa != CFG_FW_IDENTITY, 0 ) // assert if hcf_connect is called without intervening hcf_disconnect.
- HCFASSERT( ((hcf_32)(void*)ifbp & (HCF_ALIGN-1) ) == 0, (hcf_32)(void*)ifbp )
- HCFASSERT( (io_addr & 0x003F) == 0, io_addr )
+ HCFASSERT( DO_ASSERT, MERGE_2( HCF_ASSERT, 0xCAF0 ) ); //just to proof that the complete assert machinery is working
+ HCFASSERT( xa != CFG_FW_IDENTITY, 0 ); // assert if hcf_connect is called without intervening hcf_disconnect.
+ HCFASSERT( ((hcf_32)(void*)ifbp & (HCF_ALIGN-1) ) == 0, (hcf_32)(void*)ifbp );
+ HCFASSERT( (io_addr & 0x003F) == 0, io_addr );
//if Busy bit in Cmd register
if (IPW( HREG_CMD ) & HCMD_BUSY ) { /* 8 */
//. Ack all to unblock a (possibly) blocked cmd pipe line
//. Wait for Busy bit drop in Cmd register
//. Wait for Cmd bit raise in Ev register
HCF_WAIT_WHILE( ( IPW( HREG_CMD ) & HCMD_BUSY ) && (IPW( HREG_EV_STAT) & HREG_EV_CMD) == 0 );
- IF_PROT_TIME( HCFASSERT( prot_cnt, IPW( HREG_EV_STAT) ) ) /* if prot_cnt == 0, cmd_exe will fail, causing DEFUNCT */
+ IF_PROT_TIME( HCFASSERT( prot_cnt, IPW( HREG_EV_STAT) ) ); /* if prot_cnt == 0, cmd_exe will fail, causing DEFUNCT */
}
OPW( HREG_EV_ACK, ~HREG_EV_SLEEP_REQ );
#if ( (HCF_TYPE) & HCF_TYPE_PRELOADED ) == 0 /*12*/
DESC_STRCT *head = ifbp->IFB_FirstDesc[tx_rx_flag];
DESC_STRCT *copy, *p, *prev;
- HCFASSERT( tx_rx_flag == DMA_RX || tx_rx_flag == DMA_TX, tx_rx_flag )
+ HCFASSERT( tx_rx_flag == DMA_RX || tx_rx_flag == DMA_TX, tx_rx_flag );
//if FrameList
if ( head ) {
//. search for last descriptor of first FrameList
DESC_STRCT *p = descp;
hcf_16 port;
- HCFASSERT( ifbp->IFB_CntlOpt & USE_DMA, ifbp->IFB_CntlOpt) //only hcf_dma_tx_put must also be DMA_ENABLED
- HCFASSERT( tx_rx_flag == DMA_RX || tx_rx_flag == DMA_TX, tx_rx_flag )
- HCFASSERT( p , 0 )
+ HCFASSERT( ifbp->IFB_CntlOpt & USE_DMA, ifbp->IFB_CntlOpt); //only hcf_dma_tx_put must also be DMA_ENABLED
+ HCFASSERT( tx_rx_flag == DMA_RX || tx_rx_flag == DMA_TX, tx_rx_flag );
+ HCFASSERT( p , 0 );
while ( p ) {
- HCFASSERT( ((hcf_32)p & 3 ) == 0, (hcf_32)p )
- HCFASSERT( (p->BUF_CNT & ~DESC_CNT_MASK) == 0, p->BUF_CNT )
- HCFASSERT( (p->BUF_SIZE & ~DESC_CNT_MASK) == 0, p->BUF_SIZE )
+ HCFASSERT( ((hcf_32)p & 3 ) == 0, (hcf_32)p );
+ HCFASSERT( (p->BUF_CNT & ~DESC_CNT_MASK) == 0, p->BUF_CNT );
+ HCFASSERT( (p->BUF_SIZE & ~DESC_CNT_MASK) == 0, p->BUF_SIZE );
p->BUF_SIZE &= DESC_CNT_MASK; //!!this SHOULD be superfluous in case of correct MSF
p->BUF_CNT &= tx_rx_flag == DMA_RX ? 0 : DESC_CNT_MASK; //!!this SHOULD be superfluous in case of correct MSF
p->BUF_CNT |= DESC_DMA_OWNED;
if ( p->next_desc_addr ) {
-// HCFASSERT( p->buf_addr && p->buf_phys_addr && p->BUF_SIZE && +/- p->BUF_SIZE, ... )
- HCFASSERT( p->next_desc_addr->desc_phys_addr, (hcf_32)p->next_desc_addr )
+// HCFASSERT( p->buf_addr && p->buf_phys_addr && p->BUF_SIZE && +/- p->BUF_SIZE, ... );
+ HCFASSERT( p->next_desc_addr->desc_phys_addr, (hcf_32)p->next_desc_addr );
p->next_desc_phys_addr = p->next_desc_addr->desc_phys_addr;
} else { //
p->next_desc_phys_addr = 0;
if ( p->buf_addr == NULL ) { // DELWA Descriptor
- HCFASSERT( descp == p, (hcf_32)descp ) //singleton DescriptorList
- HCFASSERT( ifbp->IFB_FirstDesc[tx_rx_flag] == NULL, (hcf_32)ifbp->IFB_FirstDesc[tx_rx_flag])
- HCFASSERT( ifbp->IFB_LastDesc[tx_rx_flag] == NULL, (hcf_32)ifbp->IFB_LastDesc[tx_rx_flag])
+ HCFASSERT( descp == p, (hcf_32)descp ); //singleton DescriptorList
+ HCFASSERT( ifbp->IFB_FirstDesc[tx_rx_flag] == NULL, (hcf_32)ifbp->IFB_FirstDesc[tx_rx_flag]);
+ HCFASSERT( ifbp->IFB_LastDesc[tx_rx_flag] == NULL, (hcf_32)ifbp->IFB_LastDesc[tx_rx_flag]);
descp->BUF_CNT = 0; //&= ~DESC_DMA_OWNED;
ifbp->IFB_FirstDesc[tx_rx_flag] = descp;
// part of alternative ifbp->IFB_LastDesc[tx_rx_flag] = ifbp->IFB_FirstDesc[tx_rx_flag] = descp;
// . prepare for activation DMA controller
// part of alternative descp = descp->next_desc_addr;
} else { //a "real" FrameList, hand it over to the DMA engine
- HCFASSERT( ifbp->IFB_FirstDesc[tx_rx_flag], (hcf_32)descp )
- HCFASSERT( ifbp->IFB_LastDesc[tx_rx_flag], (hcf_32)descp )
+ HCFASSERT( ifbp->IFB_FirstDesc[tx_rx_flag], (hcf_32)descp );
+ HCFASSERT( ifbp->IFB_LastDesc[tx_rx_flag], (hcf_32)descp );
HCFASSERT( ifbp->IFB_LastDesc[tx_rx_flag]->next_desc_addr == NULL,
- (hcf_32)ifbp->IFB_LastDesc[tx_rx_flag]->next_desc_addr)
+ (hcf_32)ifbp->IFB_LastDesc[tx_rx_flag]->next_desc_addr);
// p->buf_cntl.cntl_stat |= DESC_DMA_OWNED;
ifbp->IFB_LastDesc[tx_rx_flag]->next_desc_addr = descp;
ifbp->IFB_LastDesc[tx_rx_flag]->next_desc_phys_addr = descp->desc_phys_addr;
{
int i;
DESC_STRCT *p = descp->next_desc_addr; //pointer to 2nd descriptor of frame
- HCFASSERT(p, 0)
+ HCFASSERT(p, 0);
// The 2nd descriptor contains (maybe) a SNAP header plus part or whole of the payload.
//determine decapsulation sub-flag in RxFS
i = *(wci_recordp)&descp->buf_addr[HFS_STAT] & ( HFS_STAT_MSG_TYPE | HFS_STAT_ERR );
if ( i == HFS_STAT_TUNNEL ||
( i == HFS_STAT_1042 && hcf_encap( (wci_bufp)&p->buf_addr[HCF_DASA_SIZE] ) != ENC_TUNNEL )) {
// The 2nd descriptor contains a SNAP header plus part or whole of the payload.
- HCFASSERT( p->BUF_CNT == (p->buf_addr[5] + (p->buf_addr[4]<<8) + 2*6 + 2 - 8), p->BUF_CNT )
+ HCFASSERT( p->BUF_CNT == (p->buf_addr[5] + (p->buf_addr[4]<<8) + 2*6 + 2 - 8), p->BUF_CNT );
// perform decapsulation
- HCFASSERT(p->BUF_SIZE >=8, p->BUF_SIZE)
+ HCFASSERT(p->BUF_SIZE >=8, p->BUF_SIZE);
// move SA[2:5] in the second buffer to replace part of the SNAP header
for ( i=3; i >= 0; i--) p->buf_addr[i+8] = p->buf_addr[i];
// copy DA[0:5], SA[0:1] from first buffer to second buffer
}
#endif // HCF_ENC
if ( descp == NULL ) ifbp->IFB_DmaPackets &= (hcf_16)~HREG_EV_RDMAD; //;?could be integrated into get_frame_lst
- HCFLOGEXIT( HCF_TRACE_DMA_RX_GET )
+ HCFLOGEXIT( HCF_TRACE_DMA_RX_GET );
return descp;
} // hcf_dma_rx_get
hcf_dma_rx_put( IFBP ifbp, DESC_STRCT *descp )
{
- HCFLOGENTRY( HCF_TRACE_DMA_RX_PUT, 0xDA01 )
- HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic )
- HCFASSERT_INT
+ HCFLOGENTRY( HCF_TRACE_DMA_RX_PUT, 0xDA01 );
+ HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic );
+ HCFASSERT_INT;
put_frame_lst( ifbp, descp, DMA_RX );
#if HCF_ASSERT && (HCF_ENCAP) == HCF_ENC
if ( descp->buf_addr ) {
- HCFASSERT( descp->BUF_SIZE == HCF_DMA_RX_BUF1_SIZE, descp->BUF_SIZE )
- HCFASSERT( descp->next_desc_addr, 0 ) // first descriptor should be followed by another descriptor
+ HCFASSERT( descp->BUF_SIZE == HCF_DMA_RX_BUF1_SIZE, descp->BUF_SIZE );
+ HCFASSERT( descp->next_desc_addr, 0 ); // first descriptor should be followed by another descriptor
// The second DB is for SNAP and payload purposes. It should be a minimum of 12 bytes in size.
- HCFASSERT( descp->next_desc_addr->BUF_SIZE >= 12, descp->next_desc_addr->BUF_SIZE )
+ HCFASSERT( descp->next_desc_addr->BUF_SIZE >= 12, descp->next_desc_addr->BUF_SIZE );
}
#endif // HCFASSERT / HCF_ENC
- HCFLOGEXIT( HCF_TRACE_DMA_RX_PUT )
+ HCFLOGEXIT( HCF_TRACE_DMA_RX_PUT );
} // hcf_dma_rx_put
if ( descp == NULL ) { //;?could be integrated into get_frame_lst
ifbp->IFB_DmaPackets &= (hcf_16)~HREG_EV_TDMAD;
}
- HCFLOGEXIT( HCF_TRACE_DMA_TX_GET )
+ HCFLOGEXIT( HCF_TRACE_DMA_TX_GET );
return descp;
} // hcf_dma_tx_get
#if HCF_ASSERT
int x = ifbp->IFB_FWIdentity.comp_id == COMP_ID_FW_AP ? tx_cntl & ~HFS_TX_CNTL_PORT : tx_cntl;
- HCFASSERT( (x & ~HCF_TX_CNTL_MASK ) == 0, tx_cntl )
+ HCFASSERT( (x & ~HCF_TX_CNTL_MASK ) == 0, tx_cntl );
#endif // HCF_ASSERT
- HCFLOGENTRY( HCF_TRACE_DMA_TX_PUT, 0xDA03 )
- HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic )
- HCFASSERT_INT
- HCFASSERT( ( ifbp->IFB_CntlOpt & (USE_DMA|DMA_ENABLED) ) == (USE_DMA|DMA_ENABLED), ifbp->IFB_CntlOpt)
+ HCFLOGENTRY( HCF_TRACE_DMA_TX_PUT, 0xDA03 );
+ HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic );
+ HCFASSERT_INT;
+ HCFASSERT( ( ifbp->IFB_CntlOpt & (USE_DMA|DMA_ENABLED) ) == (USE_DMA|DMA_ENABLED), ifbp->IFB_CntlOpt);
if ( descp->buf_addr ) {
*(hcf_16*)(descp->buf_addr + HFS_TX_CNTL) = tx_cntl; /*1*/
#if (HCF_ENCAP) == HCF_ENC
- HCFASSERT( descp->next_desc_addr, 0 ) //at least 2 descripors
- HCFASSERT( descp->BUF_CNT == HFS_ADDR_DEST, descp->BUF_CNT ) //exact length required for 1st buffer
- HCFASSERT( descp->BUF_SIZE >= HCF_DMA_TX_BUF1_SIZE, descp->BUF_SIZE ) //minimal storage for encapsulation
+ HCFASSERT( descp->next_desc_addr, 0 ); //at least 2 descripors
+ HCFASSERT( descp->BUF_CNT == HFS_ADDR_DEST, descp->BUF_CNT ); //exact length required for 1st buffer
+ HCFASSERT( descp->BUF_SIZE >= HCF_DMA_TX_BUF1_SIZE, descp->BUF_SIZE ); //minimal storage for encapsulation
HCFASSERT( p->BUF_CNT >= 14, p->BUF_CNT ); //at least DA, SA and 'type' in 2nd buffer
#if (HCF_TYPE) & HCF_TYPE_CCX
#endif // HCF_ENC
}
put_frame_lst( ifbp, descp, DMA_TX );
- HCFLOGEXIT( HCF_TRACE_DMA_TX_PUT )
+ HCFLOGEXIT( HCF_TRACE_DMA_TX_PUT );
} // hcf_dma_tx_put
#endif // HCF_DMA
*/
int i;
- HCFLOGENTRY( HCF_TRACE_GET_INFO, ltvp->typ )
- HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic )
- HCFASSERT_INT
- HCFASSERT( ltvp, 0 )
- HCFASSERT( 1 < ltvp->len && ltvp->len <= HCF_MAX_LTV + 1, MERGE_2( ltvp->typ, ltvp->len ) )
+ HCFLOGENTRY( HCF_TRACE_GET_INFO, ltvp->typ );
+ HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic );
+ HCFASSERT_INT;
+ HCFASSERT( ltvp, 0 );
+ HCFASSERT( 1 < ltvp->len && ltvp->len <= HCF_MAX_LTV + 1, MERGE_2( ltvp->typ, ltvp->len ) );
ltvp->len = 0; //default to: No Info Available
#if defined MSF_COMPONENT_ID || (HCF_EXT) & HCF_EXT_MB //filter out all specials
}
} else if ( type == CFG_CMD_HCF ) {
#define P ((CFG_CMD_HCF_STRCT FAR *)ltvp)
- HCFASSERT( P->cmd == CFG_CMD_HCF_REG_ACCESS, P->cmd ) //only Hermes register access supported
+ HCFASSERT( P->cmd == CFG_CMD_HCF_REG_ACCESS, P->cmd ); //only Hermes register access supported
if ( P->cmd == CFG_CMD_HCF_REG_ACCESS ) {
- HCFASSERT( P->mode < ifbp->IFB_IOBase, P->mode ) //Check Register space
+ HCFASSERT( P->mode < ifbp->IFB_IOBase, P->mode ); //Check Register space
ltvp->len = min( len, 4 ); //RESTORE ltv length
P->add_info = IPW( P->mode );
}
get_frag( ifbp, (wci_bufp)<vp->len, 2*len+2 BE_PAR(2) );
if ( IPW( HREG_STAT ) == 0xFFFF ) { //NIC removal test
ltvp->len = 0;
- HCFASSERT( DO_ASSERT, type )
+ HCFASSERT( DO_ASSERT, type );
}
}
/*12*/ } else HCFASSERT( DO_ASSERT, type ) /*NOP*/; //NOP in case HCFASSERT is dummy
}
}
HCFASSERT( rc == HCF_SUCCESS || ( rc == HCF_ERR_LEN && ifbp->IFB_AssertTrace & 1<<HCF_TRACE_PUT_INFO ),
- MERGE_2( type, rc ) ) /*20*/
- HCFLOGEXIT( HCF_TRACE_GET_INFO )
+ MERGE_2( type, rc ) ); /*20*/
+ HCFLOGEXIT( HCF_TRACE_GET_INFO );
return rc;
} // hcf_get_info
{
int rc = HCF_SUCCESS;
- HCFLOGENTRY( HCF_TRACE_PUT_INFO, ltvp->typ )
- HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic )
- HCFASSERT_INT
- HCFASSERT( ltvp, 0 )
- HCFASSERT( 1 < ltvp->len && ltvp->len <= HCF_MAX_LTV + 1, ltvp->len )
+ HCFLOGENTRY( HCF_TRACE_PUT_INFO, ltvp->typ );
+ HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic );
+ HCFASSERT_INT;
+ HCFASSERT( ltvp, 0 );
+ HCFASSERT( 1 < ltvp->len && ltvp->len <= HCF_MAX_LTV + 1, ltvp->len );
//all codes between 0xFA00 and 0xFCFF are passed to Hermes
#if (HCF_TYPE) & HCF_TYPE_WPA
#define P ((CFG_REG_ASSERT_RTNP_STRCT FAR *)ltvp)
ifbp->IFB_AssertRtn = P->rtnp;
// ifbp->IFB_AssertLvl = P->lvl; //TODO not yet supported so default is set in hcf_connect
- HCFASSERT( DO_ASSERT, MERGE_2( HCF_ASSERT, 0xCAF1 ) ) //just to proof that the complete assert machinery is working
+ HCFASSERT( DO_ASSERT, MERGE_2( HCF_ASSERT, 0xCAF1 ) ); //just to proof that the complete assert machinery is working
#undef P
break;
#endif // HCF_ASSERT_RT_MSF_RTN
break;
#endif // HCF_EXT_INFO_LOG
case CFG_CNTL_OPT: //overrule option
- HCFASSERT( ( ltvp->val[0] & ~(USE_DMA | USE_16BIT) ) == 0, ltvp->val[0] )
+ HCFASSERT( ( ltvp->val[0] & ~(USE_DMA | USE_16BIT) ) == 0, ltvp->val[0] );
if ( ( ltvp->val[0] & USE_DMA ) == 0 ) ifbp->IFB_CntlOpt &= ~USE_DMA;
ifbp->IFB_CntlOpt |= ltvp->val[0] & USE_16BIT;
break;
#if (HCF_EXT) & HCF_EXT_MB
case CFG_REG_MB: //Register MailBox
#define P ((CFG_REG_MB_STRCT FAR *)ltvp)
- HCFASSERT( ( (hcf_32)P->mb_addr & 0x0001 ) == 0, (hcf_32)P->mb_addr )
- HCFASSERT( (P)->mb_size >= 60, (P)->mb_size )
+ HCFASSERT( ( (hcf_32)P->mb_addr & 0x0001 ) == 0, (hcf_32)P->mb_addr );
+ HCFASSERT( (P)->mb_size >= 60, (P)->mb_size );
ifbp->IFB_MBp = P->mb_addr;
/* if no MB present, size must be 0 for ;?the old;? put_info_mb to work correctly */
ifbp->IFB_MBSize = ifbp->IFB_MBp == NULL ? 0 : P->mb_size;
ifbp->IFB_MBWp = ifbp->IFB_MBRp = 0;
ifbp->IFB_MBp[0] = 0; //flag the MailBox as empty
ifbp->IFB_MBInfoLen = 0;
- HCFASSERT( ifbp->IFB_MBSize >= 60 || ifbp->IFB_MBp == NULL, ifbp->IFB_MBSize )
+ HCFASSERT( ifbp->IFB_MBSize >= 60 || ifbp->IFB_MBp == NULL, ifbp->IFB_MBSize );
#undef P
break;
case CFG_MB_INFO: //store MailBoxInfoBlock
break;
case CFG_CMD_HCF:
#define P ((CFG_CMD_HCF_STRCT FAR *)ltvp)
- HCFASSERT( P->cmd == CFG_CMD_HCF_REG_ACCESS, P->cmd ) //only Hermes register access supported
+ HCFASSERT( P->cmd == CFG_CMD_HCF_REG_ACCESS, P->cmd ); //only Hermes register access supported
if ( P->cmd == CFG_CMD_HCF_REG_ACCESS ) {
- HCFASSERT( P->mode < ifbp->IFB_IOBase, P->mode ) //Check Register space
+ HCFASSERT( P->mode < ifbp->IFB_IOBase, P->mode ); //Check Register space
OPW( P->mode, P->add_info);
}
#undef P
rc = put_info( ifbp, ltvp );
}
//DO NOT !!! HCFASSERT( rc == HCF_SUCCESS, rc ) /* 20 */
- HCFLOGEXIT( HCF_TRACE_PUT_INFO )
+ HCFLOGEXIT( HCF_TRACE_PUT_INFO );
return rc;
} // hcf_put_info
hcf_16 lal = ifbp->IFB_lal - offset; //available data within LookAhead Buffer
hcf_16 j;
- HCFLOGENTRY( HCF_TRACE_RCV_MSG, offset )
- HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic )
- HCFASSERT_INT
- HCFASSERT( descp, HCF_TRACE_RCV_MSG )
- HCFASSERT( ifbp->IFB_RxLen, HCF_TRACE_RCV_MSG )
- HCFASSERT( ifbp->IFB_RxLen >= offset, MERGE_2( offset, ifbp->IFB_RxLen ) )
- HCFASSERT( ifbp->IFB_lal >= offset, offset )
- HCFASSERT( (ifbp->IFB_CntlOpt & USE_DMA) == 0, 0xDADA )
+ HCFLOGENTRY( HCF_TRACE_RCV_MSG, offset );
+ HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic );
+ HCFASSERT_INT;
+ HCFASSERT( descp, HCF_TRACE_RCV_MSG );
+ HCFASSERT( ifbp->IFB_RxLen, HCF_TRACE_RCV_MSG );
+ HCFASSERT( ifbp->IFB_RxLen >= offset, MERGE_2( offset, ifbp->IFB_RxLen ) );
+ HCFASSERT( ifbp->IFB_lal >= offset, offset );
+ HCFASSERT( (ifbp->IFB_CntlOpt & USE_DMA) == 0, 0xDADA );
if ( tot_len < 0 ) {
lal = 0; tot_len = 0; //suppress all copying activity in the do--while loop
}
do { //loop over all available fragments
// obnoxious hcf.c(1480) : warning C4769: conversion of near pointer to long integer
- HCFASSERT( ((hcf_32)descp & 3 ) == 0, (hcf_32)descp )
+ HCFASSERT( ((hcf_32)descp & 3 ) == 0, (hcf_32)descp );
cp = descp->buf_addr;
j = min( (hcf_16)tot_len, descp->BUF_SIZE ); //minimum of "what's` available" and fragment size
descp->BUF_CNT = j;
}
#endif // HCF_TYPE_WPA
(void)hcf_action( ifbp, HCF_ACT_RX_ACK ); //only 1 shot to get the data, so free the resources in the NIC
- HCFASSERT( rc == HCF_SUCCESS, rc )
- HCFLOGEXIT( HCF_TRACE_RCV_MSG )
+ HCFASSERT( rc == HCF_SUCCESS, rc );
+ HCFLOGEXIT( HCF_TRACE_RCV_MSG );
return rc;
} // hcf_rcv_msg
#endif // HCF_DL_ONLY
hcf_16 fid = 0;
- HCFASSERT( ifbp->IFB_RscInd || descp == NULL, ifbp->IFB_RscInd )
- HCFASSERT( (ifbp->IFB_CntlOpt & USE_DMA) == 0, 0xDADB )
+ HCFASSERT( ifbp->IFB_RscInd || descp == NULL, ifbp->IFB_RscInd );
+ HCFASSERT( (ifbp->IFB_CntlOpt & USE_DMA) == 0, 0xDADB );
- HCFLOGENTRY( HCF_TRACE_SEND_MSG, tx_cntl )
- HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic )
- HCFASSERT_INT
+ HCFLOGENTRY( HCF_TRACE_SEND_MSG, tx_cntl );
+ HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic );
+ HCFASSERT_INT;
/* obnoxious c:/hcf/hcf.c(1480) : warning C4769: conversion of near pointer to long integer,
* so skip */
- HCFASSERT( ((hcf_32)descp & 3 ) == 0, (hcf_32)descp )
+ HCFASSERT( ((hcf_32)descp & 3 ) == 0, (hcf_32)descp );
#if HCF_ASSERT
{ int x = ifbp->IFB_FWIdentity.comp_id == COMP_ID_FW_AP ? tx_cntl & ~HFS_TX_CNTL_PORT : tx_cntl;
- HCFASSERT( (x & ~HCF_TX_CNTL_MASK ) == 0, tx_cntl )
+ HCFASSERT( (x & ~HCF_TX_CNTL_MASK ) == 0, tx_cntl );
}
#endif // HCF_ASSERT
//copy all the fragments in a transparent fashion
for ( p = descp; p; p = p->next_desc_addr ) {
/* obnoxious warning C4769: conversion of near pointer to long integer */
- HCFASSERT( ((hcf_32)p & 3 ) == 0, (hcf_32)p )
+ HCFASSERT( ((hcf_32)p & 3 ) == 0, (hcf_32)p );
put_frag( ifbp, p->buf_addr, p->BUF_CNT BE_PAR(0) );
}
rc = cmd_exe( ifbp, HCMD_THESEUS | HCMD_BUSY | HCMD_STARTPREAMBLE, fid );
}
}
// een slecht voorbeeld doet goed volgen ;?
- HCFLOGEXIT( HCF_TRACE_SEND_MSG )
+ HCFLOGEXIT( HCF_TRACE_SEND_MSG );
return rc;
}
#endif // HCF_EXT_TX_CONT
p = descp;
do len += p->BUF_CNT; while ( ( p = p->next_desc_addr ) != NULL );
p = descp;
-//;? HCFASSERT( len <= HCF_MAX_MSG, len )
+//;? HCFASSERT( len <= HCF_MAX_MSG, len );
/*7*/ (void)setup_bap( ifbp, fid, HFS_TX_CNTL, IO_OUT );
#if (HCF_TYPE) & HCF_TYPE_TX_DELAY
- HCFASSERT( ( descp != NULL ) ^ ( tx_cntl & HFS_TX_CNTL_TX_DELAY ), tx_cntl )
+ HCFASSERT( ( descp != NULL ) ^ ( tx_cntl & HFS_TX_CNTL_TX_DELAY ), tx_cntl );
if ( tx_cntl & HFS_TX_CNTL_TX_DELAY ) {
tx_cntl &= ~HFS_TX_CNTL_TX_DELAY; //!!HFS_TX_CNTL_TX_DELAY no longer available
ifbp->IFB_TxFID = fid;
OPW( HREG_DATA_1, tx_cntl ) ;
OPW( HREG_DATA_1, 0 );
#if ! ( (HCF_TYPE) & HCF_TYPE_CCX )
- HCFASSERT( p->BUF_CNT >= 14, p->BUF_CNT )
+ HCFASSERT( p->BUF_CNT >= 14, p->BUF_CNT );
/* assume DestAddr/SrcAddr/Len/Type ALWAYS contained in 1st fragment
* otherwise life gets too cumbersome for MIC and Encapsulation !!!!!!!!
if ( p->BUF_CNT >= 14 ) { alternatively: add a safety escape !!!!!!!!!!!! } */
while ( ( p = p->next_desc_addr ) != NULL ) {
/* obnoxious c:/hcf/hcf.c(1480) : warning C4769: conversion of near pointer to long integer,
* so skip */
- HCFASSERT( ((hcf_32)p & 3 ) == 0, (hcf_32)p )
+ HCFASSERT( ((hcf_32)p & 3 ) == 0, (hcf_32)p );
put_frag( ifbp, p->buf_addr, p->BUF_CNT BE_PAR(0) );
CALC_TX_MIC( p->buf_addr, p->BUF_CNT );
}
}
// #endif // ALLOC_15
}
-// HCFASSERT( level::ifbp->IFB_RscInd, ifbp->IFB_RscInd )
- HCFLOGEXIT( HCF_TRACE_SEND_MSG )
+// HCFASSERT( level::ifbp->IFB_RscInd, ifbp->IFB_RscInd );
+ HCFLOGEXIT( HCF_TRACE_SEND_MSG );
return rc;
} // hcf_send_msg
#endif // HCF_DL_ONLY
wci_bufp buf_addr;
hcf_16 i;
- HCFLOGENTRY( HCF_TRACE_SERVICE_NIC, ifbp->IFB_IntOffCnt )
- HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic )
- HCFASSERT_INT
+ HCFLOGENTRY( HCF_TRACE_SERVICE_NIC, ifbp->IFB_IntOffCnt );
+ HCFASSERT( ifbp->IFB_Magic == HCF_MAGIC, ifbp->IFB_Magic );
+ HCFASSERT_INT;
ifbp->IFB_LinkStat = 0; // ;? to be obsoleted ASAP /* 1*/
ifbp->IFB_DSLinkStat &= ~CFG_LINK_STAT_CHANGE; /* 1*/
if ( ifbp->IFB_RscInd == 0 && stat & HREG_EV_ALLOC ) { //Note: IFB_RscInd is ALWAYS 1 for DMA
ifbp->IFB_RscInd = 1;
}
- IF_TALLY( if ( stat & HREG_EV_INFO_DROP ) ifbp->IFB_HCF_Tallies.NoBufInfo++; )
+ IF_TALLY( if ( stat & HREG_EV_INFO_DROP ) { ifbp->IFB_HCF_Tallies.NoBufInfo++; } );
#if (HCF_EXT) & HCF_EXT_INT_TICK
if ( stat & HREG_EV_TICK ) {
ifbp->IFB_TickCnt++;
}
#if (HCF_EXT) & HCF_EXT_INT_TX_EX
if ( stat & HREG_EV_TX_EXT && ( i = IPW( HREG_TX_COMPL_FID ) ) != 0 /*DAWA*/ ) {
- DAWA_ZERO_FID( HREG_TX_COMPL_FID )
+ DAWA_ZERO_FID( HREG_TX_COMPL_FID );
(void)setup_bap( ifbp, i, 0, IO_IN );
get_frag( ifbp, &ifbp->IFB_TxFsStat, HFS_SWSUP BE_PAR(1) );
}
if ( !( ifbp->IFB_CntlOpt & USE_DMA ) ) //!! be aware of the logical indentations
#endif // HCF_DMA
/*16*/ if ( stat & HREG_EV_RX && ( ifbp->IFB_RxFID = IPW( HREG_RX_FID ) ) != 0 ) { //if 0 then DAWA_ACK
- HCFASSERT( bufp, len )
- HCFASSERT( len >= HFS_DAT + 2, len )
- DAWA_ZERO_FID( HREG_RX_FID )
- HCFASSERT( ifbp->IFB_RxFID < CFG_PROD_DATA, ifbp->IFB_RxFID)
+ HCFASSERT( bufp, len );
+ HCFASSERT( len >= HFS_DAT + 2, len );
+ DAWA_ZERO_FID( HREG_RX_FID );
+ HCFASSERT( ifbp->IFB_RxFID < CFG_PROD_DATA, ifbp->IFB_RxFID);
(void)setup_bap( ifbp, ifbp->IFB_RxFID, 0, IO_IN );
get_frag( ifbp, bufp, HFS_ADDR_DEST BE_PAR(1) );
ifbp->IFB_lap = buf_addr = bufp + HFS_ADDR_DEST;
#endif // HCF_TYPE_CCX
{
#if (HCF_ENCAP) == HCF_ENC
- HCFASSERT( len >= HFS_DAT + 2 + sizeof(snap_header), len )
+ HCFASSERT( len >= HFS_DAT + 2 + sizeof(snap_header), len );
/*34*/ i = *(wci_recordp)&bufp[HFS_STAT] & ( HFS_STAT_MSG_TYPE | HFS_STAT_ERR );
if ( i == HFS_STAT_TUNNEL ||
( i == HFS_STAT_1042 && hcf_encap( (wci_bufp)&bufp[HFS_TYPE] ) != ENC_TUNNEL ) ) {
}
}
// in case of DMA: signal availability of rx and/or tx packets to MSF
- IF_USE_DMA( ifbp->IFB_DmaPackets |= stat & ( HREG_EV_RDMAD | HREG_EV_TDMAD ); )
+ IF_USE_DMA( ifbp->IFB_DmaPackets |= stat & ( HREG_EV_RDMAD | HREG_EV_TDMAD ) );
// rlav : pending HREG_EV_RDMAD or HREG_EV_TDMAD events get acknowledged here.
/*54*/ stat &= (hcf_16)~( HREG_EV_SLEEP_REQ | HREG_EV_CMD | HREG_EV_ACK_REG_READY | HREG_EV_ALLOC | HREG_EV_FW_DMA );
//a positive mask would be easier to understand /*54*/ stat &= (hcf_16)~( HREG_EV_SLEEP_REQ | HREG_EV_CMD | HREG_EV_ACK_REG_READY | HREG_EV_ALLOC | HREG_EV_FW_DMA );
- IF_USE_DMA( stat &= (hcf_16)~HREG_EV_RX; )
+ IF_USE_DMA( stat &= (hcf_16)~HREG_EV_RX );
if ( stat ) {
DAWA_ACK( stat ); /*DAWA*/
}
}
- HCFLOGEXIT( HCF_TRACE_SERVICE_NIC )
+ HCFLOGEXIT( HCF_TRACE_SERVICE_NIC );
return rc;
} // hcf_service_nic
#endif // HCF_DL_ONLY
ifbp->IFB_TickIni = INI_TICK_INI;
ifbp->IFB_DefunctStat = HCF_ERR_DEFUNCT_TIMER;
ifbp->IFB_CardStat |= CARD_STAT_DEFUNCT;
- HCFASSERT( DO_ASSERT, prot_cnt )
+ HCFASSERT( DO_ASSERT, prot_cnt );
}
}
ifbp->IFB_TickIni <<= HCF_PROT_TIME_SHFT; /*8*/
cmd_cmpl( IFBP ifbp )
{
-PROT_CNT_INI
+PROT_CNT_INI;
int rc = HCF_SUCCESS;
hcf_16 stat;
- HCFLOGENTRY( HCF_TRACE_CMD_CPL, ifbp->IFB_Cmd )
+ HCFLOGENTRY( HCF_TRACE_CMD_CPL, ifbp->IFB_Cmd );
ifbp->IFB_Cmd &= ~HCMD_BUSY; /* 2 */
HCF_WAIT_WHILE( (IPW( HREG_EV_STAT) & HREG_EV_CMD) == 0 ); /* 4 */
stat = IPW( HREG_STAT );
#if HCF_PROT_TIME
if ( prot_cnt == 0 ) {
- IF_TALLY( ifbp->IFB_HCF_Tallies.MiscErr++; )
+ IF_TALLY( ifbp->IFB_HCF_Tallies.MiscErr++ );
rc = HCF_ERR_TIME_OUT;
- HCFASSERT( DO_ASSERT, ifbp->IFB_Cmd )
+ HCFASSERT( DO_ASSERT, ifbp->IFB_Cmd );
} else
#endif // HCF_PROT_TIME
{
rc = ifbp->IFB_DefunctStat = HCF_ERR_DEFUNCT_CMD_SEQ;
ifbp->IFB_CardStat |= CARD_STAT_DEFUNCT;
}
- IF_TALLY( ifbp->IFB_HCF_Tallies.MiscErr++; )
+ IF_TALLY( ifbp->IFB_HCF_Tallies.MiscErr++ );
ifbp->IFB_ErrCmd = stat;
ifbp->IFB_ErrQualifier = IPW( HREG_RESP_0 );
- HCFASSERT( DO_ASSERT, MERGE_2( IPW( HREG_PARAM_0 ), ifbp->IFB_Cmd ) )
- HCFASSERT( DO_ASSERT, MERGE_2( ifbp->IFB_ErrQualifier, ifbp->IFB_ErrCmd ) )
+ HCFASSERT( DO_ASSERT, MERGE_2( IPW( HREG_PARAM_0 ), ifbp->IFB_Cmd ) );
+ HCFASSERT( DO_ASSERT, MERGE_2( ifbp->IFB_ErrQualifier, ifbp->IFB_ErrCmd ) );
}
}
- HCFASSERT( rc == HCF_SUCCESS, rc)
- HCFLOGEXIT( HCF_TRACE_CMD_CPL )
+ HCFASSERT( rc == HCF_SUCCESS, rc);
+ HCFLOGEXIT( HCF_TRACE_CMD_CPL );
return rc;
} // cmd_cmpl
{
int rc;
- HCFLOGENTRY( HCF_TRACE_CMD_EXE, cmd_code )
- HCFASSERT( (cmd_code & HCMD_CMD_CODE) != HCMD_TX || cmd_code & HCMD_BUSY, cmd_code ) //Tx must have Busy bit set
+ HCFLOGENTRY( HCF_TRACE_CMD_EXE, cmd_code );
+ HCFASSERT( (cmd_code & HCMD_CMD_CODE) != HCMD_TX || cmd_code & HCMD_BUSY, cmd_code ); //Tx must have Busy bit set
OPW( HREG_SW_0, HCF_MAGIC );
if ( IPW( HREG_SW_0 ) == HCF_MAGIC ) { /* 1 */
rc = ifbp->IFB_DefunctStat;
rc = cmd_cmpl( ifbp );
}
}
- HCFASSERT( rc == HCF_SUCCESS, MERGE_2( rc, cmd_code ) )
- HCFLOGEXIT( HCF_TRACE_CMD_EXE )
+ HCFASSERT( rc == HCF_SUCCESS, MERGE_2( rc, cmd_code ) );
+ HCFLOGEXIT( HCF_TRACE_CMD_EXE );
return rc;
} // cmd_exe
wci_bufp cp;
hcf_io io_port = ifbp->IFB_IOBase + HREG_AUX_DATA;
- HCFLOGENTRY( HCF_TRACE_DL, ltvp->typ )
+ HCFLOGENTRY( HCF_TRACE_DL, ltvp->typ );
#if (HCF_TYPE) & HCF_TYPE_PRELOADED
- HCFASSERT( DO_ASSERT, ltvp->mode )
+ HCFASSERT( DO_ASSERT, ltvp->mode );
#else
//if initial "program" LTV
if ( ifbp->IFB_DLMode == CFG_PROG_STOP && ltvp->mode == CFG_PROG_VOLATILE) {
} else
#endif //;? as long as the above if contains a hard coded 0, might as well leave it out even more obvious
{ //. . get number of words to program
- HCFASSERT( ltvp->segment_size, *ltvp->host_addr )
+ HCFASSERT( ltvp->segment_size, *ltvp->host_addr );
i = ltvp->segment_size/2;
//. . copy data (words) from LTV via AUX port to NIC
cp = (wci_bufp)ltvp->host_addr; //OUT_PORT_STRING_8_16 macro may modify its parameters
}
ifbp->IFB_DLMode = ltvp->mode; //save state in IFB_DLMode
#endif // HCF_TYPE_PRELOADED
- HCFASSERT( rc == HCF_SUCCESS, rc )
- HCFLOGEXIT( HCF_TRACE_DL )
+ HCFASSERT( rc == HCF_SUCCESS, rc );
+ HCFLOGEXIT( HCF_TRACE_DL );
return rc;
} // download
hcf_16 fid = 0;
#if ( (HCF_TYPE) & HCF_TYPE_HII5 ) == 0
-PROT_CNT_INI
+PROT_CNT_INI;
#endif // HCF_TYPE_HII5
- IF_DMA( HCFASSERT(!(ifbp->IFB_CntlOpt & USE_DMA), ifbp->IFB_CntlOpt) )
+ IF_DMA( HCFASSERT(!(ifbp->IFB_CntlOpt & USE_DMA), ifbp->IFB_CntlOpt) );
if ( IPW( HREG_EV_STAT) & HREG_EV_ALLOC) {
fid = IPW( HREG_ALLOC_FID );
- HCFASSERT( fid, ifbp->IFB_RscInd )
- DAWA_ZERO_FID( HREG_ALLOC_FID )
+ HCFASSERT( fid, ifbp->IFB_RscInd );
+ DAWA_ZERO_FID( HREG_ALLOC_FID );
#if ( (HCF_TYPE) & HCF_TYPE_HII5 ) == 0
HCF_WAIT_WHILE( ( IPW( HREG_EV_STAT ) & HREG_EV_ACK_REG_READY ) == 0 );
- HCFASSERT( prot_cnt, IPW( HREG_EV_STAT ) )
+ HCFASSERT( prot_cnt, IPW( HREG_EV_STAT ) );
#endif // HCF_TYPE_HII5
DAWA_ACK( HREG_EV_ALLOC ); //!!note that HREG_EV_ALLOC is written only once
// 180 degree error in logic ;? #if ALLOC_15
int i; //prevent side effects from macro
int j;
- HCFASSERT( ((hcf_32)bufp & (HCF_ALIGN-1) ) == 0, (hcf_32)bufp )
+ HCFASSERT( ((hcf_32)bufp & (HCF_ALIGN-1) ) == 0, (hcf_32)bufp );
/*1: here recovery logic for intervening BAP access between hcf_service_nic and hcf_rcv_msg COULD be added
* if current access is RxInitial
}
}
#if HCF_BIG_ENDIAN
- HCFASSERT( word_len == 0 || word_len == 2 || word_len == 4, word_len )
- HCFASSERT( word_len == 0 || ((hcf_32)bufp & 1 ) == 0, (hcf_32)bufp )
- HCFASSERT( word_len <= len, MERGE2( word_len, len ) )
+ HCFASSERT( word_len == 0 || word_len == 2 || word_len == 4, word_len );
+ HCFASSERT( word_len == 0 || ((hcf_32)bufp & 1 ) == 0, (hcf_32)bufp );
+ HCFASSERT( word_len <= len, MERGE2( word_len, len ) );
//see put_frag for an alternative implementation, but be careful about what are int's and what are
//hcf_16's
if ( word_len ) { //. if there is anything to convert
int rc = HCF_SUCCESS;
- HCFLOGENTRY( HCF_TRACE_INIT, 0 )
+ HCFLOGENTRY( HCF_TRACE_INIT, 0 );
ifbp->IFB_CardStat = 0; /* 2*/
OPW( HREG_EV_ACK, ~HREG_EV_SLEEP_REQ ); /* 4*/
- IF_PROT_TIME( calibrate( ifbp ); ) /*10*/
+ IF_PROT_TIME( calibrate( ifbp ) ); /*10*/
#if 0 // OOR
ifbp->IFB_FWIdentity.len = 2; //misuse the IFB space for a put
ifbp->IFB_FWIdentity.typ = CFG_TICK_TIME;
#endif // MSF_COMPONENT_ID
#if (HCF_DL_ONLY) == 0 /* 28 */
if ( rc == HCF_SUCCESS && ifbp->IFB_FWIdentity.comp_id >= COMP_ID_FW_STA ) {
-PROT_CNT_INI
+PROT_CNT_INI;
/**************************************************************************************
* rlav: the DMA engine needs the host to cause a 'hanging alloc event' for it to consume.
* not sure if this is the right spot in the HCF, thinking about hcf_enable...
//#else
if ( rc == HCF_SUCCESS ) {
HCF_WAIT_WHILE( (IPW( HREG_EV_STAT ) & HREG_EV_ALLOC) == 0 );
- IF_PROT_TIME( HCFASSERT(prot_cnt, IPW( HREG_EV_STAT ) ) /*NOP*/;)
+ IF_PROT_TIME( HCFASSERT(prot_cnt, IPW( HREG_EV_STAT )) );
#if HCF_DMA
if ( ! ( ifbp->IFB_CntlOpt & USE_DMA ) )
#endif // HCF_DMA
{
ifbp->IFB_RscInd = get_fid( ifbp );
- HCFASSERT( ifbp->IFB_RscInd, 0 )
+ HCFASSERT( ifbp->IFB_RscInd, 0 );
cmd_exe( ifbp, HCMD_ALLOC, 0 );
- IF_PROT_TIME( if ( prot_cnt == 0 ) rc = HCF_ERR_TIME_OUT; )
+ IF_PROT_TIME( if ( prot_cnt == 0 ) rc = HCF_ERR_TIME_OUT );
}
}
//#endif // ALLOC_15
}
#endif // HCF_DL_ONLY
- HCFASSERT( rc == HCF_SUCCESS, rc )
- HCFLOGEXIT( HCF_TRACE_INIT )
+ HCFASSERT( rc == HCF_SUCCESS, rc );
+ HCFLOGEXIT( HCF_TRACE_INIT );
return rc;
} // init
HCFTRACE( ifbp, HCF_TRACE_ISR_INFO ); /* 1 */
fid = IPW( HREG_INFO_FID );
- DAWA_ZERO_FID( HREG_INFO_FID )
+ DAWA_ZERO_FID( HREG_INFO_FID );
if ( fid ) {
(void)setup_bap( ifbp, fid, 0, IO_IN );
get_frag( ifbp, (wci_bufp)info, 4 BE_PAR(2) );
- HCFASSERT( info[0] <= HCF_MAX_LTV + 1, MERGE_2( info[1], info[0] ) ) //;? a smaller value makes more sense
+ HCFASSERT( info[0] <= HCF_MAX_LTV + 1, MERGE_2( info[1], info[0] ) ); //;? a smaller value makes more sense
#if (HCF_TALLIES) & HCF_TALLIES_NIC //Hermes tally support
if ( info[1] == CFG_TALLIES ) {
hcf_32 *p;
/*6*/ while ( 1 ) {
if ( ridp->typ == 0 || ridp->typ == info[1] ) {
if ( ridp->bufp ) {
- HCFASSERT( ridp->len >= 2, ridp->typ )
+ HCFASSERT( ridp->len >= 2, ridp->typ );
ridp->bufp[0] = min((hcf_16)(ridp->len - 1), info[0] ); //save L
ridp->bufp[1] = info[1]; //save T
get_frag( ifbp, (wci_bufp)&ridp->bufp[2], (ridp->bufp[0] - 1)*2 BE_PAR(0) );
// /*6*/ while ( 1 ) {
// if ( ridp->typ == 0 || ridp->typ == info[1] ) {
// if ( ridp->bufp ) {
-// HCFASSERT( ridp->len >= 2, ridp->typ )
+// HCFASSERT( ridp->len >= 2, ridp->typ );
// (void)setup_bap( ifbp, fid, 2, IO_IN ); //restore BAP for tallies, linkstat and specific type followed by wild card
// ridp->bufp[0] = min( ridp->len - 1, info[0] ); //save L
// get_frag( ifbp, (wci_bufp)&ridp->bufp[1], ridp->bufp[0]*2 BE_PAR(0) );
hcf_io io_port = ifbp->IFB_IOBase + HREG_DATA_1; //BAP data register
int i; //prevent side effects from macro
hcf_16 j;
- HCFASSERT( ((hcf_32)bufp & (HCF_ALIGN-1) ) == 0, (hcf_32)bufp )
+ HCFASSERT( ((hcf_32)bufp & (HCF_ALIGN-1) ) == 0, (hcf_32)bufp );
#if HCF_BIG_ENDIAN
- HCFASSERT( word_len == 0 || word_len == 2 || word_len == 4, word_len )
- HCFASSERT( word_len == 0 || ((hcf_32)bufp & 1 ) == 0, (hcf_32)bufp )
- HCFASSERT( word_len <= len, MERGE_2( word_len, len ) )
+ HCFASSERT( word_len == 0 || word_len == 2 || word_len == 4, word_len );
+ HCFASSERT( word_len == 0 || ((hcf_32)bufp & 1 ) == 0, (hcf_32)bufp );
+ HCFASSERT( word_len <= len, MERGE_2( word_len, len ) );
if ( word_len ) { //if there is anything to convert
//. convert and write the 1st hcf_16
int rc = HCF_SUCCESS;
- HCFASSERT( ifbp->IFB_CardStat == 0, MERGE_2( ltvp->typ, ifbp->IFB_CardStat ) )
- HCFASSERT( CFG_RID_CFG_MIN <= ltvp->typ && ltvp->typ <= CFG_RID_CFG_MAX, ltvp->typ )
+ HCFASSERT( ifbp->IFB_CardStat == 0, MERGE_2( ltvp->typ, ifbp->IFB_CardStat ) );
+ HCFASSERT( CFG_RID_CFG_MIN <= ltvp->typ && ltvp->typ <= CFG_RID_CFG_MAX, ltvp->typ );
if ( ifbp->IFB_CardStat == 0 && /* 20*/
( ( CFG_RID_CFG_MIN <= ltvp->typ && ltvp->typ <= CFG_RID_CFG_MAX ) ||
t != CFG_DEAUTHENTICATE_ADDR
)
) {
- HCFASSERT( DO_ASSERT, ltvp->typ )
+ HCFASSERT( DO_ASSERT, ltvp->typ );
}
}
#endif // HCF_ASSERT
hcf_16 tlen; //free length/working length/offset in WMP frame
if ( ifbp->IFB_MBp == NULL ) return rc; //;?not sufficient
- HCFASSERT( ifbp->IFB_MBp != NULL, 0 ) //!!!be careful, don't get into an endless recursion
- HCFASSERT( ifbp->IFB_MBSize, 0 )
+ HCFASSERT( ifbp->IFB_MBp != NULL, 0 ); //!!!be careful, don't get into an endless recursion
+ HCFASSERT( ifbp->IFB_MBSize, 0 );
len = 1; /* 1 */
for ( i = 0; i < ltvp->frag_cnt; i++ ) {
}
if ( len + 2 >= tlen ){ /* 6 */
//Do Not ASSERT, this is a normal condition
- IF_TALLY( ifbp->IFB_HCF_Tallies.NoBufMB++; ) /*NOP to cover against analomies with empty compound*/;
+ IF_TALLY( ifbp->IFB_HCF_Tallies.NoBufMB++ );
rc = HCF_ERR_LEN;
} else {
*dp++ = len; //write Len (= size of T+V in words to MB_Info block
HCF_STATIC int
setup_bap( IFBP ifbp, hcf_16 fid, int offset, int type )
{
-PROT_CNT_INI
+PROT_CNT_INI;
int rc;
HCFTRACE( ifbp, HCF_TRACE_STRIO );
}
else ifbp->IFB_CarryOut = 0;
HCF_WAIT_WHILE( IPW( HREG_OFFSET_1) & HCMD_BUSY );
- HCFASSERT( !( IPW( HREG_OFFSET_1) & HREG_OFFSET_ERR ), MERGE_2( fid, offset ) ) /*8*/
+ HCFASSERT( !( IPW( HREG_OFFSET_1) & HREG_OFFSET_ERR ), MERGE_2( fid, offset ) ); /*8*/
if ( prot_cnt == 0 ) {
- HCFASSERT( DO_ASSERT, MERGE_2( fid, offset ) )
+ HCFASSERT( DO_ASSERT, MERGE_2( fid, offset ) );
rc = ifbp->IFB_DefunctStat = HCF_ERR_DEFUNCT_TIME_OUT;
ifbp->IFB_CardStat |= CARD_STAT_DEFUNCT;
}
projects / mirror_ubuntu-artful-kernel.git / commitdiff